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authorRalf Baechle <ralf@linux-mips.org>2007-10-22 05:38:44 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-10-22 17:09:00 -0400
commitd04533650f64fe3367e180f3e488d92205152cd3 (patch)
tree5f183668d97d9655a8517e61afd46bfa2f80b101 /include/asm-mips/gt64120.h
parent06d428d719dece96c01532b62df4140f4e69a308 (diff)
[MIPS] time: SMP-proofing of Sibyte clockevent/clocksource code.
The BCM148 has 4 cores but there are also just 4 generic timers available so use the ZBbus cycle counter instead of it. In addition the ZBbus counter also offers a much higher resolution and 64-bit counting so I'm considering a later complete conversion to it once I figure out if all members of the Sibyte SOC family support it - the docs seem to agree but the headers files seem to disagree ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/gt64120.h')
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