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authorLen Brown <len.brown@intel.com>2006-01-27 17:18:29 -0500
committerLen Brown <len.brown@intel.com>2006-01-27 17:18:29 -0500
commit292dd876ee765c478b27c93cc51e93a558ed58bf (patch)
tree5b740e93253295baee2a9c414a6c66d03d44a9ef /include/asm-mips/dsp.h
parentd4ec6c7cc9a15a7a529719bc3b84f46812f9842e (diff)
parent9fdb62af92c741addbea15545f214a6e89460865 (diff)
Pull release into acpica branch
Diffstat (limited to 'include/asm-mips/dsp.h')
-rw-r--r--include/asm-mips/dsp.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/include/asm-mips/dsp.h b/include/asm-mips/dsp.h
index 50f556bb4978..e9bfc0813c72 100644
--- a/include/asm-mips/dsp.h
+++ b/include/asm-mips/dsp.h
@@ -16,7 +16,7 @@
16#include <asm/mipsregs.h> 16#include <asm/mipsregs.h>
17 17
18#define DSP_DEFAULT 0x00000000 18#define DSP_DEFAULT 0x00000000
19#define DSP_MASK 0x1f 19#define DSP_MASK 0x3ff
20 20
21#define __enable_dsp_hazard() \ 21#define __enable_dsp_hazard() \
22do { \ 22do { \
@@ -48,6 +48,7 @@ do { \
48 tsk->thread.dsp.dspr[3] = mflo2(); \ 48 tsk->thread.dsp.dspr[3] = mflo2(); \
49 tsk->thread.dsp.dspr[4] = mfhi3(); \ 49 tsk->thread.dsp.dspr[4] = mfhi3(); \
50 tsk->thread.dsp.dspr[5] = mflo3(); \ 50 tsk->thread.dsp.dspr[5] = mflo3(); \
51 tsk->thread.dsp.dspcontrol = rddsp(DSP_MASK); \
51} while (0) 52} while (0)
52 53
53#define save_dsp(tsk) \ 54#define save_dsp(tsk) \
@@ -64,6 +65,7 @@ do { \
64 mtlo2(tsk->thread.dsp.dspr[3]); \ 65 mtlo2(tsk->thread.dsp.dspr[3]); \
65 mthi3(tsk->thread.dsp.dspr[4]); \ 66 mthi3(tsk->thread.dsp.dspr[4]); \
66 mtlo3(tsk->thread.dsp.dspr[5]); \ 67 mtlo3(tsk->thread.dsp.dspr[5]); \
68 wrdsp(tsk->thread.dsp.dspcontrol, DSP_MASK); \
67} while (0) 69} while (0)
68 70
69#define restore_dsp(tsk) \ 71#define restore_dsp(tsk) \