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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-mips/ddb5xxx
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'include/asm-mips/ddb5xxx')
-rw-r--r--include/asm-mips/ddb5xxx/ddb5074.h38
-rw-r--r--include/asm-mips/ddb5xxx/ddb5476.h157
-rw-r--r--include/asm-mips/ddb5xxx/ddb5477.h346
-rw-r--r--include/asm-mips/ddb5xxx/ddb5xxx.h273
4 files changed, 814 insertions, 0 deletions
diff --git a/include/asm-mips/ddb5xxx/ddb5074.h b/include/asm-mips/ddb5xxx/ddb5074.h
new file mode 100644
index 000000000000..58d88306af65
--- /dev/null
+++ b/include/asm-mips/ddb5xxx/ddb5074.h
@@ -0,0 +1,38 @@
1/*
2 * include/asm-mips/ddb5074.h -- NEC DDB Vrc-5074 definitions
3 *
4 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
5 * Sony Software Development Center Europe (SDCE), Brussels
6 */
7
8#ifndef _ASM_DDB5XXX_DDB5074_H
9#define _ASM_DDB5XXX_DDB5074_H
10
11#include <asm/nile4.h>
12
13#define DDB_SDRAM_SIZE 0x04000000 /* 64MB */
14
15#define DDB_PCI_IO_BASE 0x06000000
16#define DDB_PCI_IO_SIZE 0x02000000 /* 32 MB */
17
18#define DDB_PCI_MEM_BASE 0x08000000
19#define DDB_PCI_MEM_SIZE 0x08000000 /* 128 MB */
20
21#define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE
22#define DDB_PCI_CONFIG_SIZE DDB_PCI_MEM_SIZE
23
24#define NILE4_PCI_IO_BASE 0xa6000000
25#define NILE4_PCI_MEM_BASE 0xa8000000
26#define NILE4_PCI_CFG_BASE NILE4_PCI_MEM_BASE
27#define DDB_PCI_IACK_BASE NILE4_PCI_IO_BASE
28
29#define NILE4_IRQ_BASE NUM_I8259_INTERRUPTS
30#define CPU_IRQ_BASE (NUM_NILE4_INTERRUPTS + NILE4_IRQ_BASE)
31#define CPU_NILE4_CASCADE 2
32
33extern void ddb5074_led_hex(int hex);
34extern void ddb5074_led_d2(int on);
35extern void ddb5074_led_d3(int on);
36
37extern void nile4_irq_setup(u32 base);
38#endif
diff --git a/include/asm-mips/ddb5xxx/ddb5476.h b/include/asm-mips/ddb5xxx/ddb5476.h
new file mode 100644
index 000000000000..4c23390d9354
--- /dev/null
+++ b/include/asm-mips/ddb5xxx/ddb5476.h
@@ -0,0 +1,157 @@
1/*
2 * header file specific for ddb5476
3 *
4 * Copyright (C) 2001 MontaVista Software Inc.
5 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14/*
15 * Memory map (physical address)
16 *
17 * Note most of the following address must be properly aligned by the
18 * corresponding size. For example, if PCI_IO_SIZE is 16MB, then
19 * PCI_IO_BASE must be aligned along 16MB boundary.
20 */
21#define DDB_SDRAM_BASE 0x00000000
22#define DDB_SDRAM_SIZE 0x04000000 /* 64MB */
23
24#define DDB_DCS3_BASE 0x04000000 /* flash 1 */
25#define DDB_DCS3_SIZE 0x01000000 /* 16MB */
26
27#define DDB_DCS2_BASE 0x05000000 /* flash 2 */
28#define DDB_DCS2_SIZE 0x01000000 /* 16MB */
29
30#define DDB_PCI_IO_BASE 0x06000000
31#define DDB_PCI_IO_SIZE 0x02000000 /* 32 MB */
32
33#define DDB_PCI_MEM_BASE 0x08000000
34#define DDB_PCI_MEM_SIZE 0x08000000 /* 128 MB */
35
36#define DDB_DCS5_BASE 0x13000000 /* DDB status regs */
37#define DDB_DCS5_SIZE 0x00200000 /* 2MB, 8-bit */
38
39#define DDB_DCS4_BASE 0x14000000 /* DDB control regs */
40#define DDB_DCS4_SIZE 0x00200000 /* 2MB, 8-bit */
41
42#define DDB_INTCS_BASE 0x1fa00000 /* VRC5476 control regs */
43#define DDB_INTCS_SIZE 0x00200000 /* 2MB */
44
45#define DDB_BOOTCS_BASE 0x1fc00000 /* Boot ROM / EPROM /Flash */
46#define DDB_BOOTCS_SIZE 0x00200000 /* 2 MB - doc says 4MB */
47
48
49/* aliases */
50#define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE
51#define DDB_PCI_CONFIG_SIZE DDB_PCI_MEM_SIZE
52
53/* PCI intr ack share PCIW0 with PCI IO */
54#define DDB_PCI_IACK_BASE DDB_PCI_IO_BASE
55
56/*
57 * Interrupt mapping
58 *
59 * We have three interrupt controllers:
60 *
61 * . CPU itself - 8 sources
62 * . i8259 - 16 sources
63 * . vrc5476 - 16 sources
64 *
65 * They connected as follows:
66 * all vrc5476 interrupts are routed to cpu IP2 (by software setting)
67 * all i2869 are routed to INTC in vrc5476 (by hardware connection)
68 *
69 * All VRC5476 PCI interrupts are level-triggered (no ack needed).
70 * All PCI irq but INTC are active low.
71 */
72
73/*
74 * irq number block assignment
75 */
76
77#define NUM_CPU_IRQ 8
78#define NUM_I8259_IRQ 16
79#define NUM_VRC5476_IRQ 16
80
81#define DDB_IRQ_BASE 0
82
83#define I8259_IRQ_BASE DDB_IRQ_BASE
84#define VRC5476_IRQ_BASE (I8259_IRQ_BASE + NUM_I8259_IRQ)
85#define CPU_IRQ_BASE (VRC5476_IRQ_BASE + NUM_VRC5476_IRQ)
86
87/*
88 * vrc5476 irq defs, see page 52-64 of Vrc5074 system controller manual
89 */
90
91#define VRC5476_IRQ_CPCE 0 /* cpu parity error */
92#define VRC5476_IRQ_CNTD 1 /* cpu no target */
93#define VRC5476_IRQ_MCE 2 /* memory check error */
94#define VRC5476_IRQ_DMA 3 /* DMA */
95#define VRC5476_IRQ_UART 4 /* vrc5476 builtin UART, not used */
96#define VRC5476_IRQ_WDOG 5 /* watchdog timer */
97#define VRC5476_IRQ_GPT 6 /* general purpose timer */
98#define VRC5476_IRQ_LBRT 7 /* local bus read timeout */
99#define VRC5476_IRQ_INTA 8 /* PCI INT #A */
100#define VRC5476_IRQ_INTB 9 /* PCI INT #B */
101#define VRC5476_IRQ_INTC 10 /* PCI INT #C */
102#define VRC5476_IRQ_INTD 11 /* PCI INT #D */
103#define VRC5476_IRQ_INTE 12 /* PCI INT #E */
104#define VRC5476_IRQ_RESERVED_13 13 /* reserved */
105#define VRC5476_IRQ_PCIS 14 /* PCI SERR # */
106#define VRC5476_IRQ_PCI 15 /* PCI internal error */
107
108/*
109 * i2859 irq assignment
110 */
111#define I8259_IRQ_RESERVED_0 0
112#define I8259_IRQ_KEYBOARD 1 /* M1543 default */
113#define I8259_IRQ_CASCADE 2
114#define I8259_IRQ_UART_B 3 /* M1543 default, may conflict with RTC according to schematic diagram */
115#define I8259_IRQ_UART_A 4 /* M1543 default */
116#define I8259_IRQ_PARALLEL 5 /* M1543 default */
117#define I8259_IRQ_RESERVED_6 6
118#define I8259_IRQ_RESERVED_7 7
119#define I8259_IRQ_RTC 8 /* who set this? */
120#define I8259_IRQ_USB 9 /* ddb_setup */
121#define I8259_IRQ_PMU 10 /* ddb_setup */
122#define I8259_IRQ_RESERVED_11 11
123#define I8259_IRQ_RESERVED_12 12 /* m1543_irq_setup */
124#define I8259_IRQ_RESERVED_13 13
125#define I8259_IRQ_HDC1 14 /* default and ddb_setup */
126#define I8259_IRQ_HDC2 15 /* default */
127
128
129/*
130 * misc
131 */
132#define VRC5476_I8259_CASCADE VRC5476_IRQ_INTC
133#define CPU_VRC5476_CASCADE 2
134
135#define is_i8259_irq(irq) ((irq) < NUM_I8259_IRQ)
136#define nile4_to_irq(n) ((n)+NUM_I8259_IRQ)
137#define irq_to_nile4(n) ((n)-NUM_I8259_IRQ)
138
139/*
140 * low-level irq functions
141 */
142#ifndef __ASSEMBLY__
143extern void nile4_map_irq(int nile4_irq, int cpu_irq);
144extern void nile4_map_irq_all(int cpu_irq);
145extern void nile4_enable_irq(int nile4_irq);
146extern void nile4_disable_irq(int nile4_irq);
147extern void nile4_disable_irq_all(void);
148extern u16 nile4_get_irq_stat(int cpu_irq);
149extern void nile4_enable_irq_output(int cpu_irq);
150extern void nile4_disable_irq_output(int cpu_irq);
151extern void nile4_set_pci_irq_polarity(int pci_irq, int high);
152extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level);
153extern void nile4_clear_irq(int nile4_irq);
154extern void nile4_clear_irq_mask(u32 mask);
155extern u8 nile4_i8259_iack(void);
156extern void nile4_dump_irq_status(void); /* Debug */
157#endif /* !__ASSEMBLY__ */
diff --git a/include/asm-mips/ddb5xxx/ddb5477.h b/include/asm-mips/ddb5xxx/ddb5477.h
new file mode 100644
index 000000000000..ae3e2a38fd5f
--- /dev/null
+++ b/include/asm-mips/ddb5xxx/ddb5477.h
@@ -0,0 +1,346 @@
1/***********************************************************************
2 *
3 * Copyright 2001 MontaVista Software Inc.
4 * Author: jsun@mvista.com or jsun@junsun.net
5 *
6 * include/asm-mips/ddb5xxx/ddb5477.h
7 * DDB 5477 specific definitions and macros.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 ***********************************************************************
15 */
16
17#ifndef __ASM_DDB5XXX_DDB5477_H
18#define __ASM_DDB5XXX_DDB5477_H
19
20#include <linux/config.h>
21
22/*
23 * This contains macros that are specific to DDB5477 or renamed from
24 * DDB5476.
25 */
26
27/*
28 * renamed PADRs
29 */
30#define DDB_LCS0 DDB_DCS2
31#define DDB_LCS1 DDB_DCS3
32#define DDB_LCS2 DDB_DCS4
33#define DDB_VRC5477 DDB_INTCS
34
35/*
36 * New CPU interface registers
37 */
38#define DDB_INTCTRL0 0x0400 /* Interrupt Control 0 */
39#define DDB_INTCTRL1 0x0404 /* Interrupt Control 1 */
40#define DDB_INTCTRL2 0x0408 /* Interrupt Control 2 */
41#define DDB_INTCTRL3 0x040c /* Interrupt Control 3 */
42
43#define DDB_INT0STAT 0x0420 /* INT0 Status [R] */
44#define DDB_INT1STAT 0x0428 /* INT1 Status [R] */
45#define DDB_INT2STAT 0x0430 /* INT2 Status [R] */
46#define DDB_INT3STAT 0x0438 /* INT3 Status [R] */
47#define DDB_INT4STAT 0x0440 /* INT4 Status [R] */
48#define DDB_NMISTAT 0x0450 /* NMI Status [R] */
49
50#define DDB_INTCLR32 0x0468 /* Interrupt Clear */
51
52#define DDB_INTPPES0 0x0470 /* PCI0 Interrupt Control */
53#define DDB_INTPPES1 0x0478 /* PCI1 Interrupt Control */
54
55#undef DDB_CPUSTAT /* duplicate in Vrc-5477 */
56#define DDB_CPUSTAT 0x0480 /* CPU Status [R] */
57#define DDB_BUSCTRL 0x0488 /* Internal Bus Control */
58
59
60/*
61 * Timer registers
62 */
63#define DDB_REFCTRL_L DDB_T0CTRL
64#define DDB_REFCTRL_H (DDB_T0CTRL+4)
65#define DDB_REFCNTR DDB_T0CNTR
66#define DDB_SPT0CTRL_L DDB_T1CTRL
67#define DDB_SPT0CTRL_H (DDB_T1CTRL+4)
68#define DDB_SPT1CTRL_L DDB_T2CTRL
69#define DDB_SPT1CTRL_H (DDB_T2CTRL+4)
70#define DDB_SPT1CNTR DDB_T1CTRL
71#define DDB_WDTCTRL_L DDB_T3CTRL
72#define DDB_WDTCTRL_H (DDB_T3CTRL+4)
73#define DDB_WDTCNTR DDB_T3CNTR
74
75/*
76 * DMA registers are moved. We don't care about it for now. TODO.
77 */
78
79/*
80 * BARs for ext PCI (PCI0)
81 */
82#undef DDB_BARC
83#undef DDB_BARB
84
85#define DDB_BARC0 0x0210 /* PCI0 Control */
86#define DDB_BARM010 0x0218 /* PCI0 SDRAM bank01 */
87#define DDB_BARM230 0x0220 /* PCI0 SDRAM bank23 */
88#define DDB_BAR00 0x0240 /* PCI0 LDCS0 */
89#define DDB_BAR10 0x0248 /* PCI0 LDCS1 */
90#define DDB_BAR20 0x0250 /* PCI0 LDCS2 */
91#define DDB_BAR30 0x0258 /* PCI0 LDCS3 */
92#define DDB_BAR40 0x0260 /* PCI0 LDCS4 */
93#define DDB_BAR50 0x0268 /* PCI0 LDCS5 */
94#define DDB_BARB0 0x0280 /* PCI0 BOOT */
95#define DDB_BARP00 0x0290 /* PCI0 for IOPCI Window0 */
96#define DDB_BARP10 0x0298 /* PCI0 for IOPCI Window1 */
97
98/*
99 * BARs for IOPIC (PCI1)
100 */
101#define DDB_BARC1 0x0610 /* PCI1 Control */
102#define DDB_BARM011 0x0618 /* PCI1 SDRAM bank01 */
103#define DDB_BARM231 0x0620 /* PCI1 SDRAM bank23 */
104#define DDB_BAR01 0x0640 /* PCI1 LDCS0 */
105#define DDB_BAR11 0x0648 /* PCI1 LDCS1 */
106#define DDB_BAR21 0x0650 /* PCI1 LDCS2 */
107#define DDB_BAR31 0x0658 /* PCI1 LDCS3 */
108#define DDB_BAR41 0x0660 /* PCI1 LDCS4 */
109#define DDB_BAR51 0x0668 /* PCI1 LDCS5 */
110#define DDB_BARB1 0x0680 /* PCI1 BOOT */
111#define DDB_BARP01 0x0690 /* PCI1 for ext PCI Window0 */
112#define DDB_BARP11 0x0698 /* PCI1 for ext PCI Window1 */
113
114/*
115 * Other registers for ext PCI (PCI0)
116 */
117#define DDB_PCIINIT00 0x02f0 /* PCI0 Initiator 0 */
118#define DDB_PCIINIT10 0x02f8 /* PCI0 Initiator 1 */
119
120#define DDB_PCISWP0 0x02b0 /* PCI0 Swap */
121#define DDB_PCIERR0 0x02b8 /* PCI0 Error */
122
123#define DDB_PCICTL0_L 0x02e0 /* PCI0 Control-L */
124#define DDB_PCICTL0_H 0x02e4 /* PCI0 Control-H */
125#define DDB_PCIARB0_L 0x02e8 /* PCI0 Arbitration-L */
126#define DDB_PCIARB0_H 0x02ec /* PCI0 Arbitration-H */
127
128/*
129 * Other registers for IOPCI (PCI1)
130 */
131#define DDB_IOPCIW0 0x00d0 /* PCI Address Window 0 [R/W] */
132#define DDB_IOPCIW1 0x00d8 /* PCI Address Window 1 [R/W] */
133
134#define DDB_PCIINIT01 0x06f0 /* PCI1 Initiator 0 */
135#define DDB_PCIINIT11 0x06f8 /* PCI1 Initiator 1 */
136
137#define DDB_PCISWP1 0x06b0 /* PCI1 Swap */
138#define DDB_PCIERR1 0x06b8 /* PCI1 Error */
139
140#define DDB_PCICTL1_L 0x06e0 /* PCI1 Control-L */
141#define DDB_PCICTL1_H 0x06e4 /* PCI1 Control-H */
142#define DDB_PCIARB1_L 0x06e8 /* PCI1 Arbitration-L */
143#define DDB_PCIARB1_H 0x06ec /* PCI1 Arbitration-H */
144
145/*
146 * Local Bus
147 */
148#define DDB_LCST0 0x0110 /* LB Chip Select Timing 0 */
149#define DDB_LCST1 0x0118 /* LB Chip Select Timing 1 */
150#undef DDB_LCST2
151#define DDB_LCST2 0x0120 /* LB Chip Select Timing 2 */
152#undef DDB_LCST3
153#undef DDB_LCST4
154#undef DDB_LCST5
155#undef DDB_LCST6
156#undef DDB_LCST7
157#undef DDB_LCST8
158#define DDB_ERRADR 0x0150 /* Error Address Register */
159#define DDB_ERRCS 0x0160
160#define DDB_BTM 0x0170 /* Boot Time Mode value */
161
162/*
163 * MISC registers
164 */
165#define DDB_GIUFUNSEL 0x4040 /* select dual-func pins */
166#define DDB_PIBMISC 0x0750 /* USB buffer enable / power saving */
167
168/*
169 * Memory map (physical address)
170 *
171 * Note most of the following address must be properly aligned by the
172 * corresponding size. For example, if PCI_IO_SIZE is 16MB, then
173 * PCI_IO_BASE must be aligned along 16MB boundary.
174 */
175
176/* the actual ram size is detected at run-time */
177#define DDB_SDRAM_BASE 0x00000000
178#define DDB_MAX_SDRAM_SIZE 0x08000000 /* less than 128MB */
179
180#define DDB_PCI0_MEM_BASE 0x08000000
181#define DDB_PCI0_MEM_SIZE 0x08000000 /* 128 MB */
182
183#define DDB_PCI1_MEM_BASE 0x10000000
184#define DDB_PCI1_MEM_SIZE 0x08000000 /* 128 MB */
185
186#define DDB_PCI0_CONFIG_BASE 0x18000000
187#define DDB_PCI0_CONFIG_SIZE 0x01000000 /* 16 MB */
188
189#define DDB_PCI1_CONFIG_BASE 0x19000000
190#define DDB_PCI1_CONFIG_SIZE 0x01000000 /* 16 MB */
191
192#define DDB_PCI_IO_BASE 0x1a000000 /* we concatenate two IOs */
193#define DDB_PCI0_IO_BASE 0x1a000000
194#define DDB_PCI0_IO_SIZE 0x01000000 /* 16 MB */
195#define DDB_PCI1_IO_BASE 0x1b000000
196#define DDB_PCI1_IO_SIZE 0x01000000 /* 16 MB */
197
198#define DDB_LCS0_BASE 0x1c000000 /* flash memory */
199#define DDB_LCS0_SIZE 0x01000000 /* 16 MB */
200
201#define DDB_LCS1_BASE 0x1d000000 /* misc */
202#define DDB_LCS1_SIZE 0x01000000 /* 16 MB */
203
204#define DDB_LCS2_BASE 0x1e000000 /* Mezzanine */
205#define DDB_LCS2_SIZE 0x01000000 /* 16 MB */
206
207#define DDB_VRC5477_BASE 0x1fa00000 /* VRC5477 control regs */
208#define DDB_VRC5477_SIZE 0x00200000 /* 2MB */
209
210#define DDB_BOOTCS_BASE 0x1fc00000 /* Boot ROM / EPROM /Flash */
211#define DDB_BOOTCS_SIZE 0x00200000 /* 2 MB - doc says 4MB */
212
213#define DDB_LED DDB_LCS1_BASE + 0x10000
214
215
216/*
217 * DDB5477 specific functions
218 */
219#ifndef __ASSEMBLY__
220extern void ddb5477_irq_setup(void);
221
222/* route irq to cpu int pin */
223extern void ll_vrc5477_irq_route(int vrc5477_irq, int ip);
224
225/* low-level routine for enabling vrc5477 irq, bypassing high-level */
226extern void ll_vrc5477_irq_enable(int vrc5477_irq);
227extern void ll_vrc5477_irq_disable(int vrc5477_irq);
228#endif /* !__ASSEMBLY__ */
229
230/* PCI intr ack share PCIW0 with PCI IO */
231#define DDB_PCI_IACK_BASE DDB_PCI_IO_BASE
232
233/*
234 * Interrupt mapping
235 *
236 * We have three interrupt controllers:
237 *
238 * . CPU itself - 8 sources
239 * . i8259 - 16 sources
240 * . vrc5477 - 32 sources
241 *
242 * They connected as follows:
243 * all vrc5477 interrupts are routed to cpu IP2 (by software setting)
244 * all i8359 are routed to INTC in vrc5477 (by hardware connection)
245 *
246 * All VRC5477 PCI interrupts are level-triggered (no ack needed).
247 * All PCI irq but INTC are active low.
248 */
249
250/*
251 * irq number block assignment
252 */
253
254#define NUM_CPU_IRQ 8
255#define NUM_I8259_IRQ 16
256#define NUM_VRC5477_IRQ 32
257
258#define DDB_IRQ_BASE 0
259
260#define I8259_IRQ_BASE DDB_IRQ_BASE
261#define VRC5477_IRQ_BASE (I8259_IRQ_BASE + NUM_I8259_IRQ)
262#define CPU_IRQ_BASE (VRC5477_IRQ_BASE + NUM_VRC5477_IRQ)
263
264/*
265 * vrc5477 irq defs
266 */
267
268#define VRC5477_IRQ_CPCE (0 + VRC5477_IRQ_BASE) /* cpu parity error */
269#define VRC5477_IRQ_CNTD (1 + VRC5477_IRQ_BASE) /* cpu no target */
270#define VRC5477_IRQ_I2C (2 + VRC5477_IRQ_BASE) /* I2C */
271#define VRC5477_IRQ_DMA (3 + VRC5477_IRQ_BASE) /* DMA */
272#define VRC5477_IRQ_UART0 (4 + VRC5477_IRQ_BASE)
273#define VRC5477_IRQ_WDOG (5 + VRC5477_IRQ_BASE) /* watchdog timer */
274#define VRC5477_IRQ_SPT1 (6 + VRC5477_IRQ_BASE) /* special purpose timer 1 */
275#define VRC5477_IRQ_LBRT (7 + VRC5477_IRQ_BASE) /* local bus read timeout */
276#define VRC5477_IRQ_INTA (8 + VRC5477_IRQ_BASE) /* PCI INT #A */
277#define VRC5477_IRQ_INTB (9 + VRC5477_IRQ_BASE) /* PCI INT #B */
278#define VRC5477_IRQ_INTC (10 + VRC5477_IRQ_BASE) /* PCI INT #C */
279#define VRC5477_IRQ_INTD (11 + VRC5477_IRQ_BASE) /* PCI INT #D */
280#define VRC5477_IRQ_INTE (12 + VRC5477_IRQ_BASE) /* PCI INT #E */
281#define VRC5477_IRQ_RESERVED_13 (13 + VRC5477_IRQ_BASE) /* reserved */
282#define VRC5477_IRQ_PCIS (14 + VRC5477_IRQ_BASE) /* PCI SERR # */
283#define VRC5477_IRQ_PCI (15 + VRC5477_IRQ_BASE) /* PCI internal error */
284#define VRC5477_IRQ_IOPCI_INTA (16 + VRC5477_IRQ_BASE) /* USB-H */
285#define VRC5477_IRQ_IOPCI_INTB (17 + VRC5477_IRQ_BASE) /* USB-P */
286#define VRC5477_IRQ_IOPCI_INTC (18 + VRC5477_IRQ_BASE) /* AC97 */
287#define VRC5477_IRQ_IOPCI_INTD (19 + VRC5477_IRQ_BASE) /* Reserved */
288#define VRC5477_IRQ_UART1 (20 + VRC5477_IRQ_BASE)
289#define VRC5477_IRQ_SPT0 (21 + VRC5477_IRQ_BASE) /* special purpose timer 0 */
290#define VRC5477_IRQ_GPT0 (22 + VRC5477_IRQ_BASE) /* general purpose timer 0 */
291#define VRC5477_IRQ_GPT1 (23 + VRC5477_IRQ_BASE) /* general purpose timer 1 */
292#define VRC5477_IRQ_GPT2 (24 + VRC5477_IRQ_BASE) /* general purpose timer 2 */
293#define VRC5477_IRQ_GPT3 (25 + VRC5477_IRQ_BASE) /* general purpose timer 3 */
294#define VRC5477_IRQ_GPIO (26 + VRC5477_IRQ_BASE)
295#define VRC5477_IRQ_SIO0 (27 + VRC5477_IRQ_BASE)
296#define VRC5477_IRQ_SIO1 (28 + VRC5477_IRQ_BASE)
297#define VRC5477_IRQ_RESERVED_29 (29 + VRC5477_IRQ_BASE) /* reserved */
298#define VRC5477_IRQ_IOPCISERR (30 + VRC5477_IRQ_BASE) /* IO PCI SERR # */
299#define VRC5477_IRQ_IOPCI (31 + VRC5477_IRQ_BASE)
300
301/*
302 * i2859 irq assignment
303 */
304#define I8259_IRQ_RESERVED_0 (0 + I8259_IRQ_BASE)
305#define I8259_IRQ_KEYBOARD (1 + I8259_IRQ_BASE) /* M1543 default */
306#define I8259_IRQ_CASCADE (2 + I8259_IRQ_BASE)
307#define I8259_IRQ_UART_B (3 + I8259_IRQ_BASE) /* M1543 default, may conflict with RTC according to schematic diagram */
308#define I8259_IRQ_UART_A (4 + I8259_IRQ_BASE) /* M1543 default */
309#define I8259_IRQ_PARALLEL (5 + I8259_IRQ_BASE) /* M1543 default */
310#define I8259_IRQ_RESERVED_6 (6 + I8259_IRQ_BASE)
311#define I8259_IRQ_RESERVED_7 (7 + I8259_IRQ_BASE)
312#define I8259_IRQ_RTC (8 + I8259_IRQ_BASE) /* who set this? */
313#define I8259_IRQ_USB (9 + I8259_IRQ_BASE) /* ddb_setup */
314#define I8259_IRQ_PMU (10 + I8259_IRQ_BASE) /* ddb_setup */
315#define I8259_IRQ_RESERVED_11 (11 + I8259_IRQ_BASE)
316#define I8259_IRQ_RESERVED_12 (12 + I8259_IRQ_BASE) /* m1543_irq_setup */
317#define I8259_IRQ_RESERVED_13 (13 + I8259_IRQ_BASE)
318#define I8259_IRQ_HDC1 (14 + I8259_IRQ_BASE) /* default and ddb_setup */
319#define I8259_IRQ_HDC2 (15 + I8259_IRQ_BASE) /* default */
320
321
322/*
323 * misc
324 */
325#define VRC5477_I8259_CASCADE (VRC5477_IRQ_INTC - VRC5477_IRQ_BASE)
326#define CPU_VRC5477_CASCADE 2
327
328/*
329 * debug routines
330 */
331#ifndef __ASSEMBLY__
332#if defined(CONFIG_RUNTIME_DEBUG)
333extern void vrc5477_show_pdar_regs(void);
334extern void vrc5477_show_pci_regs(void);
335extern void vrc5477_show_bar_regs(void);
336extern void vrc5477_show_int_regs(void);
337extern void vrc5477_show_all_regs(void);
338#endif
339
340/*
341 * RAM size
342 */
343extern int board_ram_size;
344#endif /* !__ASSEMBLY__ */
345
346#endif /* __ASM_DDB5XXX_DDB5477_H */
diff --git a/include/asm-mips/ddb5xxx/ddb5xxx.h b/include/asm-mips/ddb5xxx/ddb5xxx.h
new file mode 100644
index 000000000000..873c03f2c5fe
--- /dev/null
+++ b/include/asm-mips/ddb5xxx/ddb5xxx.h
@@ -0,0 +1,273 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: jsun@mvista.com or jsun@junsun.net
4 *
5 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
6 * Sony Software Development Center Europe (SDCE), Brussels
7 *
8 * include/asm-mips/ddb5xxx/ddb5xxx.h
9 * Common header for all NEC DDB 5xxx boards, including 5074, 5476, 5477.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17
18#ifndef __ASM_DDB5XXX_DDB5XXX_H
19#define __ASM_DDB5XXX_DDB5XXX_H
20
21#include <linux/config.h>
22#include <linux/types.h>
23
24/*
25 * This file is based on the following documentation:
26 *
27 * NEC Vrc 5074 System Controller Data Sheet, June 1998
28 *
29 * [jsun] It is modified so that this file only contains the macros
30 * that are true for all DDB 5xxx boards. The modification is based on
31 *
32 * uPD31577(VRC5477) VR5432-SDRAM/PCI Bridge (Luke)
33 * Preliminary Specification Decoment, Rev 1.1, 27 Dec, 2000
34 *
35 */
36
37
38#define DDB_BASE 0xbfa00000
39#define DDB_SIZE 0x00200000 /* 2 MB */
40
41
42/*
43 * Physical Device Address Registers (PDARs)
44 */
45
46#define DDB_SDRAM0 0x0000 /* SDRAM Bank 0 [R/W] */
47#define DDB_SDRAM1 0x0008 /* SDRAM Bank 1 [R/W] */
48#define DDB_DCS2 0x0010 /* Device Chip-Select 2 [R/W] */
49#define DDB_DCS3 0x0018 /* Device Chip-Select 3 [R/W] */
50#define DDB_DCS4 0x0020 /* Device Chip-Select 4 [R/W] */
51#define DDB_DCS5 0x0028 /* Device Chip-Select 5 [R/W] */
52#define DDB_DCS6 0x0030 /* Device Chip-Select 6 [R/W] */
53#define DDB_DCS7 0x0038 /* Device Chip-Select 7 [R/W] */
54#define DDB_DCS8 0x0040 /* Device Chip-Select 8 [R/W] */
55#define DDB_PCIW0 0x0060 /* PCI Address Window 0 [R/W] */
56#define DDB_PCIW1 0x0068 /* PCI Address Window 1 [R/W] */
57#define DDB_INTCS 0x0070 /* Controller Internal Registers and Devices */
58 /* [R/W] */
59#define DDB_BOOTCS 0x0078 /* Boot ROM Chip-Select [R/W] */
60/* Vrc5477 has two more, IOPCIW0, IOPCIW1 */
61
62/*
63 * CPU Interface Registers
64 */
65#define DDB_CPUSTAT 0x0080 /* CPU Status [R/W] */
66#define DDB_INTCTRL 0x0088 /* Interrupt Control [R/W] */
67#define DDB_INTSTAT0 0x0090 /* Interrupt Status 0 [R] */
68#define DDB_INTSTAT1 0x0098 /* Interrupt Status 1 and CPU Interrupt */
69 /* Enable [R/W] */
70#define DDB_INTCLR 0x00A0 /* Interrupt Clear [R/W] */
71#define DDB_INTPPES 0x00A8 /* PCI Interrupt Control [R/W] */
72
73
74/*
75 * Memory-Interface Registers
76 */
77#define DDB_MEMCTRL 0x00C0 /* Memory Control */
78#define DDB_ACSTIME 0x00C8 /* Memory Access Timing [R/W] */
79#define DDB_CHKERR 0x00D0 /* Memory Check Error Status [R] */
80
81
82/*
83 * PCI-Bus Registers
84 */
85#define DDB_PCICTRL 0x00E0 /* PCI Control [R/W] */
86#define DDB_PCIARB 0x00E8 /* PCI Arbiter [R/W] */
87#define DDB_PCIINIT0 0x00F0 /* PCI Master (Initiator) 0 [R/W] */
88#define DDB_PCIINIT1 0x00F8 /* PCI Master (Initiator) 1 [R/W] */
89#define DDB_PCIERR 0x00B8 /* PCI Error [R/W] */
90
91
92/*
93 * Local-Bus Registers
94 */
95#define DDB_LCNFG 0x0100 /* Local Bus Configuration [R/W] */
96#define DDB_LCST2 0x0110 /* Local Bus Chip-Select Timing 2 [R/W] */
97#define DDB_LCST3 0x0118 /* Local Bus Chip-Select Timing 3 [R/W] */
98#define DDB_LCST4 0x0120 /* Local Bus Chip-Select Timing 4 [R/W] */
99#define DDB_LCST5 0x0128 /* Local Bus Chip-Select Timing 5 [R/W] */
100#define DDB_LCST6 0x0130 /* Local Bus Chip-Select Timing 6 [R/W] */
101#define DDB_LCST7 0x0138 /* Local Bus Chip-Select Timing 7 [R/W] */
102#define DDB_LCST8 0x0140 /* Local Bus Chip-Select Timing 8 [R/W] */
103#define DDB_DCSFN 0x0150 /* Device Chip-Select Muxing and Output */
104 /* Enables [R/W] */
105#define DDB_DCSIO 0x0158 /* Device Chip-Selects As I/O Bits [R/W] */
106#define DDB_BCST 0x0178 /* Local Boot Chip-Select Timing [R/W] */
107
108
109/*
110 * DMA Registers
111 */
112#define DDB_DMACTRL0 0x0180 /* DMA Control 0 [R/W] */
113#define DDB_DMASRCA0 0x0188 /* DMA Source Address 0 [R/W] */
114#define DDB_DMADESA0 0x0190 /* DMA Destination Address 0 [R/W] */
115#define DDB_DMACTRL1 0x0198 /* DMA Control 1 [R/W] */
116#define DDB_DMASRCA1 0x01A0 /* DMA Source Address 1 [R/W] */
117#define DDB_DMADESA1 0x01A8 /* DMA Destination Address 1 [R/W] */
118
119
120/*
121 * Timer Registers
122 */
123#define DDB_T0CTRL 0x01C0 /* SDRAM Refresh Control [R/W] */
124#define DDB_T0CNTR 0x01C8 /* SDRAM Refresh Counter [R/W] */
125#define DDB_T1CTRL 0x01D0 /* CPU-Bus Read Time-Out Control [R/W] */
126#define DDB_T1CNTR 0x01D8 /* CPU-Bus Read Time-Out Counter [R/W] */
127#define DDB_T2CTRL 0x01E0 /* General-Purpose Timer Control [R/W] */
128#define DDB_T2CNTR 0x01E8 /* General-Purpose Timer Counter [R/W] */
129#define DDB_T3CTRL 0x01F0 /* Watchdog Timer Control [R/W] */
130#define DDB_T3CNTR 0x01F8 /* Watchdog Timer Counter [R/W] */
131
132
133/*
134 * PCI Configuration Space Registers
135 */
136#define DDB_PCI_BASE 0x0200
137
138#define DDB_VID 0x0200 /* PCI Vendor ID [R] */
139#define DDB_DID 0x0202 /* PCI Device ID [R] */
140#define DDB_PCICMD 0x0204 /* PCI Command [R/W] */
141#define DDB_PCISTS 0x0206 /* PCI Status [R/W] */
142#define DDB_REVID 0x0208 /* PCI Revision ID [R] */
143#define DDB_CLASS 0x0209 /* PCI Class Code [R] */
144#define DDB_CLSIZ 0x020C /* PCI Cache Line Size [R/W] */
145#define DDB_MLTIM 0x020D /* PCI Latency Timer [R/W] */
146#define DDB_HTYPE 0x020E /* PCI Header Type [R] */
147#define DDB_BIST 0x020F /* BIST [R] (unimplemented) */
148#define DDB_BARC 0x0210 /* PCI Base Address Register Control [R/W] */
149#define DDB_BAR0 0x0218 /* PCI Base Address Register 0 [R/W] */
150#define DDB_BAR1 0x0220 /* PCI Base Address Register 1 [R/W] */
151#define DDB_CIS 0x0228 /* PCI Cardbus CIS Pointer [R] */
152 /* (unimplemented) */
153#define DDB_SSVID 0x022C /* PCI Sub-System Vendor ID [R/W] */
154#define DDB_SSID 0x022E /* PCI Sub-System ID [R/W] */
155#define DDB_ROM 0x0230 /* Expansion ROM Base Address [R] */
156 /* (unimplemented) */
157#define DDB_INTLIN 0x023C /* PCI Interrupt Line [R/W] */
158#define DDB_INTPIN 0x023D /* PCI Interrupt Pin [R] */
159#define DDB_MINGNT 0x023E /* PCI Min_Gnt [R] (unimplemented) */
160#define DDB_MAXLAT 0x023F /* PCI Max_Lat [R] (unimplemented) */
161#define DDB_BAR2 0x0240 /* PCI Base Address Register 2 [R/W] */
162#define DDB_BAR3 0x0248 /* PCI Base Address Register 3 [R/W] */
163#define DDB_BAR4 0x0250 /* PCI Base Address Register 4 [R/W] */
164#define DDB_BAR5 0x0258 /* PCI Base Address Register 5 [R/W] */
165#define DDB_BAR6 0x0260 /* PCI Base Address Register 6 [R/W] */
166#define DDB_BAR7 0x0268 /* PCI Base Address Register 7 [R/W] */
167#define DDB_BAR8 0x0270 /* PCI Base Address Register 8 [R/W] */
168#define DDB_BARB 0x0278 /* PCI Base Address Register BOOT [R/W] */
169
170
171/*
172 * Nile 4 Register Access
173 */
174
175static inline void ddb_sync(void)
176{
177/* The DDB5074 doesn't seem to like these accesses. They kill the board on
178 * interrupt load
179 */
180#ifndef CONFIG_DDB5074
181 volatile u32 *p = (volatile u32 *)0xbfc00000;
182 (void)(*p);
183#endif
184}
185
186static inline void ddb_out32(u32 offset, u32 val)
187{
188 *(volatile u32 *)(DDB_BASE+offset) = val;
189 ddb_sync();
190}
191
192static inline u32 ddb_in32(u32 offset)
193{
194 u32 val = *(volatile u32 *)(DDB_BASE+offset);
195 ddb_sync();
196 return val;
197}
198
199static inline void ddb_out16(u32 offset, u16 val)
200{
201 *(volatile u16 *)(DDB_BASE+offset) = val;
202 ddb_sync();
203}
204
205static inline u16 ddb_in16(u32 offset)
206{
207 u16 val = *(volatile u16 *)(DDB_BASE+offset);
208 ddb_sync();
209 return val;
210}
211
212static inline void ddb_out8(u32 offset, u8 val)
213{
214 *(volatile u8 *)(DDB_BASE+offset) = val;
215 ddb_sync();
216}
217
218static inline u8 ddb_in8(u32 offset)
219{
220 u8 val = *(volatile u8 *)(DDB_BASE+offset);
221 ddb_sync();
222 return val;
223}
224
225
226/*
227 * Physical Device Address Registers
228 */
229
230extern u32
231ddb_calc_pdar(u32 phys, u32 size, int width, int on_memory_bus, int pci_visible);
232extern void
233ddb_set_pdar(u32 pdar, u32 phys, u32 size, int width,
234 int on_memory_bus, int pci_visible);
235
236/*
237 * PCI Master Registers
238 */
239
240#define DDB_PCICMD_IACK 0 /* PCI Interrupt Acknowledge */
241#define DDB_PCICMD_IO 1 /* PCI I/O Space */
242#define DDB_PCICMD_MEM 3 /* PCI Memory Space */
243#define DDB_PCICMD_CFG 5 /* PCI Configuration Space */
244
245/*
246 * additional options for pci init reg (no shifting needed)
247 */
248#define DDB_PCI_CFGTYPE1 0x200 /* for pci init0/1 regs */
249#define DDB_PCI_ACCESS_32 0x10 /* for pci init0/1 regs */
250
251
252extern void ddb_set_pmr(u32 pmr, u32 type, u32 addr, u32 options);
253
254/*
255 * we need to reset pci bus when we start up and shutdown
256 */
257extern void ddb_pci_reset_bus(void);
258
259
260/*
261 * include the board dependent part
262 */
263#if defined(CONFIG_DDB5074)
264#include <asm/ddb5xxx/ddb5074.h>
265#elif defined(CONFIG_DDB5476)
266#include <asm/ddb5xxx/ddb5476.h>
267#elif defined(CONFIG_DDB5477)
268#include <asm/ddb5xxx/ddb5477.h>
269#else
270#error "Unknown DDB board!"
271#endif
272
273#endif /* __ASM_DDB5XXX_DDB5XXX_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-21 10:40:49 -0500