[MIPS] Use the proper technical term for naming some of the cache macros.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 1 insertions, 1 deletions

diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index dff2a0a52f8f..d38fdbf845b2 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -242,7 +242,7 @@
 #define MIPS_CPU_EJTAG          0x00008000 /* EJTAG exception */
 #define MIPS_CPU_NOFPUEX        0x00010000 /* no FPU exception */
 #define MIPS_CPU_LLSC           0x00020000 /* CPU has ll/sc instructions */
-#define MIPS_CPU_SUBSET_CACHES  0x00040000 /* P-cache subset enforced */
+#define MIPS_CPU_INCLUSIVE_CACHES       0x00040000 /* P-cache subset enforced */
 #define MIPS_CPU_PREFETCH       0x00080000 /* CPU has usable prefetch */
 #define MIPS_CPU_VINT           0x00100000 /* CPU supports MIPSR2 vectored interrupts */
 #define MIPS_CPU_VEIC           0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */