Detect the MIPS R2 vectored interrupt, external interrupt controller

options and the precense of the MT ASE.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 4 insertions, 0 deletions

diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index e6927442f7b4..3bbb6431d218 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -227,6 +227,8 @@
 #define MIPS_CPU_LLSC           0x00010000 /* CPU has ll/sc instructions */
 #define MIPS_CPU_SUBSET_CACHES  0x00020000 /* P-cache subset enforced */
 #define MIPS_CPU_PREFETCH       0x00040000 /* CPU has usable prefetch */
+#define MIPS_CPU_VINT           0x00080000 /* CPU supports MIPSR2 vectored interrupts */
+#define MIPS_CPU_VEIC           0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
 
 /*
  * CPU ASE encodings
@@ -236,5 +238,7 @@
 #define MIPS_ASE_MIPS3D         0x00000004 /* MIPS-3D */
 #define MIPS_ASE_SMARTMIPS      0x00000008 /* SmartMIPS */
 #define MIPS_ASE_DSP            0x00000010 /* Signal Processing ASE */
+#define MIPS_ASE_MIPSMT         0x00000020 /* CPU supports MIPS MT */
+
 
 #endif /* _ASM_CPU_H */