[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.

It may not be perfect yet but the SB1 code is badly borken and has
horrible performance issues.

Downside: This seriously breaks support for pass 1 parts of the BCM1250
where indexed cacheops don't work quite reliable but I seem to be the
last one on the planet with a pass 1 part anyway.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 17 insertions, 18 deletions

diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index d67f43b09964..107ccbeee294 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -255,24 +255,23 @@
 #define MIPS_CPU_3K_CACHE       0x00000004 /* R3000-style caches */
 #define MIPS_CPU_4K_CACHE       0x00000008 /* R4000-style caches */
 #define MIPS_CPU_TX39_CACHE     0x00000010 /* TX3900-style caches */
-#define MIPS_CPU_SB1_CACHE      0x00000020 /* SB1-style caches */
-#define MIPS_CPU_FPU            0x00000040 /* CPU has FPU */
-#define MIPS_CPU_32FPR          0x00000080 /* 32 dbl. prec. FP registers */
-#define MIPS_CPU_COUNTER        0x00000100 /* Cycle count/compare */
-#define MIPS_CPU_WATCH          0x00000200 /* watchpoint registers */
-#define MIPS_CPU_DIVEC          0x00000400 /* dedicated interrupt vector */
-#define MIPS_CPU_VCE            0x00000800 /* virt. coherence conflict possible */
-#define MIPS_CPU_CACHE_CDEX_P   0x00001000 /* Create_Dirty_Exclusive CACHE op */
-#define MIPS_CPU_CACHE_CDEX_S   0x00002000 /* ... same for seconary cache ... */
-#define MIPS_CPU_MCHECK         0x00004000 /* Machine check exception */
-#define MIPS_CPU_EJTAG          0x00008000 /* EJTAG exception */
-#define MIPS_CPU_NOFPUEX        0x00010000 /* no FPU exception */
-#define MIPS_CPU_LLSC           0x00020000 /* CPU has ll/sc instructions */
-#define MIPS_CPU_INCLUSIVE_CACHES       0x00040000 /* P-cache subset enforced */
-#define MIPS_CPU_PREFETCH       0x00080000 /* CPU has usable prefetch */
-#define MIPS_CPU_VINT           0x00100000 /* CPU supports MIPSR2 vectored interrupts */
-#define MIPS_CPU_VEIC           0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */
-#define MIPS_CPU_ULRI           0x00400000 /* CPU has ULRI feature */
+#define MIPS_CPU_FPU            0x00000020 /* CPU has FPU */
+#define MIPS_CPU_32FPR          0x00000040 /* 32 dbl. prec. FP registers */
+#define MIPS_CPU_COUNTER        0x00000080 /* Cycle count/compare */
+#define MIPS_CPU_WATCH          0x00000100 /* watchpoint registers */
+#define MIPS_CPU_DIVEC          0x00000200 /* dedicated interrupt vector */
+#define MIPS_CPU_VCE            0x00000400 /* virt. coherence conflict possible */
+#define MIPS_CPU_CACHE_CDEX_P   0x00000800 /* Create_Dirty_Exclusive CACHE op */
+#define MIPS_CPU_CACHE_CDEX_S   0x00001000 /* ... same for seconary cache ... */
+#define MIPS_CPU_MCHECK         0x00002000 /* Machine check exception */
+#define MIPS_CPU_EJTAG          0x00004000 /* EJTAG exception */
+#define MIPS_CPU_NOFPUEX        0x00008000 /* no FPU exception */
+#define MIPS_CPU_LLSC           0x00010000 /* CPU has ll/sc instructions */
+#define MIPS_CPU_INCLUSIVE_CACHES       0x00020000 /* P-cache subset enforced */
+#define MIPS_CPU_PREFETCH       0x00040000 /* CPU has usable prefetch */
+#define MIPS_CPU_VINT           0x00080000 /* CPU supports MIPSR2 vectored interrupts */
+#define MIPS_CPU_VEIC           0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
+#define MIPS_CPU_ULRI           0x00200000 /* CPU has ULRI feature */
 
 /*
  * CPU ASE encodings