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authorRalf Baechle <ralf@linux-mips.org>2007-07-10 12:33:02 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-07-10 12:33:02 -0400
commita36920200c5b89d56120a5e839fe4a603d51b16c (patch)
treeaefb1fc4b0792ef788024fa596954a5689f15d0a /include/asm-mips/cpu.h
parentd223a86154f8c66f5a380b17e1c8091d56f47cf8 (diff)
[MIPS] Enable support for the userlocal hardware register
Which will cut down the cost of RDHWR $29 which is used to obtain the TLS pointer and so far being emulated in software down to a single cycle operation. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/cpu.h')
-rw-r--r--include/asm-mips/cpu.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index 2924069075e0..49c1f0011863 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -257,6 +257,7 @@
257#define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */ 257#define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */
258#define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */ 258#define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */
259#define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */ 259#define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */
260#define MIPS_CPU_ULRI 0x00400000 /* CPU has ULRI feature */
260 261
261/* 262/*
262 * CPU ASE encodings 263 * CPU ASE encodings