[MIPS] local_r4k_flush_cache_page fix

    
If dcache_size != icache_size or dcache_size != scache_size, or
set-associative cache, icache/scache does not flushed properly.  Make
blast_?cache_page_indexed() masks its index value correctly.  Also,
use physical address for physically indexed pcache/scache.
    
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 1 insertions, 0 deletions

diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h
index d5cf519f8fcc..140be1c67da7 100644
--- a/include/asm-mips/cpu-info.h
+++ b/include/asm-mips/cpu-info.h
@@ -39,6 +39,7 @@ struct cache_desc {
 #define MIPS_CACHE_ALIASES      0x00000004      /* Cache could have aliases */
 #define MIPS_CACHE_IC_F_DC      0x00000008      /* Ic can refill from D-cache */
 #define MIPS_IC_SNOOPS_REMOTE   0x00000010      /* Ic snoops remote stores */
+#define MIPS_CACHE_PINDEX       0x00000020      /* Physically indexed cache */
 
 struct cpuinfo_mips {
         unsigned long           udelay_val;