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authorRalf Baechle <ralf@ongar.mips.com>2005-12-09 07:20:49 -0500
committer <ralf@denk.linux-mips.net>2006-01-10 08:39:07 -0500
commit0401572a9b9b2f368176b6e53f53004fd048a566 (patch)
treeac150d269955aeba9eff5bdaa2835626510c9180 /include/asm-mips/cpu-features.h
parent11e6df65dc2bae8e7ad17ff81611ddc850b279cd (diff)
MIPS: Reorganize ISA constants strictly as bitmasks.
Signed-off-by: Ralf Baechle <ralf@ongar.mips.com>
Diffstat (limited to 'include/asm-mips/cpu-features.h')
-rw-r--r--include/asm-mips/cpu-features.h45
1 files changed, 21 insertions, 24 deletions
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h
index f8be4a470754..78c9cc2735d5 100644
--- a/include/asm-mips/cpu-features.h
+++ b/include/asm-mips/cpu-features.h
@@ -116,6 +116,27 @@
116#endif 116#endif
117#endif 117#endif
118 118
119# ifndef cpu_has_mips32r1
120# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
121# endif
122# ifndef cpu_has_mips32r2
123# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
124# endif
125# ifndef cpu_has_mips64r1
126# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
127# endif
128# ifndef cpu_has_mips64r2
129# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
130# endif
131
132/*
133 * Shortcuts ...
134 */
135#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2)
136#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2)
137#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
138#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
139
119#ifndef cpu_has_dsp 140#ifndef cpu_has_dsp
120#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) 141#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
121#endif 142#endif
@@ -144,18 +165,6 @@
144# ifndef cpu_has_64bit_addresses 165# ifndef cpu_has_64bit_addresses
145# define cpu_has_64bit_addresses 0 166# define cpu_has_64bit_addresses 0
146# endif 167# endif
147# ifndef cpu_has_mips32r1
148# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
149# endif
150# ifndef cpu_has_mips32r2
151# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
152# endif
153# ifndef cpu_has_mips64r1
154# define cpu_has_mips64r1 0
155# endif
156# ifndef cpu_has_mips64r2
157# define cpu_has_mips64r2 0
158# endif
159#endif 168#endif
160 169
161#ifdef CONFIG_64BIT 170#ifdef CONFIG_64BIT
@@ -174,18 +183,6 @@
174# ifndef cpu_has_64bit_addresses 183# ifndef cpu_has_64bit_addresses
175# define cpu_has_64bit_addresses 1 184# define cpu_has_64bit_addresses 1
176# endif 185# endif
177# ifndef cpu_has_mips32r1
178# define cpu_has_mips32r1 0
179# endif
180# ifndef cpu_has_mips32r2
181# define cpu_has_mips32r2 0
182# endif
183# ifndef cpu_has_mips64r1
184# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
185# endif
186# ifndef cpu_has_mips64r2
187# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
188# endif
189#endif 186#endif
190 187
191#ifdef CONFIG_CPU_MIPSR2 188#ifdef CONFIG_CPU_MIPSR2