aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-mips/cpu-features.h
diff options
context:
space:
mode:
authorRalf Baechle <ralf@linux-mips.org>2005-05-05 12:45:59 -0400
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 14:31:12 -0400
commit4194318c3941fa9cfaa63dfdab9054fcae5e08d3 (patch)
tree2b44341a9cb911e34efbb33a35142fd2dcd536ff /include/asm-mips/cpu-features.h
parentcd21dfcfbb5c43de54f6be795dde07397da2bc2f (diff)
Cleanup decoding of MIPSxx config registers.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/cpu-features.h')
-rw-r--r--include/asm-mips/cpu-features.h16
1 files changed, 13 insertions, 3 deletions
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h
index 9a2de642eee6..012deda63e68 100644
--- a/include/asm-mips/cpu-features.h
+++ b/include/asm-mips/cpu-features.h
@@ -4,6 +4,7 @@
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2003, 2004 Ralf Baechle 6 * Copyright (C) 2003, 2004 Ralf Baechle
7 * Copyright (C) 2004 Maciej W. Rozycki
7 */ 8 */
8#ifndef __ASM_CPU_FEATURES_H 9#ifndef __ASM_CPU_FEATURES_H
9#define __ASM_CPU_FEATURES_H 10#define __ASM_CPU_FEATURES_H
@@ -39,9 +40,6 @@
39#ifndef cpu_has_watch 40#ifndef cpu_has_watch
40#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH) 41#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
41#endif 42#endif
42#ifndef cpu_has_mips16
43#define cpu_has_mips16 (cpu_data[0].options & MIPS_CPU_MIPS16)
44#endif
45#ifndef cpu_has_divec 43#ifndef cpu_has_divec
46#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC) 44#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
47#endif 45#endif
@@ -66,6 +64,18 @@
66#ifndef cpu_has_llsc 64#ifndef cpu_has_llsc
67#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) 65#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
68#endif 66#endif
67#ifndef cpu_has_mips16
68#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
69#endif
70#ifndef cpu_has_mdmx
71#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
72#endif
73#ifndef cpu_has_mips3d
74#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
75#endif
76#ifndef cpu_has_smartmips
77#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
78#endif
69#ifndef cpu_has_vtag_icache 79#ifndef cpu_has_vtag_icache
70#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) 80#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
71#endif 81#endif