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authorRalf Baechle <ralf@linux-mips.org>2006-02-01 10:29:21 -0500
committerRalf Baechle <ralf@linux-mips.org>2006-02-07 08:30:25 -0500
commit1e32ceeca25ea30cabce137fac7e2f58fe8847db (patch)
tree603e9388af3bf1043d0039198bbb236d6b4a41dd /include/asm-mips/byteorder.h
parent7e5b24ac759176e55c8a535fff6533366168cbe9 (diff)
[MIPS] MIPS R2 optimized endianess swapping.
From Franck Bui-Huu <vagabon.xyz@gmail.com> with modifications by me. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/byteorder.h')
-rw-r--r--include/asm-mips/byteorder.h29
1 files changed, 29 insertions, 0 deletions
diff --git a/include/asm-mips/byteorder.h b/include/asm-mips/byteorder.h
index d1fe9e5c62e4..584f8128fffd 100644
--- a/include/asm-mips/byteorder.h
+++ b/include/asm-mips/byteorder.h
@@ -8,10 +8,39 @@
8#ifndef _ASM_BYTEORDER_H 8#ifndef _ASM_BYTEORDER_H
9#define _ASM_BYTEORDER_H 9#define _ASM_BYTEORDER_H
10 10
11#include <linux/config.h>
12#include <linux/compiler.h>
11#include <asm/types.h> 13#include <asm/types.h>
12 14
13#ifdef __GNUC__ 15#ifdef __GNUC__
14 16
17#ifdef CONFIG_CPU_MIPSR2
18
19static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
20{
21 __asm__(
22 " wsbh %0, %1 \n"
23 : "=r" (x)
24 : "r" (x));
25
26 return x;
27}
28#define __arch__swab16(x) ___arch__swab16(x)
29
30static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
31{
32 __asm__(
33 " wsbh %0, %1 \n"
34 " rotr %0, %0, 16 \n"
35 : "=r" (x)
36 : "r" (x));
37
38 return x;
39}
40#define __arch__swab32(x) ___arch__swab32(x)
41
42#endif /* CONFIG_CPU_MIPSR2 */
43
15#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) 44#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
16# define __BYTEORDER_HAS_U64__ 45# define __BYTEORDER_HAS_U64__
17# define __SWAB_64_THRU_32__ 46# define __SWAB_64_THRU_32__