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authorMaciej W. Rozycki <macro@linux-mips.org>2005-06-23 11:57:15 -0400
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 14:31:31 -0400
commitc4559f67b73d6c34fde0faac5c6c890a2cf3527c (patch)
tree4063b3a937215684db85cc4f70eabd99cf3b8573 /include/asm-mips/bitops.h
parent69c75fb458cd81bb29e1d9580469110b00316748 (diff)
Always use ".set mips3" rather than select between "mips2" or "mips3"
for assembling ll/sc sequences to avoid problems with 64-bit configurations. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/bitops.h')
-rw-r--r--include/asm-mips/bitops.h26
1 files changed, 12 insertions, 14 deletions
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index 1dc35879b362..d9c02bd0b18e 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -20,14 +20,12 @@
20#define SZLONG_MASK 31UL 20#define SZLONG_MASK 31UL
21#define __LL "ll " 21#define __LL "ll "
22#define __SC "sc " 22#define __SC "sc "
23#define __SET_MIPS ".set mips2 "
24#define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x)) 23#define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x))
25#elif (_MIPS_SZLONG == 64) 24#elif (_MIPS_SZLONG == 64)
26#define SZLONG_LOG 6 25#define SZLONG_LOG 6
27#define SZLONG_MASK 63UL 26#define SZLONG_MASK 63UL
28#define __LL "lld " 27#define __LL "lld "
29#define __SC "scd " 28#define __SC "scd "
30#define __SET_MIPS ".set mips3 "
31#define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x)) 29#define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x))
32#endif 30#endif
33 31
@@ -74,7 +72,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
74 72
75 if (cpu_has_llsc && R10000_LLSC_WAR) { 73 if (cpu_has_llsc && R10000_LLSC_WAR) {
76 __asm__ __volatile__( 74 __asm__ __volatile__(
77 " " __SET_MIPS " \n" 75 " .set mips3 \n"
78 "1: " __LL "%0, %1 # set_bit \n" 76 "1: " __LL "%0, %1 # set_bit \n"
79 " or %0, %2 \n" 77 " or %0, %2 \n"
80 " " __SC "%0, %1 \n" 78 " " __SC "%0, %1 \n"
@@ -84,7 +82,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
84 : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m)); 82 : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
85 } else if (cpu_has_llsc) { 83 } else if (cpu_has_llsc) {
86 __asm__ __volatile__( 84 __asm__ __volatile__(
87 " " __SET_MIPS " \n" 85 " .set mips3 \n"
88 "1: " __LL "%0, %1 # set_bit \n" 86 "1: " __LL "%0, %1 # set_bit \n"
89 " or %0, %2 \n" 87 " or %0, %2 \n"
90 " " __SC "%0, %1 \n" 88 " " __SC "%0, %1 \n"
@@ -138,7 +136,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
138 136
139 if (cpu_has_llsc && R10000_LLSC_WAR) { 137 if (cpu_has_llsc && R10000_LLSC_WAR) {
140 __asm__ __volatile__( 138 __asm__ __volatile__(
141 " " __SET_MIPS " \n" 139 " .set mips3 \n"
142 "1: " __LL "%0, %1 # clear_bit \n" 140 "1: " __LL "%0, %1 # clear_bit \n"
143 " and %0, %2 \n" 141 " and %0, %2 \n"
144 " " __SC "%0, %1 \n" 142 " " __SC "%0, %1 \n"
@@ -148,7 +146,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
148 : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m)); 146 : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m));
149 } else if (cpu_has_llsc) { 147 } else if (cpu_has_llsc) {
150 __asm__ __volatile__( 148 __asm__ __volatile__(
151 " " __SET_MIPS " \n" 149 " .set mips3 \n"
152 "1: " __LL "%0, %1 # clear_bit \n" 150 "1: " __LL "%0, %1 # clear_bit \n"
153 " and %0, %2 \n" 151 " and %0, %2 \n"
154 " " __SC "%0, %1 \n" 152 " " __SC "%0, %1 \n"
@@ -201,7 +199,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
201 unsigned long temp; 199 unsigned long temp;
202 200
203 __asm__ __volatile__( 201 __asm__ __volatile__(
204 " " __SET_MIPS " \n" 202 " .set mips3 \n"
205 "1: " __LL "%0, %1 # change_bit \n" 203 "1: " __LL "%0, %1 # change_bit \n"
206 " xor %0, %2 \n" 204 " xor %0, %2 \n"
207 " " __SC "%0, %1 \n" 205 " " __SC "%0, %1 \n"
@@ -214,7 +212,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
214 unsigned long temp; 212 unsigned long temp;
215 213
216 __asm__ __volatile__( 214 __asm__ __volatile__(
217 " " __SET_MIPS " \n" 215 " .set mips3 \n"
218 "1: " __LL "%0, %1 # change_bit \n" 216 "1: " __LL "%0, %1 # change_bit \n"
219 " xor %0, %2 \n" 217 " xor %0, %2 \n"
220 " " __SC "%0, %1 \n" 218 " " __SC "%0, %1 \n"
@@ -267,7 +265,7 @@ static inline int test_and_set_bit(unsigned long nr,
267 unsigned long temp, res; 265 unsigned long temp, res;
268 266
269 __asm__ __volatile__( 267 __asm__ __volatile__(
270 " " __SET_MIPS " \n" 268 " .set mips3 \n"
271 "1: " __LL "%0, %1 # test_and_set_bit \n" 269 "1: " __LL "%0, %1 # test_and_set_bit \n"
272 " or %2, %0, %3 \n" 270 " or %2, %0, %3 \n"
273 " " __SC "%2, %1 \n" 271 " " __SC "%2, %1 \n"
@@ -289,7 +287,7 @@ static inline int test_and_set_bit(unsigned long nr,
289 __asm__ __volatile__( 287 __asm__ __volatile__(
290 " .set push \n" 288 " .set push \n"
291 " .set noreorder \n" 289 " .set noreorder \n"
292 " " __SET_MIPS " \n" 290 " .set mips3 \n"
293 "1: " __LL "%0, %1 # test_and_set_bit \n" 291 "1: " __LL "%0, %1 # test_and_set_bit \n"
294 " or %2, %0, %3 \n" 292 " or %2, %0, %3 \n"
295 " " __SC "%2, %1 \n" 293 " " __SC "%2, %1 \n"
@@ -361,7 +359,7 @@ static inline int test_and_clear_bit(unsigned long nr,
361 unsigned long temp, res; 359 unsigned long temp, res;
362 360
363 __asm__ __volatile__( 361 __asm__ __volatile__(
364 " " __SET_MIPS " \n" 362 " .set mips3 \n"
365 "1: " __LL "%0, %1 # test_and_clear_bit \n" 363 "1: " __LL "%0, %1 # test_and_clear_bit \n"
366 " or %2, %0, %3 \n" 364 " or %2, %0, %3 \n"
367 " xor %2, %3 \n" 365 " xor %2, %3 \n"
@@ -384,7 +382,7 @@ static inline int test_and_clear_bit(unsigned long nr,
384 __asm__ __volatile__( 382 __asm__ __volatile__(
385 " .set push \n" 383 " .set push \n"
386 " .set noreorder \n" 384 " .set noreorder \n"
387 " " __SET_MIPS " \n" 385 " .set mips3 \n"
388 "1: " __LL "%0, %1 # test_and_clear_bit \n" 386 "1: " __LL "%0, %1 # test_and_clear_bit \n"
389 " or %2, %0, %3 \n" 387 " or %2, %0, %3 \n"
390 " xor %2, %3 \n" 388 " xor %2, %3 \n"
@@ -457,7 +455,7 @@ static inline int test_and_change_bit(unsigned long nr,
457 unsigned long temp, res; 455 unsigned long temp, res;
458 456
459 __asm__ __volatile__( 457 __asm__ __volatile__(
460 " " __SET_MIPS " \n" 458 " .set mips3 \n"
461 "1: " __LL "%0, %1 # test_and_change_bit \n" 459 "1: " __LL "%0, %1 # test_and_change_bit \n"
462 " xor %2, %0, %3 \n" 460 " xor %2, %0, %3 \n"
463 " " __SC "%2, %1 \n" 461 " " __SC "%2, %1 \n"
@@ -479,7 +477,7 @@ static inline int test_and_change_bit(unsigned long nr,
479 __asm__ __volatile__( 477 __asm__ __volatile__(
480 " .set push \n" 478 " .set push \n"
481 " .set noreorder \n" 479 " .set noreorder \n"
482 " " __SET_MIPS " \n" 480 " .set mips3 \n"
483 "1: " __LL "%0, %1 # test_and_change_bit \n" 481 "1: " __LL "%0, %1 # test_and_change_bit \n"
484 " xor %2, %0, %3 \n" 482 " xor %2, %0, %3 \n"
485 " " __SC "\t%2, %1 \n" 483 " " __SC "\t%2, %1 \n"
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-22 08:10:33 -0500