diff options
author | Greg Ungerer <gerg@snapgear.com> | 2005-09-11 21:18:10 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@g5.osdl.org> | 2005-09-11 23:43:47 -0400 |
commit | d871629b83774fc24db6dd2775ceaf46b433b056 (patch) | |
tree | 78bcd68ed5c497ee1f2bd5f42a936dac62c135e9 /include/asm-m68knommu | |
parent | 2d9d166e1cb2909bd8d3ac0d1ee8db83abb9fd86 (diff) |
[PATCH] m68knommu: allow for SDRAM and GPIO differences on 5270/1 and 5274/5 processors
Allow for differences in the SDRAM controller setup and GPIO pin setup
of the 5270/1 and 5274/5 parts. With separate config options for each
now this no longer needs to be board specific.
Signed-off-by: Greg Ungerer <gerg@uclinux.com>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-m68knommu')
-rw-r--r-- | include/asm-m68knommu/m527xsim.h | 21 |
1 files changed, 19 insertions, 2 deletions
diff --git a/include/asm-m68knommu/m527xsim.h b/include/asm-m68knommu/m527xsim.h index d280d013da03..e7878d0f7d7a 100644 --- a/include/asm-m68knommu/m527xsim.h +++ b/include/asm-m68knommu/m527xsim.h | |||
@@ -37,13 +37,14 @@ | |||
37 | /* | 37 | /* |
38 | * SDRAM configuration registers. | 38 | * SDRAM configuration registers. |
39 | */ | 39 | */ |
40 | #ifdef CONFIG_M5271EVB | 40 | #ifdef CONFIG_M5271 |
41 | #define MCFSIM_DCR 0x40 /* SDRAM control */ | 41 | #define MCFSIM_DCR 0x40 /* SDRAM control */ |
42 | #define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ | 42 | #define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ |
43 | #define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ | 43 | #define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ |
44 | #define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ | 44 | #define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ |
45 | #define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ | 45 | #define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ |
46 | #else | 46 | #endif |
47 | #ifdef CONFIG_M5275 | ||
47 | #define MCFSIM_DMR 0x40 /* SDRAM mode */ | 48 | #define MCFSIM_DMR 0x40 /* SDRAM mode */ |
48 | #define MCFSIM_DCR 0x44 /* SDRAM control */ | 49 | #define MCFSIM_DCR 0x44 /* SDRAM control */ |
49 | #define MCFSIM_DCFG1 0x48 /* SDRAM configuration 1 */ | 50 | #define MCFSIM_DCFG1 0x48 /* SDRAM configuration 1 */ |
@@ -54,5 +55,21 @@ | |||
54 | #define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */ | 55 | #define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */ |
55 | #endif | 56 | #endif |
56 | 57 | ||
58 | /* | ||
59 | * GPIO pins setups to enable the UARTs. | ||
60 | */ | ||
61 | #ifdef CONFIG_M5271 | ||
62 | #define MCF_GPIO_PAR_UART 0x100048 /* PAR UART address */ | ||
63 | #define UART0_ENABLE_MASK 0x000f | ||
64 | #define UART1_ENABLE_MASK 0x0ff0 | ||
65 | #define UART2_ENABLE_MASK 0x3000 | ||
66 | #endif | ||
67 | #ifdef CONFIG_M5275 | ||
68 | #define MCF_GPIO_PAR_UART 0x10007c /* PAR UART address */ | ||
69 | #define UART0_ENABLE_MASK 0x000f | ||
70 | #define UART1_ENABLE_MASK 0x00f0 | ||
71 | #define UART2_ENABLE_MASK 0x3f00 | ||
72 | #endif | ||
73 | |||
57 | /****************************************************************************/ | 74 | /****************************************************************************/ |
58 | #endif /* m527xsim_h */ | 75 | #endif /* m527xsim_h */ |