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authorGreg Ungerer <gerg@snapgear.com>2005-09-11 21:18:10 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2005-09-11 23:43:46 -0400
commit8a6e43e9ee84eb8fb39bfdf8f0b6e466905491d0 (patch)
treee833567f0b1c9e54c25244905cf630f509e66c02 /include/asm-m68knommu/mcfcache.h
parent7dd6a2aa27a7a8036fbaf60cbce38a64128d1d4d (diff)
[PATCH] m68knommu: cache support for 523x/528x processors
Add support for the cache of the ColdFIre 523x family of processors. Enable the 528x cache by default now, all final shipping silicon has the cache bug fixed. Signed-off-by: Greg Ungerer <gerg@uclinux.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-m68knommu/mcfcache.h')
-rw-r--r--include/asm-m68knommu/mcfcache.h25
1 files changed, 11 insertions, 14 deletions
diff --git a/include/asm-m68knommu/mcfcache.h b/include/asm-m68knommu/mcfcache.h
index bdd8c53ef34c..b17cd920977f 100644
--- a/include/asm-m68knommu/mcfcache.h
+++ b/include/asm-m68knommu/mcfcache.h
@@ -33,7 +33,7 @@
33.endm 33.endm
34#endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */ 34#endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */
35 35
36#if defined(CONFIG_M527x) 36#if defined(CONFIG_M523x) || defined(CONFIG_M527x)
37/* 37/*
38 * New version 2 cores have a configurable split cache arrangement. 38 * New version 2 cores have a configurable split cache arrangement.
39 * For now I am just enabling instruction cache - but ultimately I 39 * For now I am just enabling instruction cache - but ultimately I
@@ -51,23 +51,20 @@
51 movec %d0,%CACR /* enable cache */ 51 movec %d0,%CACR /* enable cache */
52 nop 52 nop
53.endm 53.endm
54#endif /* CONFIG_M527x */ 54#endif /* CONFIG_M523x || CONFIG_M527x */
55 55
56#if defined(CONFIG_M528x) 56#if defined(CONFIG_M528x)
57/*
58 * Cache is totally broken on early 5282 silicon. So far now we
59 * disable its cache all together.
60 */
61.macro CACHE_ENABLE 57.macro CACHE_ENABLE
62 movel #0x01000000,%d0
63 movec %d0,%CACR /* invalidate cache */
64 nop 58 nop
65 movel #0x0000c000,%d0 /* set SDRAM cached only */ 59 movel #0x01000000, %d0
66 movec %d0,%ACR0 60 movec %d0, %CACR /* Invalidate cache */
67 movel #0x00000000,%d0 /* no other regions cached */ 61 nop
68 movec %d0,%ACR1 62 movel #0x0000c020, %d0 /* Set SDRAM cached only */
69 movel #0x00000000,%d0 /* configure cache */ 63 movec %d0, %ACR0
70 movec %d0,%CACR /* enable cache */ 64 movel #0xff00c000, %d0 /* Cache Flash also */
65 movec %d0, %ACR1
66 movel #0x80000200, %d0 /* Setup cache mask */
67 movec %d0, %CACR /* Enable cache */
71 nop 68 nop
72.endm 69.endm
73#endif /* CONFIG_M528x */ 70#endif /* CONFIG_M528x */