diff options
| author | Joe Perches <joe@perches.com> | 2008-02-03 10:38:04 -0500 |
|---|---|---|
| committer | Adrian Bunk <bunk@kernel.org> | 2008-02-03 10:38:04 -0500 |
| commit | ab690d9fedf5103bc3057bcd20555159f613b5f2 (patch) | |
| tree | 6eb327f4dbfd88c384972ff0c4f9a1877b25cbe0 /include/asm-m68knommu/m5307sim.h | |
| parent | 62018b5b588fbefbeb4542cdb6238495b2d2ea38 (diff) | |
include/asm-m68knommu/: Spelling fixes
Signed-off-by: Joe Perches <joe@perches.com>
Acked-by: Greg Ungerer <gerg@uclinux.org>
Signed-off-by: Adrian Bunk <bunk@kernel.org>
Diffstat (limited to 'include/asm-m68knommu/m5307sim.h')
| -rw-r--r-- | include/asm-m68knommu/m5307sim.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/include/asm-m68knommu/m5307sim.h b/include/asm-m68knommu/m5307sim.h index d3ce550f6ef4..5886728409c0 100644 --- a/include/asm-m68knommu/m5307sim.h +++ b/include/asm-m68knommu/m5307sim.h | |||
| @@ -64,22 +64,22 @@ | |||
| 64 | #define MCFSIM_CSMR7 0xda /* CS 7 Mask reg (r/w) */ | 64 | #define MCFSIM_CSMR7 0xda /* CS 7 Mask reg (r/w) */ |
| 65 | #define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ | 65 | #define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ |
| 66 | #else | 66 | #else |
| 67 | #define MCFSIM_CSAR2 0x98 /* CS 2 Adress reg (r/w) */ | 67 | #define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ |
| 68 | #define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ | 68 | #define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ |
| 69 | #define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ | 69 | #define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ |
| 70 | #define MCFSIM_CSAR3 0xa4 /* CS 3 Adress reg (r/w) */ | 70 | #define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ |
| 71 | #define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ | 71 | #define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ |
| 72 | #define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ | 72 | #define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ |
| 73 | #define MCFSIM_CSAR4 0xb0 /* CS 4 Adress reg (r/w) */ | 73 | #define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */ |
| 74 | #define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */ | 74 | #define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */ |
| 75 | #define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */ | 75 | #define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */ |
| 76 | #define MCFSIM_CSAR5 0xbc /* CS 5 Adress reg (r/w) */ | 76 | #define MCFSIM_CSAR5 0xbc /* CS 5 Address reg (r/w) */ |
| 77 | #define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */ | 77 | #define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */ |
| 78 | #define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */ | 78 | #define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */ |
| 79 | #define MCFSIM_CSAR6 0xc8 /* CS 6 Adress reg (r/w) */ | 79 | #define MCFSIM_CSAR6 0xc8 /* CS 6 Address reg (r/w) */ |
| 80 | #define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */ | 80 | #define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */ |
| 81 | #define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */ | 81 | #define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */ |
| 82 | #define MCFSIM_CSAR7 0xd4 /* CS 7 Adress reg (r/w) */ | 82 | #define MCFSIM_CSAR7 0xd4 /* CS 7 Address reg (r/w) */ |
| 83 | #define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */ | 83 | #define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */ |
| 84 | #define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ | 84 | #define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ |
| 85 | #endif /* CONFIG_OLDMASK */ | 85 | #endif /* CONFIG_OLDMASK */ |