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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-m32r/smp.h
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'include/asm-m32r/smp.h')
-rw-r--r--include/asm-m32r/smp.h118
1 files changed, 118 insertions, 0 deletions
diff --git a/include/asm-m32r/smp.h b/include/asm-m32r/smp.h
new file mode 100644
index 000000000000..8cd4d0da4be1
--- /dev/null
+++ b/include/asm-m32r/smp.h
@@ -0,0 +1,118 @@
1#ifndef _ASM_M32R_SMP_H
2#define _ASM_M32R_SMP_H
3
4/* $Id$ */
5
6#include <linux/config.h>
7
8#ifdef CONFIG_SMP
9#ifndef __ASSEMBLY__
10
11#include <linux/cpumask.h>
12#include <linux/spinlock.h>
13#include <linux/threads.h>
14#include <asm/m32r.h>
15
16#define PHYSID_ARRAY_SIZE 1
17
18struct physid_mask
19{
20 unsigned long mask[PHYSID_ARRAY_SIZE];
21};
22
23typedef struct physid_mask physid_mask_t;
24
25#define physid_set(physid, map) set_bit(physid, (map).mask)
26#define physid_clear(physid, map) clear_bit(physid, (map).mask)
27#define physid_isset(physid, map) test_bit(physid, (map).mask)
28#define physid_test_and_set(physid, map) test_and_set_bit(physid, (map).mask)
29
30#define physids_and(dst, src1, src2) bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
31#define physids_or(dst, src1, src2) bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
32#define physids_clear(map) bitmap_zero((map).mask, MAX_APICS)
33#define physids_complement(dst, src) bitmap_complement((dst).mask,(src).mask, MAX_APICS)
34#define physids_empty(map) bitmap_empty((map).mask, MAX_APICS)
35#define physids_equal(map1, map2) bitmap_equal((map1).mask, (map2).mask, MAX_APICS)
36#define physids_weight(map) bitmap_weight((map).mask, MAX_APICS)
37#define physids_shift_right(d, s, n) bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS)
38#define physids_shift_left(d, s, n) bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS)
39#define physids_coerce(map) ((map).mask[0])
40
41#define physids_promote(physids) \
42 ({ \
43 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
44 __physid_mask.mask[0] = physids; \
45 __physid_mask; \
46 })
47
48#define physid_mask_of_physid(physid) \
49 ({ \
50 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
51 physid_set(physid, __physid_mask); \
52 __physid_mask; \
53 })
54
55#define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
56#define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
57
58extern physid_mask_t phys_cpu_present_map;
59
60/*
61 * Some lowlevel functions might want to know about
62 * the real CPU ID <-> CPU # mapping.
63 */
64extern volatile int physid_2_cpu[NR_CPUS];
65extern volatile int cpu_2_physid[NR_CPUS];
66#define physid_to_cpu(physid) physid_2_cpu[physid]
67#define cpu_to_physid(cpu_id) cpu_2_physid[cpu_id]
68
69#define smp_processor_id() (current_thread_info()->cpu)
70
71extern cpumask_t cpu_callout_map;
72#define cpu_possible_map cpu_callout_map
73
74static __inline__ int hard_smp_processor_id(void)
75{
76 return (int)*(volatile long *)M32R_CPUID_PORTL;
77}
78
79static __inline__ int cpu_logical_map(int cpu)
80{
81 return cpu;
82}
83
84static __inline__ int cpu_number_map(int cpu)
85{
86 return cpu;
87}
88
89static __inline__ unsigned int num_booting_cpus(void)
90{
91 return cpus_weight(cpu_callout_map);
92}
93
94extern void smp_send_timer(void);
95extern unsigned long send_IPI_mask_phys(cpumask_t, int, int);
96
97#endif /* not __ASSEMBLY__ */
98
99#define NO_PROC_ID (0xff) /* No processor magic marker */
100
101#define PROC_CHANGE_PENALTY (15) /* Schedule penalty */
102
103/*
104 * M32R-mp IPI
105 */
106#define RESCHEDULE_IPI (M32R_IRQ_IPI0-M32R_IRQ_IPI0)
107#define INVALIDATE_TLB_IPI (M32R_IRQ_IPI1-M32R_IRQ_IPI0)
108#define CALL_FUNCTION_IPI (M32R_IRQ_IPI2-M32R_IRQ_IPI0)
109#define LOCAL_TIMER_IPI (M32R_IRQ_IPI3-M32R_IRQ_IPI0)
110#define INVALIDATE_CACHE_IPI (M32R_IRQ_IPI4-M32R_IRQ_IPI0)
111#define CPU_BOOT_IPI (M32R_IRQ_IPI5-M32R_IRQ_IPI0)
112
113#define IPI_SHIFT (0)
114#define NR_IPIS (8)
115
116#endif /* CONFIG_SMP */
117
118#endif /* _ASM_M32R_SMP_H */