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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-07-12 16:41:29 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-07-12 16:41:29 -0400
commit0806ca2ab3ef7d7a1bd41a980f661a13ba11acb5 (patch)
treeb0efd7382e59de26f173f61b677a579f3f4ee137 /include/asm-ia64
parent21ba0f88ae56da82a3a15fe54d729208b64c4f4b (diff)
parent1612b18ccb2318563ba51268289dc3271a6052f7 (diff)
Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6
* 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6: [IA64] Support multiple CPUs going through OS_MCA [IA64] silence GCC ia64 unused variable warnings [IA64] prevent MCA when performing MMIO mmap to PCI config space [IA64] add sn_register_pmi_handler oemcall [IA64] Stop bit for brl instruction [IA64] SN: Correct ROM resource length for BIOS copy [IA64] Don't set psr.ic and psr.i simultaneously
Diffstat (limited to 'include/asm-ia64')
-rw-r--r--include/asm-ia64/mca.h1
-rw-r--r--include/asm-ia64/sn/sn_sal.h20
2 files changed, 21 insertions, 0 deletions
diff --git a/include/asm-ia64/mca.h b/include/asm-ia64/mca.h
index 41098f459684..edd5d01028df 100644
--- a/include/asm-ia64/mca.h
+++ b/include/asm-ia64/mca.h
@@ -48,6 +48,7 @@ enum {
48 IA64_MCA_RENDEZ_CHECKIN_NOTDONE = 0x0, 48 IA64_MCA_RENDEZ_CHECKIN_NOTDONE = 0x0,
49 IA64_MCA_RENDEZ_CHECKIN_DONE = 0x1, 49 IA64_MCA_RENDEZ_CHECKIN_DONE = 0x1,
50 IA64_MCA_RENDEZ_CHECKIN_INIT = 0x2, 50 IA64_MCA_RENDEZ_CHECKIN_INIT = 0x2,
51 IA64_MCA_RENDEZ_CHECKIN_CONCURRENT_MCA = 0x3,
51}; 52};
52 53
53/* Information maintained by the MC infrastructure */ 54/* Information maintained by the MC infrastructure */
diff --git a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h
index d3566a298fa4..676b31a08c61 100644
--- a/include/asm-ia64/sn/sn_sal.h
+++ b/include/asm-ia64/sn/sn_sal.h
@@ -32,6 +32,7 @@
32#define SN_SAL_NO_FAULT_ZONE_VIRTUAL 0x02000010 32#define SN_SAL_NO_FAULT_ZONE_VIRTUAL 0x02000010
33#define SN_SAL_NO_FAULT_ZONE_PHYSICAL 0x02000011 33#define SN_SAL_NO_FAULT_ZONE_PHYSICAL 0x02000011
34#define SN_SAL_PRINT_ERROR 0x02000012 34#define SN_SAL_PRINT_ERROR 0x02000012
35#define SN_SAL_REGISTER_PMI_HANDLER 0x02000014
35#define SN_SAL_SET_ERROR_HANDLING_FEATURES 0x0200001a // reentrant 36#define SN_SAL_SET_ERROR_HANDLING_FEATURES 0x0200001a // reentrant
36#define SN_SAL_GET_FIT_COMPT 0x0200001b // reentrant 37#define SN_SAL_GET_FIT_COMPT 0x0200001b // reentrant
37#define SN_SAL_GET_SAPIC_INFO 0x0200001d 38#define SN_SAL_GET_SAPIC_INFO 0x0200001d
@@ -680,6 +681,25 @@ sn_register_nofault_code(u64 start_addr, u64 end_addr, u64 return_addr,
680} 681}
681 682
682/* 683/*
684 * Register or unregister a function to handle a PMI received by a CPU.
685 * Before calling the registered handler, SAL sets r1 to the value that
686 * was passed in as the global_pointer.
687 *
688 * If the handler pointer is NULL, then the currently registered handler
689 * will be unregistered.
690 *
691 * Returns 0 on success, or a negative value if an error occurred.
692 */
693static inline int
694sn_register_pmi_handler(u64 handler, u64 global_pointer)
695{
696 struct ia64_sal_retval ret_stuff;
697 ia64_sal_oemcall(&ret_stuff, SN_SAL_REGISTER_PMI_HANDLER, handler,
698 global_pointer, 0, 0, 0, 0, 0);
699 return ret_stuff.status;
700}
701
702/*
683 * Change or query the coherence domain for this partition. Each cpu-based 703 * Change or query the coherence domain for this partition. Each cpu-based
684 * nasid is represented by a bit in an array of 64-bit words: 704 * nasid is represented by a bit in an array of 64-bit words:
685 * 0 = not in this partition's coherency domain 705 * 0 = not in this partition's coherency domain