diff options
author | Tony Luck <tony.luck@intel.com> | 2006-06-21 17:50:10 -0400 |
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committer | Tony Luck <tony.luck@intel.com> | 2006-06-21 17:50:10 -0400 |
commit | 1323523f505606cfd24af6122369afddefc3b09d (patch) | |
tree | a3238a27220dd91ec0918478683e59e48605865f /include/asm-ia64 | |
parent | 9ba89334552b96e2127dcafb1c46ce255ecf2667 (diff) | |
parent | 32e62c636a728cb39c0b3bd191286f2ca65d4028 (diff) |
Pull rework-memory-attribute-aliasing into release branch
Diffstat (limited to 'include/asm-ia64')
-rw-r--r-- | include/asm-ia64/io.h | 1 | ||||
-rw-r--r-- | include/asm-ia64/pgtable.h | 22 |
2 files changed, 11 insertions, 12 deletions
diff --git a/include/asm-ia64/io.h b/include/asm-ia64/io.h index c2e3742108bb..781ee2c7e8c3 100644 --- a/include/asm-ia64/io.h +++ b/include/asm-ia64/io.h | |||
@@ -88,6 +88,7 @@ phys_to_virt (unsigned long address) | |||
88 | } | 88 | } |
89 | 89 | ||
90 | #define ARCH_HAS_VALID_PHYS_ADDR_RANGE | 90 | #define ARCH_HAS_VALID_PHYS_ADDR_RANGE |
91 | extern u64 kern_mem_attribute (unsigned long phys_addr, unsigned long size); | ||
91 | extern int valid_phys_addr_range (unsigned long addr, size_t count); /* efi.c */ | 92 | extern int valid_phys_addr_range (unsigned long addr, size_t count); /* efi.c */ |
92 | extern int valid_mmap_phys_addr_range (unsigned long addr, size_t count); | 93 | extern int valid_mmap_phys_addr_range (unsigned long addr, size_t count); |
93 | 94 | ||
diff --git a/include/asm-ia64/pgtable.h b/include/asm-ia64/pgtable.h index eaac08d5e0bd..228981cadf8f 100644 --- a/include/asm-ia64/pgtable.h +++ b/include/asm-ia64/pgtable.h | |||
@@ -316,22 +316,20 @@ ia64_phys_addr_valid (unsigned long addr) | |||
316 | #define pte_mkhuge(pte) (__pte(pte_val(pte))) | 316 | #define pte_mkhuge(pte) (__pte(pte_val(pte))) |
317 | 317 | ||
318 | /* | 318 | /* |
319 | * Macro to a page protection value as "uncacheable". Note that "protection" is really a | 319 | * Make page protection values cacheable, uncacheable, or write- |
320 | * misnomer here as the protection value contains the memory attribute bits, dirty bits, | 320 | * combining. Note that "protection" is really a misnomer here as the |
321 | * and various other bits as well. | 321 | * protection value contains the memory attribute bits, dirty bits, and |
322 | * various other bits as well. | ||
322 | */ | 323 | */ |
324 | #define pgprot_cacheable(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WB) | ||
323 | #define pgprot_noncached(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_UC) | 325 | #define pgprot_noncached(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_UC) |
324 | |||
325 | /* | ||
326 | * Macro to make mark a page protection value as "write-combining". | ||
327 | * Note that "protection" is really a misnomer here as the protection | ||
328 | * value contains the memory attribute bits, dirty bits, and various | ||
329 | * other bits as well. Accesses through a write-combining translation | ||
330 | * works bypasses the caches, but does allow for consecutive writes to | ||
331 | * be combined into single (but larger) write transactions. | ||
332 | */ | ||
333 | #define pgprot_writecombine(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WC) | 326 | #define pgprot_writecombine(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WC) |
334 | 327 | ||
328 | struct file; | ||
329 | extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, | ||
330 | unsigned long size, pgprot_t vma_prot); | ||
331 | #define __HAVE_PHYS_MEM_ACCESS_PROT | ||
332 | |||
335 | static inline unsigned long | 333 | static inline unsigned long |
336 | pgd_index (unsigned long address) | 334 | pgd_index (unsigned long address) |
337 | { | 335 | { |