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authorTony Luck <tony.luck@intel.com>2005-08-29 17:15:10 -0400
committerTony Luck <tony.luck@intel.com>2005-08-29 17:15:10 -0400
commit7115c13bd6d166982212276610b27773b8c27aec (patch)
tree00c78ca82f738acdc6adfde7dede2689ed13b833 /include/asm-ia64
parent7d2e423addf3054a3238347740df6f46d4d83f3d (diff)
parent4db8699bcfa8faddb5727b1cb010a4d9b8a42e8c (diff)
Pull acpi-p-state into release branch
Diffstat (limited to 'include/asm-ia64')
-rw-r--r--include/asm-ia64/acpi.h5
-rw-r--r--include/asm-ia64/pal.h21
2 files changed, 26 insertions, 0 deletions
diff --git a/include/asm-ia64/acpi.h b/include/asm-ia64/acpi.h
index 4c06d455139c..3a544ffc5008 100644
--- a/include/asm-ia64/acpi.h
+++ b/include/asm-ia64/acpi.h
@@ -116,6 +116,11 @@ extern int __initdata nid_to_pxm_map[MAX_NUMNODES];
116 116
117extern u16 ia64_acpiid_to_sapicid[]; 117extern u16 ia64_acpiid_to_sapicid[];
118 118
119/*
120 * Refer Intel ACPI _PDC support document for bit definitions
121 */
122#define ACPI_PDC_EST_CAPABILITY_SMP 0x8
123
119#endif /*__KERNEL__*/ 124#endif /*__KERNEL__*/
120 125
121#endif /*_ASM_ACPI_H*/ 126#endif /*_ASM_ACPI_H*/
diff --git a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h
index 2303a10ee595..e828377ad295 100644
--- a/include/asm-ia64/pal.h
+++ b/include/asm-ia64/pal.h
@@ -75,6 +75,8 @@
75#define PAL_CACHE_READ 259 /* read tag & data of cacheline for diagnostic testing */ 75#define PAL_CACHE_READ 259 /* read tag & data of cacheline for diagnostic testing */
76#define PAL_CACHE_WRITE 260 /* write tag & data of cacheline for diagnostic testing */ 76#define PAL_CACHE_WRITE 260 /* write tag & data of cacheline for diagnostic testing */
77#define PAL_VM_TR_READ 261 /* read contents of translation register */ 77#define PAL_VM_TR_READ 261 /* read contents of translation register */
78#define PAL_GET_PSTATE 262 /* get the current P-state */
79#define PAL_SET_PSTATE 263 /* set the P-state */
78 80
79#ifndef __ASSEMBLY__ 81#ifndef __ASSEMBLY__
80 82
@@ -1111,6 +1113,25 @@ ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf)
1111 return iprv.status; 1113 return iprv.status;
1112} 1114}
1113 1115
1116/* Get the current P-state information */
1117static inline s64
1118ia64_pal_get_pstate (u64 *pstate_index)
1119{
1120 struct ia64_pal_retval iprv;
1121 PAL_CALL_STK(iprv, PAL_GET_PSTATE, 0, 0, 0);
1122 *pstate_index = iprv.v0;
1123 return iprv.status;
1124}
1125
1126/* Set the P-state */
1127static inline s64
1128ia64_pal_set_pstate (u64 pstate_index)
1129{
1130 struct ia64_pal_retval iprv;
1131 PAL_CALL_STK(iprv, PAL_SET_PSTATE, pstate_index, 0, 0);
1132 return iprv.status;
1133}
1134
1114/* Cause the processor to enter LIGHT HALT state, where prefetching and execution are 1135/* Cause the processor to enter LIGHT HALT state, where prefetching and execution are
1115 * suspended, but cache and TLB coherency is maintained. 1136 * suspended, but cache and TLB coherency is maintained.
1116 */ 1137 */