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authorMatthew Wilcox <matthew@wil.cx>2006-10-10 10:01:19 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2006-12-01 17:36:56 -0500
commit3efe2d84c8d909567c7976a7106114127b8c3470 (patch)
tree28b93040c032fe5b90bf4fc61fc656eea45832dc /include/asm-ia64
parent368c73d4f689dae0807d0a2aa74c61fd2b9b075f (diff)
PCI: Use pci_generic_prep_mwi on ia64
The pci_generic_prep_mwi() code does everything that pcibios_prep_mwi() does on ia64. All we need to do is be sure that pci_cache_line_size is set appropriately, and we can delete pcibios_prep_mwi(). Using SMP_CACHE_BYTES as the default was wrong on uniprocessor machines as it is only 8 bytes. The default in the generic code of L1_CACHE_BYTES is at least as good. Signed-off-by: Matthew Wilcox <matthew@wil.cx> Acked-by: Jeff Garzik <jeff@garzik.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'include/asm-ia64')
-rw-r--r--include/asm-ia64/pci.h21
1 files changed, 10 insertions, 11 deletions
diff --git a/include/asm-ia64/pci.h b/include/asm-ia64/pci.h
index ef616fd4cb1b..825eb7d882e6 100644
--- a/include/asm-ia64/pci.h
+++ b/include/asm-ia64/pci.h
@@ -26,16 +26,18 @@ void pcibios_config_init(void);
26struct pci_dev; 26struct pci_dev;
27 27
28/* 28/*
29 * PCI_DMA_BUS_IS_PHYS should be set to 1 if there is _necessarily_ a direct correspondence 29 * PCI_DMA_BUS_IS_PHYS should be set to 1 if there is _necessarily_ a direct
30 * between device bus addresses and CPU physical addresses. Platforms with a hardware I/O 30 * correspondence between device bus addresses and CPU physical addresses.
31 * MMU _must_ turn this off to suppress the bounce buffer handling code in the block and 31 * Platforms with a hardware I/O MMU _must_ turn this off to suppress the
32 * network device layers. Platforms with separate bus address spaces _must_ turn this off 32 * bounce buffer handling code in the block and network device layers.
33 * and provide a device DMA mapping implementation that takes care of the necessary 33 * Platforms with separate bus address spaces _must_ turn this off and provide
34 * a device DMA mapping implementation that takes care of the necessary
34 * address translation. 35 * address translation.
35 * 36 *
36 * For now, the ia64 platforms which may have separate/multiple bus address spaces all 37 * For now, the ia64 platforms which may have separate/multiple bus address
37 * have I/O MMUs which support the merging of physically discontiguous buffers, so we can 38 * spaces all have I/O MMUs which support the merging of physically
38 * use that as the sole factor to determine the setting of PCI_DMA_BUS_IS_PHYS. 39 * discontiguous buffers, so we can use that as the sole factor to determine
40 * the setting of PCI_DMA_BUS_IS_PHYS.
39 */ 41 */
40extern unsigned long ia64_max_iommu_merge_mask; 42extern unsigned long ia64_max_iommu_merge_mask;
41#define PCI_DMA_BUS_IS_PHYS (ia64_max_iommu_merge_mask == ~0UL) 43#define PCI_DMA_BUS_IS_PHYS (ia64_max_iommu_merge_mask == ~0UL)
@@ -52,9 +54,6 @@ pcibios_penalize_isa_irq (int irq, int active)
52 /* We don't do dynamic PCI IRQ allocation */ 54 /* We don't do dynamic PCI IRQ allocation */
53} 55}
54 56
55#define HAVE_ARCH_PCI_MWI 1
56extern int pcibios_prep_mwi (struct pci_dev *);
57
58#include <asm-generic/pci-dma-compat.h> 57#include <asm-generic/pci-dma-compat.h>
59 58
60/* pci_unmap_{single,page} is not a nop, thus... */ 59/* pci_unmap_{single,page} is not a nop, thus... */