Merge branch 'release' of master.kernel.org:/pub/scm/linux/kernel/git/aegl/linux-2.6

* 'release' of master.kernel.org:/pub/scm/linux/kernel/git/aegl/linux-2.6:
  [IA64] replace kmalloc+memset with kzalloc
  [IA64] resolve name clash by renaming is_available_memory()
  [IA64] Need export for csum_ipv6_magic
  [IA64] Fix DISCONTIGMEM without VIRTUAL_MEM_MAP
  [PATCH] Add support for type argument in PAL_GET_PSTATE
  [IA64] tidy up return value of ip_fast_csum
  [IA64] implement csum_ipv6_magic for ia64.
  [IA64] More Itanium PAL spec updates
  [IA64] Update processor_info features
  [IA64] Add se bit to Processor State Parameter structure
  [IA64] Add dp bit to cache and bus check structs
  [IA64] SN: Correctly update smp_affinty mask
  [IA64] sparse cleanups
  [IA64] IA64 Kexec/kdump

8 files changed, 132 insertions, 15 deletions

diff --git a/include/asm-ia64/checksum.h b/include/asm-ia64/checksum.h
index bd40f4756ce1..2b78582cbd61 100644
--- a/include/asm-ia64/checksum.h
+++ b/include/asm-ia64/checksum.h
@@ -70,4 +70,10 @@ static inline __sum16 csum_fold(__wsum csum)
         return (__force __sum16)~sum;
 }
 
+#define _HAVE_ARCH_IPV6_CSUM    1
+struct in6_addr;
+extern unsigned short int csum_ipv6_magic(struct in6_addr *saddr,
+        struct in6_addr *daddr, __u32 len, unsigned short proto,
+        unsigned int csum);
+
 #endif /* _ASM_IA64_CHECKSUM_H */
diff --git a/include/asm-ia64/kexec.h b/include/asm-ia64/kexec.h
new file mode 100644
index 000000000000..01c36b004747
--- /dev/null
+++ b/include/asm-ia64/kexec.h
@@ -0,0 +1,47 @@
+#ifndef _ASM_IA64_KEXEC_H
+#define _ASM_IA64_KEXEC_H
+
+
+/* Maximum physical address we can use pages from */
+#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
+/* Maximum address we can reach in physical address mode */
+#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
+/* Maximum address we can use for the control code buffer */
+#define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE
+
+#define KEXEC_CONTROL_CODE_SIZE (8192 + 8192 + 4096)
+
+/* The native architecture */
+#define KEXEC_ARCH KEXEC_ARCH_IA_64
+
+#define MAX_NOTE_BYTES 1024
+
+#define kexec_flush_icache_page(page) do { \
+                unsigned long page_addr = (unsigned long)page_address(page); \
+                flush_icache_range(page_addr, page_addr + PAGE_SIZE); \
+        } while(0)
+
+extern struct kimage *ia64_kimage;
+DECLARE_PER_CPU(u64, ia64_mca_pal_base);
+const extern unsigned int relocate_new_kernel_size;
+extern void relocate_new_kernel(unsigned long, unsigned long,
+                struct ia64_boot_param *, unsigned long);
+static inline void
+crash_setup_regs(struct pt_regs *newregs, struct pt_regs *oldregs)
+{
+}
+extern struct resource efi_memmap_res;
+extern struct resource boot_param_res;
+extern void kdump_smp_send_stop(void);
+extern void kdump_smp_send_init(void);
+extern void kexec_disable_iosapic(void);
+extern void crash_save_this_cpu(void);
+struct rsvd_region;
+extern unsigned long kdump_find_rsvd_region(unsigned long size,
+                struct rsvd_region *rsvd_regions, int n);
+extern void kdump_cpu_freeze(struct unw_frame_info *info, void *arg);
+extern int kdump_status[];
+extern atomic_t kdump_cpu_freezed;
+extern atomic_t kdump_in_progress;
+
+#endif /* _ASM_IA64_KEXEC_H */
diff --git a/include/asm-ia64/machvec.h b/include/asm-ia64/machvec.h
index 8f784f8e45b0..a3891eb3f217 100644
--- a/include/asm-ia64/machvec.h
+++ b/include/asm-ia64/machvec.h
@@ -37,6 +37,7 @@ typedef int ia64_mv_pci_legacy_write_t (struct pci_bus *, u16 port, u32 val,
                                         u8 size);
 typedef void ia64_mv_migrate_t(struct task_struct * task);
 typedef void ia64_mv_pci_fixup_bus_t (struct pci_bus *);
+typedef void ia64_mv_kernel_launch_event_t(void);
 
 /* DMA-mapping interface: */
 typedef void ia64_mv_dma_init (void);
@@ -218,6 +219,7 @@ struct ia64_machine_vector {
         ia64_mv_setup_msi_irq_t *setup_msi_irq;
         ia64_mv_teardown_msi_irq_t *teardown_msi_irq;
         ia64_mv_pci_fixup_bus_t *pci_fixup_bus;
+        ia64_mv_kernel_launch_event_t *kernel_launch_event;
 } __attribute__((__aligned__(16))); /* align attrib? see above comment */
 
 #define MACHVEC_INIT(name)                      \
@@ -318,6 +320,9 @@ extern ia64_mv_dma_supported		swiotlb_dma_supported;
 #ifndef platform_tlb_migrate_finish
 # define platform_tlb_migrate_finish    machvec_noop_mm
 #endif
+#ifndef platform_kernel_launch_event
+# define platform_kernel_launch_event   machvec_noop
+#endif
 #ifndef platform_dma_init
 # define platform_dma_init              swiotlb_init
 #endif
diff --git a/include/asm-ia64/machvec_sn2.h b/include/asm-ia64/machvec_sn2.h
index 83325f6db03e..eaa2fce0fecd 100644
--- a/include/asm-ia64/machvec_sn2.h
+++ b/include/asm-ia64/machvec_sn2.h
@@ -67,6 +67,7 @@ extern ia64_mv_dma_sync_sg_for_device	sn_dma_sync_sg_for_device;
 extern ia64_mv_dma_mapping_error        sn_dma_mapping_error;
 extern ia64_mv_dma_supported            sn_dma_supported;
 extern ia64_mv_migrate_t                sn_migrate;
+extern ia64_mv_kernel_launch_event_t    sn_kernel_launch_event;
 extern ia64_mv_setup_msi_irq_t          sn_setup_msi_irq;
 extern ia64_mv_teardown_msi_irq_t       sn_teardown_msi_irq;
 extern ia64_mv_pci_fixup_bus_t          sn_pci_fixup_bus;
@@ -121,6 +122,7 @@ extern ia64_mv_pci_fixup_bus_t		sn_pci_fixup_bus;
 #define platform_dma_mapping_error              sn_dma_mapping_error
 #define platform_dma_supported          sn_dma_supported
 #define platform_migrate                sn_migrate
+#define platform_kernel_launch_event    sn_kernel_launch_event
 #ifdef CONFIG_PCI_MSI
 #define platform_setup_msi_irq          sn_setup_msi_irq
 #define platform_teardown_msi_irq       sn_teardown_msi_irq
diff --git a/include/asm-ia64/meminit.h b/include/asm-ia64/meminit.h
index c3b1f862e6e7..c8df75901083 100644
--- a/include/asm-ia64/meminit.h
+++ b/include/asm-ia64/meminit.h
@@ -15,11 +15,12 @@
  *      - initrd (optional)
  *      - command line string
  *      - kernel code & data
+ *      - crash dumping code reserved region
  *      - Kernel memory map built from EFI memory map
  *
  * More could be added if necessary
  */
-#define IA64_MAX_RSVD_REGIONS 6
+#define IA64_MAX_RSVD_REGIONS 7
 
 struct rsvd_region {
         unsigned long start;    /* virtual address of beginning of element */
diff --git a/include/asm-ia64/page.h b/include/asm-ia64/page.h
index 947cb72b520e..485759ba9e36 100644
--- a/include/asm-ia64/page.h
+++ b/include/asm-ia64/page.h
@@ -101,7 +101,7 @@ do {						\
 
 #ifdef CONFIG_VIRTUAL_MEM_MAP
 extern int ia64_pfn_valid (unsigned long pfn);
-#elif defined(CONFIG_FLATMEM)
+#else
 # define ia64_pfn_valid(pfn) 1
 #endif
 
@@ -110,12 +110,11 @@ extern struct page *vmem_map;
 #ifdef CONFIG_DISCONTIGMEM
 # define page_to_pfn(page)      ((unsigned long) (page - vmem_map))
 # define pfn_to_page(pfn)       (vmem_map + (pfn))
+#else
+# include <asm-generic/memory_model.h>
 #endif
-#endif
-
-#if defined(CONFIG_FLATMEM) || defined(CONFIG_SPARSEMEM)
-/* FLATMEM always configures mem_map (mem_map = vmem_map if necessary) */
-#include <asm-generic/memory_model.h>
+#else
+# include <asm-generic/memory_model.h>
 #endif
 
 #ifdef CONFIG_FLATMEM
diff --git a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h
index 4283ddcc25fb..bc768153f3c9 100644
--- a/include/asm-ia64/pal.h
+++ b/include/asm-ia64/pal.h
@@ -20,6 +20,8 @@
  * 00/05/24     eranian Updated to latest PAL spec, fix structures bugs, added
  * 00/05/25     eranian Support for stack calls, and static physical calls
  * 00/06/18     eranian Support for stacked physical calls
+ * 06/10/26     rja     Support for Intel Itanium Architecture Software Developer's
+ *                      Manual Rev 2.2 (Jan 2006)
  */
 
 /*
@@ -69,6 +71,8 @@
 #define PAL_PREFETCH_VISIBILITY 41      /* Make Processor Prefetches Visible */
 #define PAL_LOGICAL_TO_PHYSICAL 42      /* returns information on logical to physical processor mapping */
 #define PAL_CACHE_SHARED_INFO   43      /* returns information on caches shared by logical processor */
+#define PAL_GET_HW_POLICY       48      /* Get current hardware resource sharing policy */
+#define PAL_SET_HW_POLICY       49      /* Set current hardware resource sharing policy */
 
 #define PAL_COPY_PAL            256     /* relocate PAL procedures and PAL PMI */
 #define PAL_HALT_INFO           257     /* return the low power capabilities of processor */
@@ -80,6 +84,11 @@
 #define PAL_SET_PSTATE          263     /* set the P-state */
 #define PAL_BRAND_INFO          274     /* Processor branding information */
 
+#define PAL_GET_PSTATE_TYPE_LASTSET     0
+#define PAL_GET_PSTATE_TYPE_AVGANDRESET 1
+#define PAL_GET_PSTATE_TYPE_AVGNORESET  2
+#define PAL_GET_PSTATE_TYPE_INSTANT     3
+
 #ifndef __ASSEMBLY__
 
 #include <linux/types.h>
@@ -102,6 +111,7 @@ typedef s64				pal_status_t;
                                                  * cache without sideeffects
                                                  * and "restrict" was 1
                                                  */
+#define PAL_STATUS_REQUIRES_MEMORY      (-9)    /* Call requires PAL memory buffer */
 
 /* Processor cache level in the heirarchy */
 typedef u64                             pal_cache_level_t;
@@ -456,7 +466,9 @@ typedef struct pal_process_state_info_s {
                                                  * by the processor
                                                  */
 
-                        reserved2       : 11,
+                        se              : 1,    /* Shared error.  MCA in a
+                                                   shared structure */
+                        reserved2       : 10,
                         cc              : 1,    /* Cache check */
                         tc              : 1,    /* TLB check */
                         bc              : 1,    /* Bus check */
@@ -487,10 +499,12 @@ typedef struct pal_cache_check_info_s {
                                                  * error occurred
                                                  */
                         wiv             : 1,    /* Way field valid */
-                        reserved2       : 10,
+                        reserved2       : 1,
+                        dp              : 1,    /* Data poisoned on MBE */
+                        reserved3       : 8,
 
                         index           : 20,   /* Cache line index */
-                        reserved3       : 2,
+                        reserved4       : 2,
 
                         is              : 1,    /* instruction set (1 == ia32) */
                         iv              : 1,    /* instruction set field valid */
@@ -557,7 +571,7 @@ typedef struct pal_bus_check_info_s {
                         type            : 8,    /* Bus xaction type*/
                         sev             : 5,    /* Bus error severity*/
                         hier            : 2,    /* Bus hierarchy level */
-                        reserved1       : 1,
+                        dp              : 1,    /* Data poisoned on MBE */
                         bsi             : 8,    /* Bus error status
                                                  * info
                                                  */
@@ -834,7 +848,9 @@ typedef union pal_bus_features_u {
                 u64     pbf_req_bus_parking                     :       1;
                 u64     pbf_bus_lock_mask                       :       1;
                 u64     pbf_enable_half_xfer_rate               :       1;
-                u64     pbf_reserved2                           :       22;
+                u64     pbf_reserved2                           :       20;
+                u64     pbf_enable_shared_line_replace          :       1;
+                u64     pbf_enable_exclusive_line_replace       :       1;
                 u64     pbf_disable_xaction_queueing            :       1;
                 u64     pbf_disable_resp_err_check              :       1;
                 u64     pbf_disable_berr_check                  :       1;
@@ -1077,6 +1093,24 @@ ia64_pal_freq_ratios (struct pal_freq_ratio *proc_ratio, struct pal_freq_ratio *
         return iprv.status;
 }
 
+/*
+ * Get the current hardware resource sharing policy of the processor
+ */
+static inline s64
+ia64_pal_get_hw_policy (u64 proc_num, u64 *cur_policy, u64 *num_impacted,
+                        u64 *la)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_GET_HW_POLICY, proc_num, 0, 0);
+        if (cur_policy)
+                *cur_policy = iprv.v0;
+        if (num_impacted)
+                *num_impacted = iprv.v1;
+        if (la)
+                *la = iprv.v2;
+        return iprv.status;
+}
+
 /* Make the processor enter HALT or one of the implementation dependent low
  * power states where prefetching and execution are suspended and cache and
  * TLB coherency is not maintained.
@@ -1112,10 +1146,10 @@ ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf)
 
 /* Get the current P-state information */
 static inline s64
-ia64_pal_get_pstate (u64 *pstate_index)
+ia64_pal_get_pstate (u64 *pstate_index, unsigned long type)
 {
         struct ia64_pal_retval iprv;
-        PAL_CALL_STK(iprv, PAL_GET_PSTATE, 0, 0, 0);
+        PAL_CALL_STK(iprv, PAL_GET_PSTATE, type, 0, 0);
         *pstate_index = iprv.v0;
         return iprv.status;
 }
@@ -1401,6 +1435,17 @@ ia64_pal_rse_info (u64 *num_phys_stacked, pal_hints_u_t *hints)
         return iprv.status;
 }
 
+/*
+ * Set the current hardware resource sharing policy of the processor
+ */
+static inline s64
+ia64_pal_set_hw_policy (u64 policy)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_SET_HW_POLICY, policy, 0, 0);
+        return iprv.status;
+}
+
 /* Cause the processor to enter SHUTDOWN state, where prefetching and execution are
  * suspended, but cause cache and TLB coherency to be maintained.
  * This is usually called in IA-32 mode.
@@ -1524,12 +1569,15 @@ typedef union pal_vm_info_1_u {
         } pal_vm_info_1_s;
 } pal_vm_info_1_u_t;
 
+#define PAL_MAX_PURGES          0xFFFF          /* all ones is means unlimited */
+
 typedef union pal_vm_info_2_u {
         u64                     pvi2_val;
         struct {
                 u64             impl_va_msb     : 8,
                                 rid_size        : 8,
-                                reserved        : 48;
+                                max_purges      : 16,
+                                reserved        : 32;
         } pal_vm_info_2_s;
 } pal_vm_info_2_u_t;
 
diff --git a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h
index be5d83ad7cb1..2c4004eb5a68 100644
--- a/include/asm-ia64/sn/sn_sal.h
+++ b/include/asm-ia64/sn/sn_sal.h
@@ -88,6 +88,8 @@
 #define  SN_SAL_INJECT_ERROR                       0x02000067
 #define  SN_SAL_SET_CPU_NUMBER                     0x02000068
 
+#define  SN_SAL_KERNEL_LAUNCH_EVENT                0x02000069
+
 /*
  * Service-specific constants
  */
@@ -1155,4 +1157,11 @@ ia64_sn_set_cpu_number(int cpu)
         SAL_CALL_NOLOCK(rv, SN_SAL_SET_CPU_NUMBER, cpu, 0, 0, 0, 0, 0, 0);
         return rv.status;
 }
+static inline int
+ia64_sn_kernel_launch_event(void)
+{
+        struct ia64_sal_retval rv;
+        SAL_CALL_NOLOCK(rv, SN_SAL_KERNEL_LAUNCH_EVENT, 0, 0, 0, 0, 0, 0, 0);
+        return rv.status;
+}
 #endif /* _ASM_IA64_SN_SN_SAL_H */