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authorTony Luck <tony.luck@intel.com>2005-10-28 14:15:08 -0400
committerTony Luck <tony.luck@intel.com>2005-10-28 14:15:08 -0400
commit0d9136fdbcdbddcd4eb5ac94c248c039193d4795 (patch)
tree2e914c8afe019302199b5d807114e5b15835dc90 /include/asm-ia64/sn
parent9189674026e86e624b1ef1b4eb430e9ad19f9641 (diff)
parent1fa92957282e4595727c1a21bf6687ea5a2d612f (diff)
Pull altix-mmr into release branch
Diffstat (limited to 'include/asm-ia64/sn')
-rw-r--r--include/asm-ia64/sn/io.h9
-rw-r--r--include/asm-ia64/sn/tioca_provider.h14
2 files changed, 16 insertions, 7 deletions
diff --git a/include/asm-ia64/sn/io.h b/include/asm-ia64/sn/io.h
index 42209733f6b1..7597a52b426c 100644
--- a/include/asm-ia64/sn/io.h
+++ b/include/asm-ia64/sn/io.h
@@ -36,6 +36,15 @@ extern void sn_dma_flush(unsigned long);
36#define __sn_readq_relaxed ___sn_readq_relaxed 36#define __sn_readq_relaxed ___sn_readq_relaxed
37 37
38/* 38/*
39 * Convenience macros for setting/clearing bits using the above accessors
40 */
41
42#define __sn_setq_relaxed(addr, val) \
43 writeq((__sn_readq_relaxed(addr) | (val)), (addr))
44#define __sn_clrq_relaxed(addr, val) \
45 writeq((__sn_readq_relaxed(addr) & ~(val)), (addr))
46
47/*
39 * The following routines are SN Platform specific, called when 48 * The following routines are SN Platform specific, called when
40 * a reference is made to inX/outX set macros. SN Platform 49 * a reference is made to inX/outX set macros. SN Platform
41 * inX set of macros ensures that Posted DMA writes on the 50 * inX set of macros ensures that Posted DMA writes on the
diff --git a/include/asm-ia64/sn/tioca_provider.h b/include/asm-ia64/sn/tioca_provider.h
index 5ccec608d325..b532ef6148ed 100644
--- a/include/asm-ia64/sn/tioca_provider.h
+++ b/include/asm-ia64/sn/tioca_provider.h
@@ -182,11 +182,11 @@ tioca_tlbflush(struct tioca_kernel *tioca_kernel)
182 * touch every CL aligned GART entry. 182 * touch every CL aligned GART entry.
183 */ 183 */
184 184
185 ca_base->ca_control2 &= ~(CA_GART_MEM_PARAM); 185 __sn_clrq_relaxed(&ca_base->ca_control2, CA_GART_MEM_PARAM);
186 ca_base->ca_control2 |= CA_GART_FLUSH_TLB; 186 __sn_setq_relaxed(&ca_base->ca_control2, CA_GART_FLUSH_TLB);
187 ca_base->ca_control2 |= 187 __sn_setq_relaxed(&ca_base->ca_control2,
188 (0x2ull << CA_GART_MEM_PARAM_SHFT); 188 (0x2ull << CA_GART_MEM_PARAM_SHFT));
189 tmp = ca_base->ca_control2; 189 tmp = __sn_readq_relaxed(&ca_base->ca_control2);
190 } 190 }
191 191
192 return; 192 return;
@@ -196,8 +196,8 @@ tioca_tlbflush(struct tioca_kernel *tioca_kernel)
196 * Gart in uncached mode ... need an explicit flush. 196 * Gart in uncached mode ... need an explicit flush.
197 */ 197 */
198 198
199 ca_base->ca_control2 |= CA_GART_FLUSH_TLB; 199 __sn_setq_relaxed(&ca_base->ca_control2, CA_GART_FLUSH_TLB);
200 tmp = ca_base->ca_control2; 200 tmp = __sn_readq_relaxed(&ca_base->ca_control2);
201} 201}
202 202
203extern uint32_t tioca_gart_found; 203extern uint32_t tioca_gart_found;