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authorGreg Edwards <edwardsg@sgi.com>2005-08-22 12:57:00 -0400
committerTony Luck <tony.luck@intel.com>2005-08-24 18:37:26 -0400
commit1b66776da71e33dff5edcc0b096ec3b7c40c75ad (patch)
tree138e13ac97b8af1f52f7fa798bc8f29851b9e176 /include/asm-ia64/sn
parent0a41e2501160587eb8f66cef3bdf1c6f2cb86997 (diff)
[IA64] clean up sn2 region definitions
Clean up some duplicate region definitions in sn2 code. Signed-off-by: Greg Edwards <edwardsg@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'include/asm-ia64/sn')
-rw-r--r--include/asm-ia64/sn/addrs.h33
1 files changed, 12 insertions, 21 deletions
diff --git a/include/asm-ia64/sn/addrs.h b/include/asm-ia64/sn/addrs.h
index 103d745dc5f2..1163a6839bcb 100644
--- a/include/asm-ia64/sn/addrs.h
+++ b/include/asm-ia64/sn/addrs.h
@@ -65,7 +65,6 @@
65 65
66#define NASID_MASK ((u64)NASID_BITMASK << NASID_SHIFT) 66#define NASID_MASK ((u64)NASID_BITMASK << NASID_SHIFT)
67#define AS_MASK ((u64)AS_BITMASK << AS_SHIFT) 67#define AS_MASK ((u64)AS_BITMASK << AS_SHIFT)
68#define REGION_BITS 0xe000000000000000UL
69 68
70 69
71/* 70/*
@@ -79,38 +78,30 @@
79#define AS_CAC_SPACE (AS_CAC_VAL << AS_SHIFT) 78#define AS_CAC_SPACE (AS_CAC_VAL << AS_SHIFT)
80 79
81 80
82/*
83 * Base addresses for various address ranges.
84 */
85#define CACHED 0xe000000000000000UL
86#define UNCACHED 0xc000000000000000UL
87#define UNCACHED_PHYS 0x8000000000000000UL
88
89
90/* 81/*
91 * Virtual Mode Local & Global MMR space. 82 * Virtual Mode Local & Global MMR space.
92 */ 83 */
93#define SH1_LOCAL_MMR_OFFSET 0x8000000000UL 84#define SH1_LOCAL_MMR_OFFSET 0x8000000000UL
94#define SH2_LOCAL_MMR_OFFSET 0x0200000000UL 85#define SH2_LOCAL_MMR_OFFSET 0x0200000000UL
95#define LOCAL_MMR_OFFSET (is_shub2() ? SH2_LOCAL_MMR_OFFSET : SH1_LOCAL_MMR_OFFSET) 86#define LOCAL_MMR_OFFSET (is_shub2() ? SH2_LOCAL_MMR_OFFSET : SH1_LOCAL_MMR_OFFSET)
96#define LOCAL_MMR_SPACE (UNCACHED | LOCAL_MMR_OFFSET) 87#define LOCAL_MMR_SPACE (__IA64_UNCACHED_OFFSET | LOCAL_MMR_OFFSET)
97#define LOCAL_PHYS_MMR_SPACE (UNCACHED_PHYS | LOCAL_MMR_OFFSET) 88#define LOCAL_PHYS_MMR_SPACE (RGN_BASE(RGN_HPAGE) | LOCAL_MMR_OFFSET)
98 89
99#define SH1_GLOBAL_MMR_OFFSET 0x0800000000UL 90#define SH1_GLOBAL_MMR_OFFSET 0x0800000000UL
100#define SH2_GLOBAL_MMR_OFFSET 0x0300000000UL 91#define SH2_GLOBAL_MMR_OFFSET 0x0300000000UL
101#define GLOBAL_MMR_OFFSET (is_shub2() ? SH2_GLOBAL_MMR_OFFSET : SH1_GLOBAL_MMR_OFFSET) 92#define GLOBAL_MMR_OFFSET (is_shub2() ? SH2_GLOBAL_MMR_OFFSET : SH1_GLOBAL_MMR_OFFSET)
102#define GLOBAL_MMR_SPACE (UNCACHED | GLOBAL_MMR_OFFSET) 93#define GLOBAL_MMR_SPACE (__IA64_UNCACHED_OFFSET | GLOBAL_MMR_OFFSET)
103 94
104/* 95/*
105 * Physical mode addresses 96 * Physical mode addresses
106 */ 97 */
107#define GLOBAL_PHYS_MMR_SPACE (UNCACHED_PHYS | GLOBAL_MMR_OFFSET) 98#define GLOBAL_PHYS_MMR_SPACE (RGN_BASE(RGN_HPAGE) | GLOBAL_MMR_OFFSET)
108 99
109 100
110/* 101/*
111 * Clear region & AS bits. 102 * Clear region & AS bits.
112 */ 103 */
113#define TO_PHYS_MASK (~(REGION_BITS | AS_MASK)) 104#define TO_PHYS_MASK (~(RGN_BITS | AS_MASK))
114 105
115 106
116/* 107/*
@@ -134,10 +125,10 @@
134/* 125/*
135 * general address defines 126 * general address defines
136 */ 127 */
137#define CAC_BASE (CACHED | AS_CAC_SPACE) 128#define CAC_BASE (PAGE_OFFSET | AS_CAC_SPACE)
138#define AMO_BASE (UNCACHED | AS_AMO_SPACE) 129#define AMO_BASE (__IA64_UNCACHED_OFFSET | AS_AMO_SPACE)
139#define AMO_PHYS_BASE (UNCACHED_PHYS | AS_AMO_SPACE) 130#define AMO_PHYS_BASE (RGN_BASE(RGN_HPAGE) | AS_AMO_SPACE)
140#define GET_BASE (CACHED | AS_GET_SPACE) 131#define GET_BASE (PAGE_OFFSET | AS_GET_SPACE)
141 132
142/* 133/*
143 * Convert Memory addresses between various addressing modes. 134 * Convert Memory addresses between various addressing modes.
@@ -164,8 +155,8 @@
164/* 155/*
165 * Macros to test for address type. 156 * Macros to test for address type.
166 */ 157 */
167#define IS_AMO_ADDRESS(x) (((u64)(x) & (REGION_BITS | AS_MASK)) == AMO_BASE) 158#define IS_AMO_ADDRESS(x) (((u64)(x) & (RGN_BITS | AS_MASK)) == AMO_BASE)
168#define IS_AMO_PHYS_ADDRESS(x) (((u64)(x) & (REGION_BITS | AS_MASK)) == AMO_PHYS_BASE) 159#define IS_AMO_PHYS_ADDRESS(x) (((u64)(x) & (RGN_BITS | AS_MASK)) == AMO_PHYS_BASE)
169 160
170 161
171/* 162/*
@@ -180,7 +171,7 @@
180#define TIO_SWIN_BASE(n, w) (TIO_IO_BASE(n) + \ 171#define TIO_SWIN_BASE(n, w) (TIO_IO_BASE(n) + \
181 ((u64) (w) << TIO_SWIN_SIZE_BITS)) 172 ((u64) (w) << TIO_SWIN_SIZE_BITS))
182#define NODE_IO_BASE(n) (GLOBAL_MMR_SPACE | NASID_SPACE(n)) 173#define NODE_IO_BASE(n) (GLOBAL_MMR_SPACE | NASID_SPACE(n))
183#define TIO_IO_BASE(n) (UNCACHED | NASID_SPACE(n)) 174#define TIO_IO_BASE(n) (__IA64_UNCACHED_OFFSET | NASID_SPACE(n))
184#define BWIN_SIZE (1UL << BWIN_SIZE_BITS) 175#define BWIN_SIZE (1UL << BWIN_SIZE_BITS)
185#define NODE_BWIN_BASE0(n) (NODE_IO_BASE(n) + BWIN_SIZE) 176#define NODE_BWIN_BASE0(n) (NODE_IO_BASE(n) + BWIN_SIZE)
186#define NODE_BWIN_BASE(n, w) (NODE_BWIN_BASE0(n) + ((u64) (w) << BWIN_SIZE_BITS)) 177#define NODE_BWIN_BASE(n, w) (NODE_BWIN_BASE0(n) + ((u64) (w) << BWIN_SIZE_BITS))