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authorJeff Garzik <jgarzik@pobox.com>2005-08-10 13:46:28 -0400
committerJeff Garzik <jgarzik@pobox.com>2005-08-10 13:46:28 -0400
commit2f058256cb64e346f4fb4499ff4e0f1c2791a4b4 (patch)
tree91e06602f4d3abb6812ea8c9bc9ba4501e14c84e /include/asm-ia64/sn
parent0274aa2506fd2fe89a58dd6cd64d3b3f7b976af8 (diff)
parent86b3786078d63242d3194ffc58ae8dae1d1bbef3 (diff)
Merge /spare/repo/linux-2.6/
Diffstat (limited to 'include/asm-ia64/sn')
-rw-r--r--include/asm-ia64/sn/addrs.h17
-rw-r--r--include/asm-ia64/sn/arch.h1
-rw-r--r--include/asm-ia64/sn/intr.h6
-rw-r--r--include/asm-ia64/sn/l1.h1
-rw-r--r--include/asm-ia64/sn/pcibr_provider.h159
-rw-r--r--include/asm-ia64/sn/pcibus_provider_defs.h3
-rw-r--r--include/asm-ia64/sn/pcidev.h16
-rw-r--r--include/asm-ia64/sn/pic.h261
-rw-r--r--include/asm-ia64/sn/shub_mmr.h346
-rw-r--r--include/asm-ia64/sn/simulator.h16
-rw-r--r--include/asm-ia64/sn/sn2/sn_hwperf.h2
-rw-r--r--include/asm-ia64/sn/sn_cpuid.h5
-rw-r--r--include/asm-ia64/sn/sn_sal.h47
-rw-r--r--include/asm-ia64/sn/tioca_provider.h1
-rw-r--r--include/asm-ia64/sn/tiocp.h256
-rw-r--r--include/asm-ia64/sn/xp.h1
16 files changed, 913 insertions, 225 deletions
diff --git a/include/asm-ia64/sn/addrs.h b/include/asm-ia64/sn/addrs.h
index 1bfdfb4d7b01..103d745dc5f2 100644
--- a/include/asm-ia64/sn/addrs.h
+++ b/include/asm-ia64/sn/addrs.h
@@ -216,6 +216,10 @@
216#define TIO_SWIN_WIDGETNUM(x) (((x) >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK) 216#define TIO_SWIN_WIDGETNUM(x) (((x) >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK)
217 217
218 218
219#define TIO_IOSPACE_ADDR(n,x) \
220 /* Move in the Chiplet ID for TIO Local Block MMR */ \
221 (REMOTE_ADDR(n,x) | 1UL << (NASID_SHIFT - 2))
222
219/* 223/*
220 * The following macros produce the correct base virtual address for 224 * The following macros produce the correct base virtual address for
221 * the hub registers. The REMOTE_HUB_* macro produce 225 * the hub registers. The REMOTE_HUB_* macro produce
@@ -233,13 +237,16 @@
233#define REMOTE_HUB_ADDR(n,x) \ 237#define REMOTE_HUB_ADDR(n,x) \
234 ((n & 1) ? \ 238 ((n & 1) ? \
235 /* TIO: */ \ 239 /* TIO: */ \
236 ((volatile u64 *)(GLOBAL_MMR_ADDR(n,x))) \ 240 (is_shub2() ? \
237 : /* SHUB: */ \ 241 /* TIO on Shub2 */ \
238 (((x) & BWIN_TOP) ? ((volatile u64 *)(GLOBAL_MMR_ADDR(n,x)))\ 242 (volatile u64 *)(TIO_IOSPACE_ADDR(n,x)) \
243 : /* TIO on shub1 */ \
244 (volatile u64 *)(GLOBAL_MMR_ADDR(n,x))) \
245 \
246 : /* SHUB1 and SHUB2 MMRs: */ \
247 (((x) & BWIN_TOP) ? ((volatile u64 *)(GLOBAL_MMR_ADDR(n,x))) \
239 : ((volatile u64 *)(NODE_SWIN_BASE(n,1) + 0x800000 + (x))))) 248 : ((volatile u64 *)(NODE_SWIN_BASE(n,1) + 0x800000 + (x)))))
240 249
241
242
243#define HUB_L(x) (*((volatile typeof(*x) *)x)) 250#define HUB_L(x) (*((volatile typeof(*x) *)x))
244#define HUB_S(x,d) (*((volatile typeof(*x) *)x) = (d)) 251#define HUB_S(x,d) (*((volatile typeof(*x) *)x) = (d))
245 252
diff --git a/include/asm-ia64/sn/arch.h b/include/asm-ia64/sn/arch.h
index 635fdce854a8..ab827d298569 100644
--- a/include/asm-ia64/sn/arch.h
+++ b/include/asm-ia64/sn/arch.h
@@ -11,6 +11,7 @@
11#ifndef _ASM_IA64_SN_ARCH_H 11#ifndef _ASM_IA64_SN_ARCH_H
12#define _ASM_IA64_SN_ARCH_H 12#define _ASM_IA64_SN_ARCH_H
13 13
14#include <linux/numa.h>
14#include <asm/types.h> 15#include <asm/types.h>
15#include <asm/percpu.h> 16#include <asm/percpu.h>
16#include <asm/sn/types.h> 17#include <asm/sn/types.h>
diff --git a/include/asm-ia64/sn/intr.h b/include/asm-ia64/sn/intr.h
index e51471fb0867..e190dd4213d5 100644
--- a/include/asm-ia64/sn/intr.h
+++ b/include/asm-ia64/sn/intr.h
@@ -9,6 +9,8 @@
9#ifndef _ASM_IA64_SN_INTR_H 9#ifndef _ASM_IA64_SN_INTR_H
10#define _ASM_IA64_SN_INTR_H 10#define _ASM_IA64_SN_INTR_H
11 11
12#include <linux/rcupdate.h>
13
12#define SGI_UART_VECTOR (0xe9) 14#define SGI_UART_VECTOR (0xe9)
13#define SGI_PCIBR_ERROR (0x33) 15#define SGI_PCIBR_ERROR (0x33)
14 16
@@ -33,7 +35,7 @@
33 35
34// The SN PROM irq struct 36// The SN PROM irq struct
35struct sn_irq_info { 37struct sn_irq_info {
36 struct sn_irq_info *irq_next; /* sharing irq list */ 38 struct sn_irq_info *irq_next; /* deprecated DO NOT USE */
37 short irq_nasid; /* Nasid IRQ is assigned to */ 39 short irq_nasid; /* Nasid IRQ is assigned to */
38 int irq_slice; /* slice IRQ is assigned to */ 40 int irq_slice; /* slice IRQ is assigned to */
39 int irq_cpuid; /* kernel logical cpuid */ 41 int irq_cpuid; /* kernel logical cpuid */
@@ -47,6 +49,8 @@ struct sn_irq_info {
47 int irq_cookie; /* unique cookie */ 49 int irq_cookie; /* unique cookie */
48 int irq_flags; /* flags */ 50 int irq_flags; /* flags */
49 int irq_share_cnt; /* num devices sharing IRQ */ 51 int irq_share_cnt; /* num devices sharing IRQ */
52 struct list_head list; /* list of sn_irq_info structs */
53 struct rcu_head rcu; /* rcu callback list */
50}; 54};
51 55
52extern void sn_send_IPI_phys(int, long, int, int); 56extern void sn_send_IPI_phys(int, long, int, int);
diff --git a/include/asm-ia64/sn/l1.h b/include/asm-ia64/sn/l1.h
index 08050d37b662..2e5f0aa38889 100644
--- a/include/asm-ia64/sn/l1.h
+++ b/include/asm-ia64/sn/l1.h
@@ -33,5 +33,6 @@
33#define L1_BRICKTYPE_PA 0x6a /* j */ 33#define L1_BRICKTYPE_PA 0x6a /* j */
34#define L1_BRICKTYPE_IA 0x6b /* k */ 34#define L1_BRICKTYPE_IA 0x6b /* k */
35#define L1_BRICKTYPE_ATHENA 0x2b /* + */ 35#define L1_BRICKTYPE_ATHENA 0x2b /* + */
36#define L1_BRICKTYPE_DAYTONA 0x7a /* z */
36 37
37#endif /* _ASM_IA64_SN_L1_H */ 38#endif /* _ASM_IA64_SN_L1_H */
diff --git a/include/asm-ia64/sn/pcibr_provider.h b/include/asm-ia64/sn/pcibr_provider.h
new file mode 100644
index 000000000000..2b42d9ece26b
--- /dev/null
+++ b/include/asm-ia64/sn/pcibr_provider.h
@@ -0,0 +1,159 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992-1997,2000-2004 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
9#define _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
10
11#include <asm/sn/intr.h>
12#include <asm/sn/pcibus_provider_defs.h>
13
14/* Workarounds */
15#define PV907516 (1 << 1) /* TIOCP: Don't write the write buffer flush reg */
16
17#define BUSTYPE_MASK 0x1
18
19/* Macros given a pcibus structure */
20#define IS_PCIX(ps) ((ps)->pbi_bridge_mode & BUSTYPE_MASK)
21#define IS_PCI_BRIDGE_ASIC(asic) (asic == PCIIO_ASIC_TYPE_PIC || \
22 asic == PCIIO_ASIC_TYPE_TIOCP)
23#define IS_PIC_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_PIC)
24
25
26/*
27 * The different PCI Bridge types supported on the SGI Altix platforms
28 */
29#define PCIBR_BRIDGETYPE_UNKNOWN -1
30#define PCIBR_BRIDGETYPE_PIC 2
31#define PCIBR_BRIDGETYPE_TIOCP 3
32
33/*
34 * Bridge 64bit Direct Map Attributes
35 */
36#define PCI64_ATTR_PREF (1ull << 59)
37#define PCI64_ATTR_PREC (1ull << 58)
38#define PCI64_ATTR_VIRTUAL (1ull << 57)
39#define PCI64_ATTR_BAR (1ull << 56)
40#define PCI64_ATTR_SWAP (1ull << 55)
41#define PCI64_ATTR_VIRTUAL1 (1ull << 54)
42
43#define PCI32_LOCAL_BASE 0
44#define PCI32_MAPPED_BASE 0x40000000
45#define PCI32_DIRECT_BASE 0x80000000
46
47#define IS_PCI32_MAPPED(x) ((uint64_t)(x) < PCI32_DIRECT_BASE && \
48 (uint64_t)(x) >= PCI32_MAPPED_BASE)
49#define IS_PCI32_DIRECT(x) ((uint64_t)(x) >= PCI32_MAPPED_BASE)
50
51
52/*
53 * Bridge PMU Address Transaltion Entry Attibutes
54 */
55#define PCI32_ATE_V (0x1 << 0)
56#define PCI32_ATE_CO (0x1 << 1)
57#define PCI32_ATE_PREC (0x1 << 2)
58#define PCI32_ATE_PREF (0x1 << 3)
59#define PCI32_ATE_BAR (0x1 << 4)
60#define PCI32_ATE_ADDR_SHFT 12
61
62#define MINIMAL_ATES_REQUIRED(addr, size) \
63 (IOPG(IOPGOFF(addr) + (size) - 1) == IOPG((size) - 1))
64
65#define MINIMAL_ATE_FLAG(addr, size) \
66 (MINIMAL_ATES_REQUIRED((uint64_t)addr, size) ? 1 : 0)
67
68/* bit 29 of the pci address is the SWAP bit */
69#define ATE_SWAPSHIFT 29
70#define ATE_SWAP_ON(x) ((x) |= (1 << ATE_SWAPSHIFT))
71#define ATE_SWAP_OFF(x) ((x) &= ~(1 << ATE_SWAPSHIFT))
72
73/*
74 * I/O page size
75 */
76#if PAGE_SIZE < 16384
77#define IOPFNSHIFT 12 /* 4K per mapped page */
78#else
79#define IOPFNSHIFT 14 /* 16K per mapped page */
80#endif
81
82#define IOPGSIZE (1 << IOPFNSHIFT)
83#define IOPG(x) ((x) >> IOPFNSHIFT)
84#define IOPGOFF(x) ((x) & (IOPGSIZE-1))
85
86#define PCIBR_DEV_SWAP_DIR (1ull << 19)
87#define PCIBR_CTRL_PAGE_SIZE (0x1 << 21)
88
89/*
90 * PMU resources.
91 */
92struct ate_resource{
93 uint64_t *ate;
94 uint64_t num_ate;
95 uint64_t lowest_free_index;
96};
97
98struct pcibus_info {
99 struct pcibus_bussoft pbi_buscommon; /* common header */
100 uint32_t pbi_moduleid;
101 short pbi_bridge_type;
102 short pbi_bridge_mode;
103
104 struct ate_resource pbi_int_ate_resource;
105 uint64_t pbi_int_ate_size;
106
107 uint64_t pbi_dir_xbase;
108 char pbi_hub_xid;
109
110 uint64_t pbi_devreg[8];
111
112 uint32_t pbi_valid_devices;
113 uint32_t pbi_enabled_devices;
114
115 spinlock_t pbi_lock;
116};
117
118/*
119 * pcibus_info structure locking macros
120 */
121inline static unsigned long
122pcibr_lock(struct pcibus_info *pcibus_info)
123{
124 unsigned long flag;
125 spin_lock_irqsave(&pcibus_info->pbi_lock, flag);
126 return(flag);
127}
128#define pcibr_unlock(pcibus_info, flag) spin_unlock_irqrestore(&pcibus_info->pbi_lock, flag)
129
130extern int pcibr_init_provider(void);
131extern void *pcibr_bus_fixup(struct pcibus_bussoft *, struct pci_controller *);
132extern dma_addr_t pcibr_dma_map(struct pci_dev *, unsigned long, size_t);
133extern dma_addr_t pcibr_dma_map_consistent(struct pci_dev *, unsigned long, size_t);
134extern void pcibr_dma_unmap(struct pci_dev *, dma_addr_t, int);
135
136/*
137 * prototypes for the bridge asic register access routines in pcibr_reg.c
138 */
139extern void pcireg_control_bit_clr(struct pcibus_info *, uint64_t);
140extern void pcireg_control_bit_set(struct pcibus_info *, uint64_t);
141extern uint64_t pcireg_tflush_get(struct pcibus_info *);
142extern uint64_t pcireg_intr_status_get(struct pcibus_info *);
143extern void pcireg_intr_enable_bit_clr(struct pcibus_info *, uint64_t);
144extern void pcireg_intr_enable_bit_set(struct pcibus_info *, uint64_t);
145extern void pcireg_intr_addr_addr_set(struct pcibus_info *, int, uint64_t);
146extern void pcireg_force_intr_set(struct pcibus_info *, int);
147extern uint64_t pcireg_wrb_flush_get(struct pcibus_info *, int);
148extern void pcireg_int_ate_set(struct pcibus_info *, int, uint64_t);
149extern uint64_t * pcireg_int_ate_addr(struct pcibus_info *, int);
150extern void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info);
151extern void pcibr_change_devices_irq(struct sn_irq_info *sn_irq_info);
152extern int pcibr_ate_alloc(struct pcibus_info *, int);
153extern void pcibr_ate_free(struct pcibus_info *, int);
154extern void ate_write(struct pcibus_info *, int, int, uint64_t);
155extern int sal_pcibr_slot_enable(struct pcibus_info *soft, int device,
156 void *resp);
157extern int sal_pcibr_slot_disable(struct pcibus_info *soft, int device,
158 int action, void *resp);
159#endif
diff --git a/include/asm-ia64/sn/pcibus_provider_defs.h b/include/asm-ia64/sn/pcibus_provider_defs.h
index 04e27d5b3820..976f5eff0539 100644
--- a/include/asm-ia64/sn/pcibus_provider_defs.h
+++ b/include/asm-ia64/sn/pcibus_provider_defs.h
@@ -37,6 +37,7 @@ struct pcibus_bussoft {
37 struct xwidget_info *bs_xwidget_info; 37 struct xwidget_info *bs_xwidget_info;
38}; 38};
39 39
40struct pci_controller;
40/* 41/*
41 * SN pci bus indirection 42 * SN pci bus indirection
42 */ 43 */
@@ -45,7 +46,7 @@ struct sn_pcibus_provider {
45 dma_addr_t (*dma_map)(struct pci_dev *, unsigned long, size_t); 46 dma_addr_t (*dma_map)(struct pci_dev *, unsigned long, size_t);
46 dma_addr_t (*dma_map_consistent)(struct pci_dev *, unsigned long, size_t); 47 dma_addr_t (*dma_map_consistent)(struct pci_dev *, unsigned long, size_t);
47 void (*dma_unmap)(struct pci_dev *, dma_addr_t, int); 48 void (*dma_unmap)(struct pci_dev *, dma_addr_t, int);
48 void * (*bus_fixup)(struct pcibus_bussoft *); 49 void * (*bus_fixup)(struct pcibus_bussoft *, struct pci_controller *);
49}; 50};
50 51
51extern struct sn_pcibus_provider *sn_pci_provider[]; 52extern struct sn_pcibus_provider *sn_pci_provider[];
diff --git a/include/asm-ia64/sn/pcidev.h b/include/asm-ia64/sn/pcidev.h
index ed4031d80811..49711d00ad04 100644
--- a/include/asm-ia64/sn/pcidev.h
+++ b/include/asm-ia64/sn/pcidev.h
@@ -10,11 +10,11 @@
10 10
11#include <linux/pci.h> 11#include <linux/pci.h>
12 12
13extern struct sn_irq_info **sn_irq;
14
15#define SN_PCIDEV_INFO(pci_dev) \ 13#define SN_PCIDEV_INFO(pci_dev) \
16 ((struct pcidev_info *)(pci_dev)->sysdata) 14 ((struct pcidev_info *)(pci_dev)->sysdata)
17 15
16#define SN_PCIBUS_BUSSOFT_INFO(pci_bus) \
17 (struct pcibus_info *)((struct pcibus_bussoft *)(PCI_CONTROLLER((pci_bus))->platform_data))
18/* 18/*
19 * Given a pci_bus, return the sn pcibus_bussoft struct. Note that 19 * Given a pci_bus, return the sn pcibus_bussoft struct. Note that
20 * this only works for root busses, not for busses represented by PPB's. 20 * this only works for root busses, not for busses represented by PPB's.
@@ -23,6 +23,8 @@ extern struct sn_irq_info **sn_irq;
23#define SN_PCIBUS_BUSSOFT(pci_bus) \ 23#define SN_PCIBUS_BUSSOFT(pci_bus) \
24 ((struct pcibus_bussoft *)(PCI_CONTROLLER((pci_bus))->platform_data)) 24 ((struct pcibus_bussoft *)(PCI_CONTROLLER((pci_bus))->platform_data))
25 25
26#define SN_PCIBUS_BUSSOFT_INFO(pci_bus) \
27 (struct pcibus_info *)((struct pcibus_bussoft *)(PCI_CONTROLLER((pci_bus))->platform_data))
26/* 28/*
27 * Given a struct pci_dev, return the sn pcibus_bussoft struct. Note 29 * Given a struct pci_dev, return the sn pcibus_bussoft struct. Note
28 * that this is not equivalent to SN_PCIBUS_BUSSOFT(pci_dev->bus) due 30 * that this is not equivalent to SN_PCIBUS_BUSSOFT(pci_dev->bus) due
@@ -50,9 +52,17 @@ struct pcidev_info {
50 52
51 struct sn_irq_info *pdi_sn_irq_info; 53 struct sn_irq_info *pdi_sn_irq_info;
52 struct sn_pcibus_provider *pdi_provider; /* sn pci ops */ 54 struct sn_pcibus_provider *pdi_provider; /* sn pci ops */
55 struct pci_dev *host_pci_dev; /* host bus link */
53}; 56};
54 57
55extern void sn_irq_fixup(struct pci_dev *pci_dev, 58extern void sn_irq_fixup(struct pci_dev *pci_dev,
56 struct sn_irq_info *sn_irq_info); 59 struct sn_irq_info *sn_irq_info);
57 60extern void sn_irq_unfixup(struct pci_dev *pci_dev);
61extern void sn_pci_controller_fixup(int segment, int busnum,
62 struct pci_bus *bus);
63extern void sn_bus_store_sysdata(struct pci_dev *dev);
64extern void sn_bus_free_sysdata(void);
65extern void sn_pci_fixup_slot(struct pci_dev *dev);
66extern void sn_pci_unfixup_slot(struct pci_dev *dev);
67extern void sn_irq_lh_init(void);
58#endif /* _ASM_IA64_SN_PCI_PCIDEV_H */ 68#endif /* _ASM_IA64_SN_PCI_PCIDEV_H */
diff --git a/include/asm-ia64/sn/pic.h b/include/asm-ia64/sn/pic.h
new file mode 100644
index 000000000000..0de82e6b0893
--- /dev/null
+++ b/include/asm-ia64/sn/pic.h
@@ -0,0 +1,261 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_PCI_PIC_H
9#define _ASM_IA64_SN_PCI_PIC_H
10
11/*
12 * PIC AS DEVICE ZERO
13 * ------------------
14 *
15 * PIC handles PCI/X busses. PCI/X requires that the 'bridge' (i.e. PIC)
16 * be designated as 'device 0'. That is a departure from earlier SGI
17 * PCI bridges. Because of that we use config space 1 to access the
18 * config space of the first actual PCI device on the bus.
19 * Here's what the PIC manual says:
20 *
21 * The current PCI-X bus specification now defines that the parent
22 * hosts bus bridge (PIC for example) must be device 0 on bus 0. PIC
23 * reduced the total number of devices from 8 to 4 and removed the
24 * device registers and windows, now only supporting devices 0,1,2, and
25 * 3. PIC did leave all 8 configuration space windows. The reason was
26 * there was nothing to gain by removing them. Here in lies the problem.
27 * The device numbering we do using 0 through 3 is unrelated to the device
28 * numbering which PCI-X requires in configuration space. In the past we
29 * correlated Configs pace and our device space 0 <-> 0, 1 <-> 1, etc.
30 * PCI-X requires we start a 1, not 0 and currently the PX brick
31 * does associate our:
32 *
33 * device 0 with configuration space window 1,
34 * device 1 with configuration space window 2,
35 * device 2 with configuration space window 3,
36 * device 3 with configuration space window 4.
37 *
38 * The net effect is that all config space access are off-by-one with
39 * relation to other per-slot accesses on the PIC.
40 * Here is a table that shows some of that:
41 *
42 * Internal Slot#
43 * |
44 * | 0 1 2 3
45 * ----------|---------------------------------------
46 * config | 0x21000 0x22000 0x23000 0x24000
47 * |
48 * even rrb | 0[0] n/a 1[0] n/a [] == implied even/odd
49 * |
50 * odd rrb | n/a 0[1] n/a 1[1]
51 * |
52 * int dev | 00 01 10 11
53 * |
54 * ext slot# | 1 2 3 4
55 * ----------|---------------------------------------
56 */
57
58#define PIC_ATE_TARGETID_SHFT 8
59#define PIC_HOST_INTR_ADDR 0x0000FFFFFFFFFFFFUL
60#define PIC_PCI64_ATTR_TARG_SHFT 60
61
62
63/*****************************************************************************
64 *********************** PIC MMR structure mapping ***************************
65 *****************************************************************************/
66
67/* NOTE: PIC WAR. PV#854697. PIC does not allow writes just to [31:0]
68 * of a 64-bit register. When writing PIC registers, always write the
69 * entire 64 bits.
70 */
71
72struct pic {
73
74 /* 0x000000-0x00FFFF -- Local Registers */
75
76 /* 0x000000-0x000057 -- Standard Widget Configuration */
77 uint64_t p_wid_id; /* 0x000000 */
78 uint64_t p_wid_stat; /* 0x000008 */
79 uint64_t p_wid_err_upper; /* 0x000010 */
80 uint64_t p_wid_err_lower; /* 0x000018 */
81 #define p_wid_err p_wid_err_lower
82 uint64_t p_wid_control; /* 0x000020 */
83 uint64_t p_wid_req_timeout; /* 0x000028 */
84 uint64_t p_wid_int_upper; /* 0x000030 */
85 uint64_t p_wid_int_lower; /* 0x000038 */
86 #define p_wid_int p_wid_int_lower
87 uint64_t p_wid_err_cmdword; /* 0x000040 */
88 uint64_t p_wid_llp; /* 0x000048 */
89 uint64_t p_wid_tflush; /* 0x000050 */
90
91 /* 0x000058-0x00007F -- Bridge-specific Widget Configuration */
92 uint64_t p_wid_aux_err; /* 0x000058 */
93 uint64_t p_wid_resp_upper; /* 0x000060 */
94 uint64_t p_wid_resp_lower; /* 0x000068 */
95 #define p_wid_resp p_wid_resp_lower
96 uint64_t p_wid_tst_pin_ctrl; /* 0x000070 */
97 uint64_t p_wid_addr_lkerr; /* 0x000078 */
98
99 /* 0x000080-0x00008F -- PMU & MAP */
100 uint64_t p_dir_map; /* 0x000080 */
101 uint64_t _pad_000088; /* 0x000088 */
102
103 /* 0x000090-0x00009F -- SSRAM */
104 uint64_t p_map_fault; /* 0x000090 */
105 uint64_t _pad_000098; /* 0x000098 */
106
107 /* 0x0000A0-0x0000AF -- Arbitration */
108 uint64_t p_arb; /* 0x0000A0 */
109 uint64_t _pad_0000A8; /* 0x0000A8 */
110
111 /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
112 uint64_t p_ate_parity_err; /* 0x0000B0 */
113 uint64_t _pad_0000B8; /* 0x0000B8 */
114
115 /* 0x0000C0-0x0000FF -- PCI/GIO */
116 uint64_t p_bus_timeout; /* 0x0000C0 */
117 uint64_t p_pci_cfg; /* 0x0000C8 */
118 uint64_t p_pci_err_upper; /* 0x0000D0 */
119 uint64_t p_pci_err_lower; /* 0x0000D8 */
120 #define p_pci_err p_pci_err_lower
121 uint64_t _pad_0000E0[4]; /* 0x0000{E0..F8} */
122
123 /* 0x000100-0x0001FF -- Interrupt */
124 uint64_t p_int_status; /* 0x000100 */
125 uint64_t p_int_enable; /* 0x000108 */
126 uint64_t p_int_rst_stat; /* 0x000110 */
127 uint64_t p_int_mode; /* 0x000118 */
128 uint64_t p_int_device; /* 0x000120 */
129 uint64_t p_int_host_err; /* 0x000128 */
130 uint64_t p_int_addr[8]; /* 0x0001{30,,,68} */
131 uint64_t p_err_int_view; /* 0x000170 */
132 uint64_t p_mult_int; /* 0x000178 */
133 uint64_t p_force_always[8]; /* 0x0001{80,,,B8} */
134 uint64_t p_force_pin[8]; /* 0x0001{C0,,,F8} */
135
136 /* 0x000200-0x000298 -- Device */
137 uint64_t p_device[4]; /* 0x0002{00,,,18} */
138 uint64_t _pad_000220[4]; /* 0x0002{20,,,38} */
139 uint64_t p_wr_req_buf[4]; /* 0x0002{40,,,58} */
140 uint64_t _pad_000260[4]; /* 0x0002{60,,,78} */
141 uint64_t p_rrb_map[2]; /* 0x0002{80,,,88} */
142 #define p_even_resp p_rrb_map[0] /* 0x000280 */
143 #define p_odd_resp p_rrb_map[1] /* 0x000288 */
144 uint64_t p_resp_status; /* 0x000290 */
145 uint64_t p_resp_clear; /* 0x000298 */
146
147 uint64_t _pad_0002A0[12]; /* 0x0002{A0..F8} */
148
149 /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
150 struct {
151 uint64_t upper; /* 0x0003{00,,,F0} */
152 uint64_t lower; /* 0x0003{08,,,F8} */
153 } p_buf_addr_match[16];
154
155 /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
156 struct {
157 uint64_t flush_w_touch; /* 0x000{400,,,5C0} */
158 uint64_t flush_wo_touch; /* 0x000{408,,,5C8} */
159 uint64_t inflight; /* 0x000{410,,,5D0} */
160 uint64_t prefetch; /* 0x000{418,,,5D8} */
161 uint64_t total_pci_retry; /* 0x000{420,,,5E0} */
162 uint64_t max_pci_retry; /* 0x000{428,,,5E8} */
163 uint64_t max_latency; /* 0x000{430,,,5F0} */
164 uint64_t clear_all; /* 0x000{438,,,5F8} */
165 } p_buf_count[8];
166
167
168 /* 0x000600-0x0009FF -- PCI/X registers */
169 uint64_t p_pcix_bus_err_addr; /* 0x000600 */
170 uint64_t p_pcix_bus_err_attr; /* 0x000608 */
171 uint64_t p_pcix_bus_err_data; /* 0x000610 */
172 uint64_t p_pcix_pio_split_addr; /* 0x000618 */
173 uint64_t p_pcix_pio_split_attr; /* 0x000620 */
174 uint64_t p_pcix_dma_req_err_attr; /* 0x000628 */
175 uint64_t p_pcix_dma_req_err_addr; /* 0x000630 */
176 uint64_t p_pcix_timeout; /* 0x000638 */
177
178 uint64_t _pad_000640[120]; /* 0x000{640,,,9F8} */
179
180 /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
181 struct {
182 uint64_t p_buf_addr; /* 0x000{A00,,,AF0} */
183 uint64_t p_buf_attr; /* 0X000{A08,,,AF8} */
184 } p_pcix_read_buf_64[16];
185
186 struct {
187 uint64_t p_buf_addr; /* 0x000{B00,,,BE0} */
188 uint64_t p_buf_attr; /* 0x000{B08,,,BE8} */
189 uint64_t p_buf_valid; /* 0x000{B10,,,BF0} */
190 uint64_t __pad1; /* 0x000{B18,,,BF8} */
191 } p_pcix_write_buf_64[8];
192
193 /* End of Local Registers -- Start of Address Map space */
194
195 char _pad_000c00[0x010000 - 0x000c00];
196
197 /* 0x010000-0x011fff -- Internal ATE RAM (Auto Parity Generation) */
198 uint64_t p_int_ate_ram[1024]; /* 0x010000-0x011fff */
199
200 /* 0x012000-0x013fff -- Internal ATE RAM (Manual Parity Generation) */
201 uint64_t p_int_ate_ram_mp[1024]; /* 0x012000-0x013fff */
202
203 char _pad_014000[0x18000 - 0x014000];
204
205 /* 0x18000-0x197F8 -- PIC Write Request Ram */
206 uint64_t p_wr_req_lower[256]; /* 0x18000 - 0x187F8 */
207 uint64_t p_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */
208 uint64_t p_wr_req_parity[256]; /* 0x19000 - 0x197F8 */
209
210 char _pad_019800[0x20000 - 0x019800];
211
212 /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */
213 union {
214 uint8_t c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */
215 uint16_t s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */
216 uint32_t l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */
217 uint64_t d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */
218 union {
219 uint8_t c[0x100 / 1];
220 uint16_t s[0x100 / 2];
221 uint32_t l[0x100 / 4];
222 uint64_t d[0x100 / 8];
223 } f[8];
224 } p_type0_cfg_dev[8]; /* 0x02{0000,,,7FFF} */
225
226 /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
227 union {
228 uint8_t c[0x1000 / 1]; /* 0x028000-0x029000 */
229 uint16_t s[0x1000 / 2]; /* 0x028000-0x029000 */
230 uint32_t l[0x1000 / 4]; /* 0x028000-0x029000 */
231 uint64_t d[0x1000 / 8]; /* 0x028000-0x029000 */
232 union {
233 uint8_t c[0x100 / 1];
234 uint16_t s[0x100 / 2];
235 uint32_t l[0x100 / 4];
236 uint64_t d[0x100 / 8];
237 } f[8];
238 } p_type1_cfg; /* 0x028000-0x029000 */
239
240 char _pad_029000[0x030000-0x029000];
241
242 /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
243 union {
244 uint8_t c[8 / 1];
245 uint16_t s[8 / 2];
246 uint32_t l[8 / 4];
247 uint64_t d[8 / 8];
248 } p_pci_iack; /* 0x030000-0x030007 */
249
250 char _pad_030007[0x040000-0x030008];
251
252 /* 0x040000-0x030007 -- PCIX Special Cycle */
253 union {
254 uint8_t c[8 / 1];
255 uint16_t s[8 / 2];
256 uint32_t l[8 / 4];
257 uint64_t d[8 / 8];
258 } p_pcix_cycle; /* 0x040000-0x040007 */
259};
260
261#endif /* _ASM_IA64_SN_PCI_PIC_H */
diff --git a/include/asm-ia64/sn/shub_mmr.h b/include/asm-ia64/sn/shub_mmr.h
index 323fa0cd8d83..7de1d1d4b71a 100644
--- a/include/asm-ia64/sn/shub_mmr.h
+++ b/include/asm-ia64/sn/shub_mmr.h
@@ -14,96 +14,98 @@
14/* Register "SH_IPI_INT" */ 14/* Register "SH_IPI_INT" */
15/* SHub Inter-Processor Interrupt Registers */ 15/* SHub Inter-Processor Interrupt Registers */
16/* ==================================================================== */ 16/* ==================================================================== */
17#define SH1_IPI_INT 0x0000000110000380 17#define SH1_IPI_INT __IA64_UL_CONST(0x0000000110000380)
18#define SH2_IPI_INT 0x0000000010000380 18#define SH2_IPI_INT __IA64_UL_CONST(0x0000000010000380)
19 19
20/* SH_IPI_INT_TYPE */ 20/* SH_IPI_INT_TYPE */
21/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ 21/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
22#define SH_IPI_INT_TYPE_SHFT 0 22#define SH_IPI_INT_TYPE_SHFT 0
23#define SH_IPI_INT_TYPE_MASK 0x0000000000000007 23#define SH_IPI_INT_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
24 24
25/* SH_IPI_INT_AGT */ 25/* SH_IPI_INT_AGT */
26/* Description: Agent, must be 0 for SHub */ 26/* Description: Agent, must be 0 for SHub */
27#define SH_IPI_INT_AGT_SHFT 3 27#define SH_IPI_INT_AGT_SHFT 3
28#define SH_IPI_INT_AGT_MASK 0x0000000000000008 28#define SH_IPI_INT_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
29 29
30/* SH_IPI_INT_PID */ 30/* SH_IPI_INT_PID */
31/* Description: Processor ID, same setting as on targeted McKinley */ 31/* Description: Processor ID, same setting as on targeted McKinley */
32#define SH_IPI_INT_PID_SHFT 4 32#define SH_IPI_INT_PID_SHFT 4
33#define SH_IPI_INT_PID_MASK 0x00000000000ffff0 33#define SH_IPI_INT_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
34 34
35/* SH_IPI_INT_BASE */ 35/* SH_IPI_INT_BASE */
36/* Description: Optional interrupt vector area, 2MB aligned */ 36/* Description: Optional interrupt vector area, 2MB aligned */
37#define SH_IPI_INT_BASE_SHFT 21 37#define SH_IPI_INT_BASE_SHFT 21
38#define SH_IPI_INT_BASE_MASK 0x0003ffffffe00000 38#define SH_IPI_INT_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
39 39
40/* SH_IPI_INT_IDX */ 40/* SH_IPI_INT_IDX */
41/* Description: Targeted McKinley interrupt vector */ 41/* Description: Targeted McKinley interrupt vector */
42#define SH_IPI_INT_IDX_SHFT 52 42#define SH_IPI_INT_IDX_SHFT 52
43#define SH_IPI_INT_IDX_MASK 0x0ff0000000000000 43#define SH_IPI_INT_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
44 44
45/* SH_IPI_INT_SEND */ 45/* SH_IPI_INT_SEND */
46/* Description: Send Interrupt Message to PI, This generates a puls */ 46/* Description: Send Interrupt Message to PI, This generates a puls */
47#define SH_IPI_INT_SEND_SHFT 63 47#define SH_IPI_INT_SEND_SHFT 63
48#define SH_IPI_INT_SEND_MASK 0x8000000000000000 48#define SH_IPI_INT_SEND_MASK __IA64_UL_CONST(0x8000000000000000)
49 49
50/* ==================================================================== */ 50/* ==================================================================== */
51/* Register "SH_EVENT_OCCURRED" */ 51/* Register "SH_EVENT_OCCURRED" */
52/* SHub Interrupt Event Occurred */ 52/* SHub Interrupt Event Occurred */
53/* ==================================================================== */ 53/* ==================================================================== */
54#define SH1_EVENT_OCCURRED 0x0000000110010000 54#define SH1_EVENT_OCCURRED __IA64_UL_CONST(0x0000000110010000)
55#define SH1_EVENT_OCCURRED_ALIAS 0x0000000110010008 55#define SH1_EVENT_OCCURRED_ALIAS __IA64_UL_CONST(0x0000000110010008)
56#define SH2_EVENT_OCCURRED 0x0000000010010000 56#define SH2_EVENT_OCCURRED __IA64_UL_CONST(0x0000000010010000)
57#define SH2_EVENT_OCCURRED_ALIAS 0x0000000010010008 57#define SH2_EVENT_OCCURRED_ALIAS __IA64_UL_CONST(0x0000000010010008)
58 58
59/* ==================================================================== */ 59/* ==================================================================== */
60/* Register "SH_PI_CAM_CONTROL" */ 60/* Register "SH_PI_CAM_CONTROL" */
61/* CRB CAM MMR Access Control */ 61/* CRB CAM MMR Access Control */
62/* ==================================================================== */ 62/* ==================================================================== */
63#define SH1_PI_CAM_CONTROL 0x0000000120050300 63#define SH1_PI_CAM_CONTROL __IA64_UL_CONST(0x0000000120050300)
64 64
65/* ==================================================================== */ 65/* ==================================================================== */
66/* Register "SH_SHUB_ID" */ 66/* Register "SH_SHUB_ID" */
67/* SHub ID Number */ 67/* SHub ID Number */
68/* ==================================================================== */ 68/* ==================================================================== */
69#define SH1_SHUB_ID 0x0000000110060580 69#define SH1_SHUB_ID __IA64_UL_CONST(0x0000000110060580)
70#define SH1_SHUB_ID_REVISION_SHFT 28 70#define SH1_SHUB_ID_REVISION_SHFT 28
71#define SH1_SHUB_ID_REVISION_MASK 0x00000000f0000000 71#define SH1_SHUB_ID_REVISION_MASK __IA64_UL_CONST(0x00000000f0000000)
72 72
73/* ==================================================================== */ 73/* ==================================================================== */
74/* Register "SH_RTC" */ 74/* Register "SH_RTC" */
75/* Real-time Clock */ 75/* Real-time Clock */
76/* ==================================================================== */ 76/* ==================================================================== */
77#define SH1_RTC 0x00000001101c0000 77#define SH1_RTC __IA64_UL_CONST(0x00000001101c0000)
78#define SH2_RTC 0x00000002101c0000 78#define SH2_RTC __IA64_UL_CONST(0x00000002101c0000)
79#define SH_RTC_MASK 0x007fffffffffffff 79#define SH_RTC_MASK __IA64_UL_CONST(0x007fffffffffffff)
80 80
81/* ==================================================================== */ 81/* ==================================================================== */
82/* Register "SH_PIO_WRITE_STATUS_0|1" */ 82/* Register "SH_PIO_WRITE_STATUS_0|1" */
83/* PIO Write Status for CPU 0 & 1 */ 83/* PIO Write Status for CPU 0 & 1 */
84/* ==================================================================== */ 84/* ==================================================================== */
85#define SH1_PIO_WRITE_STATUS_0 0x0000000120070200 85#define SH1_PIO_WRITE_STATUS_0 __IA64_UL_CONST(0x0000000120070200)
86#define SH1_PIO_WRITE_STATUS_1 0x0000000120070280 86#define SH1_PIO_WRITE_STATUS_1 __IA64_UL_CONST(0x0000000120070280)
87#define SH2_PIO_WRITE_STATUS_0 0x0000000020070200 87#define SH2_PIO_WRITE_STATUS_0 __IA64_UL_CONST(0x0000000020070200)
88#define SH2_PIO_WRITE_STATUS_1 0x0000000020070280 88#define SH2_PIO_WRITE_STATUS_1 __IA64_UL_CONST(0x0000000020070280)
89#define SH2_PIO_WRITE_STATUS_2 0x0000000020070300 89#define SH2_PIO_WRITE_STATUS_2 __IA64_UL_CONST(0x0000000020070300)
90#define SH2_PIO_WRITE_STATUS_3 0x0000000020070380 90#define SH2_PIO_WRITE_STATUS_3 __IA64_UL_CONST(0x0000000020070380)
91 91
92/* SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK */ 92/* SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK */
93/* Description: Deadlock response detected */ 93/* Description: Deadlock response detected */
94#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT 1 94#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT 1
95#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK 0x0000000000000002 95#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK \
96 __IA64_UL_CONST(0x0000000000000002)
96 97
97/* SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT */ 98/* SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT */
98/* Description: Count of currently pending PIO writes */ 99/* Description: Count of currently pending PIO writes */
99#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_SHFT 56 100#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_SHFT 56
100#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK 0x3f00000000000000 101#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK \
102 __IA64_UL_CONST(0x3f00000000000000)
101 103
102/* ==================================================================== */ 104/* ==================================================================== */
103/* Register "SH_PIO_WRITE_STATUS_0_ALIAS" */ 105/* Register "SH_PIO_WRITE_STATUS_0_ALIAS" */
104/* ==================================================================== */ 106/* ==================================================================== */
105#define SH1_PIO_WRITE_STATUS_0_ALIAS 0x0000000120070208 107#define SH1_PIO_WRITE_STATUS_0_ALIAS __IA64_UL_CONST(0x0000000120070208)
106#define SH2_PIO_WRITE_STATUS_0_ALIAS 0x0000000020070208 108#define SH2_PIO_WRITE_STATUS_0_ALIAS __IA64_UL_CONST(0x0000000020070208)
107 109
108/* ==================================================================== */ 110/* ==================================================================== */
109/* Register "SH_EVENT_OCCURRED" */ 111/* Register "SH_EVENT_OCCURRED" */
@@ -111,33 +113,33 @@
111/* ==================================================================== */ 113/* ==================================================================== */
112/* SH_EVENT_OCCURRED_UART_INT */ 114/* SH_EVENT_OCCURRED_UART_INT */
113/* Description: Pending Junk Bus UART Interrupt */ 115/* Description: Pending Junk Bus UART Interrupt */
114#define SH_EVENT_OCCURRED_UART_INT_SHFT 20 116#define SH_EVENT_OCCURRED_UART_INT_SHFT 20
115#define SH_EVENT_OCCURRED_UART_INT_MASK 0x0000000000100000 117#define SH_EVENT_OCCURRED_UART_INT_MASK __IA64_UL_CONST(0x0000000000100000)
116 118
117/* SH_EVENT_OCCURRED_IPI_INT */ 119/* SH_EVENT_OCCURRED_IPI_INT */
118/* Description: Pending IPI Interrupt */ 120/* Description: Pending IPI Interrupt */
119#define SH_EVENT_OCCURRED_IPI_INT_SHFT 28 121#define SH_EVENT_OCCURRED_IPI_INT_SHFT 28
120#define SH_EVENT_OCCURRED_IPI_INT_MASK 0x0000000010000000 122#define SH_EVENT_OCCURRED_IPI_INT_MASK __IA64_UL_CONST(0x0000000010000000)
121 123
122/* SH_EVENT_OCCURRED_II_INT0 */ 124/* SH_EVENT_OCCURRED_II_INT0 */
123/* Description: Pending II 0 Interrupt */ 125/* Description: Pending II 0 Interrupt */
124#define SH_EVENT_OCCURRED_II_INT0_SHFT 29 126#define SH_EVENT_OCCURRED_II_INT0_SHFT 29
125#define SH_EVENT_OCCURRED_II_INT0_MASK 0x0000000020000000 127#define SH_EVENT_OCCURRED_II_INT0_MASK __IA64_UL_CONST(0x0000000020000000)
126 128
127/* SH_EVENT_OCCURRED_II_INT1 */ 129/* SH_EVENT_OCCURRED_II_INT1 */
128/* Description: Pending II 1 Interrupt */ 130/* Description: Pending II 1 Interrupt */
129#define SH_EVENT_OCCURRED_II_INT1_SHFT 30 131#define SH_EVENT_OCCURRED_II_INT1_SHFT 30
130#define SH_EVENT_OCCURRED_II_INT1_MASK 0x0000000040000000 132#define SH_EVENT_OCCURRED_II_INT1_MASK __IA64_UL_CONST(0x0000000040000000)
131 133
132/* SH2_EVENT_OCCURRED_EXTIO_INT2 */ 134/* SH2_EVENT_OCCURRED_EXTIO_INT2 */
133/* Description: Pending SHUB 2 EXT IO INT2 */ 135/* Description: Pending SHUB 2 EXT IO INT2 */
134#define SH2_EVENT_OCCURRED_EXTIO_INT2_SHFT 33 136#define SH2_EVENT_OCCURRED_EXTIO_INT2_SHFT 33
135#define SH2_EVENT_OCCURRED_EXTIO_INT2_MASK 0x0000000200000000 137#define SH2_EVENT_OCCURRED_EXTIO_INT2_MASK __IA64_UL_CONST(0x0000000200000000)
136 138
137/* SH2_EVENT_OCCURRED_EXTIO_INT3 */ 139/* SH2_EVENT_OCCURRED_EXTIO_INT3 */
138/* Description: Pending SHUB 2 EXT IO INT3 */ 140/* Description: Pending SHUB 2 EXT IO INT3 */
139#define SH2_EVENT_OCCURRED_EXTIO_INT3_SHFT 34 141#define SH2_EVENT_OCCURRED_EXTIO_INT3_SHFT 34
140#define SH2_EVENT_OCCURRED_EXTIO_INT3_MASK 0x0000000400000000 142#define SH2_EVENT_OCCURRED_EXTIO_INT3_MASK __IA64_UL_CONST(0x0000000400000000)
141 143
142#define SH_ALL_INT_MASK \ 144#define SH_ALL_INT_MASK \
143 (SH_EVENT_OCCURRED_UART_INT_MASK | SH_EVENT_OCCURRED_IPI_INT_MASK | \ 145 (SH_EVENT_OCCURRED_UART_INT_MASK | SH_EVENT_OCCURRED_IPI_INT_MASK | \
@@ -149,310 +151,310 @@
149/* ==================================================================== */ 151/* ==================================================================== */
150/* LEDS */ 152/* LEDS */
151/* ==================================================================== */ 153/* ==================================================================== */
152#define SH1_REAL_JUNK_BUS_LED0 0x7fed00000UL 154#define SH1_REAL_JUNK_BUS_LED0 0x7fed00000UL
153#define SH1_REAL_JUNK_BUS_LED1 0x7fed10000UL 155#define SH1_REAL_JUNK_BUS_LED1 0x7fed10000UL
154#define SH1_REAL_JUNK_BUS_LED2 0x7fed20000UL 156#define SH1_REAL_JUNK_BUS_LED2 0x7fed20000UL
155#define SH1_REAL_JUNK_BUS_LED3 0x7fed30000UL 157#define SH1_REAL_JUNK_BUS_LED3 0x7fed30000UL
156 158
157#define SH2_REAL_JUNK_BUS_LED0 0xf0000000UL 159#define SH2_REAL_JUNK_BUS_LED0 0xf0000000UL
158#define SH2_REAL_JUNK_BUS_LED1 0xf0010000UL 160#define SH2_REAL_JUNK_BUS_LED1 0xf0010000UL
159#define SH2_REAL_JUNK_BUS_LED2 0xf0020000UL 161#define SH2_REAL_JUNK_BUS_LED2 0xf0020000UL
160#define SH2_REAL_JUNK_BUS_LED3 0xf0030000UL 162#define SH2_REAL_JUNK_BUS_LED3 0xf0030000UL
161 163
162/* ==================================================================== */ 164/* ==================================================================== */
163/* Register "SH1_PTC_0" */ 165/* Register "SH1_PTC_0" */
164/* Puge Translation Cache Message Configuration Information */ 166/* Puge Translation Cache Message Configuration Information */
165/* ==================================================================== */ 167/* ==================================================================== */
166#define SH1_PTC_0 0x00000001101a0000 168#define SH1_PTC_0 __IA64_UL_CONST(0x00000001101a0000)
167 169
168/* SH1_PTC_0_A */ 170/* SH1_PTC_0_A */
169/* Description: Type */ 171/* Description: Type */
170#define SH1_PTC_0_A_SHFT 0 172#define SH1_PTC_0_A_SHFT 0
171 173
172/* SH1_PTC_0_PS */ 174/* SH1_PTC_0_PS */
173/* Description: Page Size */ 175/* Description: Page Size */
174#define SH1_PTC_0_PS_SHFT 2 176#define SH1_PTC_0_PS_SHFT 2
175 177
176/* SH1_PTC_0_RID */ 178/* SH1_PTC_0_RID */
177/* Description: Region ID */ 179/* Description: Region ID */
178#define SH1_PTC_0_RID_SHFT 8 180#define SH1_PTC_0_RID_SHFT 8
179 181
180/* SH1_PTC_0_START */ 182/* SH1_PTC_0_START */
181/* Description: Start */ 183/* Description: Start */
182#define SH1_PTC_0_START_SHFT 63 184#define SH1_PTC_0_START_SHFT 63
183 185
184/* ==================================================================== */ 186/* ==================================================================== */
185/* Register "SH1_PTC_1" */ 187/* Register "SH1_PTC_1" */
186/* Puge Translation Cache Message Configuration Information */ 188/* Puge Translation Cache Message Configuration Information */
187/* ==================================================================== */ 189/* ==================================================================== */
188#define SH1_PTC_1 0x00000001101a0080 190#define SH1_PTC_1 __IA64_UL_CONST(0x00000001101a0080)
189 191
190/* SH1_PTC_1_START */ 192/* SH1_PTC_1_START */
191/* Description: PTC_1 Start */ 193/* Description: PTC_1 Start */
192#define SH1_PTC_1_START_SHFT 63 194#define SH1_PTC_1_START_SHFT 63
193
194 195
195/* ==================================================================== */ 196/* ==================================================================== */
196/* Register "SH2_PTC" */ 197/* Register "SH2_PTC" */
197/* Puge Translation Cache Message Configuration Information */ 198/* Puge Translation Cache Message Configuration Information */
198/* ==================================================================== */ 199/* ==================================================================== */
199#define SH2_PTC 0x0000000170000000 200#define SH2_PTC __IA64_UL_CONST(0x0000000170000000)
200 201
201/* SH2_PTC_A */ 202/* SH2_PTC_A */
202/* Description: Type */ 203/* Description: Type */
203#define SH2_PTC_A_SHFT 0 204#define SH2_PTC_A_SHFT 0
204 205
205/* SH2_PTC_PS */ 206/* SH2_PTC_PS */
206/* Description: Page Size */ 207/* Description: Page Size */
207#define SH2_PTC_PS_SHFT 2 208#define SH2_PTC_PS_SHFT 2
208 209
209/* SH2_PTC_RID */ 210/* SH2_PTC_RID */
210/* Description: Region ID */ 211/* Description: Region ID */
211#define SH2_PTC_RID_SHFT 4 212#define SH2_PTC_RID_SHFT 4
212 213
213/* SH2_PTC_START */ 214/* SH2_PTC_START */
214/* Description: Start */ 215/* Description: Start */
215#define SH2_PTC_START_SHFT 63 216#define SH2_PTC_START_SHFT 63
216 217
217/* SH2_PTC_ADDR_RID */ 218/* SH2_PTC_ADDR_RID */
218/* Description: Region ID */ 219/* Description: Region ID */
219#define SH2_PTC_ADDR_SHFT 4 220#define SH2_PTC_ADDR_SHFT 4
220#define SH2_PTC_ADDR_MASK 0x1ffffffffffff000 221#define SH2_PTC_ADDR_MASK __IA64_UL_CONST(0x1ffffffffffff000)
221 222
222/* ==================================================================== */ 223/* ==================================================================== */
223/* Register "SH_RTC1_INT_CONFIG" */ 224/* Register "SH_RTC1_INT_CONFIG" */
224/* SHub RTC 1 Interrupt Config Registers */ 225/* SHub RTC 1 Interrupt Config Registers */
225/* ==================================================================== */ 226/* ==================================================================== */
226 227
227#define SH1_RTC1_INT_CONFIG 0x0000000110001480 228#define SH1_RTC1_INT_CONFIG __IA64_UL_CONST(0x0000000110001480)
228#define SH2_RTC1_INT_CONFIG 0x0000000010001480 229#define SH2_RTC1_INT_CONFIG __IA64_UL_CONST(0x0000000010001480)
229#define SH_RTC1_INT_CONFIG_MASK 0x0ff3ffffffefffff 230#define SH_RTC1_INT_CONFIG_MASK __IA64_UL_CONST(0x0ff3ffffffefffff)
230#define SH_RTC1_INT_CONFIG_INIT 0x0000000000000000 231#define SH_RTC1_INT_CONFIG_INIT __IA64_UL_CONST(0x0000000000000000)
231 232
232/* SH_RTC1_INT_CONFIG_TYPE */ 233/* SH_RTC1_INT_CONFIG_TYPE */
233/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ 234/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
234#define SH_RTC1_INT_CONFIG_TYPE_SHFT 0 235#define SH_RTC1_INT_CONFIG_TYPE_SHFT 0
235#define SH_RTC1_INT_CONFIG_TYPE_MASK 0x0000000000000007 236#define SH_RTC1_INT_CONFIG_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
236 237
237/* SH_RTC1_INT_CONFIG_AGT */ 238/* SH_RTC1_INT_CONFIG_AGT */
238/* Description: Agent, must be 0 for SHub */ 239/* Description: Agent, must be 0 for SHub */
239#define SH_RTC1_INT_CONFIG_AGT_SHFT 3 240#define SH_RTC1_INT_CONFIG_AGT_SHFT 3
240#define SH_RTC1_INT_CONFIG_AGT_MASK 0x0000000000000008 241#define SH_RTC1_INT_CONFIG_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
241 242
242/* SH_RTC1_INT_CONFIG_PID */ 243/* SH_RTC1_INT_CONFIG_PID */
243/* Description: Processor ID, same setting as on targeted McKinley */ 244/* Description: Processor ID, same setting as on targeted McKinley */
244#define SH_RTC1_INT_CONFIG_PID_SHFT 4 245#define SH_RTC1_INT_CONFIG_PID_SHFT 4
245#define SH_RTC1_INT_CONFIG_PID_MASK 0x00000000000ffff0 246#define SH_RTC1_INT_CONFIG_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
246 247
247/* SH_RTC1_INT_CONFIG_BASE */ 248/* SH_RTC1_INT_CONFIG_BASE */
248/* Description: Optional interrupt vector area, 2MB aligned */ 249/* Description: Optional interrupt vector area, 2MB aligned */
249#define SH_RTC1_INT_CONFIG_BASE_SHFT 21 250#define SH_RTC1_INT_CONFIG_BASE_SHFT 21
250#define SH_RTC1_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 251#define SH_RTC1_INT_CONFIG_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
251 252
252/* SH_RTC1_INT_CONFIG_IDX */ 253/* SH_RTC1_INT_CONFIG_IDX */
253/* Description: Targeted McKinley interrupt vector */ 254/* Description: Targeted McKinley interrupt vector */
254#define SH_RTC1_INT_CONFIG_IDX_SHFT 52 255#define SH_RTC1_INT_CONFIG_IDX_SHFT 52
255#define SH_RTC1_INT_CONFIG_IDX_MASK 0x0ff0000000000000 256#define SH_RTC1_INT_CONFIG_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
256 257
257/* ==================================================================== */ 258/* ==================================================================== */
258/* Register "SH_RTC1_INT_ENABLE" */ 259/* Register "SH_RTC1_INT_ENABLE" */
259/* SHub RTC 1 Interrupt Enable Registers */ 260/* SHub RTC 1 Interrupt Enable Registers */
260/* ==================================================================== */ 261/* ==================================================================== */
261 262
262#define SH1_RTC1_INT_ENABLE 0x0000000110001500 263#define SH1_RTC1_INT_ENABLE __IA64_UL_CONST(0x0000000110001500)
263#define SH2_RTC1_INT_ENABLE 0x0000000010001500 264#define SH2_RTC1_INT_ENABLE __IA64_UL_CONST(0x0000000010001500)
264#define SH_RTC1_INT_ENABLE_MASK 0x0000000000000001 265#define SH_RTC1_INT_ENABLE_MASK __IA64_UL_CONST(0x0000000000000001)
265#define SH_RTC1_INT_ENABLE_INIT 0x0000000000000000 266#define SH_RTC1_INT_ENABLE_INIT __IA64_UL_CONST(0x0000000000000000)
266 267
267/* SH_RTC1_INT_ENABLE_RTC1_ENABLE */ 268/* SH_RTC1_INT_ENABLE_RTC1_ENABLE */
268/* Description: Enable RTC 1 Interrupt */ 269/* Description: Enable RTC 1 Interrupt */
269#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT 0 270#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT 0
270#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK 0x0000000000000001 271#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK \
272 __IA64_UL_CONST(0x0000000000000001)
271 273
272/* ==================================================================== */ 274/* ==================================================================== */
273/* Register "SH_RTC2_INT_CONFIG" */ 275/* Register "SH_RTC2_INT_CONFIG" */
274/* SHub RTC 2 Interrupt Config Registers */ 276/* SHub RTC 2 Interrupt Config Registers */
275/* ==================================================================== */ 277/* ==================================================================== */
276 278
277#define SH1_RTC2_INT_CONFIG 0x0000000110001580 279#define SH1_RTC2_INT_CONFIG __IA64_UL_CONST(0x0000000110001580)
278#define SH2_RTC2_INT_CONFIG 0x0000000010001580 280#define SH2_RTC2_INT_CONFIG __IA64_UL_CONST(0x0000000010001580)
279#define SH_RTC2_INT_CONFIG_MASK 0x0ff3ffffffefffff 281#define SH_RTC2_INT_CONFIG_MASK __IA64_UL_CONST(0x0ff3ffffffefffff)
280#define SH_RTC2_INT_CONFIG_INIT 0x0000000000000000 282#define SH_RTC2_INT_CONFIG_INIT __IA64_UL_CONST(0x0000000000000000)
281 283
282/* SH_RTC2_INT_CONFIG_TYPE */ 284/* SH_RTC2_INT_CONFIG_TYPE */
283/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ 285/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
284#define SH_RTC2_INT_CONFIG_TYPE_SHFT 0 286#define SH_RTC2_INT_CONFIG_TYPE_SHFT 0
285#define SH_RTC2_INT_CONFIG_TYPE_MASK 0x0000000000000007 287#define SH_RTC2_INT_CONFIG_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
286 288
287/* SH_RTC2_INT_CONFIG_AGT */ 289/* SH_RTC2_INT_CONFIG_AGT */
288/* Description: Agent, must be 0 for SHub */ 290/* Description: Agent, must be 0 for SHub */
289#define SH_RTC2_INT_CONFIG_AGT_SHFT 3 291#define SH_RTC2_INT_CONFIG_AGT_SHFT 3
290#define SH_RTC2_INT_CONFIG_AGT_MASK 0x0000000000000008 292#define SH_RTC2_INT_CONFIG_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
291 293
292/* SH_RTC2_INT_CONFIG_PID */ 294/* SH_RTC2_INT_CONFIG_PID */
293/* Description: Processor ID, same setting as on targeted McKinley */ 295/* Description: Processor ID, same setting as on targeted McKinley */
294#define SH_RTC2_INT_CONFIG_PID_SHFT 4 296#define SH_RTC2_INT_CONFIG_PID_SHFT 4
295#define SH_RTC2_INT_CONFIG_PID_MASK 0x00000000000ffff0 297#define SH_RTC2_INT_CONFIG_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
296 298
297/* SH_RTC2_INT_CONFIG_BASE */ 299/* SH_RTC2_INT_CONFIG_BASE */
298/* Description: Optional interrupt vector area, 2MB aligned */ 300/* Description: Optional interrupt vector area, 2MB aligned */
299#define SH_RTC2_INT_CONFIG_BASE_SHFT 21 301#define SH_RTC2_INT_CONFIG_BASE_SHFT 21
300#define SH_RTC2_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 302#define SH_RTC2_INT_CONFIG_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
301 303
302/* SH_RTC2_INT_CONFIG_IDX */ 304/* SH_RTC2_INT_CONFIG_IDX */
303/* Description: Targeted McKinley interrupt vector */ 305/* Description: Targeted McKinley interrupt vector */
304#define SH_RTC2_INT_CONFIG_IDX_SHFT 52 306#define SH_RTC2_INT_CONFIG_IDX_SHFT 52
305#define SH_RTC2_INT_CONFIG_IDX_MASK 0x0ff0000000000000 307#define SH_RTC2_INT_CONFIG_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
306 308
307/* ==================================================================== */ 309/* ==================================================================== */
308/* Register "SH_RTC2_INT_ENABLE" */ 310/* Register "SH_RTC2_INT_ENABLE" */
309/* SHub RTC 2 Interrupt Enable Registers */ 311/* SHub RTC 2 Interrupt Enable Registers */
310/* ==================================================================== */ 312/* ==================================================================== */
311 313
312#define SH1_RTC2_INT_ENABLE 0x0000000110001600 314#define SH1_RTC2_INT_ENABLE __IA64_UL_CONST(0x0000000110001600)
313#define SH2_RTC2_INT_ENABLE 0x0000000010001600 315#define SH2_RTC2_INT_ENABLE __IA64_UL_CONST(0x0000000010001600)
314#define SH_RTC2_INT_ENABLE_MASK 0x0000000000000001 316#define SH_RTC2_INT_ENABLE_MASK __IA64_UL_CONST(0x0000000000000001)
315#define SH_RTC2_INT_ENABLE_INIT 0x0000000000000000 317#define SH_RTC2_INT_ENABLE_INIT __IA64_UL_CONST(0x0000000000000000)
316 318
317/* SH_RTC2_INT_ENABLE_RTC2_ENABLE */ 319/* SH_RTC2_INT_ENABLE_RTC2_ENABLE */
318/* Description: Enable RTC 2 Interrupt */ 320/* Description: Enable RTC 2 Interrupt */
319#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT 0 321#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT 0
320#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK 0x0000000000000001 322#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK \
323 __IA64_UL_CONST(0x0000000000000001)
321 324
322/* ==================================================================== */ 325/* ==================================================================== */
323/* Register "SH_RTC3_INT_CONFIG" */ 326/* Register "SH_RTC3_INT_CONFIG" */
324/* SHub RTC 3 Interrupt Config Registers */ 327/* SHub RTC 3 Interrupt Config Registers */
325/* ==================================================================== */ 328/* ==================================================================== */
326 329
327#define SH1_RTC3_INT_CONFIG 0x0000000110001680 330#define SH1_RTC3_INT_CONFIG __IA64_UL_CONST(0x0000000110001680)
328#define SH2_RTC3_INT_CONFIG 0x0000000010001680 331#define SH2_RTC3_INT_CONFIG __IA64_UL_CONST(0x0000000010001680)
329#define SH_RTC3_INT_CONFIG_MASK 0x0ff3ffffffefffff 332#define SH_RTC3_INT_CONFIG_MASK __IA64_UL_CONST(0x0ff3ffffffefffff)
330#define SH_RTC3_INT_CONFIG_INIT 0x0000000000000000 333#define SH_RTC3_INT_CONFIG_INIT __IA64_UL_CONST(0x0000000000000000)
331 334
332/* SH_RTC3_INT_CONFIG_TYPE */ 335/* SH_RTC3_INT_CONFIG_TYPE */
333/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ 336/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
334#define SH_RTC3_INT_CONFIG_TYPE_SHFT 0 337#define SH_RTC3_INT_CONFIG_TYPE_SHFT 0
335#define SH_RTC3_INT_CONFIG_TYPE_MASK 0x0000000000000007 338#define SH_RTC3_INT_CONFIG_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
336 339
337/* SH_RTC3_INT_CONFIG_AGT */ 340/* SH_RTC3_INT_CONFIG_AGT */
338/* Description: Agent, must be 0 for SHub */ 341/* Description: Agent, must be 0 for SHub */
339#define SH_RTC3_INT_CONFIG_AGT_SHFT 3 342#define SH_RTC3_INT_CONFIG_AGT_SHFT 3
340#define SH_RTC3_INT_CONFIG_AGT_MASK 0x0000000000000008 343#define SH_RTC3_INT_CONFIG_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
341 344
342/* SH_RTC3_INT_CONFIG_PID */ 345/* SH_RTC3_INT_CONFIG_PID */
343/* Description: Processor ID, same setting as on targeted McKinley */ 346/* Description: Processor ID, same setting as on targeted McKinley */
344#define SH_RTC3_INT_CONFIG_PID_SHFT 4 347#define SH_RTC3_INT_CONFIG_PID_SHFT 4
345#define SH_RTC3_INT_CONFIG_PID_MASK 0x00000000000ffff0 348#define SH_RTC3_INT_CONFIG_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
346 349
347/* SH_RTC3_INT_CONFIG_BASE */ 350/* SH_RTC3_INT_CONFIG_BASE */
348/* Description: Optional interrupt vector area, 2MB aligned */ 351/* Description: Optional interrupt vector area, 2MB aligned */
349#define SH_RTC3_INT_CONFIG_BASE_SHFT 21 352#define SH_RTC3_INT_CONFIG_BASE_SHFT 21
350#define SH_RTC3_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 353#define SH_RTC3_INT_CONFIG_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
351 354
352/* SH_RTC3_INT_CONFIG_IDX */ 355/* SH_RTC3_INT_CONFIG_IDX */
353/* Description: Targeted McKinley interrupt vector */ 356/* Description: Targeted McKinley interrupt vector */
354#define SH_RTC3_INT_CONFIG_IDX_SHFT 52 357#define SH_RTC3_INT_CONFIG_IDX_SHFT 52
355#define SH_RTC3_INT_CONFIG_IDX_MASK 0x0ff0000000000000 358#define SH_RTC3_INT_CONFIG_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
356 359
357/* ==================================================================== */ 360/* ==================================================================== */
358/* Register "SH_RTC3_INT_ENABLE" */ 361/* Register "SH_RTC3_INT_ENABLE" */
359/* SHub RTC 3 Interrupt Enable Registers */ 362/* SHub RTC 3 Interrupt Enable Registers */
360/* ==================================================================== */ 363/* ==================================================================== */
361 364
362#define SH1_RTC3_INT_ENABLE 0x0000000110001700 365#define SH1_RTC3_INT_ENABLE __IA64_UL_CONST(0x0000000110001700)
363#define SH2_RTC3_INT_ENABLE 0x0000000010001700 366#define SH2_RTC3_INT_ENABLE __IA64_UL_CONST(0x0000000010001700)
364#define SH_RTC3_INT_ENABLE_MASK 0x0000000000000001 367#define SH_RTC3_INT_ENABLE_MASK __IA64_UL_CONST(0x0000000000000001)
365#define SH_RTC3_INT_ENABLE_INIT 0x0000000000000000 368#define SH_RTC3_INT_ENABLE_INIT __IA64_UL_CONST(0x0000000000000000)
366 369
367/* SH_RTC3_INT_ENABLE_RTC3_ENABLE */ 370/* SH_RTC3_INT_ENABLE_RTC3_ENABLE */
368/* Description: Enable RTC 3 Interrupt */ 371/* Description: Enable RTC 3 Interrupt */
369#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT 0 372#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT 0
370#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK 0x0000000000000001 373#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK \
374 __IA64_UL_CONST(0x0000000000000001)
371 375
372/* SH_EVENT_OCCURRED_RTC1_INT */ 376/* SH_EVENT_OCCURRED_RTC1_INT */
373/* Description: Pending RTC 1 Interrupt */ 377/* Description: Pending RTC 1 Interrupt */
374#define SH_EVENT_OCCURRED_RTC1_INT_SHFT 24 378#define SH_EVENT_OCCURRED_RTC1_INT_SHFT 24
375#define SH_EVENT_OCCURRED_RTC1_INT_MASK 0x0000000001000000 379#define SH_EVENT_OCCURRED_RTC1_INT_MASK __IA64_UL_CONST(0x0000000001000000)
376 380
377/* SH_EVENT_OCCURRED_RTC2_INT */ 381/* SH_EVENT_OCCURRED_RTC2_INT */
378/* Description: Pending RTC 2 Interrupt */ 382/* Description: Pending RTC 2 Interrupt */
379#define SH_EVENT_OCCURRED_RTC2_INT_SHFT 25 383#define SH_EVENT_OCCURRED_RTC2_INT_SHFT 25
380#define SH_EVENT_OCCURRED_RTC2_INT_MASK 0x0000000002000000 384#define SH_EVENT_OCCURRED_RTC2_INT_MASK __IA64_UL_CONST(0x0000000002000000)
381 385
382/* SH_EVENT_OCCURRED_RTC3_INT */ 386/* SH_EVENT_OCCURRED_RTC3_INT */
383/* Description: Pending RTC 3 Interrupt */ 387/* Description: Pending RTC 3 Interrupt */
384#define SH_EVENT_OCCURRED_RTC3_INT_SHFT 26 388#define SH_EVENT_OCCURRED_RTC3_INT_SHFT 26
385#define SH_EVENT_OCCURRED_RTC3_INT_MASK 0x0000000004000000 389#define SH_EVENT_OCCURRED_RTC3_INT_MASK __IA64_UL_CONST(0x0000000004000000)
386 390
387/* ==================================================================== */ 391/* ==================================================================== */
388/* Register "SH_IPI_ACCESS" */ 392/* Register "SH_IPI_ACCESS" */
389/* CPU interrupt Access Permission Bits */ 393/* CPU interrupt Access Permission Bits */
390/* ==================================================================== */ 394/* ==================================================================== */
391 395
392#define SH1_IPI_ACCESS 0x0000000110060480 396#define SH1_IPI_ACCESS __IA64_UL_CONST(0x0000000110060480)
393#define SH2_IPI_ACCESS0 0x0000000010060c00 397#define SH2_IPI_ACCESS0 __IA64_UL_CONST(0x0000000010060c00)
394#define SH2_IPI_ACCESS1 0x0000000010060c80 398#define SH2_IPI_ACCESS1 __IA64_UL_CONST(0x0000000010060c80)
395#define SH2_IPI_ACCESS2 0x0000000010060d00 399#define SH2_IPI_ACCESS2 __IA64_UL_CONST(0x0000000010060d00)
396#define SH2_IPI_ACCESS3 0x0000000010060d80 400#define SH2_IPI_ACCESS3 __IA64_UL_CONST(0x0000000010060d80)
397 401
398/* ==================================================================== */ 402/* ==================================================================== */
399/* Register "SH_INT_CMPB" */ 403/* Register "SH_INT_CMPB" */
400/* RTC Compare Value for Processor B */ 404/* RTC Compare Value for Processor B */
401/* ==================================================================== */ 405/* ==================================================================== */
402 406
403#define SH1_INT_CMPB 0x00000001101b0080 407#define SH1_INT_CMPB __IA64_UL_CONST(0x00000001101b0080)
404#define SH2_INT_CMPB 0x00000000101b0080 408#define SH2_INT_CMPB __IA64_UL_CONST(0x00000000101b0080)
405#define SH_INT_CMPB_MASK 0x007fffffffffffff 409#define SH_INT_CMPB_MASK __IA64_UL_CONST(0x007fffffffffffff)
406#define SH_INT_CMPB_INIT 0x0000000000000000 410#define SH_INT_CMPB_INIT __IA64_UL_CONST(0x0000000000000000)
407 411
408/* SH_INT_CMPB_REAL_TIME_CMPB */ 412/* SH_INT_CMPB_REAL_TIME_CMPB */
409/* Description: Real Time Clock Compare */ 413/* Description: Real Time Clock Compare */
410#define SH_INT_CMPB_REAL_TIME_CMPB_SHFT 0 414#define SH_INT_CMPB_REAL_TIME_CMPB_SHFT 0
411#define SH_INT_CMPB_REAL_TIME_CMPB_MASK 0x007fffffffffffff 415#define SH_INT_CMPB_REAL_TIME_CMPB_MASK __IA64_UL_CONST(0x007fffffffffffff)
412 416
413/* ==================================================================== */ 417/* ==================================================================== */
414/* Register "SH_INT_CMPC" */ 418/* Register "SH_INT_CMPC" */
415/* RTC Compare Value for Processor C */ 419/* RTC Compare Value for Processor C */
416/* ==================================================================== */ 420/* ==================================================================== */
417 421
418#define SH1_INT_CMPC 0x00000001101b0100 422#define SH1_INT_CMPC __IA64_UL_CONST(0x00000001101b0100)
419#define SH2_INT_CMPC 0x00000000101b0100 423#define SH2_INT_CMPC __IA64_UL_CONST(0x00000000101b0100)
420#define SH_INT_CMPC_MASK 0x007fffffffffffff 424#define SH_INT_CMPC_MASK __IA64_UL_CONST(0x007fffffffffffff)
421#define SH_INT_CMPC_INIT 0x0000000000000000 425#define SH_INT_CMPC_INIT __IA64_UL_CONST(0x0000000000000000)
422 426
423/* SH_INT_CMPC_REAL_TIME_CMPC */ 427/* SH_INT_CMPC_REAL_TIME_CMPC */
424/* Description: Real Time Clock Compare */ 428/* Description: Real Time Clock Compare */
425#define SH_INT_CMPC_REAL_TIME_CMPC_SHFT 0 429#define SH_INT_CMPC_REAL_TIME_CMPC_SHFT 0
426#define SH_INT_CMPC_REAL_TIME_CMPC_MASK 0x007fffffffffffff 430#define SH_INT_CMPC_REAL_TIME_CMPC_MASK __IA64_UL_CONST(0x007fffffffffffff)
427 431
428/* ==================================================================== */ 432/* ==================================================================== */
429/* Register "SH_INT_CMPD" */ 433/* Register "SH_INT_CMPD" */
430/* RTC Compare Value for Processor D */ 434/* RTC Compare Value for Processor D */
431/* ==================================================================== */ 435/* ==================================================================== */
432 436
433#define SH1_INT_CMPD 0x00000001101b0180 437#define SH1_INT_CMPD __IA64_UL_CONST(0x00000001101b0180)
434#define SH2_INT_CMPD 0x00000000101b0180 438#define SH2_INT_CMPD __IA64_UL_CONST(0x00000000101b0180)
435#define SH_INT_CMPD_MASK 0x007fffffffffffff 439#define SH_INT_CMPD_MASK __IA64_UL_CONST(0x007fffffffffffff)
436#define SH_INT_CMPD_INIT 0x0000000000000000 440#define SH_INT_CMPD_INIT __IA64_UL_CONST(0x0000000000000000)
437 441
438/* SH_INT_CMPD_REAL_TIME_CMPD */ 442/* SH_INT_CMPD_REAL_TIME_CMPD */
439/* Description: Real Time Clock Compare */ 443/* Description: Real Time Clock Compare */
440#define SH_INT_CMPD_REAL_TIME_CMPD_SHFT 0 444#define SH_INT_CMPD_REAL_TIME_CMPD_SHFT 0
441#define SH_INT_CMPD_REAL_TIME_CMPD_MASK 0x007fffffffffffff 445#define SH_INT_CMPD_REAL_TIME_CMPD_MASK __IA64_UL_CONST(0x007fffffffffffff)
442 446
443/* ==================================================================== */ 447/* ==================================================================== */
444/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC0" */ 448/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC0" */
445/* privilege vector for acc=0 */ 449/* privilege vector for acc=0 */
446/* ==================================================================== */ 450/* ==================================================================== */
447 451#define SH1_MD_DQLP_MMR_DIR_PRIVEC0 __IA64_UL_CONST(0x0000000100030300)
448#define SH1_MD_DQLP_MMR_DIR_PRIVEC0 0x0000000100030300
449 452
450/* ==================================================================== */ 453/* ==================================================================== */
451/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC0" */ 454/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC0" */
452/* privilege vector for acc=0 */ 455/* privilege vector for acc=0 */
453/* ==================================================================== */ 456/* ==================================================================== */
454 457#define SH1_MD_DQRP_MMR_DIR_PRIVEC0 __IA64_UL_CONST(0x0000000100050300)
455#define SH1_MD_DQRP_MMR_DIR_PRIVEC0 0x0000000100050300
456 458
457/* ==================================================================== */ 459/* ==================================================================== */
458/* Some MMRs are functionally identical (or close enough) on both SHUB1 */ 460/* Some MMRs are functionally identical (or close enough) on both SHUB1 */
@@ -484,17 +486,17 @@
484/* Engine 0 Control and Status Register */ 486/* Engine 0 Control and Status Register */
485/* ========================================================================== */ 487/* ========================================================================== */
486 488
487#define SH2_BT_ENG_CSR_0 0x0000000030040000 489#define SH2_BT_ENG_CSR_0 __IA64_UL_CONST(0x0000000030040000)
488#define SH2_BT_ENG_SRC_ADDR_0 0x0000000030040080 490#define SH2_BT_ENG_SRC_ADDR_0 __IA64_UL_CONST(0x0000000030040080)
489#define SH2_BT_ENG_DEST_ADDR_0 0x0000000030040100 491#define SH2_BT_ENG_DEST_ADDR_0 __IA64_UL_CONST(0x0000000030040100)
490#define SH2_BT_ENG_NOTIF_ADDR_0 0x0000000030040180 492#define SH2_BT_ENG_NOTIF_ADDR_0 __IA64_UL_CONST(0x0000000030040180)
491 493
492/* ========================================================================== */ 494/* ========================================================================== */
493/* BTE interfaces 1-3 */ 495/* BTE interfaces 1-3 */
494/* ========================================================================== */ 496/* ========================================================================== */
495 497
496#define SH2_BT_ENG_CSR_1 0x0000000030050000 498#define SH2_BT_ENG_CSR_1 __IA64_UL_CONST(0x0000000030050000)
497#define SH2_BT_ENG_CSR_2 0x0000000030060000 499#define SH2_BT_ENG_CSR_2 __IA64_UL_CONST(0x0000000030060000)
498#define SH2_BT_ENG_CSR_3 0x0000000030070000 500#define SH2_BT_ENG_CSR_3 __IA64_UL_CONST(0x0000000030070000)
499 501
500#endif /* _ASM_IA64_SN_SHUB_MMR_H */ 502#endif /* _ASM_IA64_SN_SHUB_MMR_H */
diff --git a/include/asm-ia64/sn/simulator.h b/include/asm-ia64/sn/simulator.h
index 78eb4f869c8b..16a48b5a039c 100644
--- a/include/asm-ia64/sn/simulator.h
+++ b/include/asm-ia64/sn/simulator.h
@@ -10,18 +10,12 @@
10 10
11#include <linux/config.h> 11#include <linux/config.h>
12 12
13#ifdef CONFIG_IA64_SGI_SN_SIM
14
15#define SNMAGIC 0xaeeeeeee8badbeefL 13#define SNMAGIC 0xaeeeeeee8badbeefL
16#define IS_RUNNING_ON_SIMULATOR() ({long sn; asm("mov %0=cpuid[%1]" : "=r"(sn) : "r"(2)); sn == SNMAGIC;}) 14#define IS_MEDUSA() ({long sn; asm("mov %0=cpuid[%1]" : "=r"(sn) : "r"(2)); sn == SNMAGIC;})
17
18#define SIMULATOR_SLEEP() asm("nop.i 0x8beef")
19
20#else
21
22#define IS_RUNNING_ON_SIMULATOR() (0)
23#define SIMULATOR_SLEEP()
24 15
25#endif 16#define SIMULATOR_SLEEP() asm("nop.i 0x8beef")
17#define IS_RUNNING_ON_SIMULATOR() (sn_prom_type)
18#define IS_RUNNING_ON_FAKE_PROM() (sn_prom_type == 2)
19extern int sn_prom_type; /* 0=hardware, 1=medusa/realprom, 2=medusa/fakeprom */
26 20
27#endif /* _ASM_IA64_SN_SIMULATOR_H */ 21#endif /* _ASM_IA64_SN_SIMULATOR_H */
diff --git a/include/asm-ia64/sn/sn2/sn_hwperf.h b/include/asm-ia64/sn/sn2/sn_hwperf.h
index b0c4d6dd77ba..df75f4c4aec3 100644
--- a/include/asm-ia64/sn/sn2/sn_hwperf.h
+++ b/include/asm-ia64/sn/sn2/sn_hwperf.h
@@ -223,4 +223,6 @@ struct sn_hwperf_ioctl_args {
223#define SN_HWPERF_OP_RECONFIGURE 253 223#define SN_HWPERF_OP_RECONFIGURE 253
224#define SN_HWPERF_OP_INVAL 254 224#define SN_HWPERF_OP_INVAL 254
225 225
226int sn_topology_open(struct inode *inode, struct file *file);
227int sn_topology_release(struct inode *inode, struct file *file);
226#endif /* SN_HWPERF_H */ 228#endif /* SN_HWPERF_H */
diff --git a/include/asm-ia64/sn/sn_cpuid.h b/include/asm-ia64/sn/sn_cpuid.h
index 20b300187669..d2c1d34dcce4 100644
--- a/include/asm-ia64/sn/sn_cpuid.h
+++ b/include/asm-ia64/sn/sn_cpuid.h
@@ -81,11 +81,6 @@
81 * 81 *
82 */ 82 */
83 83
84#ifndef CONFIG_SMP
85#define cpu_physical_id(cpuid) ((ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff)
86#endif
87
88
89#define get_node_number(addr) NASID_GET(addr) 84#define get_node_number(addr) NASID_GET(addr)
90 85
91/* 86/*
diff --git a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h
index eb0395ad0d6a..27976d223186 100644
--- a/include/asm-ia64/sn/sn_sal.h
+++ b/include/asm-ia64/sn/sn_sal.h
@@ -132,43 +132,30 @@
132#define SALRET_INVALID_ARG (-2) 132#define SALRET_INVALID_ARG (-2)
133#define SALRET_ERROR (-3) 133#define SALRET_ERROR (-3)
134 134
135#define SN_SAL_FAKE_PROM 0x02009999
135 136
136/** 137/**
137 * sn_sal_rev_major - get the major SGI SAL revision number 138 * sn_sal_revision - get the SGI SAL revision number
138 * 139 *
139 * The SGI PROM stores its version in sal_[ab]_rev_(major|minor). 140 * The SGI PROM stores its version in the sal_[ab]_rev_(major|minor).
140 * This routine simply extracts the major value from the 141 * This routine simply extracts the major and minor values and
141 * @ia64_sal_systab structure constructed by ia64_sal_init(). 142 * presents them in a u32 format.
142 */ 143 *
143static inline int 144 * For example, version 4.05 would be represented at 0x0405.
144sn_sal_rev_major(void) 145 */
146static inline u32
147sn_sal_rev(void)
145{ 148{
146 struct ia64_sal_systab *systab = efi.sal_systab; 149 struct ia64_sal_systab *systab = efi.sal_systab;
147 150
148 return (int)systab->sal_b_rev_major; 151 return (u32)(systab->sal_b_rev_major << 8 | systab->sal_b_rev_minor);
149}
150
151/**
152 * sn_sal_rev_minor - get the minor SGI SAL revision number
153 *
154 * The SGI PROM stores its version in sal_[ab]_rev_(major|minor).
155 * This routine simply extracts the minor value from the
156 * @ia64_sal_systab structure constructed by ia64_sal_init().
157 */
158static inline int
159sn_sal_rev_minor(void)
160{
161 struct ia64_sal_systab *systab = efi.sal_systab;
162
163 return (int)systab->sal_b_rev_minor;
164} 152}
165 153
166/* 154/*
167 * Specify the minimum PROM revsion required for this kernel. 155 * Specify the minimum PROM revsion required for this kernel.
168 * Note that they're stored in hex format... 156 * Note that they're stored in hex format...
169 */ 157 */
170#define SN_SAL_MIN_MAJOR 0x4 /* SN2 kernels need at least PROM 4.0 */ 158#define SN_SAL_MIN_VERSION 0x0404
171#define SN_SAL_MIN_MINOR 0x0
172 159
173/* 160/*
174 * Returns the master console nasid, if the call fails, return an illegal 161 * Returns the master console nasid, if the call fails, return an illegal
@@ -1105,4 +1092,12 @@ ia64_sn_bte_recovery(nasid_t nasid)
1105 return (int) rv.status; 1092 return (int) rv.status;
1106} 1093}
1107 1094
1095static inline int
1096ia64_sn_is_fake_prom(void)
1097{
1098 struct ia64_sal_retval rv;
1099 SAL_CALL_NOLOCK(rv, SN_SAL_FAKE_PROM, 0, 0, 0, 0, 0, 0, 0);
1100 return (rv.status == 0);
1101}
1102
1108#endif /* _ASM_IA64_SN_SN_SAL_H */ 1103#endif /* _ASM_IA64_SN_SN_SAL_H */
diff --git a/include/asm-ia64/sn/tioca_provider.h b/include/asm-ia64/sn/tioca_provider.h
index b6acc22ab239..5ccec608d325 100644
--- a/include/asm-ia64/sn/tioca_provider.h
+++ b/include/asm-ia64/sn/tioca_provider.h
@@ -201,6 +201,7 @@ tioca_tlbflush(struct tioca_kernel *tioca_kernel)
201} 201}
202 202
203extern uint32_t tioca_gart_found; 203extern uint32_t tioca_gart_found;
204extern struct list_head tioca_list;
204extern int tioca_init_provider(void); 205extern int tioca_init_provider(void);
205extern void tioca_fastwrite_enable(struct tioca_kernel *tioca_kern); 206extern void tioca_fastwrite_enable(struct tioca_kernel *tioca_kern);
206#endif /* _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H */ 207#endif /* _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H */
diff --git a/include/asm-ia64/sn/tiocp.h b/include/asm-ia64/sn/tiocp.h
new file mode 100644
index 000000000000..5f2489c9d2dd
--- /dev/null
+++ b/include/asm-ia64/sn/tiocp.h
@@ -0,0 +1,256 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003-2004 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_PCI_TIOCP_H
9#define _ASM_IA64_SN_PCI_TIOCP_H
10
11#define TIOCP_HOST_INTR_ADDR 0x003FFFFFFFFFFFFFUL
12#define TIOCP_PCI64_CMDTYPE_MEM (0x1ull << 60)
13
14
15/*****************************************************************************
16 *********************** TIOCP MMR structure mapping ***************************
17 *****************************************************************************/
18
19struct tiocp{
20
21 /* 0x000000-0x00FFFF -- Local Registers */
22
23 /* 0x000000-0x000057 -- (Legacy Widget Space) Configuration */
24 uint64_t cp_id; /* 0x000000 */
25 uint64_t cp_stat; /* 0x000008 */
26 uint64_t cp_err_upper; /* 0x000010 */
27 uint64_t cp_err_lower; /* 0x000018 */
28 #define cp_err cp_err_lower
29 uint64_t cp_control; /* 0x000020 */
30 uint64_t cp_req_timeout; /* 0x000028 */
31 uint64_t cp_intr_upper; /* 0x000030 */
32 uint64_t cp_intr_lower; /* 0x000038 */
33 #define cp_intr cp_intr_lower
34 uint64_t cp_err_cmdword; /* 0x000040 */
35 uint64_t _pad_000048; /* 0x000048 */
36 uint64_t cp_tflush; /* 0x000050 */
37
38 /* 0x000058-0x00007F -- Bridge-specific Configuration */
39 uint64_t cp_aux_err; /* 0x000058 */
40 uint64_t cp_resp_upper; /* 0x000060 */
41 uint64_t cp_resp_lower; /* 0x000068 */
42 #define cp_resp cp_resp_lower
43 uint64_t cp_tst_pin_ctrl; /* 0x000070 */
44 uint64_t cp_addr_lkerr; /* 0x000078 */
45
46 /* 0x000080-0x00008F -- PMU & MAP */
47 uint64_t cp_dir_map; /* 0x000080 */
48 uint64_t _pad_000088; /* 0x000088 */
49
50 /* 0x000090-0x00009F -- SSRAM */
51 uint64_t cp_map_fault; /* 0x000090 */
52 uint64_t _pad_000098; /* 0x000098 */
53
54 /* 0x0000A0-0x0000AF -- Arbitration */
55 uint64_t cp_arb; /* 0x0000A0 */
56 uint64_t _pad_0000A8; /* 0x0000A8 */
57
58 /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
59 uint64_t cp_ate_parity_err; /* 0x0000B0 */
60 uint64_t _pad_0000B8; /* 0x0000B8 */
61
62 /* 0x0000C0-0x0000FF -- PCI/GIO */
63 uint64_t cp_bus_timeout; /* 0x0000C0 */
64 uint64_t cp_pci_cfg; /* 0x0000C8 */
65 uint64_t cp_pci_err_upper; /* 0x0000D0 */
66 uint64_t cp_pci_err_lower; /* 0x0000D8 */
67 #define cp_pci_err cp_pci_err_lower
68 uint64_t _pad_0000E0[4]; /* 0x0000{E0..F8} */
69
70 /* 0x000100-0x0001FF -- Interrupt */
71 uint64_t cp_int_status; /* 0x000100 */
72 uint64_t cp_int_enable; /* 0x000108 */
73 uint64_t cp_int_rst_stat; /* 0x000110 */
74 uint64_t cp_int_mode; /* 0x000118 */
75 uint64_t cp_int_device; /* 0x000120 */
76 uint64_t cp_int_host_err; /* 0x000128 */
77 uint64_t cp_int_addr[8]; /* 0x0001{30,,,68} */
78 uint64_t cp_err_int_view; /* 0x000170 */
79 uint64_t cp_mult_int; /* 0x000178 */
80 uint64_t cp_force_always[8]; /* 0x0001{80,,,B8} */
81 uint64_t cp_force_pin[8]; /* 0x0001{C0,,,F8} */
82
83 /* 0x000200-0x000298 -- Device */
84 uint64_t cp_device[4]; /* 0x0002{00,,,18} */
85 uint64_t _pad_000220[4]; /* 0x0002{20,,,38} */
86 uint64_t cp_wr_req_buf[4]; /* 0x0002{40,,,58} */
87 uint64_t _pad_000260[4]; /* 0x0002{60,,,78} */
88 uint64_t cp_rrb_map[2]; /* 0x0002{80,,,88} */
89 #define cp_even_resp cp_rrb_map[0] /* 0x000280 */
90 #define cp_odd_resp cp_rrb_map[1] /* 0x000288 */
91 uint64_t cp_resp_status; /* 0x000290 */
92 uint64_t cp_resp_clear; /* 0x000298 */
93
94 uint64_t _pad_0002A0[12]; /* 0x0002{A0..F8} */
95
96 /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
97 struct {
98 uint64_t upper; /* 0x0003{00,,,F0} */
99 uint64_t lower; /* 0x0003{08,,,F8} */
100 } cp_buf_addr_match[16];
101
102 /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
103 struct {
104 uint64_t flush_w_touch; /* 0x000{400,,,5C0} */
105 uint64_t flush_wo_touch; /* 0x000{408,,,5C8} */
106 uint64_t inflight; /* 0x000{410,,,5D0} */
107 uint64_t prefetch; /* 0x000{418,,,5D8} */
108 uint64_t total_pci_retry; /* 0x000{420,,,5E0} */
109 uint64_t max_pci_retry; /* 0x000{428,,,5E8} */
110 uint64_t max_latency; /* 0x000{430,,,5F0} */
111 uint64_t clear_all; /* 0x000{438,,,5F8} */
112 } cp_buf_count[8];
113
114
115 /* 0x000600-0x0009FF -- PCI/X registers */
116 uint64_t cp_pcix_bus_err_addr; /* 0x000600 */
117 uint64_t cp_pcix_bus_err_attr; /* 0x000608 */
118 uint64_t cp_pcix_bus_err_data; /* 0x000610 */
119 uint64_t cp_pcix_pio_split_addr; /* 0x000618 */
120 uint64_t cp_pcix_pio_split_attr; /* 0x000620 */
121 uint64_t cp_pcix_dma_req_err_attr; /* 0x000628 */
122 uint64_t cp_pcix_dma_req_err_addr; /* 0x000630 */
123 uint64_t cp_pcix_timeout; /* 0x000638 */
124
125 uint64_t _pad_000640[24]; /* 0x000{640,,,6F8} */
126
127 /* 0x000700-0x000737 -- Debug Registers */
128 uint64_t cp_ct_debug_ctl; /* 0x000700 */
129 uint64_t cp_br_debug_ctl; /* 0x000708 */
130 uint64_t cp_mux3_debug_ctl; /* 0x000710 */
131 uint64_t cp_mux4_debug_ctl; /* 0x000718 */
132 uint64_t cp_mux5_debug_ctl; /* 0x000720 */
133 uint64_t cp_mux6_debug_ctl; /* 0x000728 */
134 uint64_t cp_mux7_debug_ctl; /* 0x000730 */
135
136 uint64_t _pad_000738[89]; /* 0x000{738,,,9F8} */
137
138 /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
139 struct {
140 uint64_t cp_buf_addr; /* 0x000{A00,,,AF0} */
141 uint64_t cp_buf_attr; /* 0X000{A08,,,AF8} */
142 } cp_pcix_read_buf_64[16];
143
144 struct {
145 uint64_t cp_buf_addr; /* 0x000{B00,,,BE0} */
146 uint64_t cp_buf_attr; /* 0x000{B08,,,BE8} */
147 uint64_t cp_buf_valid; /* 0x000{B10,,,BF0} */
148 uint64_t __pad1; /* 0x000{B18,,,BF8} */
149 } cp_pcix_write_buf_64[8];
150
151 /* End of Local Registers -- Start of Address Map space */
152
153 char _pad_000c00[0x010000 - 0x000c00];
154
155 /* 0x010000-0x011FF8 -- Internal ATE RAM (Auto Parity Generation) */
156 uint64_t cp_int_ate_ram[1024]; /* 0x010000-0x011FF8 */
157
158 char _pad_012000[0x14000 - 0x012000];
159
160 /* 0x014000-0x015FF8 -- Internal ATE RAM (Manual Parity Generation) */
161 uint64_t cp_int_ate_ram_mp[1024]; /* 0x014000-0x015FF8 */
162
163 char _pad_016000[0x18000 - 0x016000];
164
165 /* 0x18000-0x197F8 -- TIOCP Write Request Ram */
166 uint64_t cp_wr_req_lower[256]; /* 0x18000 - 0x187F8 */
167 uint64_t cp_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */
168 uint64_t cp_wr_req_parity[256]; /* 0x19000 - 0x197F8 */
169
170 char _pad_019800[0x1C000 - 0x019800];
171
172 /* 0x1C000-0x1EFF8 -- TIOCP Read Response Ram */
173 uint64_t cp_rd_resp_lower[512]; /* 0x1C000 - 0x1CFF8 */
174 uint64_t cp_rd_resp_upper[512]; /* 0x1D000 - 0x1DFF8 */
175 uint64_t cp_rd_resp_parity[512]; /* 0x1E000 - 0x1EFF8 */
176
177 char _pad_01F000[0x20000 - 0x01F000];
178
179 /* 0x020000-0x021FFF -- Host Device (CP) Configuration Space (not used) */
180 char _pad_020000[0x021000 - 0x20000];
181
182 /* 0x021000-0x027FFF -- PCI Device Configuration Spaces */
183 union {
184 uint8_t c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */
185 uint16_t s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */
186 uint32_t l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */
187 uint64_t d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */
188 union {
189 uint8_t c[0x100 / 1];
190 uint16_t s[0x100 / 2];
191 uint32_t l[0x100 / 4];
192 uint64_t d[0x100 / 8];
193 } f[8];
194 } cp_type0_cfg_dev[7]; /* 0x02{1000,,,7FFF} */
195
196 /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
197 union {
198 uint8_t c[0x1000 / 1]; /* 0x028000-0x029000 */
199 uint16_t s[0x1000 / 2]; /* 0x028000-0x029000 */
200 uint32_t l[0x1000 / 4]; /* 0x028000-0x029000 */
201 uint64_t d[0x1000 / 8]; /* 0x028000-0x029000 */
202 union {
203 uint8_t c[0x100 / 1];
204 uint16_t s[0x100 / 2];
205 uint32_t l[0x100 / 4];
206 uint64_t d[0x100 / 8];
207 } f[8];
208 } cp_type1_cfg; /* 0x028000-0x029000 */
209
210 char _pad_029000[0x030000-0x029000];
211
212 /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
213 union {
214 uint8_t c[8 / 1];
215 uint16_t s[8 / 2];
216 uint32_t l[8 / 4];
217 uint64_t d[8 / 8];
218 } cp_pci_iack; /* 0x030000-0x030007 */
219
220 char _pad_030007[0x040000-0x030008];
221
222 /* 0x040000-0x040007 -- PCIX Special Cycle */
223 union {
224 uint8_t c[8 / 1];
225 uint16_t s[8 / 2];
226 uint32_t l[8 / 4];
227 uint64_t d[8 / 8];
228 } cp_pcix_cycle; /* 0x040000-0x040007 */
229
230 char _pad_040007[0x200000-0x040008];
231
232 /* 0x200000-0x7FFFFF -- PCI/GIO Device Spaces */
233 union {
234 uint8_t c[0x100000 / 1];
235 uint16_t s[0x100000 / 2];
236 uint32_t l[0x100000 / 4];
237 uint64_t d[0x100000 / 8];
238 } cp_devio_raw[6]; /* 0x200000-0x7FFFFF */
239
240 #define cp_devio(n) cp_devio_raw[((n)<2)?(n*2):(n+2)]
241
242 char _pad_800000[0xA00000-0x800000];
243
244 /* 0xA00000-0xBFFFFF -- PCI/GIO Device Spaces w/flush */
245 union {
246 uint8_t c[0x100000 / 1];
247 uint16_t s[0x100000 / 2];
248 uint32_t l[0x100000 / 4];
249 uint64_t d[0x100000 / 8];
250 } cp_devio_raw_flush[6]; /* 0xA00000-0xBFFFFF */
251
252 #define cp_devio_flush(n) cp_devio_raw_flush[((n)<2)?(n*2):(n+2)]
253
254};
255
256#endif /* _ASM_IA64_SN_PCI_TIOCP_H */
diff --git a/include/asm-ia64/sn/xp.h b/include/asm-ia64/sn/xp.h
index 9902185c0288..1df1c9f61a65 100644
--- a/include/asm-ia64/sn/xp.h
+++ b/include/asm-ia64/sn/xp.h
@@ -16,7 +16,6 @@
16#define _ASM_IA64_SN_XP_H 16#define _ASM_IA64_SN_XP_H
17 17
18 18
19#include <linux/version.h>
20#include <linux/cache.h> 19#include <linux/cache.h>
21#include <linux/hardirq.h> 20#include <linux/hardirq.h>
22#include <asm/sn/types.h> 21#include <asm/sn/types.h>
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-04 23:45:05 -0500