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authorPrarit Bhargava <prarit@sgi.com>2006-01-16 22:54:40 -0500
committerTony Luck <tony.luck@intel.com>2006-01-16 22:54:40 -0500
commit53493dcf6e9e27cc9379cbf8962642986927aea9 (patch)
tree7d7cb54a7020220058b459d60f06691cea71236f /include/asm-ia64/sn/tioca.h
parentf15ac5801fdc1b217c3b8b5dbc63a09371d2ee4d (diff)
[IA64] Cleanup of arch/ia64/sn and include/asm-ia64/sn
Replace uintX_t declarations with uX declarations. Replace intX_t declarations with sX declarations. Signed-off-by: Prarit Bhargava <prarit@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'include/asm-ia64/sn/tioca.h')
-rw-r--r--include/asm-ia64/sn/tioca.h82
1 files changed, 41 insertions, 41 deletions
diff --git a/include/asm-ia64/sn/tioca.h b/include/asm-ia64/sn/tioca.h
index bc1aacfb9483..666222d7f0f6 100644
--- a/include/asm-ia64/sn/tioca.h
+++ b/include/asm-ia64/sn/tioca.h
@@ -19,47 +19,47 @@
19 */ 19 */
20 20
21struct tioca { 21struct tioca {
22 uint64_t ca_id; /* 0x000000 */ 22 u64 ca_id; /* 0x000000 */
23 uint64_t ca_control1; /* 0x000008 */ 23 u64 ca_control1; /* 0x000008 */
24 uint64_t ca_control2; /* 0x000010 */ 24 u64 ca_control2; /* 0x000010 */
25 uint64_t ca_status1; /* 0x000018 */ 25 u64 ca_status1; /* 0x000018 */
26 uint64_t ca_status2; /* 0x000020 */ 26 u64 ca_status2; /* 0x000020 */
27 uint64_t ca_gart_aperature; /* 0x000028 */ 27 u64 ca_gart_aperature; /* 0x000028 */
28 uint64_t ca_gfx_detach; /* 0x000030 */ 28 u64 ca_gfx_detach; /* 0x000030 */
29 uint64_t ca_inta_dest_addr; /* 0x000038 */ 29 u64 ca_inta_dest_addr; /* 0x000038 */
30 uint64_t ca_intb_dest_addr; /* 0x000040 */ 30 u64 ca_intb_dest_addr; /* 0x000040 */
31 uint64_t ca_err_int_dest_addr; /* 0x000048 */ 31 u64 ca_err_int_dest_addr; /* 0x000048 */
32 uint64_t ca_int_status; /* 0x000050 */ 32 u64 ca_int_status; /* 0x000050 */
33 uint64_t ca_int_status_alias; /* 0x000058 */ 33 u64 ca_int_status_alias; /* 0x000058 */
34 uint64_t ca_mult_error; /* 0x000060 */ 34 u64 ca_mult_error; /* 0x000060 */
35 uint64_t ca_mult_error_alias; /* 0x000068 */ 35 u64 ca_mult_error_alias; /* 0x000068 */
36 uint64_t ca_first_error; /* 0x000070 */ 36 u64 ca_first_error; /* 0x000070 */
37 uint64_t ca_int_mask; /* 0x000078 */ 37 u64 ca_int_mask; /* 0x000078 */
38 uint64_t ca_crm_pkterr_type; /* 0x000080 */ 38 u64 ca_crm_pkterr_type; /* 0x000080 */
39 uint64_t ca_crm_pkterr_type_alias; /* 0x000088 */ 39 u64 ca_crm_pkterr_type_alias; /* 0x000088 */
40 uint64_t ca_crm_ct_error_detail_1; /* 0x000090 */ 40 u64 ca_crm_ct_error_detail_1; /* 0x000090 */
41 uint64_t ca_crm_ct_error_detail_2; /* 0x000098 */ 41 u64 ca_crm_ct_error_detail_2; /* 0x000098 */
42 uint64_t ca_crm_tnumto; /* 0x0000A0 */ 42 u64 ca_crm_tnumto; /* 0x0000A0 */
43 uint64_t ca_gart_err; /* 0x0000A8 */ 43 u64 ca_gart_err; /* 0x0000A8 */
44 uint64_t ca_pcierr_type; /* 0x0000B0 */ 44 u64 ca_pcierr_type; /* 0x0000B0 */
45 uint64_t ca_pcierr_addr; /* 0x0000B8 */ 45 u64 ca_pcierr_addr; /* 0x0000B8 */
46 46
47 uint64_t ca_pad_0000C0[3]; /* 0x0000{C0..D0} */ 47 u64 ca_pad_0000C0[3]; /* 0x0000{C0..D0} */
48 48
49 uint64_t ca_pci_rd_buf_flush; /* 0x0000D8 */ 49 u64 ca_pci_rd_buf_flush; /* 0x0000D8 */
50 uint64_t ca_pci_dma_addr_extn; /* 0x0000E0 */ 50 u64 ca_pci_dma_addr_extn; /* 0x0000E0 */
51 uint64_t ca_agp_dma_addr_extn; /* 0x0000E8 */ 51 u64 ca_agp_dma_addr_extn; /* 0x0000E8 */
52 uint64_t ca_force_inta; /* 0x0000F0 */ 52 u64 ca_force_inta; /* 0x0000F0 */
53 uint64_t ca_force_intb; /* 0x0000F8 */ 53 u64 ca_force_intb; /* 0x0000F8 */
54 uint64_t ca_debug_vector_sel; /* 0x000100 */ 54 u64 ca_debug_vector_sel; /* 0x000100 */
55 uint64_t ca_debug_mux_core_sel; /* 0x000108 */ 55 u64 ca_debug_mux_core_sel; /* 0x000108 */
56 uint64_t ca_debug_mux_pci_sel; /* 0x000110 */ 56 u64 ca_debug_mux_pci_sel; /* 0x000110 */
57 uint64_t ca_debug_domain_sel; /* 0x000118 */ 57 u64 ca_debug_domain_sel; /* 0x000118 */
58 58
59 uint64_t ca_pad_000120[28]; /* 0x0001{20..F8} */ 59 u64 ca_pad_000120[28]; /* 0x0001{20..F8} */
60 60
61 uint64_t ca_gart_ptr_table; /* 0x200 */ 61 u64 ca_gart_ptr_table; /* 0x200 */
62 uint64_t ca_gart_tlb_addr[8]; /* 0x2{08..40} */ 62 u64 ca_gart_tlb_addr[8]; /* 0x2{08..40} */
63}; 63};
64 64
65/* 65/*