diff options
author | Prarit Bhargava <prarit@sgi.com> | 2006-01-16 22:54:40 -0500 |
---|---|---|
committer | Tony Luck <tony.luck@intel.com> | 2006-01-16 22:54:40 -0500 |
commit | 53493dcf6e9e27cc9379cbf8962642986927aea9 (patch) | |
tree | 7d7cb54a7020220058b459d60f06691cea71236f /include/asm-ia64/sn/shubio.h | |
parent | f15ac5801fdc1b217c3b8b5dbc63a09371d2ee4d (diff) |
[IA64] Cleanup of arch/ia64/sn and include/asm-ia64/sn
Replace uintX_t declarations with uX declarations.
Replace intX_t declarations with sX declarations.
Signed-off-by: Prarit Bhargava <prarit@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'include/asm-ia64/sn/shubio.h')
-rw-r--r-- | include/asm-ia64/sn/shubio.h | 1620 |
1 files changed, 810 insertions, 810 deletions
diff --git a/include/asm-ia64/sn/shubio.h b/include/asm-ia64/sn/shubio.h index 831b72111fdc..22a6f18a5313 100644 --- a/include/asm-ia64/sn/shubio.h +++ b/include/asm-ia64/sn/shubio.h | |||
@@ -227,13 +227,13 @@ | |||
227 | ************************************************************************/ | 227 | ************************************************************************/ |
228 | 228 | ||
229 | typedef union ii_wid_u { | 229 | typedef union ii_wid_u { |
230 | uint64_t ii_wid_regval; | 230 | u64 ii_wid_regval; |
231 | struct { | 231 | struct { |
232 | uint64_t w_rsvd_1:1; | 232 | u64 w_rsvd_1:1; |
233 | uint64_t w_mfg_num:11; | 233 | u64 w_mfg_num:11; |
234 | uint64_t w_part_num:16; | 234 | u64 w_part_num:16; |
235 | uint64_t w_rev_num:4; | 235 | u64 w_rev_num:4; |
236 | uint64_t w_rsvd:32; | 236 | u64 w_rsvd:32; |
237 | } ii_wid_fld_s; | 237 | } ii_wid_fld_s; |
238 | } ii_wid_u_t; | 238 | } ii_wid_u_t; |
239 | 239 | ||
@@ -246,18 +246,18 @@ typedef union ii_wid_u { | |||
246 | ************************************************************************/ | 246 | ************************************************************************/ |
247 | 247 | ||
248 | typedef union ii_wstat_u { | 248 | typedef union ii_wstat_u { |
249 | uint64_t ii_wstat_regval; | 249 | u64 ii_wstat_regval; |
250 | struct { | 250 | struct { |
251 | uint64_t w_pending:4; | 251 | u64 w_pending:4; |
252 | uint64_t w_xt_crd_to:1; | 252 | u64 w_xt_crd_to:1; |
253 | uint64_t w_xt_tail_to:1; | 253 | u64 w_xt_tail_to:1; |
254 | uint64_t w_rsvd_3:3; | 254 | u64 w_rsvd_3:3; |
255 | uint64_t w_tx_mx_rty:1; | 255 | u64 w_tx_mx_rty:1; |
256 | uint64_t w_rsvd_2:6; | 256 | u64 w_rsvd_2:6; |
257 | uint64_t w_llp_tx_cnt:8; | 257 | u64 w_llp_tx_cnt:8; |
258 | uint64_t w_rsvd_1:8; | 258 | u64 w_rsvd_1:8; |
259 | uint64_t w_crazy:1; | 259 | u64 w_crazy:1; |
260 | uint64_t w_rsvd:31; | 260 | u64 w_rsvd:31; |
261 | } ii_wstat_fld_s; | 261 | } ii_wstat_fld_s; |
262 | } ii_wstat_u_t; | 262 | } ii_wstat_u_t; |
263 | 263 | ||
@@ -269,16 +269,16 @@ typedef union ii_wstat_u { | |||
269 | ************************************************************************/ | 269 | ************************************************************************/ |
270 | 270 | ||
271 | typedef union ii_wcr_u { | 271 | typedef union ii_wcr_u { |
272 | uint64_t ii_wcr_regval; | 272 | u64 ii_wcr_regval; |
273 | struct { | 273 | struct { |
274 | uint64_t w_wid:4; | 274 | u64 w_wid:4; |
275 | uint64_t w_tag:1; | 275 | u64 w_tag:1; |
276 | uint64_t w_rsvd_1:8; | 276 | u64 w_rsvd_1:8; |
277 | uint64_t w_dst_crd:3; | 277 | u64 w_dst_crd:3; |
278 | uint64_t w_f_bad_pkt:1; | 278 | u64 w_f_bad_pkt:1; |
279 | uint64_t w_dir_con:1; | 279 | u64 w_dir_con:1; |
280 | uint64_t w_e_thresh:5; | 280 | u64 w_e_thresh:5; |
281 | uint64_t w_rsvd:41; | 281 | u64 w_rsvd:41; |
282 | } ii_wcr_fld_s; | 282 | } ii_wcr_fld_s; |
283 | } ii_wcr_u_t; | 283 | } ii_wcr_u_t; |
284 | 284 | ||
@@ -310,9 +310,9 @@ typedef union ii_wcr_u { | |||
310 | ************************************************************************/ | 310 | ************************************************************************/ |
311 | 311 | ||
312 | typedef union ii_ilapr_u { | 312 | typedef union ii_ilapr_u { |
313 | uint64_t ii_ilapr_regval; | 313 | u64 ii_ilapr_regval; |
314 | struct { | 314 | struct { |
315 | uint64_t i_region:64; | 315 | u64 i_region:64; |
316 | } ii_ilapr_fld_s; | 316 | } ii_ilapr_fld_s; |
317 | } ii_ilapr_u_t; | 317 | } ii_ilapr_u_t; |
318 | 318 | ||
@@ -330,9 +330,9 @@ typedef union ii_ilapr_u { | |||
330 | ************************************************************************/ | 330 | ************************************************************************/ |
331 | 331 | ||
332 | typedef union ii_ilapo_u { | 332 | typedef union ii_ilapo_u { |
333 | uint64_t ii_ilapo_regval; | 333 | u64 ii_ilapo_regval; |
334 | struct { | 334 | struct { |
335 | uint64_t i_io_ovrride:64; | 335 | u64 i_io_ovrride:64; |
336 | } ii_ilapo_fld_s; | 336 | } ii_ilapo_fld_s; |
337 | } ii_ilapo_u_t; | 337 | } ii_ilapo_u_t; |
338 | 338 | ||
@@ -344,12 +344,12 @@ typedef union ii_ilapo_u { | |||
344 | ************************************************************************/ | 344 | ************************************************************************/ |
345 | 345 | ||
346 | typedef union ii_iowa_u { | 346 | typedef union ii_iowa_u { |
347 | uint64_t ii_iowa_regval; | 347 | u64 ii_iowa_regval; |
348 | struct { | 348 | struct { |
349 | uint64_t i_w0_oac:1; | 349 | u64 i_w0_oac:1; |
350 | uint64_t i_rsvd_1:7; | 350 | u64 i_rsvd_1:7; |
351 | uint64_t i_wx_oac:8; | 351 | u64 i_wx_oac:8; |
352 | uint64_t i_rsvd:48; | 352 | u64 i_rsvd:48; |
353 | } ii_iowa_fld_s; | 353 | } ii_iowa_fld_s; |
354 | } ii_iowa_u_t; | 354 | } ii_iowa_u_t; |
355 | 355 | ||
@@ -363,12 +363,12 @@ typedef union ii_iowa_u { | |||
363 | ************************************************************************/ | 363 | ************************************************************************/ |
364 | 364 | ||
365 | typedef union ii_iiwa_u { | 365 | typedef union ii_iiwa_u { |
366 | uint64_t ii_iiwa_regval; | 366 | u64 ii_iiwa_regval; |
367 | struct { | 367 | struct { |
368 | uint64_t i_w0_iac:1; | 368 | u64 i_w0_iac:1; |
369 | uint64_t i_rsvd_1:7; | 369 | u64 i_rsvd_1:7; |
370 | uint64_t i_wx_iac:8; | 370 | u64 i_wx_iac:8; |
371 | uint64_t i_rsvd:48; | 371 | u64 i_rsvd:48; |
372 | } ii_iiwa_fld_s; | 372 | } ii_iiwa_fld_s; |
373 | } ii_iiwa_u_t; | 373 | } ii_iiwa_u_t; |
374 | 374 | ||
@@ -392,16 +392,16 @@ typedef union ii_iiwa_u { | |||
392 | ************************************************************************/ | 392 | ************************************************************************/ |
393 | 393 | ||
394 | typedef union ii_iidem_u { | 394 | typedef union ii_iidem_u { |
395 | uint64_t ii_iidem_regval; | 395 | u64 ii_iidem_regval; |
396 | struct { | 396 | struct { |
397 | uint64_t i_w8_dxs:8; | 397 | u64 i_w8_dxs:8; |
398 | uint64_t i_w9_dxs:8; | 398 | u64 i_w9_dxs:8; |
399 | uint64_t i_wa_dxs:8; | 399 | u64 i_wa_dxs:8; |
400 | uint64_t i_wb_dxs:8; | 400 | u64 i_wb_dxs:8; |
401 | uint64_t i_wc_dxs:8; | 401 | u64 i_wc_dxs:8; |
402 | uint64_t i_wd_dxs:8; | 402 | u64 i_wd_dxs:8; |
403 | uint64_t i_we_dxs:8; | 403 | u64 i_we_dxs:8; |
404 | uint64_t i_wf_dxs:8; | 404 | u64 i_wf_dxs:8; |
405 | } ii_iidem_fld_s; | 405 | } ii_iidem_fld_s; |
406 | } ii_iidem_u_t; | 406 | } ii_iidem_u_t; |
407 | 407 | ||
@@ -413,22 +413,22 @@ typedef union ii_iidem_u { | |||
413 | ************************************************************************/ | 413 | ************************************************************************/ |
414 | 414 | ||
415 | typedef union ii_ilcsr_u { | 415 | typedef union ii_ilcsr_u { |
416 | uint64_t ii_ilcsr_regval; | 416 | u64 ii_ilcsr_regval; |
417 | struct { | 417 | struct { |
418 | uint64_t i_nullto:6; | 418 | u64 i_nullto:6; |
419 | uint64_t i_rsvd_4:2; | 419 | u64 i_rsvd_4:2; |
420 | uint64_t i_wrmrst:1; | 420 | u64 i_wrmrst:1; |
421 | uint64_t i_rsvd_3:1; | 421 | u64 i_rsvd_3:1; |
422 | uint64_t i_llp_en:1; | 422 | u64 i_llp_en:1; |
423 | uint64_t i_bm8:1; | 423 | u64 i_bm8:1; |
424 | uint64_t i_llp_stat:2; | 424 | u64 i_llp_stat:2; |
425 | uint64_t i_remote_power:1; | 425 | u64 i_remote_power:1; |
426 | uint64_t i_rsvd_2:1; | 426 | u64 i_rsvd_2:1; |
427 | uint64_t i_maxrtry:10; | 427 | u64 i_maxrtry:10; |
428 | uint64_t i_d_avail_sel:2; | 428 | u64 i_d_avail_sel:2; |
429 | uint64_t i_rsvd_1:4; | 429 | u64 i_rsvd_1:4; |
430 | uint64_t i_maxbrst:10; | 430 | u64 i_maxbrst:10; |
431 | uint64_t i_rsvd:22; | 431 | u64 i_rsvd:22; |
432 | 432 | ||
433 | } ii_ilcsr_fld_s; | 433 | } ii_ilcsr_fld_s; |
434 | } ii_ilcsr_u_t; | 434 | } ii_ilcsr_u_t; |
@@ -441,11 +441,11 @@ typedef union ii_ilcsr_u { | |||
441 | ************************************************************************/ | 441 | ************************************************************************/ |
442 | 442 | ||
443 | typedef union ii_illr_u { | 443 | typedef union ii_illr_u { |
444 | uint64_t ii_illr_regval; | 444 | u64 ii_illr_regval; |
445 | struct { | 445 | struct { |
446 | uint64_t i_sn_cnt:16; | 446 | u64 i_sn_cnt:16; |
447 | uint64_t i_cb_cnt:16; | 447 | u64 i_cb_cnt:16; |
448 | uint64_t i_rsvd:32; | 448 | u64 i_rsvd:32; |
449 | } ii_illr_fld_s; | 449 | } ii_illr_fld_s; |
450 | } ii_illr_u_t; | 450 | } ii_illr_u_t; |
451 | 451 | ||
@@ -464,19 +464,19 @@ typedef union ii_illr_u { | |||
464 | ************************************************************************/ | 464 | ************************************************************************/ |
465 | 465 | ||
466 | typedef union ii_iidsr_u { | 466 | typedef union ii_iidsr_u { |
467 | uint64_t ii_iidsr_regval; | 467 | u64 ii_iidsr_regval; |
468 | struct { | 468 | struct { |
469 | uint64_t i_level:8; | 469 | u64 i_level:8; |
470 | uint64_t i_pi_id:1; | 470 | u64 i_pi_id:1; |
471 | uint64_t i_node:11; | 471 | u64 i_node:11; |
472 | uint64_t i_rsvd_3:4; | 472 | u64 i_rsvd_3:4; |
473 | uint64_t i_enable:1; | 473 | u64 i_enable:1; |
474 | uint64_t i_rsvd_2:3; | 474 | u64 i_rsvd_2:3; |
475 | uint64_t i_int_sent:2; | 475 | u64 i_int_sent:2; |
476 | uint64_t i_rsvd_1:2; | 476 | u64 i_rsvd_1:2; |
477 | uint64_t i_pi0_forward_int:1; | 477 | u64 i_pi0_forward_int:1; |
478 | uint64_t i_pi1_forward_int:1; | 478 | u64 i_pi1_forward_int:1; |
479 | uint64_t i_rsvd:30; | 479 | u64 i_rsvd:30; |
480 | } ii_iidsr_fld_s; | 480 | } ii_iidsr_fld_s; |
481 | } ii_iidsr_u_t; | 481 | } ii_iidsr_u_t; |
482 | 482 | ||
@@ -492,13 +492,13 @@ typedef union ii_iidsr_u { | |||
492 | ************************************************************************/ | 492 | ************************************************************************/ |
493 | 493 | ||
494 | typedef union ii_igfx0_u { | 494 | typedef union ii_igfx0_u { |
495 | uint64_t ii_igfx0_regval; | 495 | u64 ii_igfx0_regval; |
496 | struct { | 496 | struct { |
497 | uint64_t i_w_num:4; | 497 | u64 i_w_num:4; |
498 | uint64_t i_pi_id:1; | 498 | u64 i_pi_id:1; |
499 | uint64_t i_n_num:12; | 499 | u64 i_n_num:12; |
500 | uint64_t i_p_num:1; | 500 | u64 i_p_num:1; |
501 | uint64_t i_rsvd:46; | 501 | u64 i_rsvd:46; |
502 | } ii_igfx0_fld_s; | 502 | } ii_igfx0_fld_s; |
503 | } ii_igfx0_u_t; | 503 | } ii_igfx0_u_t; |
504 | 504 | ||
@@ -514,13 +514,13 @@ typedef union ii_igfx0_u { | |||
514 | ************************************************************************/ | 514 | ************************************************************************/ |
515 | 515 | ||
516 | typedef union ii_igfx1_u { | 516 | typedef union ii_igfx1_u { |
517 | uint64_t ii_igfx1_regval; | 517 | u64 ii_igfx1_regval; |
518 | struct { | 518 | struct { |
519 | uint64_t i_w_num:4; | 519 | u64 i_w_num:4; |
520 | uint64_t i_pi_id:1; | 520 | u64 i_pi_id:1; |
521 | uint64_t i_n_num:12; | 521 | u64 i_n_num:12; |
522 | uint64_t i_p_num:1; | 522 | u64 i_p_num:1; |
523 | uint64_t i_rsvd:46; | 523 | u64 i_rsvd:46; |
524 | } ii_igfx1_fld_s; | 524 | } ii_igfx1_fld_s; |
525 | } ii_igfx1_u_t; | 525 | } ii_igfx1_u_t; |
526 | 526 | ||
@@ -532,9 +532,9 @@ typedef union ii_igfx1_u { | |||
532 | ************************************************************************/ | 532 | ************************************************************************/ |
533 | 533 | ||
534 | typedef union ii_iscr0_u { | 534 | typedef union ii_iscr0_u { |
535 | uint64_t ii_iscr0_regval; | 535 | u64 ii_iscr0_regval; |
536 | struct { | 536 | struct { |
537 | uint64_t i_scratch:64; | 537 | u64 i_scratch:64; |
538 | } ii_iscr0_fld_s; | 538 | } ii_iscr0_fld_s; |
539 | } ii_iscr0_u_t; | 539 | } ii_iscr0_u_t; |
540 | 540 | ||
@@ -546,9 +546,9 @@ typedef union ii_iscr0_u { | |||
546 | ************************************************************************/ | 546 | ************************************************************************/ |
547 | 547 | ||
548 | typedef union ii_iscr1_u { | 548 | typedef union ii_iscr1_u { |
549 | uint64_t ii_iscr1_regval; | 549 | u64 ii_iscr1_regval; |
550 | struct { | 550 | struct { |
551 | uint64_t i_scratch:64; | 551 | u64 i_scratch:64; |
552 | } ii_iscr1_fld_s; | 552 | } ii_iscr1_fld_s; |
553 | } ii_iscr1_u_t; | 553 | } ii_iscr1_u_t; |
554 | 554 | ||
@@ -580,13 +580,13 @@ typedef union ii_iscr1_u { | |||
580 | ************************************************************************/ | 580 | ************************************************************************/ |
581 | 581 | ||
582 | typedef union ii_itte1_u { | 582 | typedef union ii_itte1_u { |
583 | uint64_t ii_itte1_regval; | 583 | u64 ii_itte1_regval; |
584 | struct { | 584 | struct { |
585 | uint64_t i_offset:5; | 585 | u64 i_offset:5; |
586 | uint64_t i_rsvd_1:3; | 586 | u64 i_rsvd_1:3; |
587 | uint64_t i_w_num:4; | 587 | u64 i_w_num:4; |
588 | uint64_t i_iosp:1; | 588 | u64 i_iosp:1; |
589 | uint64_t i_rsvd:51; | 589 | u64 i_rsvd:51; |
590 | } ii_itte1_fld_s; | 590 | } ii_itte1_fld_s; |
591 | } ii_itte1_u_t; | 591 | } ii_itte1_u_t; |
592 | 592 | ||
@@ -618,13 +618,13 @@ typedef union ii_itte1_u { | |||
618 | ************************************************************************/ | 618 | ************************************************************************/ |
619 | 619 | ||
620 | typedef union ii_itte2_u { | 620 | typedef union ii_itte2_u { |
621 | uint64_t ii_itte2_regval; | 621 | u64 ii_itte2_regval; |
622 | struct { | 622 | struct { |
623 | uint64_t i_offset:5; | 623 | u64 i_offset:5; |
624 | uint64_t i_rsvd_1:3; | 624 | u64 i_rsvd_1:3; |
625 | uint64_t i_w_num:4; | 625 | u64 i_w_num:4; |
626 | uint64_t i_iosp:1; | 626 | u64 i_iosp:1; |
627 | uint64_t i_rsvd:51; | 627 | u64 i_rsvd:51; |
628 | } ii_itte2_fld_s; | 628 | } ii_itte2_fld_s; |
629 | } ii_itte2_u_t; | 629 | } ii_itte2_u_t; |
630 | 630 | ||
@@ -656,13 +656,13 @@ typedef union ii_itte2_u { | |||
656 | ************************************************************************/ | 656 | ************************************************************************/ |
657 | 657 | ||
658 | typedef union ii_itte3_u { | 658 | typedef union ii_itte3_u { |
659 | uint64_t ii_itte3_regval; | 659 | u64 ii_itte3_regval; |
660 | struct { | 660 | struct { |
661 | uint64_t i_offset:5; | 661 | u64 i_offset:5; |
662 | uint64_t i_rsvd_1:3; | 662 | u64 i_rsvd_1:3; |
663 | uint64_t i_w_num:4; | 663 | u64 i_w_num:4; |
664 | uint64_t i_iosp:1; | 664 | u64 i_iosp:1; |
665 | uint64_t i_rsvd:51; | 665 | u64 i_rsvd:51; |
666 | } ii_itte3_fld_s; | 666 | } ii_itte3_fld_s; |
667 | } ii_itte3_u_t; | 667 | } ii_itte3_u_t; |
668 | 668 | ||
@@ -694,13 +694,13 @@ typedef union ii_itte3_u { | |||
694 | ************************************************************************/ | 694 | ************************************************************************/ |
695 | 695 | ||
696 | typedef union ii_itte4_u { | 696 | typedef union ii_itte4_u { |
697 | uint64_t ii_itte4_regval; | 697 | u64 ii_itte4_regval; |
698 | struct { | 698 | struct { |
699 | uint64_t i_offset:5; | 699 | u64 i_offset:5; |
700 | uint64_t i_rsvd_1:3; | 700 | u64 i_rsvd_1:3; |
701 | uint64_t i_w_num:4; | 701 | u64 i_w_num:4; |
702 | uint64_t i_iosp:1; | 702 | u64 i_iosp:1; |
703 | uint64_t i_rsvd:51; | 703 | u64 i_rsvd:51; |
704 | } ii_itte4_fld_s; | 704 | } ii_itte4_fld_s; |
705 | } ii_itte4_u_t; | 705 | } ii_itte4_u_t; |
706 | 706 | ||
@@ -732,13 +732,13 @@ typedef union ii_itte4_u { | |||
732 | ************************************************************************/ | 732 | ************************************************************************/ |
733 | 733 | ||
734 | typedef union ii_itte5_u { | 734 | typedef union ii_itte5_u { |
735 | uint64_t ii_itte5_regval; | 735 | u64 ii_itte5_regval; |
736 | struct { | 736 | struct { |
737 | uint64_t i_offset:5; | 737 | u64 i_offset:5; |
738 | uint64_t i_rsvd_1:3; | 738 | u64 i_rsvd_1:3; |
739 | uint64_t i_w_num:4; | 739 | u64 i_w_num:4; |
740 | uint64_t i_iosp:1; | 740 | u64 i_iosp:1; |
741 | uint64_t i_rsvd:51; | 741 | u64 i_rsvd:51; |
742 | } ii_itte5_fld_s; | 742 | } ii_itte5_fld_s; |
743 | } ii_itte5_u_t; | 743 | } ii_itte5_u_t; |
744 | 744 | ||
@@ -770,13 +770,13 @@ typedef union ii_itte5_u { | |||
770 | ************************************************************************/ | 770 | ************************************************************************/ |
771 | 771 | ||
772 | typedef union ii_itte6_u { | 772 | typedef union ii_itte6_u { |
773 | uint64_t ii_itte6_regval; | 773 | u64 ii_itte6_regval; |
774 | struct { | 774 | struct { |
775 | uint64_t i_offset:5; | 775 | u64 i_offset:5; |
776 | uint64_t i_rsvd_1:3; | 776 | u64 i_rsvd_1:3; |
777 | uint64_t i_w_num:4; | 777 | u64 i_w_num:4; |
778 | uint64_t i_iosp:1; | 778 | u64 i_iosp:1; |
779 | uint64_t i_rsvd:51; | 779 | u64 i_rsvd:51; |
780 | } ii_itte6_fld_s; | 780 | } ii_itte6_fld_s; |
781 | } ii_itte6_u_t; | 781 | } ii_itte6_u_t; |
782 | 782 | ||
@@ -808,13 +808,13 @@ typedef union ii_itte6_u { | |||
808 | ************************************************************************/ | 808 | ************************************************************************/ |
809 | 809 | ||
810 | typedef union ii_itte7_u { | 810 | typedef union ii_itte7_u { |
811 | uint64_t ii_itte7_regval; | 811 | u64 ii_itte7_regval; |
812 | struct { | 812 | struct { |
813 | uint64_t i_offset:5; | 813 | u64 i_offset:5; |
814 | uint64_t i_rsvd_1:3; | 814 | u64 i_rsvd_1:3; |
815 | uint64_t i_w_num:4; | 815 | u64 i_w_num:4; |
816 | uint64_t i_iosp:1; | 816 | u64 i_iosp:1; |
817 | uint64_t i_rsvd:51; | 817 | u64 i_rsvd:51; |
818 | } ii_itte7_fld_s; | 818 | } ii_itte7_fld_s; |
819 | } ii_itte7_u_t; | 819 | } ii_itte7_u_t; |
820 | 820 | ||
@@ -843,22 +843,22 @@ typedef union ii_itte7_u { | |||
843 | ************************************************************************/ | 843 | ************************************************************************/ |
844 | 844 | ||
845 | typedef union ii_iprb0_u { | 845 | typedef union ii_iprb0_u { |
846 | uint64_t ii_iprb0_regval; | 846 | u64 ii_iprb0_regval; |
847 | struct { | 847 | struct { |
848 | uint64_t i_c:8; | 848 | u64 i_c:8; |
849 | uint64_t i_na:14; | 849 | u64 i_na:14; |
850 | uint64_t i_rsvd_2:2; | 850 | u64 i_rsvd_2:2; |
851 | uint64_t i_nb:14; | 851 | u64 i_nb:14; |
852 | uint64_t i_rsvd_1:2; | 852 | u64 i_rsvd_1:2; |
853 | uint64_t i_m:2; | 853 | u64 i_m:2; |
854 | uint64_t i_f:1; | 854 | u64 i_f:1; |
855 | uint64_t i_of_cnt:5; | 855 | u64 i_of_cnt:5; |
856 | uint64_t i_error:1; | 856 | u64 i_error:1; |
857 | uint64_t i_rd_to:1; | 857 | u64 i_rd_to:1; |
858 | uint64_t i_spur_wr:1; | 858 | u64 i_spur_wr:1; |
859 | uint64_t i_spur_rd:1; | 859 | u64 i_spur_rd:1; |
860 | uint64_t i_rsvd:11; | 860 | u64 i_rsvd:11; |
861 | uint64_t i_mult_err:1; | 861 | u64 i_mult_err:1; |
862 | } ii_iprb0_fld_s; | 862 | } ii_iprb0_fld_s; |
863 | } ii_iprb0_u_t; | 863 | } ii_iprb0_u_t; |
864 | 864 | ||
@@ -887,22 +887,22 @@ typedef union ii_iprb0_u { | |||
887 | ************************************************************************/ | 887 | ************************************************************************/ |
888 | 888 | ||
889 | typedef union ii_iprb8_u { | 889 | typedef union ii_iprb8_u { |
890 | uint64_t ii_iprb8_regval; | 890 | u64 ii_iprb8_regval; |
891 | struct { | 891 | struct { |
892 | uint64_t i_c:8; | 892 | u64 i_c:8; |
893 | uint64_t i_na:14; | 893 | u64 i_na:14; |
894 | uint64_t i_rsvd_2:2; | 894 | u64 i_rsvd_2:2; |
895 | uint64_t i_nb:14; | 895 | u64 i_nb:14; |
896 | uint64_t i_rsvd_1:2; | 896 | u64 i_rsvd_1:2; |
897 | uint64_t i_m:2; | 897 | u64 i_m:2; |
898 | uint64_t i_f:1; | 898 | u64 i_f:1; |
899 | uint64_t i_of_cnt:5; | 899 | u64 i_of_cnt:5; |
900 | uint64_t i_error:1; | 900 | u64 i_error:1; |
901 | uint64_t i_rd_to:1; | 901 | u64 i_rd_to:1; |
902 | uint64_t i_spur_wr:1; | 902 | u64 i_spur_wr:1; |
903 | uint64_t i_spur_rd:1; | 903 | u64 i_spur_rd:1; |
904 | uint64_t i_rsvd:11; | 904 | u64 i_rsvd:11; |
905 | uint64_t i_mult_err:1; | 905 | u64 i_mult_err:1; |
906 | } ii_iprb8_fld_s; | 906 | } ii_iprb8_fld_s; |
907 | } ii_iprb8_u_t; | 907 | } ii_iprb8_u_t; |
908 | 908 | ||
@@ -931,22 +931,22 @@ typedef union ii_iprb8_u { | |||
931 | ************************************************************************/ | 931 | ************************************************************************/ |
932 | 932 | ||
933 | typedef union ii_iprb9_u { | 933 | typedef union ii_iprb9_u { |
934 | uint64_t ii_iprb9_regval; | 934 | u64 ii_iprb9_regval; |
935 | struct { | 935 | struct { |
936 | uint64_t i_c:8; | 936 | u64 i_c:8; |
937 | uint64_t i_na:14; | 937 | u64 i_na:14; |
938 | uint64_t i_rsvd_2:2; | 938 | u64 i_rsvd_2:2; |
939 | uint64_t i_nb:14; | 939 | u64 i_nb:14; |
940 | uint64_t i_rsvd_1:2; | 940 | u64 i_rsvd_1:2; |
941 | uint64_t i_m:2; | 941 | u64 i_m:2; |
942 | uint64_t i_f:1; | 942 | u64 i_f:1; |
943 | uint64_t i_of_cnt:5; | 943 | u64 i_of_cnt:5; |
944 | uint64_t i_error:1; | 944 | u64 i_error:1; |
945 | uint64_t i_rd_to:1; | 945 | u64 i_rd_to:1; |
946 | uint64_t i_spur_wr:1; | 946 | u64 i_spur_wr:1; |
947 | uint64_t i_spur_rd:1; | 947 | u64 i_spur_rd:1; |
948 | uint64_t i_rsvd:11; | 948 | u64 i_rsvd:11; |
949 | uint64_t i_mult_err:1; | 949 | u64 i_mult_err:1; |
950 | } ii_iprb9_fld_s; | 950 | } ii_iprb9_fld_s; |
951 | } ii_iprb9_u_t; | 951 | } ii_iprb9_u_t; |
952 | 952 | ||
@@ -975,22 +975,22 @@ typedef union ii_iprb9_u { | |||
975 | ************************************************************************/ | 975 | ************************************************************************/ |
976 | 976 | ||
977 | typedef union ii_iprba_u { | 977 | typedef union ii_iprba_u { |
978 | uint64_t ii_iprba_regval; | 978 | u64 ii_iprba_regval; |
979 | struct { | 979 | struct { |
980 | uint64_t i_c:8; | 980 | u64 i_c:8; |
981 | uint64_t i_na:14; | 981 | u64 i_na:14; |
982 | uint64_t i_rsvd_2:2; | 982 | u64 i_rsvd_2:2; |
983 | uint64_t i_nb:14; | 983 | u64 i_nb:14; |
984 | uint64_t i_rsvd_1:2; | 984 | u64 i_rsvd_1:2; |
985 | uint64_t i_m:2; | 985 | u64 i_m:2; |
986 | uint64_t i_f:1; | 986 | u64 i_f:1; |
987 | uint64_t i_of_cnt:5; | 987 | u64 i_of_cnt:5; |
988 | uint64_t i_error:1; | 988 | u64 i_error:1; |
989 | uint64_t i_rd_to:1; | 989 | u64 i_rd_to:1; |
990 | uint64_t i_spur_wr:1; | 990 | u64 i_spur_wr:1; |
991 | uint64_t i_spur_rd:1; | 991 | u64 i_spur_rd:1; |
992 | uint64_t i_rsvd:11; | 992 | u64 i_rsvd:11; |
993 | uint64_t i_mult_err:1; | 993 | u64 i_mult_err:1; |
994 | } ii_iprba_fld_s; | 994 | } ii_iprba_fld_s; |
995 | } ii_iprba_u_t; | 995 | } ii_iprba_u_t; |
996 | 996 | ||
@@ -1019,22 +1019,22 @@ typedef union ii_iprba_u { | |||
1019 | ************************************************************************/ | 1019 | ************************************************************************/ |
1020 | 1020 | ||
1021 | typedef union ii_iprbb_u { | 1021 | typedef union ii_iprbb_u { |
1022 | uint64_t ii_iprbb_regval; | 1022 | u64 ii_iprbb_regval; |
1023 | struct { | 1023 | struct { |
1024 | uint64_t i_c:8; | 1024 | u64 i_c:8; |
1025 | uint64_t i_na:14; | 1025 | u64 i_na:14; |
1026 | uint64_t i_rsvd_2:2; | 1026 | u64 i_rsvd_2:2; |
1027 | uint64_t i_nb:14; | 1027 | u64 i_nb:14; |
1028 | uint64_t i_rsvd_1:2; | 1028 | u64 i_rsvd_1:2; |
1029 | uint64_t i_m:2; | 1029 | u64 i_m:2; |
1030 | uint64_t i_f:1; | 1030 | u64 i_f:1; |
1031 | uint64_t i_of_cnt:5; | 1031 | u64 i_of_cnt:5; |
1032 | uint64_t i_error:1; | 1032 | u64 i_error:1; |
1033 | uint64_t i_rd_to:1; | 1033 | u64 i_rd_to:1; |
1034 | uint64_t i_spur_wr:1; | 1034 | u64 i_spur_wr:1; |
1035 | uint64_t i_spur_rd:1; | 1035 | u64 i_spur_rd:1; |
1036 | uint64_t i_rsvd:11; | 1036 | u64 i_rsvd:11; |
1037 | uint64_t i_mult_err:1; | 1037 | u64 i_mult_err:1; |
1038 | } ii_iprbb_fld_s; | 1038 | } ii_iprbb_fld_s; |
1039 | } ii_iprbb_u_t; | 1039 | } ii_iprbb_u_t; |
1040 | 1040 | ||
@@ -1063,22 +1063,22 @@ typedef union ii_iprbb_u { | |||
1063 | ************************************************************************/ | 1063 | ************************************************************************/ |
1064 | 1064 | ||
1065 | typedef union ii_iprbc_u { | 1065 | typedef union ii_iprbc_u { |
1066 | uint64_t ii_iprbc_regval; | 1066 | u64 ii_iprbc_regval; |
1067 | struct { | 1067 | struct { |
1068 | uint64_t i_c:8; | 1068 | u64 i_c:8; |
1069 | uint64_t i_na:14; | 1069 | u64 i_na:14; |
1070 | uint64_t i_rsvd_2:2; | 1070 | u64 i_rsvd_2:2; |
1071 | uint64_t i_nb:14; | 1071 | u64 i_nb:14; |
1072 | uint64_t i_rsvd_1:2; | 1072 | u64 i_rsvd_1:2; |
1073 | uint64_t i_m:2; | 1073 | u64 i_m:2; |
1074 | uint64_t i_f:1; | 1074 | u64 i_f:1; |
1075 | uint64_t i_of_cnt:5; | 1075 | u64 i_of_cnt:5; |
1076 | uint64_t i_error:1; | 1076 | u64 i_error:1; |
1077 | uint64_t i_rd_to:1; | 1077 | u64 i_rd_to:1; |
1078 | uint64_t i_spur_wr:1; | 1078 | u64 i_spur_wr:1; |
1079 | uint64_t i_spur_rd:1; | 1079 | u64 i_spur_rd:1; |
1080 | uint64_t i_rsvd:11; | 1080 | u64 i_rsvd:11; |
1081 | uint64_t i_mult_err:1; | 1081 | u64 i_mult_err:1; |
1082 | } ii_iprbc_fld_s; | 1082 | } ii_iprbc_fld_s; |
1083 | } ii_iprbc_u_t; | 1083 | } ii_iprbc_u_t; |
1084 | 1084 | ||
@@ -1107,22 +1107,22 @@ typedef union ii_iprbc_u { | |||
1107 | ************************************************************************/ | 1107 | ************************************************************************/ |
1108 | 1108 | ||
1109 | typedef union ii_iprbd_u { | 1109 | typedef union ii_iprbd_u { |
1110 | uint64_t ii_iprbd_regval; | 1110 | u64 ii_iprbd_regval; |
1111 | struct { | 1111 | struct { |
1112 | uint64_t i_c:8; | 1112 | u64 i_c:8; |
1113 | uint64_t i_na:14; | 1113 | u64 i_na:14; |
1114 | uint64_t i_rsvd_2:2; | 1114 | u64 i_rsvd_2:2; |
1115 | uint64_t i_nb:14; | 1115 | u64 i_nb:14; |
1116 | uint64_t i_rsvd_1:2; | 1116 | u64 i_rsvd_1:2; |
1117 | uint64_t i_m:2; | 1117 | u64 i_m:2; |
1118 | uint64_t i_f:1; | 1118 | u64 i_f:1; |
1119 | uint64_t i_of_cnt:5; | 1119 | u64 i_of_cnt:5; |
1120 | uint64_t i_error:1; | 1120 | u64 i_error:1; |
1121 | uint64_t i_rd_to:1; | 1121 | u64 i_rd_to:1; |
1122 | uint64_t i_spur_wr:1; | 1122 | u64 i_spur_wr:1; |
1123 | uint64_t i_spur_rd:1; | 1123 | u64 i_spur_rd:1; |
1124 | uint64_t i_rsvd:11; | 1124 | u64 i_rsvd:11; |
1125 | uint64_t i_mult_err:1; | 1125 | u64 i_mult_err:1; |
1126 | } ii_iprbd_fld_s; | 1126 | } ii_iprbd_fld_s; |
1127 | } ii_iprbd_u_t; | 1127 | } ii_iprbd_u_t; |
1128 | 1128 | ||
@@ -1151,22 +1151,22 @@ typedef union ii_iprbd_u { | |||
1151 | ************************************************************************/ | 1151 | ************************************************************************/ |
1152 | 1152 | ||
1153 | typedef union ii_iprbe_u { | 1153 | typedef union ii_iprbe_u { |
1154 | uint64_t ii_iprbe_regval; | 1154 | u64 ii_iprbe_regval; |
1155 | struct { | 1155 | struct { |
1156 | uint64_t i_c:8; | 1156 | u64 i_c:8; |
1157 | uint64_t i_na:14; | 1157 | u64 i_na:14; |
1158 | uint64_t i_rsvd_2:2; | 1158 | u64 i_rsvd_2:2; |
1159 | uint64_t i_nb:14; | 1159 | u64 i_nb:14; |
1160 | uint64_t i_rsvd_1:2; | 1160 | u64 i_rsvd_1:2; |
1161 | uint64_t i_m:2; | 1161 | u64 i_m:2; |
1162 | uint64_t i_f:1; | 1162 | u64 i_f:1; |
1163 | uint64_t i_of_cnt:5; | 1163 | u64 i_of_cnt:5; |
1164 | uint64_t i_error:1; | 1164 | u64 i_error:1; |
1165 | uint64_t i_rd_to:1; | 1165 | u64 i_rd_to:1; |
1166 | uint64_t i_spur_wr:1; | 1166 | u64 i_spur_wr:1; |
1167 | uint64_t i_spur_rd:1; | 1167 | u64 i_spur_rd:1; |
1168 | uint64_t i_rsvd:11; | 1168 | u64 i_rsvd:11; |
1169 | uint64_t i_mult_err:1; | 1169 | u64 i_mult_err:1; |
1170 | } ii_iprbe_fld_s; | 1170 | } ii_iprbe_fld_s; |
1171 | } ii_iprbe_u_t; | 1171 | } ii_iprbe_u_t; |
1172 | 1172 | ||
@@ -1195,22 +1195,22 @@ typedef union ii_iprbe_u { | |||
1195 | ************************************************************************/ | 1195 | ************************************************************************/ |
1196 | 1196 | ||
1197 | typedef union ii_iprbf_u { | 1197 | typedef union ii_iprbf_u { |
1198 | uint64_t ii_iprbf_regval; | 1198 | u64 ii_iprbf_regval; |
1199 | struct { | 1199 | struct { |
1200 | uint64_t i_c:8; | 1200 | u64 i_c:8; |
1201 | uint64_t i_na:14; | 1201 | u64 i_na:14; |
1202 | uint64_t i_rsvd_2:2; | 1202 | u64 i_rsvd_2:2; |
1203 | uint64_t i_nb:14; | 1203 | u64 i_nb:14; |
1204 | uint64_t i_rsvd_1:2; | 1204 | u64 i_rsvd_1:2; |
1205 | uint64_t i_m:2; | 1205 | u64 i_m:2; |
1206 | uint64_t i_f:1; | 1206 | u64 i_f:1; |
1207 | uint64_t i_of_cnt:5; | 1207 | u64 i_of_cnt:5; |
1208 | uint64_t i_error:1; | 1208 | u64 i_error:1; |
1209 | uint64_t i_rd_to:1; | 1209 | u64 i_rd_to:1; |
1210 | uint64_t i_spur_wr:1; | 1210 | u64 i_spur_wr:1; |
1211 | uint64_t i_spur_rd:1; | 1211 | u64 i_spur_rd:1; |
1212 | uint64_t i_rsvd:11; | 1212 | u64 i_rsvd:11; |
1213 | uint64_t i_mult_err:1; | 1213 | u64 i_mult_err:1; |
1214 | } ii_iprbe_fld_s; | 1214 | } ii_iprbe_fld_s; |
1215 | } ii_iprbf_u_t; | 1215 | } ii_iprbf_u_t; |
1216 | 1216 | ||
@@ -1232,10 +1232,10 @@ typedef union ii_iprbf_u { | |||
1232 | ************************************************************************/ | 1232 | ************************************************************************/ |
1233 | 1233 | ||
1234 | typedef union ii_ixcc_u { | 1234 | typedef union ii_ixcc_u { |
1235 | uint64_t ii_ixcc_regval; | 1235 | u64 ii_ixcc_regval; |
1236 | struct { | 1236 | struct { |
1237 | uint64_t i_time_out:26; | 1237 | u64 i_time_out:26; |
1238 | uint64_t i_rsvd:38; | 1238 | u64 i_rsvd:38; |
1239 | } ii_ixcc_fld_s; | 1239 | } ii_ixcc_fld_s; |
1240 | } ii_ixcc_u_t; | 1240 | } ii_ixcc_u_t; |
1241 | 1241 | ||
@@ -1256,16 +1256,16 @@ typedef union ii_ixcc_u { | |||
1256 | ************************************************************************/ | 1256 | ************************************************************************/ |
1257 | 1257 | ||
1258 | typedef union ii_imem_u { | 1258 | typedef union ii_imem_u { |
1259 | uint64_t ii_imem_regval; | 1259 | u64 ii_imem_regval; |
1260 | struct { | 1260 | struct { |
1261 | uint64_t i_w0_esd:1; | 1261 | u64 i_w0_esd:1; |
1262 | uint64_t i_rsvd_3:3; | 1262 | u64 i_rsvd_3:3; |
1263 | uint64_t i_b0_esd:1; | 1263 | u64 i_b0_esd:1; |
1264 | uint64_t i_rsvd_2:3; | 1264 | u64 i_rsvd_2:3; |
1265 | uint64_t i_b1_esd:1; | 1265 | u64 i_b1_esd:1; |
1266 | uint64_t i_rsvd_1:3; | 1266 | u64 i_rsvd_1:3; |
1267 | uint64_t i_clr_precise:1; | 1267 | u64 i_clr_precise:1; |
1268 | uint64_t i_rsvd:51; | 1268 | u64 i_rsvd:51; |
1269 | } ii_imem_fld_s; | 1269 | } ii_imem_fld_s; |
1270 | } ii_imem_u_t; | 1270 | } ii_imem_u_t; |
1271 | 1271 | ||
@@ -1294,13 +1294,13 @@ typedef union ii_imem_u { | |||
1294 | ************************************************************************/ | 1294 | ************************************************************************/ |
1295 | 1295 | ||
1296 | typedef union ii_ixtt_u { | 1296 | typedef union ii_ixtt_u { |
1297 | uint64_t ii_ixtt_regval; | 1297 | u64 ii_ixtt_regval; |
1298 | struct { | 1298 | struct { |
1299 | uint64_t i_tail_to:26; | 1299 | u64 i_tail_to:26; |
1300 | uint64_t i_rsvd_1:6; | 1300 | u64 i_rsvd_1:6; |
1301 | uint64_t i_rrsp_ps:23; | 1301 | u64 i_rrsp_ps:23; |
1302 | uint64_t i_rrsp_to:5; | 1302 | u64 i_rrsp_to:5; |
1303 | uint64_t i_rsvd:4; | 1303 | u64 i_rsvd:4; |
1304 | } ii_ixtt_fld_s; | 1304 | } ii_ixtt_fld_s; |
1305 | } ii_ixtt_u_t; | 1305 | } ii_ixtt_u_t; |
1306 | 1306 | ||
@@ -1316,37 +1316,37 @@ typedef union ii_ixtt_u { | |||
1316 | ************************************************************************/ | 1316 | ************************************************************************/ |
1317 | 1317 | ||
1318 | typedef union ii_ieclr_u { | 1318 | typedef union ii_ieclr_u { |
1319 | uint64_t ii_ieclr_regval; | 1319 | u64 ii_ieclr_regval; |
1320 | struct { | 1320 | struct { |
1321 | uint64_t i_e_prb_0:1; | 1321 | u64 i_e_prb_0:1; |
1322 | uint64_t i_rsvd:7; | 1322 | u64 i_rsvd:7; |
1323 | uint64_t i_e_prb_8:1; | 1323 | u64 i_e_prb_8:1; |
1324 | uint64_t i_e_prb_9:1; | 1324 | u64 i_e_prb_9:1; |
1325 | uint64_t i_e_prb_a:1; | 1325 | u64 i_e_prb_a:1; |
1326 | uint64_t i_e_prb_b:1; | 1326 | u64 i_e_prb_b:1; |
1327 | uint64_t i_e_prb_c:1; | 1327 | u64 i_e_prb_c:1; |
1328 | uint64_t i_e_prb_d:1; | 1328 | u64 i_e_prb_d:1; |
1329 | uint64_t i_e_prb_e:1; | 1329 | u64 i_e_prb_e:1; |
1330 | uint64_t i_e_prb_f:1; | 1330 | u64 i_e_prb_f:1; |
1331 | uint64_t i_e_crazy:1; | 1331 | u64 i_e_crazy:1; |
1332 | uint64_t i_e_bte_0:1; | 1332 | u64 i_e_bte_0:1; |
1333 | uint64_t i_e_bte_1:1; | 1333 | u64 i_e_bte_1:1; |
1334 | uint64_t i_reserved_1:10; | 1334 | u64 i_reserved_1:10; |
1335 | uint64_t i_spur_rd_hdr:1; | 1335 | u64 i_spur_rd_hdr:1; |
1336 | uint64_t i_cam_intr_to:1; | 1336 | u64 i_cam_intr_to:1; |
1337 | uint64_t i_cam_overflow:1; | 1337 | u64 i_cam_overflow:1; |
1338 | uint64_t i_cam_read_miss:1; | 1338 | u64 i_cam_read_miss:1; |
1339 | uint64_t i_ioq_rep_underflow:1; | 1339 | u64 i_ioq_rep_underflow:1; |
1340 | uint64_t i_ioq_req_underflow:1; | 1340 | u64 i_ioq_req_underflow:1; |
1341 | uint64_t i_ioq_rep_overflow:1; | 1341 | u64 i_ioq_rep_overflow:1; |
1342 | uint64_t i_ioq_req_overflow:1; | 1342 | u64 i_ioq_req_overflow:1; |
1343 | uint64_t i_iiq_rep_overflow:1; | 1343 | u64 i_iiq_rep_overflow:1; |
1344 | uint64_t i_iiq_req_overflow:1; | 1344 | u64 i_iiq_req_overflow:1; |
1345 | uint64_t i_ii_xn_rep_cred_overflow:1; | 1345 | u64 i_ii_xn_rep_cred_overflow:1; |
1346 | uint64_t i_ii_xn_req_cred_overflow:1; | 1346 | u64 i_ii_xn_req_cred_overflow:1; |
1347 | uint64_t i_ii_xn_invalid_cmd:1; | 1347 | u64 i_ii_xn_invalid_cmd:1; |
1348 | uint64_t i_xn_ii_invalid_cmd:1; | 1348 | u64 i_xn_ii_invalid_cmd:1; |
1349 | uint64_t i_reserved_2:21; | 1349 | u64 i_reserved_2:21; |
1350 | } ii_ieclr_fld_s; | 1350 | } ii_ieclr_fld_s; |
1351 | } ii_ieclr_u_t; | 1351 | } ii_ieclr_u_t; |
1352 | 1352 | ||
@@ -1360,12 +1360,12 @@ typedef union ii_ieclr_u { | |||
1360 | ************************************************************************/ | 1360 | ************************************************************************/ |
1361 | 1361 | ||
1362 | typedef union ii_ibcr_u { | 1362 | typedef union ii_ibcr_u { |
1363 | uint64_t ii_ibcr_regval; | 1363 | u64 ii_ibcr_regval; |
1364 | struct { | 1364 | struct { |
1365 | uint64_t i_count:4; | 1365 | u64 i_count:4; |
1366 | uint64_t i_rsvd_1:4; | 1366 | u64 i_rsvd_1:4; |
1367 | uint64_t i_soft_reset:1; | 1367 | u64 i_soft_reset:1; |
1368 | uint64_t i_rsvd:55; | 1368 | u64 i_rsvd:55; |
1369 | } ii_ibcr_fld_s; | 1369 | } ii_ibcr_fld_s; |
1370 | } ii_ibcr_u_t; | 1370 | } ii_ibcr_u_t; |
1371 | 1371 | ||
@@ -1399,22 +1399,22 @@ typedef union ii_ibcr_u { | |||
1399 | ************************************************************************/ | 1399 | ************************************************************************/ |
1400 | 1400 | ||
1401 | typedef union ii_ixsm_u { | 1401 | typedef union ii_ixsm_u { |
1402 | uint64_t ii_ixsm_regval; | 1402 | u64 ii_ixsm_regval; |
1403 | struct { | 1403 | struct { |
1404 | uint64_t i_byte_en:32; | 1404 | u64 i_byte_en:32; |
1405 | uint64_t i_reserved:1; | 1405 | u64 i_reserved:1; |
1406 | uint64_t i_tag:3; | 1406 | u64 i_tag:3; |
1407 | uint64_t i_alt_pactyp:4; | 1407 | u64 i_alt_pactyp:4; |
1408 | uint64_t i_bo:1; | 1408 | u64 i_bo:1; |
1409 | uint64_t i_error:1; | 1409 | u64 i_error:1; |
1410 | uint64_t i_vbpm:1; | 1410 | u64 i_vbpm:1; |
1411 | uint64_t i_gbr:1; | 1411 | u64 i_gbr:1; |
1412 | uint64_t i_ds:2; | 1412 | u64 i_ds:2; |
1413 | uint64_t i_ct:1; | 1413 | u64 i_ct:1; |
1414 | uint64_t i_tnum:5; | 1414 | u64 i_tnum:5; |
1415 | uint64_t i_pactyp:4; | 1415 | u64 i_pactyp:4; |
1416 | uint64_t i_sidn:4; | 1416 | u64 i_sidn:4; |
1417 | uint64_t i_didn:4; | 1417 | u64 i_didn:4; |
1418 | } ii_ixsm_fld_s; | 1418 | } ii_ixsm_fld_s; |
1419 | } ii_ixsm_u_t; | 1419 | } ii_ixsm_u_t; |
1420 | 1420 | ||
@@ -1426,11 +1426,11 @@ typedef union ii_ixsm_u { | |||
1426 | ************************************************************************/ | 1426 | ************************************************************************/ |
1427 | 1427 | ||
1428 | typedef union ii_ixss_u { | 1428 | typedef union ii_ixss_u { |
1429 | uint64_t ii_ixss_regval; | 1429 | u64 ii_ixss_regval; |
1430 | struct { | 1430 | struct { |
1431 | uint64_t i_sideband:8; | 1431 | u64 i_sideband:8; |
1432 | uint64_t i_rsvd:55; | 1432 | u64 i_rsvd:55; |
1433 | uint64_t i_valid:1; | 1433 | u64 i_valid:1; |
1434 | } ii_ixss_fld_s; | 1434 | } ii_ixss_fld_s; |
1435 | } ii_ixss_u_t; | 1435 | } ii_ixss_u_t; |
1436 | 1436 | ||
@@ -1447,17 +1447,17 @@ typedef union ii_ixss_u { | |||
1447 | ************************************************************************/ | 1447 | ************************************************************************/ |
1448 | 1448 | ||
1449 | typedef union ii_ilct_u { | 1449 | typedef union ii_ilct_u { |
1450 | uint64_t ii_ilct_regval; | 1450 | u64 ii_ilct_regval; |
1451 | struct { | 1451 | struct { |
1452 | uint64_t i_test_seed:20; | 1452 | u64 i_test_seed:20; |
1453 | uint64_t i_test_mask:8; | 1453 | u64 i_test_mask:8; |
1454 | uint64_t i_test_data:20; | 1454 | u64 i_test_data:20; |
1455 | uint64_t i_test_valid:1; | 1455 | u64 i_test_valid:1; |
1456 | uint64_t i_test_cberr:1; | 1456 | u64 i_test_cberr:1; |
1457 | uint64_t i_test_flit:3; | 1457 | u64 i_test_flit:3; |
1458 | uint64_t i_test_clear:1; | 1458 | u64 i_test_clear:1; |
1459 | uint64_t i_test_err_capture:1; | 1459 | u64 i_test_err_capture:1; |
1460 | uint64_t i_rsvd:9; | 1460 | u64 i_rsvd:9; |
1461 | } ii_ilct_fld_s; | 1461 | } ii_ilct_fld_s; |
1462 | } ii_ilct_u_t; | 1462 | } ii_ilct_u_t; |
1463 | 1463 | ||
@@ -1482,20 +1482,20 @@ typedef union ii_ilct_u { | |||
1482 | ************************************************************************/ | 1482 | ************************************************************************/ |
1483 | 1483 | ||
1484 | typedef union ii_iieph1_u { | 1484 | typedef union ii_iieph1_u { |
1485 | uint64_t ii_iieph1_regval; | 1485 | u64 ii_iieph1_regval; |
1486 | struct { | 1486 | struct { |
1487 | uint64_t i_command:7; | 1487 | u64 i_command:7; |
1488 | uint64_t i_rsvd_5:1; | 1488 | u64 i_rsvd_5:1; |
1489 | uint64_t i_suppl:14; | 1489 | u64 i_suppl:14; |
1490 | uint64_t i_rsvd_4:1; | 1490 | u64 i_rsvd_4:1; |
1491 | uint64_t i_source:14; | 1491 | u64 i_source:14; |
1492 | uint64_t i_rsvd_3:1; | 1492 | u64 i_rsvd_3:1; |
1493 | uint64_t i_err_type:4; | 1493 | u64 i_err_type:4; |
1494 | uint64_t i_rsvd_2:4; | 1494 | u64 i_rsvd_2:4; |
1495 | uint64_t i_overrun:1; | 1495 | u64 i_overrun:1; |
1496 | uint64_t i_rsvd_1:3; | 1496 | u64 i_rsvd_1:3; |
1497 | uint64_t i_valid:1; | 1497 | u64 i_valid:1; |
1498 | uint64_t i_rsvd:13; | 1498 | u64 i_rsvd:13; |
1499 | } ii_iieph1_fld_s; | 1499 | } ii_iieph1_fld_s; |
1500 | } ii_iieph1_u_t; | 1500 | } ii_iieph1_u_t; |
1501 | 1501 | ||
@@ -1511,13 +1511,13 @@ typedef union ii_iieph1_u { | |||
1511 | ************************************************************************/ | 1511 | ************************************************************************/ |
1512 | 1512 | ||
1513 | typedef union ii_iieph2_u { | 1513 | typedef union ii_iieph2_u { |
1514 | uint64_t ii_iieph2_regval; | 1514 | u64 ii_iieph2_regval; |
1515 | struct { | 1515 | struct { |
1516 | uint64_t i_rsvd_0:3; | 1516 | u64 i_rsvd_0:3; |
1517 | uint64_t i_address:47; | 1517 | u64 i_address:47; |
1518 | uint64_t i_rsvd_1:10; | 1518 | u64 i_rsvd_1:10; |
1519 | uint64_t i_tail:1; | 1519 | u64 i_tail:1; |
1520 | uint64_t i_rsvd:3; | 1520 | u64 i_rsvd:3; |
1521 | } ii_iieph2_fld_s; | 1521 | } ii_iieph2_fld_s; |
1522 | } ii_iieph2_u_t; | 1522 | } ii_iieph2_u_t; |
1523 | 1523 | ||
@@ -1532,9 +1532,9 @@ typedef union ii_iieph2_u { | |||
1532 | ************************************************************************/ | 1532 | ************************************************************************/ |
1533 | 1533 | ||
1534 | typedef union ii_islapr_u { | 1534 | typedef union ii_islapr_u { |
1535 | uint64_t ii_islapr_regval; | 1535 | u64 ii_islapr_regval; |
1536 | struct { | 1536 | struct { |
1537 | uint64_t i_region:64; | 1537 | u64 i_region:64; |
1538 | } ii_islapr_fld_s; | 1538 | } ii_islapr_fld_s; |
1539 | } ii_islapr_u_t; | 1539 | } ii_islapr_u_t; |
1540 | 1540 | ||
@@ -1547,10 +1547,10 @@ typedef union ii_islapr_u { | |||
1547 | ************************************************************************/ | 1547 | ************************************************************************/ |
1548 | 1548 | ||
1549 | typedef union ii_islapo_u { | 1549 | typedef union ii_islapo_u { |
1550 | uint64_t ii_islapo_regval; | 1550 | u64 ii_islapo_regval; |
1551 | struct { | 1551 | struct { |
1552 | uint64_t i_io_sbx_ovrride:56; | 1552 | u64 i_io_sbx_ovrride:56; |
1553 | uint64_t i_rsvd:8; | 1553 | u64 i_rsvd:8; |
1554 | } ii_islapo_fld_s; | 1554 | } ii_islapo_fld_s; |
1555 | } ii_islapo_u_t; | 1555 | } ii_islapo_u_t; |
1556 | 1556 | ||
@@ -1563,14 +1563,14 @@ typedef union ii_islapo_u { | |||
1563 | ************************************************************************/ | 1563 | ************************************************************************/ |
1564 | 1564 | ||
1565 | typedef union ii_iwi_u { | 1565 | typedef union ii_iwi_u { |
1566 | uint64_t ii_iwi_regval; | 1566 | u64 ii_iwi_regval; |
1567 | struct { | 1567 | struct { |
1568 | uint64_t i_prescale:24; | 1568 | u64 i_prescale:24; |
1569 | uint64_t i_rsvd:8; | 1569 | u64 i_rsvd:8; |
1570 | uint64_t i_timeout:8; | 1570 | u64 i_timeout:8; |
1571 | uint64_t i_rsvd1:8; | 1571 | u64 i_rsvd1:8; |
1572 | uint64_t i_intrpt_retry_period:8; | 1572 | u64 i_intrpt_retry_period:8; |
1573 | uint64_t i_rsvd2:8; | 1573 | u64 i_rsvd2:8; |
1574 | } ii_iwi_fld_s; | 1574 | } ii_iwi_fld_s; |
1575 | } ii_iwi_u_t; | 1575 | } ii_iwi_u_t; |
1576 | 1576 | ||
@@ -1582,26 +1582,26 @@ typedef union ii_iwi_u { | |||
1582 | ************************************************************************/ | 1582 | ************************************************************************/ |
1583 | 1583 | ||
1584 | typedef union ii_iwel_u { | 1584 | typedef union ii_iwel_u { |
1585 | uint64_t ii_iwel_regval; | 1585 | u64 ii_iwel_regval; |
1586 | struct { | 1586 | struct { |
1587 | uint64_t i_intr_timed_out:1; | 1587 | u64 i_intr_timed_out:1; |
1588 | uint64_t i_rsvd:7; | 1588 | u64 i_rsvd:7; |
1589 | uint64_t i_cam_overflow:1; | 1589 | u64 i_cam_overflow:1; |
1590 | uint64_t i_cam_read_miss:1; | 1590 | u64 i_cam_read_miss:1; |
1591 | uint64_t i_rsvd1:2; | 1591 | u64 i_rsvd1:2; |
1592 | uint64_t i_ioq_rep_underflow:1; | 1592 | u64 i_ioq_rep_underflow:1; |
1593 | uint64_t i_ioq_req_underflow:1; | 1593 | u64 i_ioq_req_underflow:1; |
1594 | uint64_t i_ioq_rep_overflow:1; | 1594 | u64 i_ioq_rep_overflow:1; |
1595 | uint64_t i_ioq_req_overflow:1; | 1595 | u64 i_ioq_req_overflow:1; |
1596 | uint64_t i_iiq_rep_overflow:1; | 1596 | u64 i_iiq_rep_overflow:1; |
1597 | uint64_t i_iiq_req_overflow:1; | 1597 | u64 i_iiq_req_overflow:1; |
1598 | uint64_t i_rsvd2:6; | 1598 | u64 i_rsvd2:6; |
1599 | uint64_t i_ii_xn_rep_cred_over_under:1; | 1599 | u64 i_ii_xn_rep_cred_over_under:1; |
1600 | uint64_t i_ii_xn_req_cred_over_under:1; | 1600 | u64 i_ii_xn_req_cred_over_under:1; |
1601 | uint64_t i_rsvd3:6; | 1601 | u64 i_rsvd3:6; |
1602 | uint64_t i_ii_xn_invalid_cmd:1; | 1602 | u64 i_ii_xn_invalid_cmd:1; |
1603 | uint64_t i_xn_ii_invalid_cmd:1; | 1603 | u64 i_xn_ii_invalid_cmd:1; |
1604 | uint64_t i_rsvd4:30; | 1604 | u64 i_rsvd4:30; |
1605 | } ii_iwel_fld_s; | 1605 | } ii_iwel_fld_s; |
1606 | } ii_iwel_u_t; | 1606 | } ii_iwel_u_t; |
1607 | 1607 | ||
@@ -1612,22 +1612,22 @@ typedef union ii_iwel_u { | |||
1612 | ************************************************************************/ | 1612 | ************************************************************************/ |
1613 | 1613 | ||
1614 | typedef union ii_iwc_u { | 1614 | typedef union ii_iwc_u { |
1615 | uint64_t ii_iwc_regval; | 1615 | u64 ii_iwc_regval; |
1616 | struct { | 1616 | struct { |
1617 | uint64_t i_dma_byte_swap:1; | 1617 | u64 i_dma_byte_swap:1; |
1618 | uint64_t i_rsvd:3; | 1618 | u64 i_rsvd:3; |
1619 | uint64_t i_cam_read_lines_reset:1; | 1619 | u64 i_cam_read_lines_reset:1; |
1620 | uint64_t i_rsvd1:3; | 1620 | u64 i_rsvd1:3; |
1621 | uint64_t i_ii_xn_cred_over_under_log:1; | 1621 | u64 i_ii_xn_cred_over_under_log:1; |
1622 | uint64_t i_rsvd2:19; | 1622 | u64 i_rsvd2:19; |
1623 | uint64_t i_xn_rep_iq_depth:5; | 1623 | u64 i_xn_rep_iq_depth:5; |
1624 | uint64_t i_rsvd3:3; | 1624 | u64 i_rsvd3:3; |
1625 | uint64_t i_xn_req_iq_depth:5; | 1625 | u64 i_xn_req_iq_depth:5; |
1626 | uint64_t i_rsvd4:3; | 1626 | u64 i_rsvd4:3; |
1627 | uint64_t i_iiq_depth:6; | 1627 | u64 i_iiq_depth:6; |
1628 | uint64_t i_rsvd5:12; | 1628 | u64 i_rsvd5:12; |
1629 | uint64_t i_force_rep_cred:1; | 1629 | u64 i_force_rep_cred:1; |
1630 | uint64_t i_force_req_cred:1; | 1630 | u64 i_force_req_cred:1; |
1631 | } ii_iwc_fld_s; | 1631 | } ii_iwc_fld_s; |
1632 | } ii_iwc_u_t; | 1632 | } ii_iwc_u_t; |
1633 | 1633 | ||
@@ -1638,12 +1638,12 @@ typedef union ii_iwc_u { | |||
1638 | ************************************************************************/ | 1638 | ************************************************************************/ |
1639 | 1639 | ||
1640 | typedef union ii_iws_u { | 1640 | typedef union ii_iws_u { |
1641 | uint64_t ii_iws_regval; | 1641 | u64 ii_iws_regval; |
1642 | struct { | 1642 | struct { |
1643 | uint64_t i_xn_rep_iq_credits:5; | 1643 | u64 i_xn_rep_iq_credits:5; |
1644 | uint64_t i_rsvd:3; | 1644 | u64 i_rsvd:3; |
1645 | uint64_t i_xn_req_iq_credits:5; | 1645 | u64 i_xn_req_iq_credits:5; |
1646 | uint64_t i_rsvd1:51; | 1646 | u64 i_rsvd1:51; |
1647 | } ii_iws_fld_s; | 1647 | } ii_iws_fld_s; |
1648 | } ii_iws_u_t; | 1648 | } ii_iws_u_t; |
1649 | 1649 | ||
@@ -1654,26 +1654,26 @@ typedef union ii_iws_u { | |||
1654 | ************************************************************************/ | 1654 | ************************************************************************/ |
1655 | 1655 | ||
1656 | typedef union ii_iweim_u { | 1656 | typedef union ii_iweim_u { |
1657 | uint64_t ii_iweim_regval; | 1657 | u64 ii_iweim_regval; |
1658 | struct { | 1658 | struct { |
1659 | uint64_t i_intr_timed_out:1; | 1659 | u64 i_intr_timed_out:1; |
1660 | uint64_t i_rsvd:7; | 1660 | u64 i_rsvd:7; |
1661 | uint64_t i_cam_overflow:1; | 1661 | u64 i_cam_overflow:1; |
1662 | uint64_t i_cam_read_miss:1; | 1662 | u64 i_cam_read_miss:1; |
1663 | uint64_t i_rsvd1:2; | 1663 | u64 i_rsvd1:2; |
1664 | uint64_t i_ioq_rep_underflow:1; | 1664 | u64 i_ioq_rep_underflow:1; |
1665 | uint64_t i_ioq_req_underflow:1; | 1665 | u64 i_ioq_req_underflow:1; |
1666 | uint64_t i_ioq_rep_overflow:1; | 1666 | u64 i_ioq_rep_overflow:1; |
1667 | uint64_t i_ioq_req_overflow:1; | 1667 | u64 i_ioq_req_overflow:1; |
1668 | uint64_t i_iiq_rep_overflow:1; | 1668 | u64 i_iiq_rep_overflow:1; |
1669 | uint64_t i_iiq_req_overflow:1; | 1669 | u64 i_iiq_req_overflow:1; |
1670 | uint64_t i_rsvd2:6; | 1670 | u64 i_rsvd2:6; |
1671 | uint64_t i_ii_xn_rep_cred_overflow:1; | 1671 | u64 i_ii_xn_rep_cred_overflow:1; |
1672 | uint64_t i_ii_xn_req_cred_overflow:1; | 1672 | u64 i_ii_xn_req_cred_overflow:1; |
1673 | uint64_t i_rsvd3:6; | 1673 | u64 i_rsvd3:6; |
1674 | uint64_t i_ii_xn_invalid_cmd:1; | 1674 | u64 i_ii_xn_invalid_cmd:1; |
1675 | uint64_t i_xn_ii_invalid_cmd:1; | 1675 | u64 i_xn_ii_invalid_cmd:1; |
1676 | uint64_t i_rsvd4:30; | 1676 | u64 i_rsvd4:30; |
1677 | } ii_iweim_fld_s; | 1677 | } ii_iweim_fld_s; |
1678 | } ii_iweim_u_t; | 1678 | } ii_iweim_u_t; |
1679 | 1679 | ||
@@ -1688,13 +1688,13 @@ typedef union ii_iweim_u { | |||
1688 | ************************************************************************/ | 1688 | ************************************************************************/ |
1689 | 1689 | ||
1690 | typedef union ii_ipca_u { | 1690 | typedef union ii_ipca_u { |
1691 | uint64_t ii_ipca_regval; | 1691 | u64 ii_ipca_regval; |
1692 | struct { | 1692 | struct { |
1693 | uint64_t i_wid:4; | 1693 | u64 i_wid:4; |
1694 | uint64_t i_adjust:1; | 1694 | u64 i_adjust:1; |
1695 | uint64_t i_rsvd_1:3; | 1695 | u64 i_rsvd_1:3; |
1696 | uint64_t i_field:2; | 1696 | u64 i_field:2; |
1697 | uint64_t i_rsvd:54; | 1697 | u64 i_rsvd:54; |
1698 | } ii_ipca_fld_s; | 1698 | } ii_ipca_fld_s; |
1699 | } ii_ipca_u_t; | 1699 | } ii_ipca_u_t; |
1700 | 1700 | ||
@@ -1709,12 +1709,12 @@ typedef union ii_ipca_u { | |||
1709 | ************************************************************************/ | 1709 | ************************************************************************/ |
1710 | 1710 | ||
1711 | typedef union ii_iprte0a_u { | 1711 | typedef union ii_iprte0a_u { |
1712 | uint64_t ii_iprte0a_regval; | 1712 | u64 ii_iprte0a_regval; |
1713 | struct { | 1713 | struct { |
1714 | uint64_t i_rsvd_1:54; | 1714 | u64 i_rsvd_1:54; |
1715 | uint64_t i_widget:4; | 1715 | u64 i_widget:4; |
1716 | uint64_t i_to_cnt:5; | 1716 | u64 i_to_cnt:5; |
1717 | uint64_t i_vld:1; | 1717 | u64 i_vld:1; |
1718 | } ii_iprte0a_fld_s; | 1718 | } ii_iprte0a_fld_s; |
1719 | } ii_iprte0a_u_t; | 1719 | } ii_iprte0a_u_t; |
1720 | 1720 | ||
@@ -1729,12 +1729,12 @@ typedef union ii_iprte0a_u { | |||
1729 | ************************************************************************/ | 1729 | ************************************************************************/ |
1730 | 1730 | ||
1731 | typedef union ii_iprte1a_u { | 1731 | typedef union ii_iprte1a_u { |
1732 | uint64_t ii_iprte1a_regval; | 1732 | u64 ii_iprte1a_regval; |
1733 | struct { | 1733 | struct { |
1734 | uint64_t i_rsvd_1:54; | 1734 | u64 i_rsvd_1:54; |
1735 | uint64_t i_widget:4; | 1735 | u64 i_widget:4; |
1736 | uint64_t i_to_cnt:5; | 1736 | u64 i_to_cnt:5; |
1737 | uint64_t i_vld:1; | 1737 | u64 i_vld:1; |
1738 | } ii_iprte1a_fld_s; | 1738 | } ii_iprte1a_fld_s; |
1739 | } ii_iprte1a_u_t; | 1739 | } ii_iprte1a_u_t; |
1740 | 1740 | ||
@@ -1749,12 +1749,12 @@ typedef union ii_iprte1a_u { | |||
1749 | ************************************************************************/ | 1749 | ************************************************************************/ |
1750 | 1750 | ||
1751 | typedef union ii_iprte2a_u { | 1751 | typedef union ii_iprte2a_u { |
1752 | uint64_t ii_iprte2a_regval; | 1752 | u64 ii_iprte2a_regval; |
1753 | struct { | 1753 | struct { |
1754 | uint64_t i_rsvd_1:54; | 1754 | u64 i_rsvd_1:54; |
1755 | uint64_t i_widget:4; | 1755 | u64 i_widget:4; |
1756 | uint64_t i_to_cnt:5; | 1756 | u64 i_to_cnt:5; |
1757 | uint64_t i_vld:1; | 1757 | u64 i_vld:1; |
1758 | } ii_iprte2a_fld_s; | 1758 | } ii_iprte2a_fld_s; |
1759 | } ii_iprte2a_u_t; | 1759 | } ii_iprte2a_u_t; |
1760 | 1760 | ||
@@ -1769,12 +1769,12 @@ typedef union ii_iprte2a_u { | |||
1769 | ************************************************************************/ | 1769 | ************************************************************************/ |
1770 | 1770 | ||
1771 | typedef union ii_iprte3a_u { | 1771 | typedef union ii_iprte3a_u { |
1772 | uint64_t ii_iprte3a_regval; | 1772 | u64 ii_iprte3a_regval; |
1773 | struct { | 1773 | struct { |
1774 | uint64_t i_rsvd_1:54; | 1774 | u64 i_rsvd_1:54; |
1775 | uint64_t i_widget:4; | 1775 | u64 i_widget:4; |
1776 | uint64_t i_to_cnt:5; | 1776 | u64 i_to_cnt:5; |
1777 | uint64_t i_vld:1; | 1777 | u64 i_vld:1; |
1778 | } ii_iprte3a_fld_s; | 1778 | } ii_iprte3a_fld_s; |
1779 | } ii_iprte3a_u_t; | 1779 | } ii_iprte3a_u_t; |
1780 | 1780 | ||
@@ -1789,12 +1789,12 @@ typedef union ii_iprte3a_u { | |||
1789 | ************************************************************************/ | 1789 | ************************************************************************/ |
1790 | 1790 | ||
1791 | typedef union ii_iprte4a_u { | 1791 | typedef union ii_iprte4a_u { |
1792 | uint64_t ii_iprte4a_regval; | 1792 | u64 ii_iprte4a_regval; |
1793 | struct { | 1793 | struct { |
1794 | uint64_t i_rsvd_1:54; | 1794 | u64 i_rsvd_1:54; |
1795 | uint64_t i_widget:4; | 1795 | u64 i_widget:4; |
1796 | uint64_t i_to_cnt:5; | 1796 | u64 i_to_cnt:5; |
1797 | uint64_t i_vld:1; | 1797 | u64 i_vld:1; |
1798 | } ii_iprte4a_fld_s; | 1798 | } ii_iprte4a_fld_s; |
1799 | } ii_iprte4a_u_t; | 1799 | } ii_iprte4a_u_t; |
1800 | 1800 | ||
@@ -1809,12 +1809,12 @@ typedef union ii_iprte4a_u { | |||
1809 | ************************************************************************/ | 1809 | ************************************************************************/ |
1810 | 1810 | ||
1811 | typedef union ii_iprte5a_u { | 1811 | typedef union ii_iprte5a_u { |
1812 | uint64_t ii_iprte5a_regval; | 1812 | u64 ii_iprte5a_regval; |
1813 | struct { | 1813 | struct { |
1814 | uint64_t i_rsvd_1:54; | 1814 | u64 i_rsvd_1:54; |
1815 | uint64_t i_widget:4; | 1815 | u64 i_widget:4; |
1816 | uint64_t i_to_cnt:5; | 1816 | u64 i_to_cnt:5; |
1817 | uint64_t i_vld:1; | 1817 | u64 i_vld:1; |
1818 | } ii_iprte5a_fld_s; | 1818 | } ii_iprte5a_fld_s; |
1819 | } ii_iprte5a_u_t; | 1819 | } ii_iprte5a_u_t; |
1820 | 1820 | ||
@@ -1829,12 +1829,12 @@ typedef union ii_iprte5a_u { | |||
1829 | ************************************************************************/ | 1829 | ************************************************************************/ |
1830 | 1830 | ||
1831 | typedef union ii_iprte6a_u { | 1831 | typedef union ii_iprte6a_u { |
1832 | uint64_t ii_iprte6a_regval; | 1832 | u64 ii_iprte6a_regval; |
1833 | struct { | 1833 | struct { |
1834 | uint64_t i_rsvd_1:54; | 1834 | u64 i_rsvd_1:54; |
1835 | uint64_t i_widget:4; | 1835 | u64 i_widget:4; |
1836 | uint64_t i_to_cnt:5; | 1836 | u64 i_to_cnt:5; |
1837 | uint64_t i_vld:1; | 1837 | u64 i_vld:1; |
1838 | } ii_iprte6a_fld_s; | 1838 | } ii_iprte6a_fld_s; |
1839 | } ii_iprte6a_u_t; | 1839 | } ii_iprte6a_u_t; |
1840 | 1840 | ||
@@ -1849,12 +1849,12 @@ typedef union ii_iprte6a_u { | |||
1849 | ************************************************************************/ | 1849 | ************************************************************************/ |
1850 | 1850 | ||
1851 | typedef union ii_iprte7a_u { | 1851 | typedef union ii_iprte7a_u { |
1852 | uint64_t ii_iprte7a_regval; | 1852 | u64 ii_iprte7a_regval; |
1853 | struct { | 1853 | struct { |
1854 | uint64_t i_rsvd_1:54; | 1854 | u64 i_rsvd_1:54; |
1855 | uint64_t i_widget:4; | 1855 | u64 i_widget:4; |
1856 | uint64_t i_to_cnt:5; | 1856 | u64 i_to_cnt:5; |
1857 | uint64_t i_vld:1; | 1857 | u64 i_vld:1; |
1858 | } ii_iprtea7_fld_s; | 1858 | } ii_iprtea7_fld_s; |
1859 | } ii_iprte7a_u_t; | 1859 | } ii_iprte7a_u_t; |
1860 | 1860 | ||
@@ -1869,12 +1869,12 @@ typedef union ii_iprte7a_u { | |||
1869 | ************************************************************************/ | 1869 | ************************************************************************/ |
1870 | 1870 | ||
1871 | typedef union ii_iprte0b_u { | 1871 | typedef union ii_iprte0b_u { |
1872 | uint64_t ii_iprte0b_regval; | 1872 | u64 ii_iprte0b_regval; |
1873 | struct { | 1873 | struct { |
1874 | uint64_t i_rsvd_1:3; | 1874 | u64 i_rsvd_1:3; |
1875 | uint64_t i_address:47; | 1875 | u64 i_address:47; |
1876 | uint64_t i_init:3; | 1876 | u64 i_init:3; |
1877 | uint64_t i_source:11; | 1877 | u64 i_source:11; |
1878 | } ii_iprte0b_fld_s; | 1878 | } ii_iprte0b_fld_s; |
1879 | } ii_iprte0b_u_t; | 1879 | } ii_iprte0b_u_t; |
1880 | 1880 | ||
@@ -1889,12 +1889,12 @@ typedef union ii_iprte0b_u { | |||
1889 | ************************************************************************/ | 1889 | ************************************************************************/ |
1890 | 1890 | ||
1891 | typedef union ii_iprte1b_u { | 1891 | typedef union ii_iprte1b_u { |
1892 | uint64_t ii_iprte1b_regval; | 1892 | u64 ii_iprte1b_regval; |
1893 | struct { | 1893 | struct { |
1894 | uint64_t i_rsvd_1:3; | 1894 | u64 i_rsvd_1:3; |
1895 | uint64_t i_address:47; | 1895 | u64 i_address:47; |
1896 | uint64_t i_init:3; | 1896 | u64 i_init:3; |
1897 | uint64_t i_source:11; | 1897 | u64 i_source:11; |
1898 | } ii_iprte1b_fld_s; | 1898 | } ii_iprte1b_fld_s; |
1899 | } ii_iprte1b_u_t; | 1899 | } ii_iprte1b_u_t; |
1900 | 1900 | ||
@@ -1909,12 +1909,12 @@ typedef union ii_iprte1b_u { | |||
1909 | ************************************************************************/ | 1909 | ************************************************************************/ |
1910 | 1910 | ||
1911 | typedef union ii_iprte2b_u { | 1911 | typedef union ii_iprte2b_u { |
1912 | uint64_t ii_iprte2b_regval; | 1912 | u64 ii_iprte2b_regval; |
1913 | struct { | 1913 | struct { |
1914 | uint64_t i_rsvd_1:3; | 1914 | u64 i_rsvd_1:3; |
1915 | uint64_t i_address:47; | 1915 | u64 i_address:47; |
1916 | uint64_t i_init:3; | 1916 | u64 i_init:3; |
1917 | uint64_t i_source:11; | 1917 | u64 i_source:11; |
1918 | } ii_iprte2b_fld_s; | 1918 | } ii_iprte2b_fld_s; |
1919 | } ii_iprte2b_u_t; | 1919 | } ii_iprte2b_u_t; |
1920 | 1920 | ||
@@ -1929,12 +1929,12 @@ typedef union ii_iprte2b_u { | |||
1929 | ************************************************************************/ | 1929 | ************************************************************************/ |
1930 | 1930 | ||
1931 | typedef union ii_iprte3b_u { | 1931 | typedef union ii_iprte3b_u { |
1932 | uint64_t ii_iprte3b_regval; | 1932 | u64 ii_iprte3b_regval; |
1933 | struct { | 1933 | struct { |
1934 | uint64_t i_rsvd_1:3; | 1934 | u64 i_rsvd_1:3; |
1935 | uint64_t i_address:47; | 1935 | u64 i_address:47; |
1936 | uint64_t i_init:3; | 1936 | u64 i_init:3; |
1937 | uint64_t i_source:11; | 1937 | u64 i_source:11; |
1938 | } ii_iprte3b_fld_s; | 1938 | } ii_iprte3b_fld_s; |
1939 | } ii_iprte3b_u_t; | 1939 | } ii_iprte3b_u_t; |
1940 | 1940 | ||
@@ -1949,12 +1949,12 @@ typedef union ii_iprte3b_u { | |||
1949 | ************************************************************************/ | 1949 | ************************************************************************/ |
1950 | 1950 | ||
1951 | typedef union ii_iprte4b_u { | 1951 | typedef union ii_iprte4b_u { |
1952 | uint64_t ii_iprte4b_regval; | 1952 | u64 ii_iprte4b_regval; |
1953 | struct { | 1953 | struct { |
1954 | uint64_t i_rsvd_1:3; | 1954 | u64 i_rsvd_1:3; |
1955 | uint64_t i_address:47; | 1955 | u64 i_address:47; |
1956 | uint64_t i_init:3; | 1956 | u64 i_init:3; |
1957 | uint64_t i_source:11; | 1957 | u64 i_source:11; |
1958 | } ii_iprte4b_fld_s; | 1958 | } ii_iprte4b_fld_s; |
1959 | } ii_iprte4b_u_t; | 1959 | } ii_iprte4b_u_t; |
1960 | 1960 | ||
@@ -1969,12 +1969,12 @@ typedef union ii_iprte4b_u { | |||
1969 | ************************************************************************/ | 1969 | ************************************************************************/ |
1970 | 1970 | ||
1971 | typedef union ii_iprte5b_u { | 1971 | typedef union ii_iprte5b_u { |
1972 | uint64_t ii_iprte5b_regval; | 1972 | u64 ii_iprte5b_regval; |
1973 | struct { | 1973 | struct { |
1974 | uint64_t i_rsvd_1:3; | 1974 | u64 i_rsvd_1:3; |
1975 | uint64_t i_address:47; | 1975 | u64 i_address:47; |
1976 | uint64_t i_init:3; | 1976 | u64 i_init:3; |
1977 | uint64_t i_source:11; | 1977 | u64 i_source:11; |
1978 | } ii_iprte5b_fld_s; | 1978 | } ii_iprte5b_fld_s; |
1979 | } ii_iprte5b_u_t; | 1979 | } ii_iprte5b_u_t; |
1980 | 1980 | ||
@@ -1989,12 +1989,12 @@ typedef union ii_iprte5b_u { | |||
1989 | ************************************************************************/ | 1989 | ************************************************************************/ |
1990 | 1990 | ||
1991 | typedef union ii_iprte6b_u { | 1991 | typedef union ii_iprte6b_u { |
1992 | uint64_t ii_iprte6b_regval; | 1992 | u64 ii_iprte6b_regval; |
1993 | struct { | 1993 | struct { |
1994 | uint64_t i_rsvd_1:3; | 1994 | u64 i_rsvd_1:3; |
1995 | uint64_t i_address:47; | 1995 | u64 i_address:47; |
1996 | uint64_t i_init:3; | 1996 | u64 i_init:3; |
1997 | uint64_t i_source:11; | 1997 | u64 i_source:11; |
1998 | 1998 | ||
1999 | } ii_iprte6b_fld_s; | 1999 | } ii_iprte6b_fld_s; |
2000 | } ii_iprte6b_u_t; | 2000 | } ii_iprte6b_u_t; |
@@ -2010,12 +2010,12 @@ typedef union ii_iprte6b_u { | |||
2010 | ************************************************************************/ | 2010 | ************************************************************************/ |
2011 | 2011 | ||
2012 | typedef union ii_iprte7b_u { | 2012 | typedef union ii_iprte7b_u { |
2013 | uint64_t ii_iprte7b_regval; | 2013 | u64 ii_iprte7b_regval; |
2014 | struct { | 2014 | struct { |
2015 | uint64_t i_rsvd_1:3; | 2015 | u64 i_rsvd_1:3; |
2016 | uint64_t i_address:47; | 2016 | u64 i_address:47; |
2017 | uint64_t i_init:3; | 2017 | u64 i_init:3; |
2018 | uint64_t i_source:11; | 2018 | u64 i_source:11; |
2019 | } ii_iprte7b_fld_s; | 2019 | } ii_iprte7b_fld_s; |
2020 | } ii_iprte7b_u_t; | 2020 | } ii_iprte7b_u_t; |
2021 | 2021 | ||
@@ -2038,13 +2038,13 @@ typedef union ii_iprte7b_u { | |||
2038 | ************************************************************************/ | 2038 | ************************************************************************/ |
2039 | 2039 | ||
2040 | typedef union ii_ipdr_u { | 2040 | typedef union ii_ipdr_u { |
2041 | uint64_t ii_ipdr_regval; | 2041 | u64 ii_ipdr_regval; |
2042 | struct { | 2042 | struct { |
2043 | uint64_t i_te:3; | 2043 | u64 i_te:3; |
2044 | uint64_t i_rsvd_1:1; | 2044 | u64 i_rsvd_1:1; |
2045 | uint64_t i_pnd:1; | 2045 | u64 i_pnd:1; |
2046 | uint64_t i_init_rpcnt:1; | 2046 | u64 i_init_rpcnt:1; |
2047 | uint64_t i_rsvd:58; | 2047 | u64 i_rsvd:58; |
2048 | } ii_ipdr_fld_s; | 2048 | } ii_ipdr_fld_s; |
2049 | } ii_ipdr_u_t; | 2049 | } ii_ipdr_u_t; |
2050 | 2050 | ||
@@ -2066,11 +2066,11 @@ typedef union ii_ipdr_u { | |||
2066 | ************************************************************************/ | 2066 | ************************************************************************/ |
2067 | 2067 | ||
2068 | typedef union ii_icdr_u { | 2068 | typedef union ii_icdr_u { |
2069 | uint64_t ii_icdr_regval; | 2069 | u64 ii_icdr_regval; |
2070 | struct { | 2070 | struct { |
2071 | uint64_t i_crb_num:4; | 2071 | u64 i_crb_num:4; |
2072 | uint64_t i_pnd:1; | 2072 | u64 i_pnd:1; |
2073 | uint64_t i_rsvd:59; | 2073 | u64 i_rsvd:59; |
2074 | } ii_icdr_fld_s; | 2074 | } ii_icdr_fld_s; |
2075 | } ii_icdr_u_t; | 2075 | } ii_icdr_u_t; |
2076 | 2076 | ||
@@ -2092,13 +2092,13 @@ typedef union ii_icdr_u { | |||
2092 | ************************************************************************/ | 2092 | ************************************************************************/ |
2093 | 2093 | ||
2094 | typedef union ii_ifdr_u { | 2094 | typedef union ii_ifdr_u { |
2095 | uint64_t ii_ifdr_regval; | 2095 | u64 ii_ifdr_regval; |
2096 | struct { | 2096 | struct { |
2097 | uint64_t i_ioq_max_rq:7; | 2097 | u64 i_ioq_max_rq:7; |
2098 | uint64_t i_set_ioq_rq:1; | 2098 | u64 i_set_ioq_rq:1; |
2099 | uint64_t i_ioq_max_rp:7; | 2099 | u64 i_ioq_max_rp:7; |
2100 | uint64_t i_set_ioq_rp:1; | 2100 | u64 i_set_ioq_rp:1; |
2101 | uint64_t i_rsvd:48; | 2101 | u64 i_rsvd:48; |
2102 | } ii_ifdr_fld_s; | 2102 | } ii_ifdr_fld_s; |
2103 | } ii_ifdr_u_t; | 2103 | } ii_ifdr_u_t; |
2104 | 2104 | ||
@@ -2114,12 +2114,12 @@ typedef union ii_ifdr_u { | |||
2114 | ************************************************************************/ | 2114 | ************************************************************************/ |
2115 | 2115 | ||
2116 | typedef union ii_iiap_u { | 2116 | typedef union ii_iiap_u { |
2117 | uint64_t ii_iiap_regval; | 2117 | u64 ii_iiap_regval; |
2118 | struct { | 2118 | struct { |
2119 | uint64_t i_rq_mls:6; | 2119 | u64 i_rq_mls:6; |
2120 | uint64_t i_rsvd_1:2; | 2120 | u64 i_rsvd_1:2; |
2121 | uint64_t i_rp_mls:6; | 2121 | u64 i_rp_mls:6; |
2122 | uint64_t i_rsvd:50; | 2122 | u64 i_rsvd:50; |
2123 | } ii_iiap_fld_s; | 2123 | } ii_iiap_fld_s; |
2124 | } ii_iiap_u_t; | 2124 | } ii_iiap_u_t; |
2125 | 2125 | ||
@@ -2133,22 +2133,22 @@ typedef union ii_iiap_u { | |||
2133 | ************************************************************************/ | 2133 | ************************************************************************/ |
2134 | 2134 | ||
2135 | typedef union ii_icmr_u { | 2135 | typedef union ii_icmr_u { |
2136 | uint64_t ii_icmr_regval; | 2136 | u64 ii_icmr_regval; |
2137 | struct { | 2137 | struct { |
2138 | uint64_t i_sp_msg:1; | 2138 | u64 i_sp_msg:1; |
2139 | uint64_t i_rd_hdr:1; | 2139 | u64 i_rd_hdr:1; |
2140 | uint64_t i_rsvd_4:2; | 2140 | u64 i_rsvd_4:2; |
2141 | uint64_t i_c_cnt:4; | 2141 | u64 i_c_cnt:4; |
2142 | uint64_t i_rsvd_3:4; | 2142 | u64 i_rsvd_3:4; |
2143 | uint64_t i_clr_rqpd:1; | 2143 | u64 i_clr_rqpd:1; |
2144 | uint64_t i_clr_rppd:1; | 2144 | u64 i_clr_rppd:1; |
2145 | uint64_t i_rsvd_2:2; | 2145 | u64 i_rsvd_2:2; |
2146 | uint64_t i_fc_cnt:4; | 2146 | u64 i_fc_cnt:4; |
2147 | uint64_t i_crb_vld:15; | 2147 | u64 i_crb_vld:15; |
2148 | uint64_t i_crb_mark:15; | 2148 | u64 i_crb_mark:15; |
2149 | uint64_t i_rsvd_1:2; | 2149 | u64 i_rsvd_1:2; |
2150 | uint64_t i_precise:1; | 2150 | u64 i_precise:1; |
2151 | uint64_t i_rsvd:11; | 2151 | u64 i_rsvd:11; |
2152 | } ii_icmr_fld_s; | 2152 | } ii_icmr_fld_s; |
2153 | } ii_icmr_u_t; | 2153 | } ii_icmr_u_t; |
2154 | 2154 | ||
@@ -2161,13 +2161,13 @@ typedef union ii_icmr_u { | |||
2161 | ************************************************************************/ | 2161 | ************************************************************************/ |
2162 | 2162 | ||
2163 | typedef union ii_iccr_u { | 2163 | typedef union ii_iccr_u { |
2164 | uint64_t ii_iccr_regval; | 2164 | u64 ii_iccr_regval; |
2165 | struct { | 2165 | struct { |
2166 | uint64_t i_crb_num:4; | 2166 | u64 i_crb_num:4; |
2167 | uint64_t i_rsvd_1:4; | 2167 | u64 i_rsvd_1:4; |
2168 | uint64_t i_cmd:8; | 2168 | u64 i_cmd:8; |
2169 | uint64_t i_pending:1; | 2169 | u64 i_pending:1; |
2170 | uint64_t i_rsvd:47; | 2170 | u64 i_rsvd:47; |
2171 | } ii_iccr_fld_s; | 2171 | } ii_iccr_fld_s; |
2172 | } ii_iccr_u_t; | 2172 | } ii_iccr_u_t; |
2173 | 2173 | ||
@@ -2178,10 +2178,10 @@ typedef union ii_iccr_u { | |||
2178 | ************************************************************************/ | 2178 | ************************************************************************/ |
2179 | 2179 | ||
2180 | typedef union ii_icto_u { | 2180 | typedef union ii_icto_u { |
2181 | uint64_t ii_icto_regval; | 2181 | u64 ii_icto_regval; |
2182 | struct { | 2182 | struct { |
2183 | uint64_t i_timeout:8; | 2183 | u64 i_timeout:8; |
2184 | uint64_t i_rsvd:56; | 2184 | u64 i_rsvd:56; |
2185 | } ii_icto_fld_s; | 2185 | } ii_icto_fld_s; |
2186 | } ii_icto_u_t; | 2186 | } ii_icto_u_t; |
2187 | 2187 | ||
@@ -2197,10 +2197,10 @@ typedef union ii_icto_u { | |||
2197 | ************************************************************************/ | 2197 | ************************************************************************/ |
2198 | 2198 | ||
2199 | typedef union ii_ictp_u { | 2199 | typedef union ii_ictp_u { |
2200 | uint64_t ii_ictp_regval; | 2200 | u64 ii_ictp_regval; |
2201 | struct { | 2201 | struct { |
2202 | uint64_t i_prescale:24; | 2202 | u64 i_prescale:24; |
2203 | uint64_t i_rsvd:40; | 2203 | u64 i_rsvd:40; |
2204 | } ii_ictp_fld_s; | 2204 | } ii_ictp_fld_s; |
2205 | } ii_ictp_u_t; | 2205 | } ii_ictp_u_t; |
2206 | 2206 | ||
@@ -2228,14 +2228,14 @@ typedef union ii_ictp_u { | |||
2228 | ************************************************************************/ | 2228 | ************************************************************************/ |
2229 | 2229 | ||
2230 | typedef union ii_icrb0_a_u { | 2230 | typedef union ii_icrb0_a_u { |
2231 | uint64_t ii_icrb0_a_regval; | 2231 | u64 ii_icrb0_a_regval; |
2232 | struct { | 2232 | struct { |
2233 | uint64_t ia_iow:1; | 2233 | u64 ia_iow:1; |
2234 | uint64_t ia_vld:1; | 2234 | u64 ia_vld:1; |
2235 | uint64_t ia_addr:47; | 2235 | u64 ia_addr:47; |
2236 | uint64_t ia_tnum:5; | 2236 | u64 ia_tnum:5; |
2237 | uint64_t ia_sidn:4; | 2237 | u64 ia_sidn:4; |
2238 | uint64_t ia_rsvd:6; | 2238 | u64 ia_rsvd:6; |
2239 | } ii_icrb0_a_fld_s; | 2239 | } ii_icrb0_a_fld_s; |
2240 | } ii_icrb0_a_u_t; | 2240 | } ii_icrb0_a_u_t; |
2241 | 2241 | ||
@@ -2249,30 +2249,30 @@ typedef union ii_icrb0_a_u { | |||
2249 | ************************************************************************/ | 2249 | ************************************************************************/ |
2250 | 2250 | ||
2251 | typedef union ii_icrb0_b_u { | 2251 | typedef union ii_icrb0_b_u { |
2252 | uint64_t ii_icrb0_b_regval; | 2252 | u64 ii_icrb0_b_regval; |
2253 | struct { | 2253 | struct { |
2254 | uint64_t ib_xt_err:1; | 2254 | u64 ib_xt_err:1; |
2255 | uint64_t ib_mark:1; | 2255 | u64 ib_mark:1; |
2256 | uint64_t ib_ln_uce:1; | 2256 | u64 ib_ln_uce:1; |
2257 | uint64_t ib_errcode:3; | 2257 | u64 ib_errcode:3; |
2258 | uint64_t ib_error:1; | 2258 | u64 ib_error:1; |
2259 | uint64_t ib_stall__bte_1:1; | 2259 | u64 ib_stall__bte_1:1; |
2260 | uint64_t ib_stall__bte_0:1; | 2260 | u64 ib_stall__bte_0:1; |
2261 | uint64_t ib_stall__intr:1; | 2261 | u64 ib_stall__intr:1; |
2262 | uint64_t ib_stall_ib:1; | 2262 | u64 ib_stall_ib:1; |
2263 | uint64_t ib_intvn:1; | 2263 | u64 ib_intvn:1; |
2264 | uint64_t ib_wb:1; | 2264 | u64 ib_wb:1; |
2265 | uint64_t ib_hold:1; | 2265 | u64 ib_hold:1; |
2266 | uint64_t ib_ack:1; | 2266 | u64 ib_ack:1; |
2267 | uint64_t ib_resp:1; | 2267 | u64 ib_resp:1; |
2268 | uint64_t ib_ack_cnt:11; | 2268 | u64 ib_ack_cnt:11; |
2269 | uint64_t ib_rsvd:7; | 2269 | u64 ib_rsvd:7; |
2270 | uint64_t ib_exc:5; | 2270 | u64 ib_exc:5; |
2271 | uint64_t ib_init:3; | 2271 | u64 ib_init:3; |
2272 | uint64_t ib_imsg:8; | 2272 | u64 ib_imsg:8; |
2273 | uint64_t ib_imsgtype:2; | 2273 | u64 ib_imsgtype:2; |
2274 | uint64_t ib_use_old:1; | 2274 | u64 ib_use_old:1; |
2275 | uint64_t ib_rsvd_1:11; | 2275 | u64 ib_rsvd_1:11; |
2276 | } ii_icrb0_b_fld_s; | 2276 | } ii_icrb0_b_fld_s; |
2277 | } ii_icrb0_b_u_t; | 2277 | } ii_icrb0_b_u_t; |
2278 | 2278 | ||
@@ -2286,17 +2286,17 @@ typedef union ii_icrb0_b_u { | |||
2286 | ************************************************************************/ | 2286 | ************************************************************************/ |
2287 | 2287 | ||
2288 | typedef union ii_icrb0_c_u { | 2288 | typedef union ii_icrb0_c_u { |
2289 | uint64_t ii_icrb0_c_regval; | 2289 | u64 ii_icrb0_c_regval; |
2290 | struct { | 2290 | struct { |
2291 | uint64_t ic_source:15; | 2291 | u64 ic_source:15; |
2292 | uint64_t ic_size:2; | 2292 | u64 ic_size:2; |
2293 | uint64_t ic_ct:1; | 2293 | u64 ic_ct:1; |
2294 | uint64_t ic_bte_num:1; | 2294 | u64 ic_bte_num:1; |
2295 | uint64_t ic_gbr:1; | 2295 | u64 ic_gbr:1; |
2296 | uint64_t ic_resprqd:1; | 2296 | u64 ic_resprqd:1; |
2297 | uint64_t ic_bo:1; | 2297 | u64 ic_bo:1; |
2298 | uint64_t ic_suppl:15; | 2298 | u64 ic_suppl:15; |
2299 | uint64_t ic_rsvd:27; | 2299 | u64 ic_rsvd:27; |
2300 | } ii_icrb0_c_fld_s; | 2300 | } ii_icrb0_c_fld_s; |
2301 | } ii_icrb0_c_u_t; | 2301 | } ii_icrb0_c_u_t; |
2302 | 2302 | ||
@@ -2310,14 +2310,14 @@ typedef union ii_icrb0_c_u { | |||
2310 | ************************************************************************/ | 2310 | ************************************************************************/ |
2311 | 2311 | ||
2312 | typedef union ii_icrb0_d_u { | 2312 | typedef union ii_icrb0_d_u { |
2313 | uint64_t ii_icrb0_d_regval; | 2313 | u64 ii_icrb0_d_regval; |
2314 | struct { | 2314 | struct { |
2315 | uint64_t id_pa_be:43; | 2315 | u64 id_pa_be:43; |
2316 | uint64_t id_bte_op:1; | 2316 | u64 id_bte_op:1; |
2317 | uint64_t id_pr_psc:4; | 2317 | u64 id_pr_psc:4; |
2318 | uint64_t id_pr_cnt:4; | 2318 | u64 id_pr_cnt:4; |
2319 | uint64_t id_sleep:1; | 2319 | u64 id_sleep:1; |
2320 | uint64_t id_rsvd:11; | 2320 | u64 id_rsvd:11; |
2321 | } ii_icrb0_d_fld_s; | 2321 | } ii_icrb0_d_fld_s; |
2322 | } ii_icrb0_d_u_t; | 2322 | } ii_icrb0_d_u_t; |
2323 | 2323 | ||
@@ -2331,14 +2331,14 @@ typedef union ii_icrb0_d_u { | |||
2331 | ************************************************************************/ | 2331 | ************************************************************************/ |
2332 | 2332 | ||
2333 | typedef union ii_icrb0_e_u { | 2333 | typedef union ii_icrb0_e_u { |
2334 | uint64_t ii_icrb0_e_regval; | 2334 | u64 ii_icrb0_e_regval; |
2335 | struct { | 2335 | struct { |
2336 | uint64_t ie_timeout:8; | 2336 | u64 ie_timeout:8; |
2337 | uint64_t ie_context:15; | 2337 | u64 ie_context:15; |
2338 | uint64_t ie_rsvd:1; | 2338 | u64 ie_rsvd:1; |
2339 | uint64_t ie_tvld:1; | 2339 | u64 ie_tvld:1; |
2340 | uint64_t ie_cvld:1; | 2340 | u64 ie_cvld:1; |
2341 | uint64_t ie_rsvd_0:38; | 2341 | u64 ie_rsvd_0:38; |
2342 | } ii_icrb0_e_fld_s; | 2342 | } ii_icrb0_e_fld_s; |
2343 | } ii_icrb0_e_u_t; | 2343 | } ii_icrb0_e_u_t; |
2344 | 2344 | ||
@@ -2351,12 +2351,12 @@ typedef union ii_icrb0_e_u { | |||
2351 | ************************************************************************/ | 2351 | ************************************************************************/ |
2352 | 2352 | ||
2353 | typedef union ii_icsml_u { | 2353 | typedef union ii_icsml_u { |
2354 | uint64_t ii_icsml_regval; | 2354 | u64 ii_icsml_regval; |
2355 | struct { | 2355 | struct { |
2356 | uint64_t i_tt_addr:47; | 2356 | u64 i_tt_addr:47; |
2357 | uint64_t i_newsuppl_ex:14; | 2357 | u64 i_newsuppl_ex:14; |
2358 | uint64_t i_reserved:2; | 2358 | u64 i_reserved:2; |
2359 | uint64_t i_overflow:1; | 2359 | u64 i_overflow:1; |
2360 | } ii_icsml_fld_s; | 2360 | } ii_icsml_fld_s; |
2361 | } ii_icsml_u_t; | 2361 | } ii_icsml_u_t; |
2362 | 2362 | ||
@@ -2369,10 +2369,10 @@ typedef union ii_icsml_u { | |||
2369 | ************************************************************************/ | 2369 | ************************************************************************/ |
2370 | 2370 | ||
2371 | typedef union ii_icsmm_u { | 2371 | typedef union ii_icsmm_u { |
2372 | uint64_t ii_icsmm_regval; | 2372 | u64 ii_icsmm_regval; |
2373 | struct { | 2373 | struct { |
2374 | uint64_t i_tt_ack_cnt:11; | 2374 | u64 i_tt_ack_cnt:11; |
2375 | uint64_t i_reserved:53; | 2375 | u64 i_reserved:53; |
2376 | } ii_icsmm_fld_s; | 2376 | } ii_icsmm_fld_s; |
2377 | } ii_icsmm_u_t; | 2377 | } ii_icsmm_u_t; |
2378 | 2378 | ||
@@ -2385,48 +2385,48 @@ typedef union ii_icsmm_u { | |||
2385 | ************************************************************************/ | 2385 | ************************************************************************/ |
2386 | 2386 | ||
2387 | typedef union ii_icsmh_u { | 2387 | typedef union ii_icsmh_u { |
2388 | uint64_t ii_icsmh_regval; | 2388 | u64 ii_icsmh_regval; |
2389 | struct { | 2389 | struct { |
2390 | uint64_t i_tt_vld:1; | 2390 | u64 i_tt_vld:1; |
2391 | uint64_t i_xerr:1; | 2391 | u64 i_xerr:1; |
2392 | uint64_t i_ft_cwact_o:1; | 2392 | u64 i_ft_cwact_o:1; |
2393 | uint64_t i_ft_wact_o:1; | 2393 | u64 i_ft_wact_o:1; |
2394 | uint64_t i_ft_active_o:1; | 2394 | u64 i_ft_active_o:1; |
2395 | uint64_t i_sync:1; | 2395 | u64 i_sync:1; |
2396 | uint64_t i_mnusg:1; | 2396 | u64 i_mnusg:1; |
2397 | uint64_t i_mnusz:1; | 2397 | u64 i_mnusz:1; |
2398 | uint64_t i_plusz:1; | 2398 | u64 i_plusz:1; |
2399 | uint64_t i_plusg:1; | 2399 | u64 i_plusg:1; |
2400 | uint64_t i_tt_exc:5; | 2400 | u64 i_tt_exc:5; |
2401 | uint64_t i_tt_wb:1; | 2401 | u64 i_tt_wb:1; |
2402 | uint64_t i_tt_hold:1; | 2402 | u64 i_tt_hold:1; |
2403 | uint64_t i_tt_ack:1; | 2403 | u64 i_tt_ack:1; |
2404 | uint64_t i_tt_resp:1; | 2404 | u64 i_tt_resp:1; |
2405 | uint64_t i_tt_intvn:1; | 2405 | u64 i_tt_intvn:1; |
2406 | uint64_t i_g_stall_bte1:1; | 2406 | u64 i_g_stall_bte1:1; |
2407 | uint64_t i_g_stall_bte0:1; | 2407 | u64 i_g_stall_bte0:1; |
2408 | uint64_t i_g_stall_il:1; | 2408 | u64 i_g_stall_il:1; |
2409 | uint64_t i_g_stall_ib:1; | 2409 | u64 i_g_stall_ib:1; |
2410 | uint64_t i_tt_imsg:8; | 2410 | u64 i_tt_imsg:8; |
2411 | uint64_t i_tt_imsgtype:2; | 2411 | u64 i_tt_imsgtype:2; |
2412 | uint64_t i_tt_use_old:1; | 2412 | u64 i_tt_use_old:1; |
2413 | uint64_t i_tt_respreqd:1; | 2413 | u64 i_tt_respreqd:1; |
2414 | uint64_t i_tt_bte_num:1; | 2414 | u64 i_tt_bte_num:1; |
2415 | uint64_t i_cbn:1; | 2415 | u64 i_cbn:1; |
2416 | uint64_t i_match:1; | 2416 | u64 i_match:1; |
2417 | uint64_t i_rpcnt_lt_34:1; | 2417 | u64 i_rpcnt_lt_34:1; |
2418 | uint64_t i_rpcnt_ge_34:1; | 2418 | u64 i_rpcnt_ge_34:1; |
2419 | uint64_t i_rpcnt_lt_18:1; | 2419 | u64 i_rpcnt_lt_18:1; |
2420 | uint64_t i_rpcnt_ge_18:1; | 2420 | u64 i_rpcnt_ge_18:1; |
2421 | uint64_t i_rpcnt_lt_2:1; | 2421 | u64 i_rpcnt_lt_2:1; |
2422 | uint64_t i_rpcnt_ge_2:1; | 2422 | u64 i_rpcnt_ge_2:1; |
2423 | uint64_t i_rqcnt_lt_18:1; | 2423 | u64 i_rqcnt_lt_18:1; |
2424 | uint64_t i_rqcnt_ge_18:1; | 2424 | u64 i_rqcnt_ge_18:1; |
2425 | uint64_t i_rqcnt_lt_2:1; | 2425 | u64 i_rqcnt_lt_2:1; |
2426 | uint64_t i_rqcnt_ge_2:1; | 2426 | u64 i_rqcnt_ge_2:1; |
2427 | uint64_t i_tt_device:7; | 2427 | u64 i_tt_device:7; |
2428 | uint64_t i_tt_init:3; | 2428 | u64 i_tt_init:3; |
2429 | uint64_t i_reserved:5; | 2429 | u64 i_reserved:5; |
2430 | } ii_icsmh_fld_s; | 2430 | } ii_icsmh_fld_s; |
2431 | } ii_icsmh_u_t; | 2431 | } ii_icsmh_u_t; |
2432 | 2432 | ||
@@ -2439,14 +2439,14 @@ typedef union ii_icsmh_u { | |||
2439 | ************************************************************************/ | 2439 | ************************************************************************/ |
2440 | 2440 | ||
2441 | typedef union ii_idbss_u { | 2441 | typedef union ii_idbss_u { |
2442 | uint64_t ii_idbss_regval; | 2442 | u64 ii_idbss_regval; |
2443 | struct { | 2443 | struct { |
2444 | uint64_t i_iioclk_core_submenu:3; | 2444 | u64 i_iioclk_core_submenu:3; |
2445 | uint64_t i_rsvd:5; | 2445 | u64 i_rsvd:5; |
2446 | uint64_t i_fsbclk_wrapper_submenu:3; | 2446 | u64 i_fsbclk_wrapper_submenu:3; |
2447 | uint64_t i_rsvd_1:5; | 2447 | u64 i_rsvd_1:5; |
2448 | uint64_t i_iioclk_menu:5; | 2448 | u64 i_iioclk_menu:5; |
2449 | uint64_t i_rsvd_2:43; | 2449 | u64 i_rsvd_2:43; |
2450 | } ii_idbss_fld_s; | 2450 | } ii_idbss_fld_s; |
2451 | } ii_idbss_u_t; | 2451 | } ii_idbss_u_t; |
2452 | 2452 | ||
@@ -2466,13 +2466,13 @@ typedef union ii_idbss_u { | |||
2466 | ************************************************************************/ | 2466 | ************************************************************************/ |
2467 | 2467 | ||
2468 | typedef union ii_ibls0_u { | 2468 | typedef union ii_ibls0_u { |
2469 | uint64_t ii_ibls0_regval; | 2469 | u64 ii_ibls0_regval; |
2470 | struct { | 2470 | struct { |
2471 | uint64_t i_length:16; | 2471 | u64 i_length:16; |
2472 | uint64_t i_error:1; | 2472 | u64 i_error:1; |
2473 | uint64_t i_rsvd_1:3; | 2473 | u64 i_rsvd_1:3; |
2474 | uint64_t i_busy:1; | 2474 | u64 i_busy:1; |
2475 | uint64_t i_rsvd:43; | 2475 | u64 i_rsvd:43; |
2476 | } ii_ibls0_fld_s; | 2476 | } ii_ibls0_fld_s; |
2477 | } ii_ibls0_u_t; | 2477 | } ii_ibls0_u_t; |
2478 | 2478 | ||
@@ -2487,11 +2487,11 @@ typedef union ii_ibls0_u { | |||
2487 | ************************************************************************/ | 2487 | ************************************************************************/ |
2488 | 2488 | ||
2489 | typedef union ii_ibsa0_u { | 2489 | typedef union ii_ibsa0_u { |
2490 | uint64_t ii_ibsa0_regval; | 2490 | u64 ii_ibsa0_regval; |
2491 | struct { | 2491 | struct { |
2492 | uint64_t i_rsvd_1:7; | 2492 | u64 i_rsvd_1:7; |
2493 | uint64_t i_addr:42; | 2493 | u64 i_addr:42; |
2494 | uint64_t i_rsvd:15; | 2494 | u64 i_rsvd:15; |
2495 | } ii_ibsa0_fld_s; | 2495 | } ii_ibsa0_fld_s; |
2496 | } ii_ibsa0_u_t; | 2496 | } ii_ibsa0_u_t; |
2497 | 2497 | ||
@@ -2506,11 +2506,11 @@ typedef union ii_ibsa0_u { | |||
2506 | ************************************************************************/ | 2506 | ************************************************************************/ |
2507 | 2507 | ||
2508 | typedef union ii_ibda0_u { | 2508 | typedef union ii_ibda0_u { |
2509 | uint64_t ii_ibda0_regval; | 2509 | u64 ii_ibda0_regval; |
2510 | struct { | 2510 | struct { |
2511 | uint64_t i_rsvd_1:7; | 2511 | u64 i_rsvd_1:7; |
2512 | uint64_t i_addr:42; | 2512 | u64 i_addr:42; |
2513 | uint64_t i_rsvd:15; | 2513 | u64 i_rsvd:15; |
2514 | } ii_ibda0_fld_s; | 2514 | } ii_ibda0_fld_s; |
2515 | } ii_ibda0_u_t; | 2515 | } ii_ibda0_u_t; |
2516 | 2516 | ||
@@ -2527,14 +2527,14 @@ typedef union ii_ibda0_u { | |||
2527 | ************************************************************************/ | 2527 | ************************************************************************/ |
2528 | 2528 | ||
2529 | typedef union ii_ibct0_u { | 2529 | typedef union ii_ibct0_u { |
2530 | uint64_t ii_ibct0_regval; | 2530 | u64 ii_ibct0_regval; |
2531 | struct { | 2531 | struct { |
2532 | uint64_t i_zerofill:1; | 2532 | u64 i_zerofill:1; |
2533 | uint64_t i_rsvd_2:3; | 2533 | u64 i_rsvd_2:3; |
2534 | uint64_t i_notify:1; | 2534 | u64 i_notify:1; |
2535 | uint64_t i_rsvd_1:3; | 2535 | u64 i_rsvd_1:3; |
2536 | uint64_t i_poison:1; | 2536 | u64 i_poison:1; |
2537 | uint64_t i_rsvd:55; | 2537 | u64 i_rsvd:55; |
2538 | } ii_ibct0_fld_s; | 2538 | } ii_ibct0_fld_s; |
2539 | } ii_ibct0_u_t; | 2539 | } ii_ibct0_u_t; |
2540 | 2540 | ||
@@ -2546,11 +2546,11 @@ typedef union ii_ibct0_u { | |||
2546 | ************************************************************************/ | 2546 | ************************************************************************/ |
2547 | 2547 | ||
2548 | typedef union ii_ibna0_u { | 2548 | typedef union ii_ibna0_u { |
2549 | uint64_t ii_ibna0_regval; | 2549 | u64 ii_ibna0_regval; |
2550 | struct { | 2550 | struct { |
2551 | uint64_t i_rsvd_1:7; | 2551 | u64 i_rsvd_1:7; |
2552 | uint64_t i_addr:42; | 2552 | u64 i_addr:42; |
2553 | uint64_t i_rsvd:15; | 2553 | u64 i_rsvd:15; |
2554 | } ii_ibna0_fld_s; | 2554 | } ii_ibna0_fld_s; |
2555 | } ii_ibna0_u_t; | 2555 | } ii_ibna0_u_t; |
2556 | 2556 | ||
@@ -2563,13 +2563,13 @@ typedef union ii_ibna0_u { | |||
2563 | ************************************************************************/ | 2563 | ************************************************************************/ |
2564 | 2564 | ||
2565 | typedef union ii_ibia0_u { | 2565 | typedef union ii_ibia0_u { |
2566 | uint64_t ii_ibia0_regval; | 2566 | u64 ii_ibia0_regval; |
2567 | struct { | 2567 | struct { |
2568 | uint64_t i_rsvd_2:1; | 2568 | u64 i_rsvd_2:1; |
2569 | uint64_t i_node_id:11; | 2569 | u64 i_node_id:11; |
2570 | uint64_t i_rsvd_1:4; | 2570 | u64 i_rsvd_1:4; |
2571 | uint64_t i_level:7; | 2571 | u64 i_level:7; |
2572 | uint64_t i_rsvd:41; | 2572 | u64 i_rsvd:41; |
2573 | } ii_ibia0_fld_s; | 2573 | } ii_ibia0_fld_s; |
2574 | } ii_ibia0_u_t; | 2574 | } ii_ibia0_u_t; |
2575 | 2575 | ||
@@ -2589,13 +2589,13 @@ typedef union ii_ibia0_u { | |||
2589 | ************************************************************************/ | 2589 | ************************************************************************/ |
2590 | 2590 | ||
2591 | typedef union ii_ibls1_u { | 2591 | typedef union ii_ibls1_u { |
2592 | uint64_t ii_ibls1_regval; | 2592 | u64 ii_ibls1_regval; |
2593 | struct { | 2593 | struct { |
2594 | uint64_t i_length:16; | 2594 | u64 i_length:16; |
2595 | uint64_t i_error:1; | 2595 | u64 i_error:1; |
2596 | uint64_t i_rsvd_1:3; | 2596 | u64 i_rsvd_1:3; |
2597 | uint64_t i_busy:1; | 2597 | u64 i_busy:1; |
2598 | uint64_t i_rsvd:43; | 2598 | u64 i_rsvd:43; |
2599 | } ii_ibls1_fld_s; | 2599 | } ii_ibls1_fld_s; |
2600 | } ii_ibls1_u_t; | 2600 | } ii_ibls1_u_t; |
2601 | 2601 | ||
@@ -2610,11 +2610,11 @@ typedef union ii_ibls1_u { | |||
2610 | ************************************************************************/ | 2610 | ************************************************************************/ |
2611 | 2611 | ||
2612 | typedef union ii_ibsa1_u { | 2612 | typedef union ii_ibsa1_u { |
2613 | uint64_t ii_ibsa1_regval; | 2613 | u64 ii_ibsa1_regval; |
2614 | struct { | 2614 | struct { |
2615 | uint64_t i_rsvd_1:7; | 2615 | u64 i_rsvd_1:7; |
2616 | uint64_t i_addr:33; | 2616 | u64 i_addr:33; |
2617 | uint64_t i_rsvd:24; | 2617 | u64 i_rsvd:24; |
2618 | } ii_ibsa1_fld_s; | 2618 | } ii_ibsa1_fld_s; |
2619 | } ii_ibsa1_u_t; | 2619 | } ii_ibsa1_u_t; |
2620 | 2620 | ||
@@ -2629,11 +2629,11 @@ typedef union ii_ibsa1_u { | |||
2629 | ************************************************************************/ | 2629 | ************************************************************************/ |
2630 | 2630 | ||
2631 | typedef union ii_ibda1_u { | 2631 | typedef union ii_ibda1_u { |
2632 | uint64_t ii_ibda1_regval; | 2632 | u64 ii_ibda1_regval; |
2633 | struct { | 2633 | struct { |
2634 | uint64_t i_rsvd_1:7; | 2634 | u64 i_rsvd_1:7; |
2635 | uint64_t i_addr:33; | 2635 | u64 i_addr:33; |
2636 | uint64_t i_rsvd:24; | 2636 | u64 i_rsvd:24; |
2637 | } ii_ibda1_fld_s; | 2637 | } ii_ibda1_fld_s; |
2638 | } ii_ibda1_u_t; | 2638 | } ii_ibda1_u_t; |
2639 | 2639 | ||
@@ -2650,14 +2650,14 @@ typedef union ii_ibda1_u { | |||
2650 | ************************************************************************/ | 2650 | ************************************************************************/ |
2651 | 2651 | ||
2652 | typedef union ii_ibct1_u { | 2652 | typedef union ii_ibct1_u { |
2653 | uint64_t ii_ibct1_regval; | 2653 | u64 ii_ibct1_regval; |
2654 | struct { | 2654 | struct { |
2655 | uint64_t i_zerofill:1; | 2655 | u64 i_zerofill:1; |
2656 | uint64_t i_rsvd_2:3; | 2656 | u64 i_rsvd_2:3; |
2657 | uint64_t i_notify:1; | 2657 | u64 i_notify:1; |
2658 | uint64_t i_rsvd_1:3; | 2658 | u64 i_rsvd_1:3; |
2659 | uint64_t i_poison:1; | 2659 | u64 i_poison:1; |
2660 | uint64_t i_rsvd:55; | 2660 | u64 i_rsvd:55; |
2661 | } ii_ibct1_fld_s; | 2661 | } ii_ibct1_fld_s; |
2662 | } ii_ibct1_u_t; | 2662 | } ii_ibct1_u_t; |
2663 | 2663 | ||
@@ -2669,11 +2669,11 @@ typedef union ii_ibct1_u { | |||
2669 | ************************************************************************/ | 2669 | ************************************************************************/ |
2670 | 2670 | ||
2671 | typedef union ii_ibna1_u { | 2671 | typedef union ii_ibna1_u { |
2672 | uint64_t ii_ibna1_regval; | 2672 | u64 ii_ibna1_regval; |
2673 | struct { | 2673 | struct { |
2674 | uint64_t i_rsvd_1:7; | 2674 | u64 i_rsvd_1:7; |
2675 | uint64_t i_addr:33; | 2675 | u64 i_addr:33; |
2676 | uint64_t i_rsvd:24; | 2676 | u64 i_rsvd:24; |
2677 | } ii_ibna1_fld_s; | 2677 | } ii_ibna1_fld_s; |
2678 | } ii_ibna1_u_t; | 2678 | } ii_ibna1_u_t; |
2679 | 2679 | ||
@@ -2686,13 +2686,13 @@ typedef union ii_ibna1_u { | |||
2686 | ************************************************************************/ | 2686 | ************************************************************************/ |
2687 | 2687 | ||
2688 | typedef union ii_ibia1_u { | 2688 | typedef union ii_ibia1_u { |
2689 | uint64_t ii_ibia1_regval; | 2689 | u64 ii_ibia1_regval; |
2690 | struct { | 2690 | struct { |
2691 | uint64_t i_pi_id:1; | 2691 | u64 i_pi_id:1; |
2692 | uint64_t i_node_id:8; | 2692 | u64 i_node_id:8; |
2693 | uint64_t i_rsvd_1:7; | 2693 | u64 i_rsvd_1:7; |
2694 | uint64_t i_level:7; | 2694 | u64 i_level:7; |
2695 | uint64_t i_rsvd:41; | 2695 | u64 i_rsvd:41; |
2696 | } ii_ibia1_fld_s; | 2696 | } ii_ibia1_fld_s; |
2697 | } ii_ibia1_u_t; | 2697 | } ii_ibia1_u_t; |
2698 | 2698 | ||
@@ -2712,12 +2712,12 @@ typedef union ii_ibia1_u { | |||
2712 | ************************************************************************/ | 2712 | ************************************************************************/ |
2713 | 2713 | ||
2714 | typedef union ii_ipcr_u { | 2714 | typedef union ii_ipcr_u { |
2715 | uint64_t ii_ipcr_regval; | 2715 | u64 ii_ipcr_regval; |
2716 | struct { | 2716 | struct { |
2717 | uint64_t i_ippr0_c:4; | 2717 | u64 i_ippr0_c:4; |
2718 | uint64_t i_ippr1_c:4; | 2718 | u64 i_ippr1_c:4; |
2719 | uint64_t i_icct:8; | 2719 | u64 i_icct:8; |
2720 | uint64_t i_rsvd:48; | 2720 | u64 i_rsvd:48; |
2721 | } ii_ipcr_fld_s; | 2721 | } ii_ipcr_fld_s; |
2722 | } ii_ipcr_u_t; | 2722 | } ii_ipcr_u_t; |
2723 | 2723 | ||
@@ -2728,10 +2728,10 @@ typedef union ii_ipcr_u { | |||
2728 | ************************************************************************/ | 2728 | ************************************************************************/ |
2729 | 2729 | ||
2730 | typedef union ii_ippr_u { | 2730 | typedef union ii_ippr_u { |
2731 | uint64_t ii_ippr_regval; | 2731 | u64 ii_ippr_regval; |
2732 | struct { | 2732 | struct { |
2733 | uint64_t i_ippr0:32; | 2733 | u64 i_ippr0:32; |
2734 | uint64_t i_ippr1:32; | 2734 | u64 i_ippr1:32; |
2735 | } ii_ippr_fld_s; | 2735 | } ii_ippr_fld_s; |
2736 | } ii_ippr_u_t; | 2736 | } ii_ippr_u_t; |
2737 | 2737 | ||
@@ -3267,15 +3267,15 @@ typedef ii_icrb0_e_u_t icrbe_t; | |||
3267 | #define IO_PERF_SETS 32 | 3267 | #define IO_PERF_SETS 32 |
3268 | 3268 | ||
3269 | /* Bit for the widget in inbound access register */ | 3269 | /* Bit for the widget in inbound access register */ |
3270 | #define IIO_IIWA_WIDGET(_w) ((uint64_t)(1ULL << _w)) | 3270 | #define IIO_IIWA_WIDGET(_w) ((u64)(1ULL << _w)) |
3271 | /* Bit for the widget in outbound access register */ | 3271 | /* Bit for the widget in outbound access register */ |
3272 | #define IIO_IOWA_WIDGET(_w) ((uint64_t)(1ULL << _w)) | 3272 | #define IIO_IOWA_WIDGET(_w) ((u64)(1ULL << _w)) |
3273 | 3273 | ||
3274 | /* NOTE: The following define assumes that we are going to get | 3274 | /* NOTE: The following define assumes that we are going to get |
3275 | * widget numbers from 8 thru F and the device numbers within | 3275 | * widget numbers from 8 thru F and the device numbers within |
3276 | * widget from 0 thru 7. | 3276 | * widget from 0 thru 7. |
3277 | */ | 3277 | */ |
3278 | #define IIO_IIDEM_WIDGETDEV_MASK(w, d) ((uint64_t)(1ULL << (8 * ((w) - 8) + (d)))) | 3278 | #define IIO_IIDEM_WIDGETDEV_MASK(w, d) ((u64)(1ULL << (8 * ((w) - 8) + (d)))) |
3279 | 3279 | ||
3280 | /* IO Interrupt Destination Register */ | 3280 | /* IO Interrupt Destination Register */ |
3281 | #define IIO_IIDSR_SENT_SHIFT 28 | 3281 | #define IIO_IIDSR_SENT_SHIFT 28 |
@@ -3302,9 +3302,9 @@ typedef ii_icrb0_e_u_t icrbe_t; | |||
3302 | */ | 3302 | */ |
3303 | 3303 | ||
3304 | typedef union hubii_wcr_u { | 3304 | typedef union hubii_wcr_u { |
3305 | uint64_t wcr_reg_value; | 3305 | u64 wcr_reg_value; |
3306 | struct { | 3306 | struct { |
3307 | uint64_t wcr_widget_id:4, /* LLP crossbar credit */ | 3307 | u64 wcr_widget_id:4, /* LLP crossbar credit */ |
3308 | wcr_tag_mode:1, /* Tag mode */ | 3308 | wcr_tag_mode:1, /* Tag mode */ |
3309 | wcr_rsvd1:8, /* Reserved */ | 3309 | wcr_rsvd1:8, /* Reserved */ |
3310 | wcr_xbar_crd:3, /* LLP crossbar credit */ | 3310 | wcr_xbar_crd:3, /* LLP crossbar credit */ |
@@ -3324,9 +3324,9 @@ performance registers */ | |||
3324 | performed */ | 3324 | performed */ |
3325 | 3325 | ||
3326 | typedef union io_perf_sel { | 3326 | typedef union io_perf_sel { |
3327 | uint64_t perf_sel_reg; | 3327 | u64 perf_sel_reg; |
3328 | struct { | 3328 | struct { |
3329 | uint64_t perf_ippr0:4, perf_ippr1:4, perf_icct:8, perf_rsvd:48; | 3329 | u64 perf_ippr0:4, perf_ippr1:4, perf_icct:8, perf_rsvd:48; |
3330 | } perf_sel_bits; | 3330 | } perf_sel_bits; |
3331 | } io_perf_sel_t; | 3331 | } io_perf_sel_t; |
3332 | 3332 | ||
@@ -3334,24 +3334,24 @@ typedef union io_perf_sel { | |||
3334 | hardware problems there is only one counter, not two. */ | 3334 | hardware problems there is only one counter, not two. */ |
3335 | 3335 | ||
3336 | typedef union io_perf_cnt { | 3336 | typedef union io_perf_cnt { |
3337 | uint64_t perf_cnt; | 3337 | u64 perf_cnt; |
3338 | struct { | 3338 | struct { |
3339 | uint64_t perf_cnt:20, perf_rsvd2:12, perf_rsvd1:32; | 3339 | u64 perf_cnt:20, perf_rsvd2:12, perf_rsvd1:32; |
3340 | } perf_cnt_bits; | 3340 | } perf_cnt_bits; |
3341 | 3341 | ||
3342 | } io_perf_cnt_t; | 3342 | } io_perf_cnt_t; |
3343 | 3343 | ||
3344 | typedef union iprte_a { | 3344 | typedef union iprte_a { |
3345 | uint64_t entry; | 3345 | u64 entry; |
3346 | struct { | 3346 | struct { |
3347 | uint64_t i_rsvd_1:3; | 3347 | u64 i_rsvd_1:3; |
3348 | uint64_t i_addr:38; | 3348 | u64 i_addr:38; |
3349 | uint64_t i_init:3; | 3349 | u64 i_init:3; |
3350 | uint64_t i_source:8; | 3350 | u64 i_source:8; |
3351 | uint64_t i_rsvd:2; | 3351 | u64 i_rsvd:2; |
3352 | uint64_t i_widget:4; | 3352 | u64 i_widget:4; |
3353 | uint64_t i_to_cnt:5; | 3353 | u64 i_to_cnt:5; |
3354 | uint64_t i_vld:1; | 3354 | u64 i_vld:1; |
3355 | } iprte_fields; | 3355 | } iprte_fields; |
3356 | } iprte_a_t; | 3356 | } iprte_a_t; |
3357 | 3357 | ||