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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-ia64/processor.h
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'include/asm-ia64/processor.h')
-rw-r--r--include/asm-ia64/processor.h698
1 files changed, 698 insertions, 0 deletions
diff --git a/include/asm-ia64/processor.h b/include/asm-ia64/processor.h
new file mode 100644
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1#ifndef _ASM_IA64_PROCESSOR_H
2#define _ASM_IA64_PROCESSOR_H
3
4/*
5 * Copyright (C) 1998-2004 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 * Stephane Eranian <eranian@hpl.hp.com>
8 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
9 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
10 *
11 * 11/24/98 S.Eranian added ia64_set_iva()
12 * 12/03/99 D. Mosberger implement thread_saved_pc() via kernel unwind API
13 * 06/16/00 A. Mallick added csd/ssd/tssd for ia32 support
14 */
15
16#include <linux/config.h>
17
18#include <asm/intrinsics.h>
19#include <asm/kregs.h>
20#include <asm/ptrace.h>
21#include <asm/ustack.h>
22
23/* Our arch specific arch_init_sched_domain is in arch/ia64/kernel/domain.c */
24#define ARCH_HAS_SCHED_DOMAIN
25
26#define IA64_NUM_DBG_REGS 8
27/*
28 * Limits for PMC and PMD are set to less than maximum architected values
29 * but should be sufficient for a while
30 */
31#define IA64_NUM_PMC_REGS 32
32#define IA64_NUM_PMD_REGS 32
33
34#define DEFAULT_MAP_BASE __IA64_UL_CONST(0x2000000000000000)
35#define DEFAULT_TASK_SIZE __IA64_UL_CONST(0xa000000000000000)
36
37/*
38 * TASK_SIZE really is a mis-named. It really is the maximum user
39 * space address (plus one). On IA-64, there are five regions of 2TB
40 * each (assuming 8KB page size), for a total of 8TB of user virtual
41 * address space.
42 */
43#define TASK_SIZE (current->thread.task_size)
44
45/*
46 * MM_VM_SIZE(mm) gives the maximum address (plus 1) which may contain a mapping for
47 * address-space MM. Note that with 32-bit tasks, this is still DEFAULT_TASK_SIZE,
48 * because the kernel may have installed helper-mappings above TASK_SIZE. For example,
49 * for x86 emulation, the LDT and GDT are mapped above TASK_SIZE.
50 */
51#define MM_VM_SIZE(mm) DEFAULT_TASK_SIZE
52
53/*
54 * This decides where the kernel will search for a free chunk of vm
55 * space during mmap's.
56 */
57#define TASK_UNMAPPED_BASE (current->thread.map_base)
58
59#define IA64_THREAD_FPH_VALID (__IA64_UL(1) << 0) /* floating-point high state valid? */
60#define IA64_THREAD_DBG_VALID (__IA64_UL(1) << 1) /* debug registers valid? */
61#define IA64_THREAD_PM_VALID (__IA64_UL(1) << 2) /* performance registers valid? */
62#define IA64_THREAD_UAC_NOPRINT (__IA64_UL(1) << 3) /* don't log unaligned accesses */
63#define IA64_THREAD_UAC_SIGBUS (__IA64_UL(1) << 4) /* generate SIGBUS on unaligned acc. */
64 /* bit 5 is currently unused */
65#define IA64_THREAD_FPEMU_NOPRINT (__IA64_UL(1) << 6) /* don't log any fpswa faults */
66#define IA64_THREAD_FPEMU_SIGFPE (__IA64_UL(1) << 7) /* send a SIGFPE for fpswa faults */
67
68#define IA64_THREAD_UAC_SHIFT 3
69#define IA64_THREAD_UAC_MASK (IA64_THREAD_UAC_NOPRINT | IA64_THREAD_UAC_SIGBUS)
70#define IA64_THREAD_FPEMU_SHIFT 6
71#define IA64_THREAD_FPEMU_MASK (IA64_THREAD_FPEMU_NOPRINT | IA64_THREAD_FPEMU_SIGFPE)
72
73
74/*
75 * This shift should be large enough to be able to represent 1000000000/itc_freq with good
76 * accuracy while being small enough to fit 10*1000000000<<IA64_NSEC_PER_CYC_SHIFT in 64 bits
77 * (this will give enough slack to represent 10 seconds worth of time as a scaled number).
78 */
79#define IA64_NSEC_PER_CYC_SHIFT 30
80
81#ifndef __ASSEMBLY__
82
83#include <linux/cache.h>
84#include <linux/compiler.h>
85#include <linux/threads.h>
86#include <linux/types.h>
87
88#include <asm/fpu.h>
89#include <asm/page.h>
90#include <asm/percpu.h>
91#include <asm/rse.h>
92#include <asm/unwind.h>
93#include <asm/atomic.h>
94#ifdef CONFIG_NUMA
95#include <asm/nodedata.h>
96#endif
97
98/* like above but expressed as bitfields for more efficient access: */
99struct ia64_psr {
100 __u64 reserved0 : 1;
101 __u64 be : 1;
102 __u64 up : 1;
103 __u64 ac : 1;
104 __u64 mfl : 1;
105 __u64 mfh : 1;
106 __u64 reserved1 : 7;
107 __u64 ic : 1;
108 __u64 i : 1;
109 __u64 pk : 1;
110 __u64 reserved2 : 1;
111 __u64 dt : 1;
112 __u64 dfl : 1;
113 __u64 dfh : 1;
114 __u64 sp : 1;
115 __u64 pp : 1;
116 __u64 di : 1;
117 __u64 si : 1;
118 __u64 db : 1;
119 __u64 lp : 1;
120 __u64 tb : 1;
121 __u64 rt : 1;
122 __u64 reserved3 : 4;
123 __u64 cpl : 2;
124 __u64 is : 1;
125 __u64 mc : 1;
126 __u64 it : 1;
127 __u64 id : 1;
128 __u64 da : 1;
129 __u64 dd : 1;
130 __u64 ss : 1;
131 __u64 ri : 2;
132 __u64 ed : 1;
133 __u64 bn : 1;
134 __u64 reserved4 : 19;
135};
136
137/*
138 * CPU type, hardware bug flags, and per-CPU state. Frequently used
139 * state comes earlier:
140 */
141struct cpuinfo_ia64 {
142 __u32 softirq_pending;
143 __u64 itm_delta; /* # of clock cycles between clock ticks */
144 __u64 itm_next; /* interval timer mask value to use for next clock tick */
145 __u64 nsec_per_cyc; /* (1000000000<<IA64_NSEC_PER_CYC_SHIFT)/itc_freq */
146 __u64 unimpl_va_mask; /* mask of unimplemented virtual address bits (from PAL) */
147 __u64 unimpl_pa_mask; /* mask of unimplemented physical address bits (from PAL) */
148 __u64 *pgd_quick;
149 __u64 *pmd_quick;
150 __u64 pgtable_cache_sz;
151 __u64 itc_freq; /* frequency of ITC counter */
152 __u64 proc_freq; /* frequency of processor */
153 __u64 cyc_per_usec; /* itc_freq/1000000 */
154 __u64 ptce_base;
155 __u32 ptce_count[2];
156 __u32 ptce_stride[2];
157 struct task_struct *ksoftirqd; /* kernel softirq daemon for this CPU */
158
159#ifdef CONFIG_SMP
160 __u64 loops_per_jiffy;
161 int cpu;
162#endif
163
164 /* CPUID-derived information: */
165 __u64 ppn;
166 __u64 features;
167 __u8 number;
168 __u8 revision;
169 __u8 model;
170 __u8 family;
171 __u8 archrev;
172 char vendor[16];
173
174#ifdef CONFIG_NUMA
175 struct ia64_node_data *node_data;
176#endif
177};
178
179DECLARE_PER_CPU(struct cpuinfo_ia64, cpu_info);
180
181/*
182 * The "local" data variable. It refers to the per-CPU data of the currently executing
183 * CPU, much like "current" points to the per-task data of the currently executing task.
184 * Do not use the address of local_cpu_data, since it will be different from
185 * cpu_data(smp_processor_id())!
186 */
187#define local_cpu_data (&__ia64_per_cpu_var(cpu_info))
188#define cpu_data(cpu) (&per_cpu(cpu_info, cpu))
189
190extern void identify_cpu (struct cpuinfo_ia64 *);
191extern void print_cpu_info (struct cpuinfo_ia64 *);
192
193typedef struct {
194 unsigned long seg;
195} mm_segment_t;
196
197#define SET_UNALIGN_CTL(task,value) \
198({ \
199 (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_UAC_MASK) \
200 | (((value) << IA64_THREAD_UAC_SHIFT) & IA64_THREAD_UAC_MASK)); \
201 0; \
202})
203#define GET_UNALIGN_CTL(task,addr) \
204({ \
205 put_user(((task)->thread.flags & IA64_THREAD_UAC_MASK) >> IA64_THREAD_UAC_SHIFT, \
206 (int __user *) (addr)); \
207})
208
209#define SET_FPEMU_CTL(task,value) \
210({ \
211 (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_FPEMU_MASK) \
212 | (((value) << IA64_THREAD_FPEMU_SHIFT) & IA64_THREAD_FPEMU_MASK)); \
213 0; \
214})
215#define GET_FPEMU_CTL(task,addr) \
216({ \
217 put_user(((task)->thread.flags & IA64_THREAD_FPEMU_MASK) >> IA64_THREAD_FPEMU_SHIFT, \
218 (int __user *) (addr)); \
219})
220
221#ifdef CONFIG_IA32_SUPPORT
222struct desc_struct {
223 unsigned int a, b;
224};
225
226#define desc_empty(desc) (!((desc)->a + (desc)->b))
227#define desc_equal(desc1, desc2) (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
228
229#define GDT_ENTRY_TLS_ENTRIES 3
230#define GDT_ENTRY_TLS_MIN 6
231#define GDT_ENTRY_TLS_MAX (GDT_ENTRY_TLS_MIN + GDT_ENTRY_TLS_ENTRIES - 1)
232
233#define TLS_SIZE (GDT_ENTRY_TLS_ENTRIES * 8)
234
235struct partial_page_list;
236#endif
237
238struct thread_struct {
239 __u32 flags; /* various thread flags (see IA64_THREAD_*) */
240 /* writing on_ustack is performance-critical, so it's worth spending 8 bits on it... */
241 __u8 on_ustack; /* executing on user-stacks? */
242 __u8 pad[3];
243 __u64 ksp; /* kernel stack pointer */
244 __u64 map_base; /* base address for get_unmapped_area() */
245 __u64 task_size; /* limit for task size */
246 __u64 rbs_bot; /* the base address for the RBS */
247 int last_fph_cpu; /* CPU that may hold the contents of f32-f127 */
248
249#ifdef CONFIG_IA32_SUPPORT
250 __u64 eflag; /* IA32 EFLAGS reg */
251 __u64 fsr; /* IA32 floating pt status reg */
252 __u64 fcr; /* IA32 floating pt control reg */
253 __u64 fir; /* IA32 fp except. instr. reg */
254 __u64 fdr; /* IA32 fp except. data reg */
255 __u64 old_k1; /* old value of ar.k1 */
256 __u64 old_iob; /* old IOBase value */
257 struct partial_page_list *ppl; /* partial page list for 4K page size issue */
258 /* cached TLS descriptors. */
259 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
260
261# define INIT_THREAD_IA32 .eflag = 0, \
262 .fsr = 0, \
263 .fcr = 0x17800000037fULL, \
264 .fir = 0, \
265 .fdr = 0, \
266 .old_k1 = 0, \
267 .old_iob = 0, \
268 .ppl = NULL,
269#else
270# define INIT_THREAD_IA32
271#endif /* CONFIG_IA32_SUPPORT */
272#ifdef CONFIG_PERFMON
273 __u64 pmcs[IA64_NUM_PMC_REGS];
274 __u64 pmds[IA64_NUM_PMD_REGS];
275 void *pfm_context; /* pointer to detailed PMU context */
276 unsigned long pfm_needs_checking; /* when >0, pending perfmon work on kernel exit */
277# define INIT_THREAD_PM .pmcs = {0UL, }, \
278 .pmds = {0UL, }, \
279 .pfm_context = NULL, \
280 .pfm_needs_checking = 0UL,
281#else
282# define INIT_THREAD_PM
283#endif
284 __u64 dbr[IA64_NUM_DBG_REGS];
285 __u64 ibr[IA64_NUM_DBG_REGS];
286 struct ia64_fpreg fph[96]; /* saved/loaded on demand */
287};
288
289#define INIT_THREAD { \
290 .flags = 0, \
291 .on_ustack = 0, \
292 .ksp = 0, \
293 .map_base = DEFAULT_MAP_BASE, \
294 .rbs_bot = STACK_TOP - DEFAULT_USER_STACK_SIZE, \
295 .task_size = DEFAULT_TASK_SIZE, \
296 .last_fph_cpu = -1, \
297 INIT_THREAD_IA32 \
298 INIT_THREAD_PM \
299 .dbr = {0, }, \
300 .ibr = {0, }, \
301 .fph = {{{{0}}}, } \
302}
303
304#define start_thread(regs,new_ip,new_sp) do { \
305 set_fs(USER_DS); \
306 regs->cr_ipsr = ((regs->cr_ipsr | (IA64_PSR_BITS_TO_SET | IA64_PSR_CPL)) \
307 & ~(IA64_PSR_BITS_TO_CLEAR | IA64_PSR_RI | IA64_PSR_IS)); \
308 regs->cr_iip = new_ip; \
309 regs->ar_rsc = 0xf; /* eager mode, privilege level 3 */ \
310 regs->ar_rnat = 0; \
311 regs->ar_bspstore = current->thread.rbs_bot; \
312 regs->ar_fpsr = FPSR_DEFAULT; \
313 regs->loadrs = 0; \
314 regs->r8 = current->mm->dumpable; /* set "don't zap registers" flag */ \
315 regs->r12 = new_sp - 16; /* allocate 16 byte scratch area */ \
316 if (unlikely(!current->mm->dumpable)) { \
317 /* \
318 * Zap scratch regs to avoid leaking bits between processes with different \
319 * uid/privileges. \
320 */ \
321 regs->ar_pfs = 0; regs->b0 = 0; regs->pr = 0; \
322 regs->r1 = 0; regs->r9 = 0; regs->r11 = 0; regs->r13 = 0; regs->r15 = 0; \
323 } \
324} while (0)
325
326/* Forward declarations, a strange C thing... */
327struct mm_struct;
328struct task_struct;
329
330/*
331 * Free all resources held by a thread. This is called after the
332 * parent of DEAD_TASK has collected the exit status of the task via
333 * wait().
334 */
335#define release_thread(dead_task)
336
337/* Prepare to copy thread state - unlazy all lazy status */
338#define prepare_to_copy(tsk) do { } while (0)
339
340/*
341 * This is the mechanism for creating a new kernel thread.
342 *
343 * NOTE 1: Only a kernel-only process (ie the swapper or direct
344 * descendants who haven't done an "execve()") should use this: it
345 * will work within a system call from a "real" process, but the
346 * process memory space will not be free'd until both the parent and
347 * the child have exited.
348 *
349 * NOTE 2: This MUST NOT be an inlined function. Otherwise, we get
350 * into trouble in init/main.c when the child thread returns to
351 * do_basic_setup() and the timing is such that free_initmem() has
352 * been called already.
353 */
354extern pid_t kernel_thread (int (*fn)(void *), void *arg, unsigned long flags);
355
356/* Get wait channel for task P. */
357extern unsigned long get_wchan (struct task_struct *p);
358
359/* Return instruction pointer of blocked task TSK. */
360#define KSTK_EIP(tsk) \
361 ({ \
362 struct pt_regs *_regs = ia64_task_regs(tsk); \
363 _regs->cr_iip + ia64_psr(_regs)->ri; \
364 })
365
366/* Return stack pointer of blocked task TSK. */
367#define KSTK_ESP(tsk) ((tsk)->thread.ksp)
368
369extern void ia64_getreg_unknown_kr (void);
370extern void ia64_setreg_unknown_kr (void);
371
372#define ia64_get_kr(regnum) \
373({ \
374 unsigned long r = 0; \
375 \
376 switch (regnum) { \
377 case 0: r = ia64_getreg(_IA64_REG_AR_KR0); break; \
378 case 1: r = ia64_getreg(_IA64_REG_AR_KR1); break; \
379 case 2: r = ia64_getreg(_IA64_REG_AR_KR2); break; \
380 case 3: r = ia64_getreg(_IA64_REG_AR_KR3); break; \
381 case 4: r = ia64_getreg(_IA64_REG_AR_KR4); break; \
382 case 5: r = ia64_getreg(_IA64_REG_AR_KR5); break; \
383 case 6: r = ia64_getreg(_IA64_REG_AR_KR6); break; \
384 case 7: r = ia64_getreg(_IA64_REG_AR_KR7); break; \
385 default: ia64_getreg_unknown_kr(); break; \
386 } \
387 r; \
388})
389
390#define ia64_set_kr(regnum, r) \
391({ \
392 switch (regnum) { \
393 case 0: ia64_setreg(_IA64_REG_AR_KR0, r); break; \
394 case 1: ia64_setreg(_IA64_REG_AR_KR1, r); break; \
395 case 2: ia64_setreg(_IA64_REG_AR_KR2, r); break; \
396 case 3: ia64_setreg(_IA64_REG_AR_KR3, r); break; \
397 case 4: ia64_setreg(_IA64_REG_AR_KR4, r); break; \
398 case 5: ia64_setreg(_IA64_REG_AR_KR5, r); break; \
399 case 6: ia64_setreg(_IA64_REG_AR_KR6, r); break; \
400 case 7: ia64_setreg(_IA64_REG_AR_KR7, r); break; \
401 default: ia64_setreg_unknown_kr(); break; \
402 } \
403})
404
405/*
406 * The following three macros can't be inline functions because we don't have struct
407 * task_struct at this point.
408 */
409
410/* Return TRUE if task T owns the fph partition of the CPU we're running on. */
411#define ia64_is_local_fpu_owner(t) \
412({ \
413 struct task_struct *__ia64_islfo_task = (t); \
414 (__ia64_islfo_task->thread.last_fph_cpu == smp_processor_id() \
415 && __ia64_islfo_task == (struct task_struct *) ia64_get_kr(IA64_KR_FPU_OWNER)); \
416})
417
418/* Mark task T as owning the fph partition of the CPU we're running on. */
419#define ia64_set_local_fpu_owner(t) do { \
420 struct task_struct *__ia64_slfo_task = (t); \
421 __ia64_slfo_task->thread.last_fph_cpu = smp_processor_id(); \
422 ia64_set_kr(IA64_KR_FPU_OWNER, (unsigned long) __ia64_slfo_task); \
423} while (0)
424
425/* Mark the fph partition of task T as being invalid on all CPUs. */
426#define ia64_drop_fpu(t) ((t)->thread.last_fph_cpu = -1)
427
428extern void __ia64_init_fpu (void);
429extern void __ia64_save_fpu (struct ia64_fpreg *fph);
430extern void __ia64_load_fpu (struct ia64_fpreg *fph);
431extern void ia64_save_debug_regs (unsigned long *save_area);
432extern void ia64_load_debug_regs (unsigned long *save_area);
433
434#ifdef CONFIG_IA32_SUPPORT
435extern void ia32_save_state (struct task_struct *task);
436extern void ia32_load_state (struct task_struct *task);
437#endif
438
439#define ia64_fph_enable() do { ia64_rsm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
440#define ia64_fph_disable() do { ia64_ssm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
441
442/* load fp 0.0 into fph */
443static inline void
444ia64_init_fpu (void) {
445 ia64_fph_enable();
446 __ia64_init_fpu();
447 ia64_fph_disable();
448}
449
450/* save f32-f127 at FPH */
451static inline void
452ia64_save_fpu (struct ia64_fpreg *fph) {
453 ia64_fph_enable();
454 __ia64_save_fpu(fph);
455 ia64_fph_disable();
456}
457
458/* load f32-f127 from FPH */
459static inline void
460ia64_load_fpu (struct ia64_fpreg *fph) {
461 ia64_fph_enable();
462 __ia64_load_fpu(fph);
463 ia64_fph_disable();
464}
465
466static inline __u64
467ia64_clear_ic (void)
468{
469 __u64 psr;
470 psr = ia64_getreg(_IA64_REG_PSR);
471 ia64_stop();
472 ia64_rsm(IA64_PSR_I | IA64_PSR_IC);
473 ia64_srlz_i();
474 return psr;
475}
476
477/*
478 * Restore the psr.
479 */
480static inline void
481ia64_set_psr (__u64 psr)
482{
483 ia64_stop();
484 ia64_setreg(_IA64_REG_PSR_L, psr);
485 ia64_srlz_d();
486}
487
488/*
489 * Insert a translation into an instruction and/or data translation
490 * register.
491 */
492static inline void
493ia64_itr (__u64 target_mask, __u64 tr_num,
494 __u64 vmaddr, __u64 pte,
495 __u64 log_page_size)
496{
497 ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
498 ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
499 ia64_stop();
500 if (target_mask & 0x1)
501 ia64_itri(tr_num, pte);
502 if (target_mask & 0x2)
503 ia64_itrd(tr_num, pte);
504}
505
506/*
507 * Insert a translation into the instruction and/or data translation
508 * cache.
509 */
510static inline void
511ia64_itc (__u64 target_mask, __u64 vmaddr, __u64 pte,
512 __u64 log_page_size)
513{
514 ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
515 ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
516 ia64_stop();
517 /* as per EAS2.6, itc must be the last instruction in an instruction group */
518 if (target_mask & 0x1)
519 ia64_itci(pte);
520 if (target_mask & 0x2)
521 ia64_itcd(pte);
522}
523
524/*
525 * Purge a range of addresses from instruction and/or data translation
526 * register(s).
527 */
528static inline void
529ia64_ptr (__u64 target_mask, __u64 vmaddr, __u64 log_size)
530{
531 if (target_mask & 0x1)
532 ia64_ptri(vmaddr, (log_size << 2));
533 if (target_mask & 0x2)
534 ia64_ptrd(vmaddr, (log_size << 2));
535}
536
537/* Set the interrupt vector address. The address must be suitably aligned (32KB). */
538static inline void
539ia64_set_iva (void *ivt_addr)
540{
541 ia64_setreg(_IA64_REG_CR_IVA, (__u64) ivt_addr);
542 ia64_srlz_i();
543}
544
545/* Set the page table address and control bits. */
546static inline void
547ia64_set_pta (__u64 pta)
548{
549 /* Note: srlz.i implies srlz.d */
550 ia64_setreg(_IA64_REG_CR_PTA, pta);
551 ia64_srlz_i();
552}
553
554static inline void
555ia64_eoi (void)
556{
557 ia64_setreg(_IA64_REG_CR_EOI, 0);
558 ia64_srlz_d();
559}
560
561#define cpu_relax() ia64_hint(ia64_hint_pause)
562
563static inline void
564ia64_set_lrr0 (unsigned long val)
565{
566 ia64_setreg(_IA64_REG_CR_LRR0, val);
567 ia64_srlz_d();
568}
569
570static inline void
571ia64_set_lrr1 (unsigned long val)
572{
573 ia64_setreg(_IA64_REG_CR_LRR1, val);
574 ia64_srlz_d();
575}
576
577
578/*
579 * Given the address to which a spill occurred, return the unat bit
580 * number that corresponds to this address.
581 */
582static inline __u64
583ia64_unat_pos (void *spill_addr)
584{
585 return ((__u64) spill_addr >> 3) & 0x3f;
586}
587
588/*
589 * Set the NaT bit of an integer register which was spilled at address
590 * SPILL_ADDR. UNAT is the mask to be updated.
591 */
592static inline void
593ia64_set_unat (__u64 *unat, void *spill_addr, unsigned long nat)
594{
595 __u64 bit = ia64_unat_pos(spill_addr);
596 __u64 mask = 1UL << bit;
597
598 *unat = (*unat & ~mask) | (nat << bit);
599}
600
601/*
602 * Return saved PC of a blocked thread.
603 * Note that the only way T can block is through a call to schedule() -> switch_to().
604 */
605static inline unsigned long
606thread_saved_pc (struct task_struct *t)
607{
608 struct unw_frame_info info;
609 unsigned long ip;
610
611 unw_init_from_blocked_task(&info, t);
612 if (unw_unwind(&info) < 0)
613 return 0;
614 unw_get_ip(&info, &ip);
615 return ip;
616}
617
618/*
619 * Get the current instruction/program counter value.
620 */
621#define current_text_addr() \
622 ({ void *_pc; _pc = (void *)ia64_getreg(_IA64_REG_IP); _pc; })
623
624static inline __u64
625ia64_get_ivr (void)
626{
627 __u64 r;
628 ia64_srlz_d();
629 r = ia64_getreg(_IA64_REG_CR_IVR);
630 ia64_srlz_d();
631 return r;
632}
633
634static inline void
635ia64_set_dbr (__u64 regnum, __u64 value)
636{
637 __ia64_set_dbr(regnum, value);
638#ifdef CONFIG_ITANIUM
639 ia64_srlz_d();
640#endif
641}
642
643static inline __u64
644ia64_get_dbr (__u64 regnum)
645{
646 __u64 retval;
647
648 retval = __ia64_get_dbr(regnum);
649#ifdef CONFIG_ITANIUM
650 ia64_srlz_d();
651#endif
652 return retval;
653}
654
655static inline __u64
656ia64_rotr (__u64 w, __u64 n)
657{
658 return (w >> n) | (w << (64 - n));
659}
660
661#define ia64_rotl(w,n) ia64_rotr((w), (64) - (n))
662
663/*
664 * Take a mapped kernel address and return the equivalent address
665 * in the region 7 identity mapped virtual area.
666 */
667static inline void *
668ia64_imva (void *addr)
669{
670 void *result;
671 result = (void *) ia64_tpa(addr);
672 return __va(result);
673}
674
675#define ARCH_HAS_PREFETCH
676#define ARCH_HAS_PREFETCHW
677#define ARCH_HAS_SPINLOCK_PREFETCH
678#define PREFETCH_STRIDE L1_CACHE_BYTES
679
680static inline void
681prefetch (const void *x)
682{
683 ia64_lfetch(ia64_lfhint_none, x);
684}
685
686static inline void
687prefetchw (const void *x)
688{
689 ia64_lfetch_excl(ia64_lfhint_none, x);
690}
691
692#define spin_lock_prefetch(x) prefetchw(x)
693
694extern unsigned long boot_option_idle_override;
695
696#endif /* !__ASSEMBLY__ */
697
698#endif /* _ASM_IA64_PROCESSOR_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 10:36:33 -0500