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authorDavid S. Miller <davem@davemloft.net>2005-06-02 15:55:50 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2005-06-28 00:52:45 -0400
commite24c2d963a604d9eaa560c90371fa387d3eec8f1 (patch)
tree66be193d59dd22fac0b62980769c4f19e045b5a2 /include/asm-ia64/pci.h
parent2311b1f2bbd36fa5f366a7448c718b2556e0f02c (diff)
[PATCH] PCI: DMA bursting advice
After seeing, at best, "guesses" as to the following kind of information in several drivers, I decided that we really need a way for platforms to specifically give advice in this area for what works best with their PCI controller implementation. Basically, this new interface gives DMA bursting advice on PCI. There are three forms of the advice: 1) Burst as much as possible, it is not necessary to end bursts on some particular boundary for best performance. 2) Burst on some byte count multiple. A DMA burst to some multiple of number of bytes may be done, but it is important to end the burst on an exact multiple for best performance. The best example of this I am aware of are the PPC64 PCI controllers, where if you end a burst mid-cacheline then chip has to refetch the data and the IOMMU translations which hurts performance a lot. 3) Burst on a single byte count multiple. Bursts shall end exactly on the next multiple boundary for best performance. Sparc64 and Alpha's PCI controllers operate this way. They disconnect any device which tries to burst across a cacheline boundary. Actually, newer sparc64 PCI controllers do not have this behavior. That is why the "pdev" is passed into the interface, so I can add code later to check which PCI controller the system is using and give advice accordingly. Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'include/asm-ia64/pci.h')
-rw-r--r--include/asm-ia64/pci.h17
1 files changed, 17 insertions, 0 deletions
diff --git a/include/asm-ia64/pci.h b/include/asm-ia64/pci.h
index a8314ee4e7d2..c9f1ab4e477d 100644
--- a/include/asm-ia64/pci.h
+++ b/include/asm-ia64/pci.h
@@ -82,6 +82,23 @@ extern int pcibios_prep_mwi (struct pci_dev *);
82#define sg_dma_len(sg) ((sg)->dma_length) 82#define sg_dma_len(sg) ((sg)->dma_length)
83#define sg_dma_address(sg) ((sg)->dma_address) 83#define sg_dma_address(sg) ((sg)->dma_address)
84 84
85static inline void pci_dma_burst_advice(struct pci_dev *pdev,
86 enum pci_dma_burst_strategy *strat,
87 unsigned long *strategy_parameter)
88{
89 unsigned long cacheline_size;
90 u8 byte;
91
92 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
93 if (byte == 0)
94 cacheline_size = 1024;
95 else
96 cacheline_size = (int) byte * 4;
97
98 *strat = PCI_DMA_BURST_MULTIPLE;
99 *strategy_parameter = cacheline_size;
100}
101
85#define HAVE_PCI_MMAP 102#define HAVE_PCI_MMAP
86extern int pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma, 103extern int pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
87 enum pci_mmap_state mmap_state, int write_combine); 104 enum pci_mmap_state mmap_state, int write_combine);