Fix typos concerning hierarchy

        heirarchical, hierachical -> hierarchical
        heirarchy, hierachy -> hierarchy

Signed-off-by: Uwe Kleine-König <zeisberg@informatik.uni-freiburg.de>
Signed-off-by: Adrian Bunk <bunk@stusta.de>

1 files changed, 7 insertions, 7 deletions

diff --git a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h
index bc768153f3c9..e43021a99a20 100644
--- a/include/asm-ia64/pal.h
+++ b/include/asm-ia64/pal.h
@@ -32,7 +32,7 @@
 #define PAL_CACHE_FLUSH         1       /* flush i/d cache */
 #define PAL_CACHE_INFO          2       /* get detailed i/d cache info */
 #define PAL_CACHE_INIT          3       /* initialize i/d cache */
-#define PAL_CACHE_SUMMARY       4       /* get summary of cache heirarchy */
+#define PAL_CACHE_SUMMARY       4       /* get summary of cache hierarchy */
 #define PAL_MEM_ATTRIB          5       /* list supported memory attributes */
 #define PAL_PTCE_INFO           6       /* purge TLB info */
 #define PAL_VM_INFO             7       /* return supported virtual memory features */
@@ -113,14 +113,14 @@ typedef s64				pal_status_t;
                                                  */
 #define PAL_STATUS_REQUIRES_MEMORY      (-9)    /* Call requires PAL memory buffer */
 
-/* Processor cache level in the heirarchy */
+/* Processor cache level in the hierarchy */
 typedef u64                             pal_cache_level_t;
 #define PAL_CACHE_LEVEL_L0              0       /* L0 */
 #define PAL_CACHE_LEVEL_L1              1       /* L1 */
 #define PAL_CACHE_LEVEL_L2              2       /* L2 */
 
 
-/* Processor cache type at a particular level in the heirarchy */
+/* Processor cache type at a particular level in the hierarchy */
 
 typedef u64                             pal_cache_type_t;
 #define PAL_CACHE_TYPE_INSTRUCTION      1       /* Instruction cache */
@@ -272,14 +272,14 @@ typedef struct pal_cache_protection_info_s {
 #define PAL_CACHE_PROT_METHOD_ECC               3       /* ECC protection */
 
 
-/* Processor cache line identification in the heirarchy */
+/* Processor cache line identification in the hierarchy */
 typedef union pal_cache_line_id_u {
         u64                     pclid_data;
         struct {
                 u64             cache_type      : 8,    /* 7-0 cache type */
                                 level           : 8,    /* 15-8 level of the
                                                          * cache in the
-                                                         * heirarchy.
+                                                         * hierarchy.
                                                          */
                                 way             : 8,    /* 23-16 way in the set
                                                          */
@@ -292,7 +292,7 @@ typedef union pal_cache_line_id_u {
                 u64             cache_type      : 8,    /* 7-0 cache type */
                                 level           : 8,    /* 15-8 level of the
                                                          * cache in the
-                                                         * heirarchy.
+                                                         * hierarchy.
                                                          */
                                 way             : 8,    /* 23-16 way in the set
                                                          */
@@ -978,7 +978,7 @@ ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr)
         return iprv.status;
 }
 
-/* Return summary information about the heirarchy of caches controlled by the processor */
+/* Return summary information about the hierarchy of caches controlled by the processor */
 static inline s64
 ia64_pal_cache_summary (u64 *cache_levels, u64 *unique_caches)
 {