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authorTony Luck <tony.luck@intel.com>2006-06-05 16:54:14 -0400
committerTony Luck <tony.luck@intel.com>2006-06-05 16:54:14 -0400
commit76d08bb3f09054edc45326ce5c698a3f6c45f5d0 (patch)
tree5d0197f8ad8e4f778d6f117bcf49f9467fcdc0dd /include/asm-ia64/pal.h
parent672c6108a51bf559d19595d9f8193dfd81f0f752 (diff)
[IA64] Add "model name" to /proc/cpuinfo
Linux ia64 port tried to decode the processor family number to something human-readable, but Intel brandnames don't change synchronously with updates to the family number. Adopt a more i386-like approach and just print the family number in decimal. Add a new field "model name" that uses PAL_BRAND_INFO to find the official name for the cpu, or on older systems, falls back to using the well-known codenames (Merced, McKinley, Madison). Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'include/asm-ia64/pal.h')
-rw-r--r--include/asm-ia64/pal.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h
index 37e52a2836b0..312109d7be97 100644
--- a/include/asm-ia64/pal.h
+++ b/include/asm-ia64/pal.h
@@ -78,6 +78,7 @@
78#define PAL_VM_TR_READ 261 /* read contents of translation register */ 78#define PAL_VM_TR_READ 261 /* read contents of translation register */
79#define PAL_GET_PSTATE 262 /* get the current P-state */ 79#define PAL_GET_PSTATE 262 /* get the current P-state */
80#define PAL_SET_PSTATE 263 /* set the P-state */ 80#define PAL_SET_PSTATE 263 /* set the P-state */
81#define PAL_BRAND_INFO 274 /* Processor branding information */
81 82
82#ifndef __ASSEMBLY__ 83#ifndef __ASSEMBLY__
83 84
@@ -1133,6 +1134,15 @@ ia64_pal_set_pstate (u64 pstate_index)
1133 return iprv.status; 1134 return iprv.status;
1134} 1135}
1135 1136
1137/* Processor branding information*/
1138static inline s64
1139ia64_pal_get_brand_info (char *brand_info)
1140{
1141 struct ia64_pal_retval iprv;
1142 PAL_CALL_STK(iprv, PAL_BRAND_INFO, 0, (u64)brand_info, 0);
1143 return iprv.status;
1144}
1145
1136/* Cause the processor to enter LIGHT HALT state, where prefetching and execution are 1146/* Cause the processor to enter LIGHT HALT state, where prefetching and execution are
1137 * suspended, but cache and TLB coherency is maintained. 1147 * suspended, but cache and TLB coherency is maintained.
1138 */ 1148 */