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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-ia64/pal.h
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'include/asm-ia64/pal.h')
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diff --git a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h
new file mode 100644
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1#ifndef _ASM_IA64_PAL_H
2#define _ASM_IA64_PAL_H
3
4/*
5 * Processor Abstraction Layer definitions.
6 *
7 * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0
8 * chapter 11 IA-64 Processor Abstraction Layer
9 *
10 * Copyright (C) 1998-2001 Hewlett-Packard Co
11 * David Mosberger-Tang <davidm@hpl.hp.com>
12 * Stephane Eranian <eranian@hpl.hp.com>
13 * Copyright (C) 1999 VA Linux Systems
14 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
15 * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
16 *
17 * 99/10/01 davidm Make sure we pass zero for reserved parameters.
18 * 00/03/07 davidm Updated pal_cache_flush() to be in sync with PAL v2.6.
19 * 00/03/23 cfleck Modified processor min-state save area to match updated PAL & SAL info
20 * 00/05/24 eranian Updated to latest PAL spec, fix structures bugs, added
21 * 00/05/25 eranian Support for stack calls, and static physical calls
22 * 00/06/18 eranian Support for stacked physical calls
23 */
24
25/*
26 * Note that some of these calls use a static-register only calling
27 * convention which has nothing to do with the regular calling
28 * convention.
29 */
30#define PAL_CACHE_FLUSH 1 /* flush i/d cache */
31#define PAL_CACHE_INFO 2 /* get detailed i/d cache info */
32#define PAL_CACHE_INIT 3 /* initialize i/d cache */
33#define PAL_CACHE_SUMMARY 4 /* get summary of cache heirarchy */
34#define PAL_MEM_ATTRIB 5 /* list supported memory attributes */
35#define PAL_PTCE_INFO 6 /* purge TLB info */
36#define PAL_VM_INFO 7 /* return supported virtual memory features */
37#define PAL_VM_SUMMARY 8 /* return summary on supported vm features */
38#define PAL_BUS_GET_FEATURES 9 /* return processor bus interface features settings */
39#define PAL_BUS_SET_FEATURES 10 /* set processor bus features */
40#define PAL_DEBUG_INFO 11 /* get number of debug registers */
41#define PAL_FIXED_ADDR 12 /* get fixed component of processors's directed address */
42#define PAL_FREQ_BASE 13 /* base frequency of the platform */
43#define PAL_FREQ_RATIOS 14 /* ratio of processor, bus and ITC frequency */
44#define PAL_PERF_MON_INFO 15 /* return performance monitor info */
45#define PAL_PLATFORM_ADDR 16 /* set processor interrupt block and IO port space addr */
46#define PAL_PROC_GET_FEATURES 17 /* get configurable processor features & settings */
47#define PAL_PROC_SET_FEATURES 18 /* enable/disable configurable processor features */
48#define PAL_RSE_INFO 19 /* return rse information */
49#define PAL_VERSION 20 /* return version of PAL code */
50#define PAL_MC_CLEAR_LOG 21 /* clear all processor log info */
51#define PAL_MC_DRAIN 22 /* drain operations which could result in an MCA */
52#define PAL_MC_EXPECTED 23 /* set/reset expected MCA indicator */
53#define PAL_MC_DYNAMIC_STATE 24 /* get processor dynamic state */
54#define PAL_MC_ERROR_INFO 25 /* get processor MCA info and static state */
55#define PAL_MC_RESUME 26 /* Return to interrupted process */
56#define PAL_MC_REGISTER_MEM 27 /* Register memory for PAL to use during MCAs and inits */
57#define PAL_HALT 28 /* enter the low power HALT state */
58#define PAL_HALT_LIGHT 29 /* enter the low power light halt state*/
59#define PAL_COPY_INFO 30 /* returns info needed to relocate PAL */
60#define PAL_CACHE_LINE_INIT 31 /* init tags & data of cache line */
61#define PAL_PMI_ENTRYPOINT 32 /* register PMI memory entry points with the processor */
62#define PAL_ENTER_IA_32_ENV 33 /* enter IA-32 system environment */
63#define PAL_VM_PAGE_SIZE 34 /* return vm TC and page walker page sizes */
64
65#define PAL_MEM_FOR_TEST 37 /* get amount of memory needed for late processor test */
66#define PAL_CACHE_PROT_INFO 38 /* get i/d cache protection info */
67#define PAL_REGISTER_INFO 39 /* return AR and CR register information*/
68#define PAL_SHUTDOWN 40 /* enter processor shutdown state */
69#define PAL_PREFETCH_VISIBILITY 41 /* Make Processor Prefetches Visible */
70
71#define PAL_COPY_PAL 256 /* relocate PAL procedures and PAL PMI */
72#define PAL_HALT_INFO 257 /* return the low power capabilities of processor */
73#define PAL_TEST_PROC 258 /* perform late processor self-test */
74#define PAL_CACHE_READ 259 /* read tag & data of cacheline for diagnostic testing */
75#define PAL_CACHE_WRITE 260 /* write tag & data of cacheline for diagnostic testing */
76#define PAL_VM_TR_READ 261 /* read contents of translation register */
77
78#ifndef __ASSEMBLY__
79
80#include <linux/types.h>
81#include <asm/fpu.h>
82
83/*
84 * Data types needed to pass information into PAL procedures and
85 * interpret information returned by them.
86 */
87
88/* Return status from the PAL procedure */
89typedef s64 pal_status_t;
90
91#define PAL_STATUS_SUCCESS 0 /* No error */
92#define PAL_STATUS_UNIMPLEMENTED (-1) /* Unimplemented procedure */
93#define PAL_STATUS_EINVAL (-2) /* Invalid argument */
94#define PAL_STATUS_ERROR (-3) /* Error */
95#define PAL_STATUS_CACHE_INIT_FAIL (-4) /* Could not initialize the
96 * specified level and type of
97 * cache without sideeffects
98 * and "restrict" was 1
99 */
100
101/* Processor cache level in the heirarchy */
102typedef u64 pal_cache_level_t;
103#define PAL_CACHE_LEVEL_L0 0 /* L0 */
104#define PAL_CACHE_LEVEL_L1 1 /* L1 */
105#define PAL_CACHE_LEVEL_L2 2 /* L2 */
106
107
108/* Processor cache type at a particular level in the heirarchy */
109
110typedef u64 pal_cache_type_t;
111#define PAL_CACHE_TYPE_INSTRUCTION 1 /* Instruction cache */
112#define PAL_CACHE_TYPE_DATA 2 /* Data or unified cache */
113#define PAL_CACHE_TYPE_INSTRUCTION_DATA 3 /* Both Data & Instruction */
114
115
116#define PAL_CACHE_FLUSH_INVALIDATE 1 /* Invalidate clean lines */
117#define PAL_CACHE_FLUSH_CHK_INTRS 2 /* check for interrupts/mc while flushing */
118
119/* Processor cache line size in bytes */
120typedef int pal_cache_line_size_t;
121
122/* Processor cache line state */
123typedef u64 pal_cache_line_state_t;
124#define PAL_CACHE_LINE_STATE_INVALID 0 /* Invalid */
125#define PAL_CACHE_LINE_STATE_SHARED 1 /* Shared */
126#define PAL_CACHE_LINE_STATE_EXCLUSIVE 2 /* Exclusive */
127#define PAL_CACHE_LINE_STATE_MODIFIED 3 /* Modified */
128
129typedef struct pal_freq_ratio {
130 u64 den : 32, num : 32; /* numerator & denominator */
131} itc_ratio, proc_ratio;
132
133typedef union pal_cache_config_info_1_s {
134 struct {
135 u64 u : 1, /* 0 Unified cache ? */
136 at : 2, /* 2-1 Cache mem attr*/
137 reserved : 5, /* 7-3 Reserved */
138 associativity : 8, /* 16-8 Associativity*/
139 line_size : 8, /* 23-17 Line size */
140 stride : 8, /* 31-24 Stride */
141 store_latency : 8, /*39-32 Store latency*/
142 load_latency : 8, /* 47-40 Load latency*/
143 store_hints : 8, /* 55-48 Store hints*/
144 load_hints : 8; /* 63-56 Load hints */
145 } pcci1_bits;
146 u64 pcci1_data;
147} pal_cache_config_info_1_t;
148
149typedef union pal_cache_config_info_2_s {
150 struct {
151 u64 cache_size : 32, /*cache size in bytes*/
152
153
154 alias_boundary : 8, /* 39-32 aliased addr
155 * separation for max
156 * performance.
157 */
158 tag_ls_bit : 8, /* 47-40 LSb of addr*/
159 tag_ms_bit : 8, /* 55-48 MSb of addr*/
160 reserved : 8; /* 63-56 Reserved */
161 } pcci2_bits;
162 u64 pcci2_data;
163} pal_cache_config_info_2_t;
164
165
166typedef struct pal_cache_config_info_s {
167 pal_status_t pcci_status;
168 pal_cache_config_info_1_t pcci_info_1;
169 pal_cache_config_info_2_t pcci_info_2;
170 u64 pcci_reserved;
171} pal_cache_config_info_t;
172
173#define pcci_ld_hints pcci_info_1.pcci1_bits.load_hints
174#define pcci_st_hints pcci_info_1.pcci1_bits.store_hints
175#define pcci_ld_latency pcci_info_1.pcci1_bits.load_latency
176#define pcci_st_latency pcci_info_1.pcci1_bits.store_latency
177#define pcci_stride pcci_info_1.pcci1_bits.stride
178#define pcci_line_size pcci_info_1.pcci1_bits.line_size
179#define pcci_assoc pcci_info_1.pcci1_bits.associativity
180#define pcci_cache_attr pcci_info_1.pcci1_bits.at
181#define pcci_unified pcci_info_1.pcci1_bits.u
182#define pcci_tag_msb pcci_info_2.pcci2_bits.tag_ms_bit
183#define pcci_tag_lsb pcci_info_2.pcci2_bits.tag_ls_bit
184#define pcci_alias_boundary pcci_info_2.pcci2_bits.alias_boundary
185#define pcci_cache_size pcci_info_2.pcci2_bits.cache_size
186
187
188
189/* Possible values for cache attributes */
190
191#define PAL_CACHE_ATTR_WT 0 /* Write through cache */
192#define PAL_CACHE_ATTR_WB 1 /* Write back cache */
193#define PAL_CACHE_ATTR_WT_OR_WB 2 /* Either write thru or write
194 * back depending on TLB
195 * memory attributes
196 */
197
198
199/* Possible values for cache hints */
200
201#define PAL_CACHE_HINT_TEMP_1 0 /* Temporal level 1 */
202#define PAL_CACHE_HINT_NTEMP_1 1 /* Non-temporal level 1 */
203#define PAL_CACHE_HINT_NTEMP_ALL 3 /* Non-temporal all levels */
204
205/* Processor cache protection information */
206typedef union pal_cache_protection_element_u {
207 u32 pcpi_data;
208 struct {
209 u32 data_bits : 8, /* # data bits covered by
210 * each unit of protection
211 */
212
213 tagprot_lsb : 6, /* Least -do- */
214 tagprot_msb : 6, /* Most Sig. tag address
215 * bit that this
216 * protection covers.
217 */
218 prot_bits : 6, /* # of protection bits */
219 method : 4, /* Protection method */
220 t_d : 2; /* Indicates which part
221 * of the cache this
222 * protection encoding
223 * applies.
224 */
225 } pcp_info;
226} pal_cache_protection_element_t;
227
228#define pcpi_cache_prot_part pcp_info.t_d
229#define pcpi_prot_method pcp_info.method
230#define pcpi_prot_bits pcp_info.prot_bits
231#define pcpi_tagprot_msb pcp_info.tagprot_msb
232#define pcpi_tagprot_lsb pcp_info.tagprot_lsb
233#define pcpi_data_bits pcp_info.data_bits
234
235/* Processor cache part encodings */
236#define PAL_CACHE_PROT_PART_DATA 0 /* Data protection */
237#define PAL_CACHE_PROT_PART_TAG 1 /* Tag protection */
238#define PAL_CACHE_PROT_PART_TAG_DATA 2 /* Tag+data protection (tag is
239 * more significant )
240 */
241#define PAL_CACHE_PROT_PART_DATA_TAG 3 /* Data+tag protection (data is
242 * more significant )
243 */
244#define PAL_CACHE_PROT_PART_MAX 6
245
246
247typedef struct pal_cache_protection_info_s {
248 pal_status_t pcpi_status;
249 pal_cache_protection_element_t pcp_info[PAL_CACHE_PROT_PART_MAX];
250} pal_cache_protection_info_t;
251
252
253/* Processor cache protection method encodings */
254#define PAL_CACHE_PROT_METHOD_NONE 0 /* No protection */
255#define PAL_CACHE_PROT_METHOD_ODD_PARITY 1 /* Odd parity */
256#define PAL_CACHE_PROT_METHOD_EVEN_PARITY 2 /* Even parity */
257#define PAL_CACHE_PROT_METHOD_ECC 3 /* ECC protection */
258
259
260/* Processor cache line identification in the heirarchy */
261typedef union pal_cache_line_id_u {
262 u64 pclid_data;
263 struct {
264 u64 cache_type : 8, /* 7-0 cache type */
265 level : 8, /* 15-8 level of the
266 * cache in the
267 * heirarchy.
268 */
269 way : 8, /* 23-16 way in the set
270 */
271 part : 8, /* 31-24 part of the
272 * cache
273 */
274 reserved : 32; /* 63-32 is reserved*/
275 } pclid_info_read;
276 struct {
277 u64 cache_type : 8, /* 7-0 cache type */
278 level : 8, /* 15-8 level of the
279 * cache in the
280 * heirarchy.
281 */
282 way : 8, /* 23-16 way in the set
283 */
284 part : 8, /* 31-24 part of the
285 * cache
286 */
287 mesi : 8, /* 39-32 cache line
288 * state
289 */
290 start : 8, /* 47-40 lsb of data to
291 * invert
292 */
293 length : 8, /* 55-48 #bits to
294 * invert
295 */
296 trigger : 8; /* 63-56 Trigger error
297 * by doing a load
298 * after the write
299 */
300
301 } pclid_info_write;
302} pal_cache_line_id_u_t;
303
304#define pclid_read_part pclid_info_read.part
305#define pclid_read_way pclid_info_read.way
306#define pclid_read_level pclid_info_read.level
307#define pclid_read_cache_type pclid_info_read.cache_type
308
309#define pclid_write_trigger pclid_info_write.trigger
310#define pclid_write_length pclid_info_write.length
311#define pclid_write_start pclid_info_write.start
312#define pclid_write_mesi pclid_info_write.mesi
313#define pclid_write_part pclid_info_write.part
314#define pclid_write_way pclid_info_write.way
315#define pclid_write_level pclid_info_write.level
316#define pclid_write_cache_type pclid_info_write.cache_type
317
318/* Processor cache line part encodings */
319#define PAL_CACHE_LINE_ID_PART_DATA 0 /* Data */
320#define PAL_CACHE_LINE_ID_PART_TAG 1 /* Tag */
321#define PAL_CACHE_LINE_ID_PART_DATA_PROT 2 /* Data protection */
322#define PAL_CACHE_LINE_ID_PART_TAG_PROT 3 /* Tag protection */
323#define PAL_CACHE_LINE_ID_PART_DATA_TAG_PROT 4 /* Data+tag
324 * protection
325 */
326typedef struct pal_cache_line_info_s {
327 pal_status_t pcli_status; /* Return status of the read cache line
328 * info call.
329 */
330 u64 pcli_data; /* 64-bit data, tag, protection bits .. */
331 u64 pcli_data_len; /* data length in bits */
332 pal_cache_line_state_t pcli_cache_line_state; /* mesi state */
333
334} pal_cache_line_info_t;
335
336
337/* Machine Check related crap */
338
339/* Pending event status bits */
340typedef u64 pal_mc_pending_events_t;
341
342#define PAL_MC_PENDING_MCA (1 << 0)
343#define PAL_MC_PENDING_INIT (1 << 1)
344
345/* Error information type */
346typedef u64 pal_mc_info_index_t;
347
348#define PAL_MC_INFO_PROCESSOR 0 /* Processor */
349#define PAL_MC_INFO_CACHE_CHECK 1 /* Cache check */
350#define PAL_MC_INFO_TLB_CHECK 2 /* Tlb check */
351#define PAL_MC_INFO_BUS_CHECK 3 /* Bus check */
352#define PAL_MC_INFO_REQ_ADDR 4 /* Requestor address */
353#define PAL_MC_INFO_RESP_ADDR 5 /* Responder address */
354#define PAL_MC_INFO_TARGET_ADDR 6 /* Target address */
355#define PAL_MC_INFO_IMPL_DEP 7 /* Implementation
356 * dependent
357 */
358
359
360typedef struct pal_process_state_info_s {
361 u64 reserved1 : 2,
362 rz : 1, /* PAL_CHECK processor
363 * rendezvous
364 * successful.
365 */
366
367 ra : 1, /* PAL_CHECK attempted
368 * a rendezvous.
369 */
370 me : 1, /* Distinct multiple
371 * errors occurred
372 */
373
374 mn : 1, /* Min. state save
375 * area has been
376 * registered with PAL
377 */
378
379 sy : 1, /* Storage integrity
380 * synched
381 */
382
383
384 co : 1, /* Continuable */
385 ci : 1, /* MC isolated */
386 us : 1, /* Uncontained storage
387 * damage.
388 */
389
390
391 hd : 1, /* Non-essential hw
392 * lost (no loss of
393 * functionality)
394 * causing the
395 * processor to run in
396 * degraded mode.
397 */
398
399 tl : 1, /* 1 => MC occurred
400 * after an instr was
401 * executed but before
402 * the trap that
403 * resulted from instr
404 * execution was
405 * generated.
406 * (Trap Lost )
407 */
408 mi : 1, /* More information available
409 * call PAL_MC_ERROR_INFO
410 */
411 pi : 1, /* Precise instruction pointer */
412 pm : 1, /* Precise min-state save area */
413
414 dy : 1, /* Processor dynamic
415 * state valid
416 */
417
418
419 in : 1, /* 0 = MC, 1 = INIT */
420 rs : 1, /* RSE valid */
421 cm : 1, /* MC corrected */
422 ex : 1, /* MC is expected */
423 cr : 1, /* Control regs valid*/
424 pc : 1, /* Perf cntrs valid */
425 dr : 1, /* Debug regs valid */
426 tr : 1, /* Translation regs
427 * valid
428 */
429 rr : 1, /* Region regs valid */
430 ar : 1, /* App regs valid */
431 br : 1, /* Branch regs valid */
432 pr : 1, /* Predicate registers
433 * valid
434 */
435
436 fp : 1, /* fp registers valid*/
437 b1 : 1, /* Preserved bank one
438 * general registers
439 * are valid
440 */
441 b0 : 1, /* Preserved bank zero
442 * general registers
443 * are valid
444 */
445 gr : 1, /* General registers
446 * are valid
447 * (excl. banked regs)
448 */
449 dsize : 16, /* size of dynamic
450 * state returned
451 * by the processor
452 */
453
454 reserved2 : 11,
455 cc : 1, /* Cache check */
456 tc : 1, /* TLB check */
457 bc : 1, /* Bus check */
458 rc : 1, /* Register file check */
459 uc : 1; /* Uarch check */
460
461} pal_processor_state_info_t;
462
463typedef struct pal_cache_check_info_s {
464 u64 op : 4, /* Type of cache
465 * operation that
466 * caused the machine
467 * check.
468 */
469 level : 2, /* Cache level */
470 reserved1 : 2,
471 dl : 1, /* Failure in data part
472 * of cache line
473 */
474 tl : 1, /* Failure in tag part
475 * of cache line
476 */
477 dc : 1, /* Failure in dcache */
478 ic : 1, /* Failure in icache */
479 mesi : 3, /* Cache line state */
480 mv : 1, /* mesi valid */
481 way : 5, /* Way in which the
482 * error occurred
483 */
484 wiv : 1, /* Way field valid */
485 reserved2 : 10,
486
487 index : 20, /* Cache line index */
488 reserved3 : 2,
489
490 is : 1, /* instruction set (1 == ia32) */
491 iv : 1, /* instruction set field valid */
492 pl : 2, /* privilege level */
493 pv : 1, /* privilege level field valid */
494 mcc : 1, /* Machine check corrected */
495 tv : 1, /* Target address
496 * structure is valid
497 */
498 rq : 1, /* Requester identifier
499 * structure is valid
500 */
501 rp : 1, /* Responder identifier
502 * structure is valid
503 */
504 pi : 1; /* Precise instruction pointer
505 * structure is valid
506 */
507} pal_cache_check_info_t;
508
509typedef struct pal_tlb_check_info_s {
510
511 u64 tr_slot : 8, /* Slot# of TR where
512 * error occurred
513 */
514 trv : 1, /* tr_slot field is valid */
515 reserved1 : 1,
516 level : 2, /* TLB level where failure occurred */
517 reserved2 : 4,
518 dtr : 1, /* Fail in data TR */
519 itr : 1, /* Fail in inst TR */
520 dtc : 1, /* Fail in data TC */
521 itc : 1, /* Fail in inst. TC */
522 op : 4, /* Cache operation */
523 reserved3 : 30,
524
525 is : 1, /* instruction set (1 == ia32) */
526 iv : 1, /* instruction set field valid */
527 pl : 2, /* privilege level */
528 pv : 1, /* privilege level field valid */
529 mcc : 1, /* Machine check corrected */
530 tv : 1, /* Target address
531 * structure is valid
532 */
533 rq : 1, /* Requester identifier
534 * structure is valid
535 */
536 rp : 1, /* Responder identifier
537 * structure is valid
538 */
539 pi : 1; /* Precise instruction pointer
540 * structure is valid
541 */
542} pal_tlb_check_info_t;
543
544typedef struct pal_bus_check_info_s {
545 u64 size : 5, /* Xaction size */
546 ib : 1, /* Internal bus error */
547 eb : 1, /* External bus error */
548 cc : 1, /* Error occurred
549 * during cache-cache
550 * transfer.
551 */
552 type : 8, /* Bus xaction type*/
553 sev : 5, /* Bus error severity*/
554 hier : 2, /* Bus hierarchy level */
555 reserved1 : 1,
556 bsi : 8, /* Bus error status
557 * info
558 */
559 reserved2 : 22,
560
561 is : 1, /* instruction set (1 == ia32) */
562 iv : 1, /* instruction set field valid */
563 pl : 2, /* privilege level */
564 pv : 1, /* privilege level field valid */
565 mcc : 1, /* Machine check corrected */
566 tv : 1, /* Target address
567 * structure is valid
568 */
569 rq : 1, /* Requester identifier
570 * structure is valid
571 */
572 rp : 1, /* Responder identifier
573 * structure is valid
574 */
575 pi : 1; /* Precise instruction pointer
576 * structure is valid
577 */
578} pal_bus_check_info_t;
579
580typedef struct pal_reg_file_check_info_s {
581 u64 id : 4, /* Register file identifier */
582 op : 4, /* Type of register
583 * operation that
584 * caused the machine
585 * check.
586 */
587 reg_num : 7, /* Register number */
588 rnv : 1, /* reg_num valid */
589 reserved2 : 38,
590
591 is : 1, /* instruction set (1 == ia32) */
592 iv : 1, /* instruction set field valid */
593 pl : 2, /* privilege level */
594 pv : 1, /* privilege level field valid */
595 mcc : 1, /* Machine check corrected */
596 reserved3 : 3,
597 pi : 1; /* Precise instruction pointer
598 * structure is valid
599 */
600} pal_reg_file_check_info_t;
601
602typedef struct pal_uarch_check_info_s {
603 u64 sid : 5, /* Structure identification */
604 level : 3, /* Level of failure */
605 array_id : 4, /* Array identification */
606 op : 4, /* Type of
607 * operation that
608 * caused the machine
609 * check.
610 */
611 way : 6, /* Way of structure */
612 wv : 1, /* way valid */
613 xv : 1, /* index valid */
614 reserved1 : 8,
615 index : 8, /* Index or set of the uarch
616 * structure that failed.
617 */
618 reserved2 : 24,
619
620 is : 1, /* instruction set (1 == ia32) */
621 iv : 1, /* instruction set field valid */
622 pl : 2, /* privilege level */
623 pv : 1, /* privilege level field valid */
624 mcc : 1, /* Machine check corrected */
625 tv : 1, /* Target address
626 * structure is valid
627 */
628 rq : 1, /* Requester identifier
629 * structure is valid
630 */
631 rp : 1, /* Responder identifier
632 * structure is valid
633 */
634 pi : 1; /* Precise instruction pointer
635 * structure is valid
636 */
637} pal_uarch_check_info_t;
638
639typedef union pal_mc_error_info_u {
640 u64 pmei_data;
641 pal_processor_state_info_t pme_processor;
642 pal_cache_check_info_t pme_cache;
643 pal_tlb_check_info_t pme_tlb;
644 pal_bus_check_info_t pme_bus;
645 pal_reg_file_check_info_t pme_reg_file;
646 pal_uarch_check_info_t pme_uarch;
647} pal_mc_error_info_t;
648
649#define pmci_proc_unknown_check pme_processor.uc
650#define pmci_proc_bus_check pme_processor.bc
651#define pmci_proc_tlb_check pme_processor.tc
652#define pmci_proc_cache_check pme_processor.cc
653#define pmci_proc_dynamic_state_size pme_processor.dsize
654#define pmci_proc_gpr_valid pme_processor.gr
655#define pmci_proc_preserved_bank0_gpr_valid pme_processor.b0
656#define pmci_proc_preserved_bank1_gpr_valid pme_processor.b1
657#define pmci_proc_fp_valid pme_processor.fp
658#define pmci_proc_predicate_regs_valid pme_processor.pr
659#define pmci_proc_branch_regs_valid pme_processor.br
660#define pmci_proc_app_regs_valid pme_processor.ar
661#define pmci_proc_region_regs_valid pme_processor.rr
662#define pmci_proc_translation_regs_valid pme_processor.tr
663#define pmci_proc_debug_regs_valid pme_processor.dr
664#define pmci_proc_perf_counters_valid pme_processor.pc
665#define pmci_proc_control_regs_valid pme_processor.cr
666#define pmci_proc_machine_check_expected pme_processor.ex
667#define pmci_proc_machine_check_corrected pme_processor.cm
668#define pmci_proc_rse_valid pme_processor.rs
669#define pmci_proc_machine_check_or_init pme_processor.in
670#define pmci_proc_dynamic_state_valid pme_processor.dy
671#define pmci_proc_operation pme_processor.op
672#define pmci_proc_trap_lost pme_processor.tl
673#define pmci_proc_hardware_damage pme_processor.hd
674#define pmci_proc_uncontained_storage_damage pme_processor.us
675#define pmci_proc_machine_check_isolated pme_processor.ci
676#define pmci_proc_continuable pme_processor.co
677#define pmci_proc_storage_intergrity_synced pme_processor.sy
678#define pmci_proc_min_state_save_area_regd pme_processor.mn
679#define pmci_proc_distinct_multiple_errors pme_processor.me
680#define pmci_proc_pal_attempted_rendezvous pme_processor.ra
681#define pmci_proc_pal_rendezvous_complete pme_processor.rz
682
683
684#define pmci_cache_level pme_cache.level
685#define pmci_cache_line_state pme_cache.mesi
686#define pmci_cache_line_state_valid pme_cache.mv
687#define pmci_cache_line_index pme_cache.index
688#define pmci_cache_instr_cache_fail pme_cache.ic
689#define pmci_cache_data_cache_fail pme_cache.dc
690#define pmci_cache_line_tag_fail pme_cache.tl
691#define pmci_cache_line_data_fail pme_cache.dl
692#define pmci_cache_operation pme_cache.op
693#define pmci_cache_way_valid pme_cache.wv
694#define pmci_cache_target_address_valid pme_cache.tv
695#define pmci_cache_way pme_cache.way
696#define pmci_cache_mc pme_cache.mc
697
698#define pmci_tlb_instr_translation_cache_fail pme_tlb.itc
699#define pmci_tlb_data_translation_cache_fail pme_tlb.dtc
700#define pmci_tlb_instr_translation_reg_fail pme_tlb.itr
701#define pmci_tlb_data_translation_reg_fail pme_tlb.dtr
702#define pmci_tlb_translation_reg_slot pme_tlb.tr_slot
703#define pmci_tlb_mc pme_tlb.mc
704
705#define pmci_bus_status_info pme_bus.bsi
706#define pmci_bus_req_address_valid pme_bus.rq
707#define pmci_bus_resp_address_valid pme_bus.rp
708#define pmci_bus_target_address_valid pme_bus.tv
709#define pmci_bus_error_severity pme_bus.sev
710#define pmci_bus_transaction_type pme_bus.type
711#define pmci_bus_cache_cache_transfer pme_bus.cc
712#define pmci_bus_transaction_size pme_bus.size
713#define pmci_bus_internal_error pme_bus.ib
714#define pmci_bus_external_error pme_bus.eb
715#define pmci_bus_mc pme_bus.mc
716
717/*
718 * NOTE: this min_state_save area struct only includes the 1KB
719 * architectural state save area. The other 3 KB is scratch space
720 * for PAL.
721 */
722
723typedef struct pal_min_state_area_s {
724 u64 pmsa_nat_bits; /* nat bits for saved GRs */
725 u64 pmsa_gr[15]; /* GR1 - GR15 */
726 u64 pmsa_bank0_gr[16]; /* GR16 - GR31 */
727 u64 pmsa_bank1_gr[16]; /* GR16 - GR31 */
728 u64 pmsa_pr; /* predicate registers */
729 u64 pmsa_br0; /* branch register 0 */
730 u64 pmsa_rsc; /* ar.rsc */
731 u64 pmsa_iip; /* cr.iip */
732 u64 pmsa_ipsr; /* cr.ipsr */
733 u64 pmsa_ifs; /* cr.ifs */
734 u64 pmsa_xip; /* previous iip */
735 u64 pmsa_xpsr; /* previous psr */
736 u64 pmsa_xfs; /* previous ifs */
737 u64 pmsa_br1; /* branch register 1 */
738 u64 pmsa_reserved[70]; /* pal_min_state_area should total to 1KB */
739} pal_min_state_area_t;
740
741
742struct ia64_pal_retval {
743 /*
744 * A zero status value indicates call completed without error.
745 * A negative status value indicates reason of call failure.
746 * A positive status value indicates success but an
747 * informational value should be printed (e.g., "reboot for
748 * change to take effect").
749 */
750 s64 status;
751 u64 v0;
752 u64 v1;
753 u64 v2;
754};
755
756/*
757 * Note: Currently unused PAL arguments are generally labeled
758 * "reserved" so the value specified in the PAL documentation
759 * (generally 0) MUST be passed. Reserved parameters are not optional
760 * parameters.
761 */
762extern struct ia64_pal_retval ia64_pal_call_static (u64, u64, u64, u64, u64);
763extern struct ia64_pal_retval ia64_pal_call_stacked (u64, u64, u64, u64);
764extern struct ia64_pal_retval ia64_pal_call_phys_static (u64, u64, u64, u64);
765extern struct ia64_pal_retval ia64_pal_call_phys_stacked (u64, u64, u64, u64);
766extern void ia64_save_scratch_fpregs (struct ia64_fpreg *);
767extern void ia64_load_scratch_fpregs (struct ia64_fpreg *);
768
769#define PAL_CALL(iprv,a0,a1,a2,a3) do { \
770 struct ia64_fpreg fr[6]; \
771 ia64_save_scratch_fpregs(fr); \
772 iprv = ia64_pal_call_static(a0, a1, a2, a3, 0); \
773 ia64_load_scratch_fpregs(fr); \
774} while (0)
775
776#define PAL_CALL_IC_OFF(iprv,a0,a1,a2,a3) do { \
777 struct ia64_fpreg fr[6]; \
778 ia64_save_scratch_fpregs(fr); \
779 iprv = ia64_pal_call_static(a0, a1, a2, a3, 1); \
780 ia64_load_scratch_fpregs(fr); \
781} while (0)
782
783#define PAL_CALL_STK(iprv,a0,a1,a2,a3) do { \
784 struct ia64_fpreg fr[6]; \
785 ia64_save_scratch_fpregs(fr); \
786 iprv = ia64_pal_call_stacked(a0, a1, a2, a3); \
787 ia64_load_scratch_fpregs(fr); \
788} while (0)
789
790#define PAL_CALL_PHYS(iprv,a0,a1,a2,a3) do { \
791 struct ia64_fpreg fr[6]; \
792 ia64_save_scratch_fpregs(fr); \
793 iprv = ia64_pal_call_phys_static(a0, a1, a2, a3); \
794 ia64_load_scratch_fpregs(fr); \
795} while (0)
796
797#define PAL_CALL_PHYS_STK(iprv,a0,a1,a2,a3) do { \
798 struct ia64_fpreg fr[6]; \
799 ia64_save_scratch_fpregs(fr); \
800 iprv = ia64_pal_call_phys_stacked(a0, a1, a2, a3); \
801 ia64_load_scratch_fpregs(fr); \
802} while (0)
803
804typedef int (*ia64_pal_handler) (u64, ...);
805extern ia64_pal_handler ia64_pal;
806extern void ia64_pal_handler_init (void *);
807
808extern ia64_pal_handler ia64_pal;
809
810extern pal_cache_config_info_t l0d_cache_config_info;
811extern pal_cache_config_info_t l0i_cache_config_info;
812extern pal_cache_config_info_t l1_cache_config_info;
813extern pal_cache_config_info_t l2_cache_config_info;
814
815extern pal_cache_protection_info_t l0d_cache_protection_info;
816extern pal_cache_protection_info_t l0i_cache_protection_info;
817extern pal_cache_protection_info_t l1_cache_protection_info;
818extern pal_cache_protection_info_t l2_cache_protection_info;
819
820extern pal_cache_config_info_t pal_cache_config_info_get(pal_cache_level_t,
821 pal_cache_type_t);
822
823extern pal_cache_protection_info_t pal_cache_protection_info_get(pal_cache_level_t,
824 pal_cache_type_t);
825
826
827extern void pal_error(int);
828
829
830/* Useful wrappers for the current list of pal procedures */
831
832typedef union pal_bus_features_u {
833 u64 pal_bus_features_val;
834 struct {
835 u64 pbf_reserved1 : 29;
836 u64 pbf_req_bus_parking : 1;
837 u64 pbf_bus_lock_mask : 1;
838 u64 pbf_enable_half_xfer_rate : 1;
839 u64 pbf_reserved2 : 22;
840 u64 pbf_disable_xaction_queueing : 1;
841 u64 pbf_disable_resp_err_check : 1;
842 u64 pbf_disable_berr_check : 1;
843 u64 pbf_disable_bus_req_internal_err_signal : 1;
844 u64 pbf_disable_bus_req_berr_signal : 1;
845 u64 pbf_disable_bus_init_event_check : 1;
846 u64 pbf_disable_bus_init_event_signal : 1;
847 u64 pbf_disable_bus_addr_err_check : 1;
848 u64 pbf_disable_bus_addr_err_signal : 1;
849 u64 pbf_disable_bus_data_err_check : 1;
850 } pal_bus_features_s;
851} pal_bus_features_u_t;
852
853extern void pal_bus_features_print (u64);
854
855/* Provide information about configurable processor bus features */
856static inline s64
857ia64_pal_bus_get_features (pal_bus_features_u_t *features_avail,
858 pal_bus_features_u_t *features_status,
859 pal_bus_features_u_t *features_control)
860{
861 struct ia64_pal_retval iprv;
862 PAL_CALL_PHYS(iprv, PAL_BUS_GET_FEATURES, 0, 0, 0);
863 if (features_avail)
864 features_avail->pal_bus_features_val = iprv.v0;
865 if (features_status)
866 features_status->pal_bus_features_val = iprv.v1;
867 if (features_control)
868 features_control->pal_bus_features_val = iprv.v2;
869 return iprv.status;
870}
871
872/* Enables/disables specific processor bus features */
873static inline s64
874ia64_pal_bus_set_features (pal_bus_features_u_t feature_select)
875{
876 struct ia64_pal_retval iprv;
877 PAL_CALL_PHYS(iprv, PAL_BUS_SET_FEATURES, feature_select.pal_bus_features_val, 0, 0);
878 return iprv.status;
879}
880
881/* Get detailed cache information */
882static inline s64
883ia64_pal_cache_config_info (u64 cache_level, u64 cache_type, pal_cache_config_info_t *conf)
884{
885 struct ia64_pal_retval iprv;
886
887 PAL_CALL(iprv, PAL_CACHE_INFO, cache_level, cache_type, 0);
888
889 if (iprv.status == 0) {
890 conf->pcci_status = iprv.status;
891 conf->pcci_info_1.pcci1_data = iprv.v0;
892 conf->pcci_info_2.pcci2_data = iprv.v1;
893 conf->pcci_reserved = iprv.v2;
894 }
895 return iprv.status;
896
897}
898
899/* Get detailed cche protection information */
900static inline s64
901ia64_pal_cache_prot_info (u64 cache_level, u64 cache_type, pal_cache_protection_info_t *prot)
902{
903 struct ia64_pal_retval iprv;
904
905 PAL_CALL(iprv, PAL_CACHE_PROT_INFO, cache_level, cache_type, 0);
906
907 if (iprv.status == 0) {
908 prot->pcpi_status = iprv.status;
909 prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff;
910 prot->pcp_info[1].pcpi_data = iprv.v0 >> 32;
911 prot->pcp_info[2].pcpi_data = iprv.v1 & 0xffffffff;
912 prot->pcp_info[3].pcpi_data = iprv.v1 >> 32;
913 prot->pcp_info[4].pcpi_data = iprv.v2 & 0xffffffff;
914 prot->pcp_info[5].pcpi_data = iprv.v2 >> 32;
915 }
916 return iprv.status;
917}
918
919/*
920 * Flush the processor instruction or data caches. *PROGRESS must be
921 * initialized to zero before calling this for the first time..
922 */
923static inline s64
924ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector)
925{
926 struct ia64_pal_retval iprv;
927 PAL_CALL_IC_OFF(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
928 if (vector)
929 *vector = iprv.v0;
930 *progress = iprv.v1;
931 return iprv.status;
932}
933
934
935/* Initialize the processor controlled caches */
936static inline s64
937ia64_pal_cache_init (u64 level, u64 cache_type, u64 rest)
938{
939 struct ia64_pal_retval iprv;
940 PAL_CALL(iprv, PAL_CACHE_INIT, level, cache_type, rest);
941 return iprv.status;
942}
943
944/* Initialize the tags and data of a data or unified cache line of
945 * processor controlled cache to known values without the availability
946 * of backing memory.
947 */
948static inline s64
949ia64_pal_cache_line_init (u64 physical_addr, u64 data_value)
950{
951 struct ia64_pal_retval iprv;
952 PAL_CALL(iprv, PAL_CACHE_LINE_INIT, physical_addr, data_value, 0);
953 return iprv.status;
954}
955
956
957/* Read the data and tag of a processor controlled cache line for diags */
958static inline s64
959ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr)
960{
961 struct ia64_pal_retval iprv;
962 PAL_CALL(iprv, PAL_CACHE_READ, line_id.pclid_data, physical_addr, 0);
963 return iprv.status;
964}
965
966/* Return summary information about the heirarchy of caches controlled by the processor */
967static inline s64
968ia64_pal_cache_summary (u64 *cache_levels, u64 *unique_caches)
969{
970 struct ia64_pal_retval iprv;
971 PAL_CALL(iprv, PAL_CACHE_SUMMARY, 0, 0, 0);
972 if (cache_levels)
973 *cache_levels = iprv.v0;
974 if (unique_caches)
975 *unique_caches = iprv.v1;
976 return iprv.status;
977}
978
979/* Write the data and tag of a processor-controlled cache line for diags */
980static inline s64
981ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data)
982{
983 struct ia64_pal_retval iprv;
984 PAL_CALL(iprv, PAL_CACHE_WRITE, line_id.pclid_data, physical_addr, data);
985 return iprv.status;
986}
987
988
989/* Return the parameters needed to copy relocatable PAL procedures from ROM to memory */
990static inline s64
991ia64_pal_copy_info (u64 copy_type, u64 num_procs, u64 num_iopics,
992 u64 *buffer_size, u64 *buffer_align)
993{
994 struct ia64_pal_retval iprv;
995 PAL_CALL(iprv, PAL_COPY_INFO, copy_type, num_procs, num_iopics);
996 if (buffer_size)
997 *buffer_size = iprv.v0;
998 if (buffer_align)
999 *buffer_align = iprv.v1;
1000 return iprv.status;
1001}
1002
1003/* Copy relocatable PAL procedures from ROM to memory */
1004static inline s64
1005ia64_pal_copy_pal (u64 target_addr, u64 alloc_size, u64 processor, u64 *pal_proc_offset)
1006{
1007 struct ia64_pal_retval iprv;
1008 PAL_CALL(iprv, PAL_COPY_PAL, target_addr, alloc_size, processor);
1009 if (pal_proc_offset)
1010 *pal_proc_offset = iprv.v0;
1011 return iprv.status;
1012}
1013
1014/* Return the number of instruction and data debug register pairs */
1015static inline s64
1016ia64_pal_debug_info (u64 *inst_regs, u64 *data_regs)
1017{
1018 struct ia64_pal_retval iprv;
1019 PAL_CALL(iprv, PAL_DEBUG_INFO, 0, 0, 0);
1020 if (inst_regs)
1021 *inst_regs = iprv.v0;
1022 if (data_regs)
1023 *data_regs = iprv.v1;
1024
1025 return iprv.status;
1026}
1027
1028#ifdef TBD
1029/* Switch from IA64-system environment to IA-32 system environment */
1030static inline s64
1031ia64_pal_enter_ia32_env (ia32_env1, ia32_env2, ia32_env3)
1032{
1033 struct ia64_pal_retval iprv;
1034 PAL_CALL(iprv, PAL_ENTER_IA_32_ENV, ia32_env1, ia32_env2, ia32_env3);
1035 return iprv.status;
1036}
1037#endif
1038
1039/* Get unique geographical address of this processor on its bus */
1040static inline s64
1041ia64_pal_fixed_addr (u64 *global_unique_addr)
1042{
1043 struct ia64_pal_retval iprv;
1044 PAL_CALL(iprv, PAL_FIXED_ADDR, 0, 0, 0);
1045 if (global_unique_addr)
1046 *global_unique_addr = iprv.v0;
1047 return iprv.status;
1048}
1049
1050/* Get base frequency of the platform if generated by the processor */
1051static inline s64
1052ia64_pal_freq_base (u64 *platform_base_freq)
1053{
1054 struct ia64_pal_retval iprv;
1055 PAL_CALL(iprv, PAL_FREQ_BASE, 0, 0, 0);
1056 if (platform_base_freq)
1057 *platform_base_freq = iprv.v0;
1058 return iprv.status;
1059}
1060
1061/*
1062 * Get the ratios for processor frequency, bus frequency and interval timer to
1063 * to base frequency of the platform
1064 */
1065static inline s64
1066ia64_pal_freq_ratios (struct pal_freq_ratio *proc_ratio, struct pal_freq_ratio *bus_ratio,
1067 struct pal_freq_ratio *itc_ratio)
1068{
1069 struct ia64_pal_retval iprv;
1070 PAL_CALL(iprv, PAL_FREQ_RATIOS, 0, 0, 0);
1071 if (proc_ratio)
1072 *(u64 *)proc_ratio = iprv.v0;
1073 if (bus_ratio)
1074 *(u64 *)bus_ratio = iprv.v1;
1075 if (itc_ratio)
1076 *(u64 *)itc_ratio = iprv.v2;
1077 return iprv.status;
1078}
1079
1080/* Make the processor enter HALT or one of the implementation dependent low
1081 * power states where prefetching and execution are suspended and cache and
1082 * TLB coherency is not maintained.
1083 */
1084static inline s64
1085ia64_pal_halt (u64 halt_state)
1086{
1087 struct ia64_pal_retval iprv;
1088 PAL_CALL(iprv, PAL_HALT, halt_state, 0, 0);
1089 return iprv.status;
1090}
1091
1092typedef union pal_power_mgmt_info_u {
1093 u64 ppmi_data;
1094 struct {
1095 u64 exit_latency : 16,
1096 entry_latency : 16,
1097 power_consumption : 28,
1098 im : 1,
1099 co : 1,
1100 reserved : 2;
1101 } pal_power_mgmt_info_s;
1102} pal_power_mgmt_info_u_t;
1103
1104/* Return information about processor's optional power management capabilities. */
1105static inline s64
1106ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf)
1107{
1108 struct ia64_pal_retval iprv;
1109 PAL_CALL_STK(iprv, PAL_HALT_INFO, (unsigned long) power_buf, 0, 0);
1110 return iprv.status;
1111}
1112
1113/* Cause the processor to enter LIGHT HALT state, where prefetching and execution are
1114 * suspended, but cache and TLB coherency is maintained.
1115 */
1116static inline s64
1117ia64_pal_halt_light (void)
1118{
1119 struct ia64_pal_retval iprv;
1120 PAL_CALL(iprv, PAL_HALT_LIGHT, 0, 0, 0);
1121 return iprv.status;
1122}
1123
1124/* Clear all the processor error logging registers and reset the indicator that allows
1125 * the error logging registers to be written. This procedure also checks the pending
1126 * machine check bit and pending INIT bit and reports their states.
1127 */
1128static inline s64
1129ia64_pal_mc_clear_log (u64 *pending_vector)
1130{
1131 struct ia64_pal_retval iprv;
1132 PAL_CALL(iprv, PAL_MC_CLEAR_LOG, 0, 0, 0);
1133 if (pending_vector)
1134 *pending_vector = iprv.v0;
1135 return iprv.status;
1136}
1137
1138/* Ensure that all outstanding transactions in a processor are completed or that any
1139 * MCA due to thes outstanding transaction is taken.
1140 */
1141static inline s64
1142ia64_pal_mc_drain (void)
1143{
1144 struct ia64_pal_retval iprv;
1145 PAL_CALL(iprv, PAL_MC_DRAIN, 0, 0, 0);
1146 return iprv.status;
1147}
1148
1149/* Return the machine check dynamic processor state */
1150static inline s64
1151ia64_pal_mc_dynamic_state (u64 offset, u64 *size, u64 *pds)
1152{
1153 struct ia64_pal_retval iprv;
1154 PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, offset, 0, 0);
1155 if (size)
1156 *size = iprv.v0;
1157 if (pds)
1158 *pds = iprv.v1;
1159 return iprv.status;
1160}
1161
1162/* Return processor machine check information */
1163static inline s64
1164ia64_pal_mc_error_info (u64 info_index, u64 type_index, u64 *size, u64 *error_info)
1165{
1166 struct ia64_pal_retval iprv;
1167 PAL_CALL(iprv, PAL_MC_ERROR_INFO, info_index, type_index, 0);
1168 if (size)
1169 *size = iprv.v0;
1170 if (error_info)
1171 *error_info = iprv.v1;
1172 return iprv.status;
1173}
1174
1175/* Inform PALE_CHECK whether a machine check is expected so that PALE_CHECK willnot
1176 * attempt to correct any expected machine checks.
1177 */
1178static inline s64
1179ia64_pal_mc_expected (u64 expected, u64 *previous)
1180{
1181 struct ia64_pal_retval iprv;
1182 PAL_CALL(iprv, PAL_MC_EXPECTED, expected, 0, 0);
1183 if (previous)
1184 *previous = iprv.v0;
1185 return iprv.status;
1186}
1187
1188/* Register a platform dependent location with PAL to which it can save
1189 * minimal processor state in the event of a machine check or initialization
1190 * event.
1191 */
1192static inline s64
1193ia64_pal_mc_register_mem (u64 physical_addr)
1194{
1195 struct ia64_pal_retval iprv;
1196 PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, 0, 0);
1197 return iprv.status;
1198}
1199
1200/* Restore minimal architectural processor state, set CMC interrupt if necessary
1201 * and resume execution
1202 */
1203static inline s64
1204ia64_pal_mc_resume (u64 set_cmci, u64 save_ptr)
1205{
1206 struct ia64_pal_retval iprv;
1207 PAL_CALL(iprv, PAL_MC_RESUME, set_cmci, save_ptr, 0);
1208 return iprv.status;
1209}
1210
1211/* Return the memory attributes implemented by the processor */
1212static inline s64
1213ia64_pal_mem_attrib (u64 *mem_attrib)
1214{
1215 struct ia64_pal_retval iprv;
1216 PAL_CALL(iprv, PAL_MEM_ATTRIB, 0, 0, 0);
1217 if (mem_attrib)
1218 *mem_attrib = iprv.v0 & 0xff;
1219 return iprv.status;
1220}
1221
1222/* Return the amount of memory needed for second phase of processor
1223 * self-test and the required alignment of memory.
1224 */
1225static inline s64
1226ia64_pal_mem_for_test (u64 *bytes_needed, u64 *alignment)
1227{
1228 struct ia64_pal_retval iprv;
1229 PAL_CALL(iprv, PAL_MEM_FOR_TEST, 0, 0, 0);
1230 if (bytes_needed)
1231 *bytes_needed = iprv.v0;
1232 if (alignment)
1233 *alignment = iprv.v1;
1234 return iprv.status;
1235}
1236
1237typedef union pal_perf_mon_info_u {
1238 u64 ppmi_data;
1239 struct {
1240 u64 generic : 8,
1241 width : 8,
1242 cycles : 8,
1243 retired : 8,
1244 reserved : 32;
1245 } pal_perf_mon_info_s;
1246} pal_perf_mon_info_u_t;
1247
1248/* Return the performance monitor information about what can be counted
1249 * and how to configure the monitors to count the desired events.
1250 */
1251static inline s64
1252ia64_pal_perf_mon_info (u64 *pm_buffer, pal_perf_mon_info_u_t *pm_info)
1253{
1254 struct ia64_pal_retval iprv;
1255 PAL_CALL(iprv, PAL_PERF_MON_INFO, (unsigned long) pm_buffer, 0, 0);
1256 if (pm_info)
1257 pm_info->ppmi_data = iprv.v0;
1258 return iprv.status;
1259}
1260
1261/* Specifies the physical address of the processor interrupt block
1262 * and I/O port space.
1263 */
1264static inline s64
1265ia64_pal_platform_addr (u64 type, u64 physical_addr)
1266{
1267 struct ia64_pal_retval iprv;
1268 PAL_CALL(iprv, PAL_PLATFORM_ADDR, type, physical_addr, 0);
1269 return iprv.status;
1270}
1271
1272/* Set the SAL PMI entrypoint in memory */
1273static inline s64
1274ia64_pal_pmi_entrypoint (u64 sal_pmi_entry_addr)
1275{
1276 struct ia64_pal_retval iprv;
1277 PAL_CALL(iprv, PAL_PMI_ENTRYPOINT, sal_pmi_entry_addr, 0, 0);
1278 return iprv.status;
1279}
1280
1281struct pal_features_s;
1282/* Provide information about configurable processor features */
1283static inline s64
1284ia64_pal_proc_get_features (u64 *features_avail,
1285 u64 *features_status,
1286 u64 *features_control)
1287{
1288 struct ia64_pal_retval iprv;
1289 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, 0, 0);
1290 if (iprv.status == 0) {
1291 *features_avail = iprv.v0;
1292 *features_status = iprv.v1;
1293 *features_control = iprv.v2;
1294 }
1295 return iprv.status;
1296}
1297
1298/* Enable/disable processor dependent features */
1299static inline s64
1300ia64_pal_proc_set_features (u64 feature_select)
1301{
1302 struct ia64_pal_retval iprv;
1303 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, feature_select, 0, 0);
1304 return iprv.status;
1305}
1306
1307/*
1308 * Put everything in a struct so we avoid the global offset table whenever
1309 * possible.
1310 */
1311typedef struct ia64_ptce_info_s {
1312 u64 base;
1313 u32 count[2];
1314 u32 stride[2];
1315} ia64_ptce_info_t;
1316
1317/* Return the information required for the architected loop used to purge
1318 * (initialize) the entire TC
1319 */
1320static inline s64
1321ia64_get_ptce (ia64_ptce_info_t *ptce)
1322{
1323 struct ia64_pal_retval iprv;
1324
1325 if (!ptce)
1326 return -1;
1327
1328 PAL_CALL(iprv, PAL_PTCE_INFO, 0, 0, 0);
1329 if (iprv.status == 0) {
1330 ptce->base = iprv.v0;
1331 ptce->count[0] = iprv.v1 >> 32;
1332 ptce->count[1] = iprv.v1 & 0xffffffff;
1333 ptce->stride[0] = iprv.v2 >> 32;
1334 ptce->stride[1] = iprv.v2 & 0xffffffff;
1335 }
1336 return iprv.status;
1337}
1338
1339/* Return info about implemented application and control registers. */
1340static inline s64
1341ia64_pal_register_info (u64 info_request, u64 *reg_info_1, u64 *reg_info_2)
1342{
1343 struct ia64_pal_retval iprv;
1344 PAL_CALL(iprv, PAL_REGISTER_INFO, info_request, 0, 0);
1345 if (reg_info_1)
1346 *reg_info_1 = iprv.v0;
1347 if (reg_info_2)
1348 *reg_info_2 = iprv.v1;
1349 return iprv.status;
1350}
1351
1352typedef union pal_hints_u {
1353 u64 ph_data;
1354 struct {
1355 u64 si : 1,
1356 li : 1,
1357 reserved : 62;
1358 } pal_hints_s;
1359} pal_hints_u_t;
1360
1361/* Return information about the register stack and RSE for this processor
1362 * implementation.
1363 */
1364static inline s64
1365ia64_pal_rse_info (u64 *num_phys_stacked, pal_hints_u_t *hints)
1366{
1367 struct ia64_pal_retval iprv;
1368 PAL_CALL(iprv, PAL_RSE_INFO, 0, 0, 0);
1369 if (num_phys_stacked)
1370 *num_phys_stacked = iprv.v0;
1371 if (hints)
1372 hints->ph_data = iprv.v1;
1373 return iprv.status;
1374}
1375
1376/* Cause the processor to enter SHUTDOWN state, where prefetching and execution are
1377 * suspended, but cause cache and TLB coherency to be maintained.
1378 * This is usually called in IA-32 mode.
1379 */
1380static inline s64
1381ia64_pal_shutdown (void)
1382{
1383 struct ia64_pal_retval iprv;
1384 PAL_CALL(iprv, PAL_SHUTDOWN, 0, 0, 0);
1385 return iprv.status;
1386}
1387
1388/* Perform the second phase of processor self-test. */
1389static inline s64
1390ia64_pal_test_proc (u64 test_addr, u64 test_size, u64 attributes, u64 *self_test_state)
1391{
1392 struct ia64_pal_retval iprv;
1393 PAL_CALL(iprv, PAL_TEST_PROC, test_addr, test_size, attributes);
1394 if (self_test_state)
1395 *self_test_state = iprv.v0;
1396 return iprv.status;
1397}
1398
1399typedef union pal_version_u {
1400 u64 pal_version_val;
1401 struct {
1402 u64 pv_pal_b_rev : 8;
1403 u64 pv_pal_b_model : 8;
1404 u64 pv_reserved1 : 8;
1405 u64 pv_pal_vendor : 8;
1406 u64 pv_pal_a_rev : 8;
1407 u64 pv_pal_a_model : 8;
1408 u64 pv_reserved2 : 16;
1409 } pal_version_s;
1410} pal_version_u_t;
1411
1412
1413/* Return PAL version information */
1414static inline s64
1415ia64_pal_version (pal_version_u_t *pal_min_version, pal_version_u_t *pal_cur_version)
1416{
1417 struct ia64_pal_retval iprv;
1418 PAL_CALL_PHYS(iprv, PAL_VERSION, 0, 0, 0);
1419 if (pal_min_version)
1420 pal_min_version->pal_version_val = iprv.v0;
1421
1422 if (pal_cur_version)
1423 pal_cur_version->pal_version_val = iprv.v1;
1424
1425 return iprv.status;
1426}
1427
1428typedef union pal_tc_info_u {
1429 u64 pti_val;
1430 struct {
1431 u64 num_sets : 8,
1432 associativity : 8,
1433 num_entries : 16,
1434 pf : 1,
1435 unified : 1,
1436 reduce_tr : 1,
1437 reserved : 29;
1438 } pal_tc_info_s;
1439} pal_tc_info_u_t;
1440
1441#define tc_reduce_tr pal_tc_info_s.reduce_tr
1442#define tc_unified pal_tc_info_s.unified
1443#define tc_pf pal_tc_info_s.pf
1444#define tc_num_entries pal_tc_info_s.num_entries
1445#define tc_associativity pal_tc_info_s.associativity
1446#define tc_num_sets pal_tc_info_s.num_sets
1447
1448
1449/* Return information about the virtual memory characteristics of the processor
1450 * implementation.
1451 */
1452static inline s64
1453ia64_pal_vm_info (u64 tc_level, u64 tc_type, pal_tc_info_u_t *tc_info, u64 *tc_pages)
1454{
1455 struct ia64_pal_retval iprv;
1456 PAL_CALL(iprv, PAL_VM_INFO, tc_level, tc_type, 0);
1457 if (tc_info)
1458 tc_info->pti_val = iprv.v0;
1459 if (tc_pages)
1460 *tc_pages = iprv.v1;
1461 return iprv.status;
1462}
1463
1464/* Get page size information about the virtual memory characteristics of the processor
1465 * implementation.
1466 */
1467static inline s64
1468ia64_pal_vm_page_size (u64 *tr_pages, u64 *vw_pages)
1469{
1470 struct ia64_pal_retval iprv;
1471 PAL_CALL(iprv, PAL_VM_PAGE_SIZE, 0, 0, 0);
1472 if (tr_pages)
1473 *tr_pages = iprv.v0;
1474 if (vw_pages)
1475 *vw_pages = iprv.v1;
1476 return iprv.status;
1477}
1478
1479typedef union pal_vm_info_1_u {
1480 u64 pvi1_val;
1481 struct {
1482 u64 vw : 1,
1483 phys_add_size : 7,
1484 key_size : 8,
1485 max_pkr : 8,
1486 hash_tag_id : 8,
1487 max_dtr_entry : 8,
1488 max_itr_entry : 8,
1489 max_unique_tcs : 8,
1490 num_tc_levels : 8;
1491 } pal_vm_info_1_s;
1492} pal_vm_info_1_u_t;
1493
1494typedef union pal_vm_info_2_u {
1495 u64 pvi2_val;
1496 struct {
1497 u64 impl_va_msb : 8,
1498 rid_size : 8,
1499 reserved : 48;
1500 } pal_vm_info_2_s;
1501} pal_vm_info_2_u_t;
1502
1503/* Get summary information about the virtual memory characteristics of the processor
1504 * implementation.
1505 */
1506static inline s64
1507ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2)
1508{
1509 struct ia64_pal_retval iprv;
1510 PAL_CALL(iprv, PAL_VM_SUMMARY, 0, 0, 0);
1511 if (vm_info_1)
1512 vm_info_1->pvi1_val = iprv.v0;
1513 if (vm_info_2)
1514 vm_info_2->pvi2_val = iprv.v1;
1515 return iprv.status;
1516}
1517
1518typedef union pal_itr_valid_u {
1519 u64 piv_val;
1520 struct {
1521 u64 access_rights_valid : 1,
1522 priv_level_valid : 1,
1523 dirty_bit_valid : 1,
1524 mem_attr_valid : 1,
1525 reserved : 60;
1526 } pal_tr_valid_s;
1527} pal_tr_valid_u_t;
1528
1529/* Read a translation register */
1530static inline s64
1531ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid)
1532{
1533 struct ia64_pal_retval iprv;
1534 PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)ia64_tpa(tr_buffer));
1535 if (tr_valid)
1536 tr_valid->piv_val = iprv.v0;
1537 return iprv.status;
1538}
1539
1540/*
1541 * PAL_PREFETCH_VISIBILITY transaction types
1542 */
1543#define PAL_VISIBILITY_VIRTUAL 0
1544#define PAL_VISIBILITY_PHYSICAL 1
1545
1546/*
1547 * PAL_PREFETCH_VISIBILITY return codes
1548 */
1549#define PAL_VISIBILITY_OK 1
1550#define PAL_VISIBILITY_OK_REMOTE_NEEDED 0
1551#define PAL_VISIBILITY_INVAL_ARG -2
1552#define PAL_VISIBILITY_ERROR -3
1553
1554static inline s64
1555ia64_pal_prefetch_visibility (s64 trans_type)
1556{
1557 struct ia64_pal_retval iprv;
1558 PAL_CALL(iprv, PAL_PREFETCH_VISIBILITY, trans_type, 0, 0);
1559 return iprv.status;
1560}
1561
1562#endif /* __ASSEMBLY__ */
1563
1564#endif /* _ASM_IA64_PAL_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 10:52:50 -0500