diff options
author | H. Peter Anvin <hpa@zytor.com> | 2007-07-11 15:18:29 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-07-12 13:55:54 -0400 |
commit | ec481536b15eb0520d8f0204b0294480050fe1f8 (patch) | |
tree | 3f959a26ca58477734ea1e4d5370b2d3a33a1680 /include/asm-i386 | |
parent | f8c09377d754f35a135454181b869ab527cc0757 (diff) |
Unify the CPU features vectors between i386 and x86-64
Unify the handling of the CPU features vectors between i386 and x86-64.
This also adopts the collapsing of features which are required at
compile-time into constant tests from x86-64 to i386.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'include/asm-i386')
-rw-r--r-- | include/asm-i386/cpufeature.h | 17 | ||||
-rw-r--r-- | include/asm-i386/required-features.h | 38 |
2 files changed, 41 insertions, 14 deletions
diff --git a/include/asm-i386/cpufeature.h b/include/asm-i386/cpufeature.h index f514e906643a..7ea5f4a6706f 100644 --- a/include/asm-i386/cpufeature.h +++ b/include/asm-i386/cpufeature.h | |||
@@ -81,6 +81,7 @@ | |||
81 | #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ | 81 | #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ |
82 | #define X86_FEATURE_LAPIC_TIMER_BROKEN (3*32+ 14) /* lapic timer broken in C1 */ | 82 | #define X86_FEATURE_LAPIC_TIMER_BROKEN (3*32+ 14) /* lapic timer broken in C1 */ |
83 | #define X86_FEATURE_SYNC_RDTSC (3*32+15) /* RDTSC synchronizes the CPU */ | 83 | #define X86_FEATURE_SYNC_RDTSC (3*32+15) /* RDTSC synchronizes the CPU */ |
84 | #define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */ | ||
84 | 85 | ||
85 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ | 86 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ |
86 | #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ | 87 | #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ |
@@ -108,11 +109,17 @@ | |||
108 | #define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */ | 109 | #define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */ |
109 | #define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */ | 110 | #define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */ |
110 | 111 | ||
111 | #define cpu_has(c, bit) \ | 112 | #define cpu_has(c, bit) \ |
112 | ((__builtin_constant_p(bit) && (bit) < 32 && \ | 113 | (__builtin_constant_p(bit) && \ |
113 | (1UL << (bit)) & REQUIRED_MASK1) ? \ | 114 | ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) || \ |
114 | 1 : \ | 115 | (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) || \ |
115 | test_bit(bit, (c)->x86_capability)) | 116 | (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) || \ |
117 | (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) || \ | ||
118 | (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) || \ | ||
119 | (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) || \ | ||
120 | (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) ) \ | ||
121 | ? 1 : \ | ||
122 | test_bit(bit, (c)->x86_capability)) | ||
116 | #define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit) | 123 | #define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit) |
117 | 124 | ||
118 | #define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU) | 125 | #define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU) |
diff --git a/include/asm-i386/required-features.h b/include/asm-i386/required-features.h index 9db866c1e64c..a9c3b1147bd0 100644 --- a/include/asm-i386/required-features.h +++ b/include/asm-i386/required-features.h | |||
@@ -3,32 +3,52 @@ | |||
3 | 3 | ||
4 | /* Define minimum CPUID feature set for kernel These bits are checked | 4 | /* Define minimum CPUID feature set for kernel These bits are checked |
5 | really early to actually display a visible error message before the | 5 | really early to actually display a visible error message before the |
6 | kernel dies. Only add word 0 bits here | 6 | kernel dies. Make sure to assign features to the proper mask! |
7 | 7 | ||
8 | Some requirements that are not in CPUID yet are also in the | 8 | Some requirements that are not in CPUID yet are also in the |
9 | CONFIG_X86_MINIMUM_CPU mode which is checked too. | 9 | CONFIG_X86_MINIMUM_CPU_FAMILY which is checked too. |
10 | 10 | ||
11 | The real information is in arch/i386/Kconfig.cpu, this just converts | 11 | The real information is in arch/i386/Kconfig.cpu, this just converts |
12 | the CONFIGs into a bitmask */ | 12 | the CONFIGs into a bitmask */ |
13 | 13 | ||
14 | #ifndef CONFIG_MATH_EMULATION | ||
15 | # define NEED_FPU (1<<(X86_FEATURE_FPU & 31)) | ||
16 | #else | ||
17 | # define NEED_FPU 0 | ||
18 | #endif | ||
19 | |||
14 | #ifdef CONFIG_X86_PAE | 20 | #ifdef CONFIG_X86_PAE |
15 | #define NEED_PAE (1<<X86_FEATURE_PAE) | 21 | # define NEED_PAE (1<<(X86_FEATURE_PAE & 31)) |
16 | #else | 22 | #else |
17 | #define NEED_PAE 0 | 23 | # define NEED_PAE 0 |
18 | #endif | 24 | #endif |
19 | 25 | ||
20 | #ifdef CONFIG_X86_CMOV | 26 | #ifdef CONFIG_X86_CMOV |
21 | #define NEED_CMOV (1<<X86_FEATURE_CMOV) | 27 | # define NEED_CMOV (1<<(X86_FEATURE_CMOV & 31)) |
22 | #else | 28 | #else |
23 | #define NEED_CMOV 0 | 29 | # define NEED_CMOV 0 |
24 | #endif | 30 | #endif |
25 | 31 | ||
26 | #ifdef CONFIG_X86_CMPXCHG64 | 32 | #ifdef CONFIG_X86_CMPXCHG64 |
27 | #define NEED_CMPXCHG64 (1<<X86_FEATURE_CX8) | 33 | # define NEED_CX8 (1<<(X86_FEATURE_CX8 & 31)) |
34 | #else | ||
35 | # define NEED_CX8 0 | ||
36 | #endif | ||
37 | |||
38 | #define REQUIRED_MASK0 (NEED_FPU|NEED_PAE|NEED_CMOV|NEED_CX8) | ||
39 | |||
40 | #ifdef CONFIG_X86_USE_3DNOW | ||
41 | # define NEED_3DNOW (1<<(X86_FEATURE_3DNOW & 31)) | ||
28 | #else | 42 | #else |
29 | #define NEED_CMPXCHG64 0 | 43 | # define NEED_3DNOW 0 |
30 | #endif | 44 | #endif |
31 | 45 | ||
32 | #define REQUIRED_MASK1 (NEED_PAE|NEED_CMOV|NEED_CMPXCHG64) | 46 | #define REQUIRED_MASK1 (NEED_3DNOW) |
47 | |||
48 | #define REQUIRED_MASK2 0 | ||
49 | #define REQUIRED_MASK3 0 | ||
50 | #define REQUIRED_MASK4 0 | ||
51 | #define REQUIRED_MASK5 0 | ||
52 | #define REQUIRED_MASK6 0 | ||
33 | 53 | ||
34 | #endif | 54 | #endif |