diff options
author | Jeremy Fitzhardinge <jeremy@goop.org> | 2007-05-02 13:27:15 -0400 |
---|---|---|
committer | Andi Kleen <andi@basil.nowhere.org> | 2007-05-02 13:27:15 -0400 |
commit | d4c104771a1c58e3de2a888b73b0ba1b54c0ae76 (patch) | |
tree | 77ca2c6771e946aa926cb21c06702fdc7d230364 /include/asm-i386/tlbflush.h | |
parent | 63f70270ccd981ce40a8ff58c03a8c2e97e368be (diff) |
[PATCH] i386: PARAVIRT: add flush_tlb_others paravirt_op
This patch adds a pv_op for flush_tlb_others. Linux running on native
hardware uses cross-CPU IPIs to flush the TLB on any CPU which may
have a particular mm's pagetable entries cached in its TLB. This is
inefficient in a paravirtualized environment, since the hypervisor
knows which real CPUs actually contain cached mappings, which may be a
small subset of a guest's VCPUs.
Signed-off-by: Jeremy Fitzhardinge <jeremy@xensource.com>
Signed-off-by: Andi Kleen <ak@suse.de>
Diffstat (limited to 'include/asm-i386/tlbflush.h')
-rw-r--r-- | include/asm-i386/tlbflush.h | 19 |
1 files changed, 17 insertions, 2 deletions
diff --git a/include/asm-i386/tlbflush.h b/include/asm-i386/tlbflush.h index 4dd82840d53b..db7f77eacfa0 100644 --- a/include/asm-i386/tlbflush.h +++ b/include/asm-i386/tlbflush.h | |||
@@ -79,11 +79,15 @@ | |||
79 | * - flush_tlb_range(vma, start, end) flushes a range of pages | 79 | * - flush_tlb_range(vma, start, end) flushes a range of pages |
80 | * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages | 80 | * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages |
81 | * - flush_tlb_pgtables(mm, start, end) flushes a range of page tables | 81 | * - flush_tlb_pgtables(mm, start, end) flushes a range of page tables |
82 | * - flush_tlb_others(cpumask, mm, va) flushes a TLBs on other cpus | ||
82 | * | 83 | * |
83 | * ..but the i386 has somewhat limited tlb flushing capabilities, | 84 | * ..but the i386 has somewhat limited tlb flushing capabilities, |
84 | * and page-granular flushes are available only on i486 and up. | 85 | * and page-granular flushes are available only on i486 and up. |
85 | */ | 86 | */ |
86 | 87 | ||
88 | #define TLB_FLUSH_ALL 0xffffffff | ||
89 | |||
90 | |||
87 | #ifndef CONFIG_SMP | 91 | #ifndef CONFIG_SMP |
88 | 92 | ||
89 | #define flush_tlb() __flush_tlb() | 93 | #define flush_tlb() __flush_tlb() |
@@ -110,7 +114,12 @@ static inline void flush_tlb_range(struct vm_area_struct *vma, | |||
110 | __flush_tlb(); | 114 | __flush_tlb(); |
111 | } | 115 | } |
112 | 116 | ||
113 | #else | 117 | static inline void native_flush_tlb_others(const cpumask_t *cpumask, |
118 | struct mm_struct *mm, unsigned long va) | ||
119 | { | ||
120 | } | ||
121 | |||
122 | #else /* SMP */ | ||
114 | 123 | ||
115 | #include <asm/smp.h> | 124 | #include <asm/smp.h> |
116 | 125 | ||
@@ -129,6 +138,9 @@ static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long st | |||
129 | flush_tlb_mm(vma->vm_mm); | 138 | flush_tlb_mm(vma->vm_mm); |
130 | } | 139 | } |
131 | 140 | ||
141 | void native_flush_tlb_others(const cpumask_t *cpumask, struct mm_struct *mm, | ||
142 | unsigned long va); | ||
143 | |||
132 | #define TLBSTATE_OK 1 | 144 | #define TLBSTATE_OK 1 |
133 | #define TLBSTATE_LAZY 2 | 145 | #define TLBSTATE_LAZY 2 |
134 | 146 | ||
@@ -139,8 +151,11 @@ struct tlb_state | |||
139 | char __cacheline_padding[L1_CACHE_BYTES-8]; | 151 | char __cacheline_padding[L1_CACHE_BYTES-8]; |
140 | }; | 152 | }; |
141 | DECLARE_PER_CPU(struct tlb_state, cpu_tlbstate); | 153 | DECLARE_PER_CPU(struct tlb_state, cpu_tlbstate); |
154 | #endif /* SMP */ | ||
142 | 155 | ||
143 | 156 | #ifndef CONFIG_PARAVIRT | |
157 | #define flush_tlb_others(mask, mm, va) \ | ||
158 | native_flush_tlb_others(&mask, mm, va) | ||
144 | #endif | 159 | #endif |
145 | 160 | ||
146 | #define flush_tlb_kernel_range(start, end) flush_tlb_all() | 161 | #define flush_tlb_kernel_range(start, end) flush_tlb_all() |