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authorSiddha, Suresh B <suresh.b.siddha@intel.com>2005-10-30 17:59:30 -0500
committerLinus Torvalds <torvalds@g5.osdl.org>2005-10-30 20:37:11 -0500
commitd16aafff2570abb557a5cb18c98027aabd602e22 (patch)
treeb2ce02548c87f162cbae7071b0195505d355bbb1 /include/asm-i386/pgtable-3level.h
parentd5cd4aadd3d220afac8e3e6d922e333592551f7d (diff)
[PATCH] intel_cacheinfo: remove MAX_CACHE_LEAVES limit
Initial internal version of Venki's cpuid(4) deterministic cache parameter identification patch used static arrays of size MAX_CACHE_LEAVES. Final patch which made to the base used dynamic array allocation, with this MAX_CACHE_LEAVES limit hunk still in place. cpuid(4) already has a mechanism to find out the number of cache levels implemented and there is no need for this hardcoded MAX_CACHE_LEAVES limit. So remove the MAX_CACHE_LEAVES limit from the routine which calculates the number of cache levels using cpuid(4) Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Cc: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-i386/pgtable-3level.h')
0 files changed, 0 insertions, 0 deletions