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author | Linus Torvalds <torvalds@woody.osdl.org> | 2006-12-07 11:59:11 -0500 |
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committer | Linus Torvalds <torvalds@woody.osdl.org> | 2006-12-07 11:59:11 -0500 |
commit | 4522d58275f124105819723e24e912c8e5bf3cdd (patch) | |
tree | b92c29014fadffe049c1925676037f0092b8d112 /include/asm-i386/msr.h | |
parent | 6cf24f031bc97cb5a7c9df3b6e73c45b628b2b28 (diff) | |
parent | 64a26a731235b59c9d73bbe82c1f896d57400d37 (diff) |
Merge branch 'for-linus' of git://one.firstfloor.org/home/andi/git/linux-2.6
* 'for-linus' of git://one.firstfloor.org/home/andi/git/linux-2.6: (156 commits)
[PATCH] x86-64: Export smp_call_function_single
[PATCH] i386: Clean up smp_tune_scheduling()
[PATCH] unwinder: move .eh_frame to RODATA
[PATCH] unwinder: fully support linker generated .eh_frame_hdr section
[PATCH] x86-64: don't use set_irq_regs()
[PATCH] x86-64: check vector in setup_ioapic_dest to verify if need setup_IO_APIC_irq
[PATCH] x86-64: Make ix86 default to HIGHMEM4G instead of NOHIGHMEM
[PATCH] i386: replace kmalloc+memset with kzalloc
[PATCH] x86-64: remove remaining pc98 code
[PATCH] x86-64: remove unused variable
[PATCH] x86-64: Fix constraints in atomic_add_return()
[PATCH] x86-64: fix asm constraints in i386 atomic_add_return
[PATCH] x86-64: Correct documentation for bzImage protocol v2.05
[PATCH] x86-64: replace kmalloc+memset with kzalloc in MTRR code
[PATCH] x86-64: Fix numaq build error
[PATCH] x86-64: include/asm-x86_64/cpufeature.h isn't a userspace header
[PATCH] unwinder: Add debugging output to the Dwarf2 unwinder
[PATCH] x86-64: Clarify error message in GART code
[PATCH] x86-64: Fix interrupt race in idle callback (3rd try)
[PATCH] x86-64: Remove unwind stack pointer alignment forcing again
...
Fixed conflict in include/linux/uaccess.h manually
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-i386/msr.h')
-rw-r--r-- | include/asm-i386/msr.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/include/asm-i386/msr.h b/include/asm-i386/msr.h index 62b76cd96957..5679d4993072 100644 --- a/include/asm-i386/msr.h +++ b/include/asm-i386/msr.h | |||
@@ -1,6 +1,10 @@ | |||
1 | #ifndef __ASM_MSR_H | 1 | #ifndef __ASM_MSR_H |
2 | #define __ASM_MSR_H | 2 | #define __ASM_MSR_H |
3 | 3 | ||
4 | #ifdef CONFIG_PARAVIRT | ||
5 | #include <asm/paravirt.h> | ||
6 | #else | ||
7 | |||
4 | /* | 8 | /* |
5 | * Access to machine-specific registers (available on 586 and better only) | 9 | * Access to machine-specific registers (available on 586 and better only) |
6 | * Note: the rd* operations modify the parameters directly (without using | 10 | * Note: the rd* operations modify the parameters directly (without using |
@@ -77,6 +81,7 @@ static inline void wrmsrl (unsigned long msr, unsigned long long val) | |||
77 | __asm__ __volatile__("rdpmc" \ | 81 | __asm__ __volatile__("rdpmc" \ |
78 | : "=a" (low), "=d" (high) \ | 82 | : "=a" (low), "=d" (high) \ |
79 | : "c" (counter)) | 83 | : "c" (counter)) |
84 | #endif /* !CONFIG_PARAVIRT */ | ||
80 | 85 | ||
81 | /* symbolic names for some interesting MSRs */ | 86 | /* symbolic names for some interesting MSRs */ |
82 | /* Intel defined MSRs. */ | 87 | /* Intel defined MSRs. */ |
@@ -141,6 +146,10 @@ static inline void wrmsrl (unsigned long msr, unsigned long long val) | |||
141 | #define MSR_IA32_MC0_ADDR 0x402 | 146 | #define MSR_IA32_MC0_ADDR 0x402 |
142 | #define MSR_IA32_MC0_MISC 0x403 | 147 | #define MSR_IA32_MC0_MISC 0x403 |
143 | 148 | ||
149 | #define MSR_IA32_PEBS_ENABLE 0x3f1 | ||
150 | #define MSR_IA32_DS_AREA 0x600 | ||
151 | #define MSR_IA32_PERF_CAPABILITIES 0x345 | ||
152 | |||
144 | /* Pentium IV performance counter MSRs */ | 153 | /* Pentium IV performance counter MSRs */ |
145 | #define MSR_P4_BPU_PERFCTR0 0x300 | 154 | #define MSR_P4_BPU_PERFCTR0 0x300 |
146 | #define MSR_P4_BPU_PERFCTR1 0x301 | 155 | #define MSR_P4_BPU_PERFCTR1 0x301 |
@@ -284,4 +293,13 @@ static inline void wrmsrl (unsigned long msr, unsigned long long val) | |||
284 | #define MSR_TMTA_LRTI_READOUT 0x80868018 | 293 | #define MSR_TMTA_LRTI_READOUT 0x80868018 |
285 | #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a | 294 | #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a |
286 | 295 | ||
296 | /* Intel Core-based CPU performance counters */ | ||
297 | #define MSR_CORE_PERF_FIXED_CTR0 0x309 | ||
298 | #define MSR_CORE_PERF_FIXED_CTR1 0x30a | ||
299 | #define MSR_CORE_PERF_FIXED_CTR2 0x30b | ||
300 | #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d | ||
301 | #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e | ||
302 | #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f | ||
303 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 | ||
304 | |||
287 | #endif /* __ASM_MSR_H */ | 305 | #endif /* __ASM_MSR_H */ |