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authorDave Jones <davej@redhat.com>2006-12-12 17:41:41 -0500
committerDave Jones <davej@redhat.com>2006-12-12 17:41:41 -0500
commitc4366889dda8110247be59ca41fddb82951a8c26 (patch)
tree705c1a996bed8fd48ce94ff33ec9fd00f9b94875 /include/asm-i386/msr.h
parentdb2fb9db5735cc532fd4fc55e94b9a3c3750378e (diff)
parente1036502e5263851259d147771226161e5ccc85a (diff)
Merge ../linus
Conflicts: drivers/cpufreq/cpufreq.c
Diffstat (limited to 'include/asm-i386/msr.h')
-rw-r--r--include/asm-i386/msr.h18
1 files changed, 18 insertions, 0 deletions
diff --git a/include/asm-i386/msr.h b/include/asm-i386/msr.h
index 8c31887e1cfa..609a3899475c 100644
--- a/include/asm-i386/msr.h
+++ b/include/asm-i386/msr.h
@@ -1,6 +1,10 @@
1#ifndef __ASM_MSR_H 1#ifndef __ASM_MSR_H
2#define __ASM_MSR_H 2#define __ASM_MSR_H
3 3
4#ifdef CONFIG_PARAVIRT
5#include <asm/paravirt.h>
6#else
7
4/* 8/*
5 * Access to machine-specific registers (available on 586 and better only) 9 * Access to machine-specific registers (available on 586 and better only)
6 * Note: the rd* operations modify the parameters directly (without using 10 * Note: the rd* operations modify the parameters directly (without using
@@ -77,6 +81,7 @@ static inline void wrmsrl (unsigned long msr, unsigned long long val)
77 __asm__ __volatile__("rdpmc" \ 81 __asm__ __volatile__("rdpmc" \
78 : "=a" (low), "=d" (high) \ 82 : "=a" (low), "=d" (high) \
79 : "c" (counter)) 83 : "c" (counter))
84#endif /* !CONFIG_PARAVIRT */
80 85
81/* symbolic names for some interesting MSRs */ 86/* symbolic names for some interesting MSRs */
82/* Intel defined MSRs. */ 87/* Intel defined MSRs. */
@@ -146,6 +151,10 @@ static inline void wrmsrl (unsigned long msr, unsigned long long val)
146#define MSR_IA32_MC0_ADDR 0x402 151#define MSR_IA32_MC0_ADDR 0x402
147#define MSR_IA32_MC0_MISC 0x403 152#define MSR_IA32_MC0_MISC 0x403
148 153
154#define MSR_IA32_PEBS_ENABLE 0x3f1
155#define MSR_IA32_DS_AREA 0x600
156#define MSR_IA32_PERF_CAPABILITIES 0x345
157
149/* Pentium IV performance counter MSRs */ 158/* Pentium IV performance counter MSRs */
150#define MSR_P4_BPU_PERFCTR0 0x300 159#define MSR_P4_BPU_PERFCTR0 0x300
151#define MSR_P4_BPU_PERFCTR1 0x301 160#define MSR_P4_BPU_PERFCTR1 0x301
@@ -289,4 +298,13 @@ static inline void wrmsrl (unsigned long msr, unsigned long long val)
289#define MSR_TMTA_LRTI_READOUT 0x80868018 298#define MSR_TMTA_LRTI_READOUT 0x80868018
290#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 299#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
291 300
301/* Intel Core-based CPU performance counters */
302#define MSR_CORE_PERF_FIXED_CTR0 0x309
303#define MSR_CORE_PERF_FIXED_CTR1 0x30a
304#define MSR_CORE_PERF_FIXED_CTR2 0x30b
305#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d
306#define MSR_CORE_PERF_GLOBAL_STATUS 0x38e
307#define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
308#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390
309
292#endif /* __ASM_MSR_H */ 310#endif /* __ASM_MSR_H */