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authorH. Peter Anvin <hpa@zytor.com>2007-05-02 13:27:12 -0400
committerAndi Kleen <andi@basil.nowhere.org>2007-05-02 13:27:12 -0400
commit4bc5aa91fb1e544ad37805520030a0d9fc6e11d3 (patch)
tree207870aad2f53fcec914ea5084de4fdfe1a02a23 /include/asm-i386/msr-index.h
parentb6e3590f8145c77b8fcef3247e2412335221412f (diff)
[PATCH] x86: Clean up x86 control register and MSR macros (corrected)
This patch is based on Rusty's recent cleanup of the EFLAGS-related macros; it extends the same kind of cleanup to control registers and MSRs. It also unifies these between i386 and x86-64; at least with regards to MSRs, the two had definitely gotten out of sync. Signed-off-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Andi Kleen <ak@suse.de>
Diffstat (limited to 'include/asm-i386/msr-index.h')
-rw-r--r--include/asm-i386/msr-index.h273
1 files changed, 273 insertions, 0 deletions
diff --git a/include/asm-i386/msr-index.h b/include/asm-i386/msr-index.h
new file mode 100644
index 000000000000..f1190802283d
--- /dev/null
+++ b/include/asm-i386/msr-index.h
@@ -0,0 +1,273 @@
1#ifndef __ASM_MSR_INDEX_H
2#define __ASM_MSR_INDEX_H
3
4/* CPU model specific register (MSR) numbers */
5
6/* x86-64 specific MSRs */
7#define MSR_EFER 0xc0000080 /* extended feature register */
8#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
9#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
10#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
11#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
12#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
13#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
14#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
15
16/* EFER bits: */
17#define _EFER_SCE 0 /* SYSCALL/SYSRET */
18#define _EFER_LME 8 /* Long mode enable */
19#define _EFER_LMA 10 /* Long mode active (read-only) */
20#define _EFER_NX 11 /* No execute enable */
21
22#define EFER_SCE (1<<_EFER_SCE)
23#define EFER_LME (1<<_EFER_LME)
24#define EFER_LMA (1<<_EFER_LMA)
25#define EFER_NX (1<<_EFER_NX)
26
27/* Intel MSRs. Some also available on other CPUs */
28#define MSR_IA32_PERFCTR0 0x000000c1
29#define MSR_IA32_PERFCTR1 0x000000c2
30#define MSR_FSB_FREQ 0x000000cd
31
32#define MSR_MTRRcap 0x000000fe
33#define MSR_IA32_BBL_CR_CTL 0x00000119
34
35#define MSR_IA32_SYSENTER_CS 0x00000174
36#define MSR_IA32_SYSENTER_ESP 0x00000175
37#define MSR_IA32_SYSENTER_EIP 0x00000176
38
39#define MSR_IA32_MCG_CAP 0x00000179
40#define MSR_IA32_MCG_STATUS 0x0000017a
41#define MSR_IA32_MCG_CTL 0x0000017b
42
43#define MSR_IA32_PEBS_ENABLE 0x000003f1
44#define MSR_IA32_DS_AREA 0x00000600
45#define MSR_IA32_PERF_CAPABILITIES 0x00000345
46
47#define MSR_MTRRfix64K_00000 0x00000250
48#define MSR_MTRRfix16K_80000 0x00000258
49#define MSR_MTRRfix16K_A0000 0x00000259
50#define MSR_MTRRfix4K_C0000 0x00000268
51#define MSR_MTRRfix4K_C8000 0x00000269
52#define MSR_MTRRfix4K_D0000 0x0000026a
53#define MSR_MTRRfix4K_D8000 0x0000026b
54#define MSR_MTRRfix4K_E0000 0x0000026c
55#define MSR_MTRRfix4K_E8000 0x0000026d
56#define MSR_MTRRfix4K_F0000 0x0000026e
57#define MSR_MTRRfix4K_F8000 0x0000026f
58#define MSR_MTRRdefType 0x000002ff
59
60#define MSR_IA32_DEBUGCTLMSR 0x000001d9
61#define MSR_IA32_LASTBRANCHFROMIP 0x000001db
62#define MSR_IA32_LASTBRANCHTOIP 0x000001dc
63#define MSR_IA32_LASTINTFROMIP 0x000001dd
64#define MSR_IA32_LASTINTTOIP 0x000001de
65
66#define MSR_IA32_MC0_CTL 0x00000400
67#define MSR_IA32_MC0_STATUS 0x00000401
68#define MSR_IA32_MC0_ADDR 0x00000402
69#define MSR_IA32_MC0_MISC 0x00000403
70
71#define MSR_P6_PERFCTR0 0x000000c1
72#define MSR_P6_PERFCTR1 0x000000c2
73#define MSR_P6_EVNTSEL0 0x00000186
74#define MSR_P6_EVNTSEL1 0x00000187
75
76/* K7/K8 MSRs. Not complete. See the architecture manual for a more
77 complete list. */
78#define MSR_K7_EVNTSEL0 0xc0010000
79#define MSR_K7_PERFCTR0 0xc0010004
80#define MSR_K7_EVNTSEL1 0xc0010001
81#define MSR_K7_PERFCTR1 0xc0010005
82#define MSR_K7_EVNTSEL2 0xc0010002
83#define MSR_K7_PERFCTR2 0xc0010006
84#define MSR_K7_EVNTSEL3 0xc0010003
85#define MSR_K7_PERFCTR3 0xc0010007
86#define MSR_K8_TOP_MEM1 0xc001001a
87#define MSR_K7_CLK_CTL 0xc001001b
88#define MSR_K8_TOP_MEM2 0xc001001d
89#define MSR_K8_SYSCFG 0xc0010010
90#define MSR_K7_HWCR 0xc0010015
91#define MSR_K8_HWCR 0xc0010015
92#define MSR_K7_FID_VID_CTL 0xc0010041
93#define MSR_K7_FID_VID_STATUS 0xc0010042
94#define MSR_K8_ENABLE_C1E 0xc0010055
95
96/* K6 MSRs */
97#define MSR_K6_EFER 0xc0000080
98#define MSR_K6_STAR 0xc0000081
99#define MSR_K6_WHCR 0xc0000082
100#define MSR_K6_UWCCR 0xc0000085
101#define MSR_K6_EPMR 0xc0000086
102#define MSR_K6_PSOR 0xc0000087
103#define MSR_K6_PFIR 0xc0000088
104
105/* Centaur-Hauls/IDT defined MSRs. */
106#define MSR_IDT_FCR1 0x00000107
107#define MSR_IDT_FCR2 0x00000108
108#define MSR_IDT_FCR3 0x00000109
109#define MSR_IDT_FCR4 0x0000010a
110
111#define MSR_IDT_MCR0 0x00000110
112#define MSR_IDT_MCR1 0x00000111
113#define MSR_IDT_MCR2 0x00000112
114#define MSR_IDT_MCR3 0x00000113
115#define MSR_IDT_MCR4 0x00000114
116#define MSR_IDT_MCR5 0x00000115
117#define MSR_IDT_MCR6 0x00000116
118#define MSR_IDT_MCR7 0x00000117
119#define MSR_IDT_MCR_CTRL 0x00000120
120
121/* VIA Cyrix defined MSRs*/
122#define MSR_VIA_FCR 0x00001107
123#define MSR_VIA_LONGHAUL 0x0000110a
124#define MSR_VIA_RNG 0x0000110b
125#define MSR_VIA_BCR2 0x00001147
126
127/* Transmeta defined MSRs */
128#define MSR_TMTA_LONGRUN_CTRL 0x80868010
129#define MSR_TMTA_LONGRUN_FLAGS 0x80868011
130#define MSR_TMTA_LRTI_READOUT 0x80868018
131#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
132
133/* Intel defined MSRs. */
134#define MSR_IA32_P5_MC_ADDR 0x00000000
135#define MSR_IA32_P5_MC_TYPE 0x00000001
136#define MSR_IA32_TSC 0x00000010
137#define MSR_IA32_PLATFORM_ID 0x00000017
138#define MSR_IA32_EBL_CR_POWERON 0x0000002a
139
140#define MSR_IA32_APICBASE 0x0000001b
141#define MSR_IA32_APICBASE_BSP (1<<8)
142#define MSR_IA32_APICBASE_ENABLE (1<<11)
143#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
144
145#define MSR_IA32_UCODE_WRITE 0x00000079
146#define MSR_IA32_UCODE_REV 0x0000008b
147
148#define MSR_IA32_PERF_STATUS 0x00000198
149#define MSR_IA32_PERF_CTL 0x00000199
150
151#define MSR_IA32_MPERF 0x000000e7
152#define MSR_IA32_APERF 0x000000e8
153
154#define MSR_IA32_THERM_CONTROL 0x0000019a
155#define MSR_IA32_THERM_INTERRUPT 0x0000019b
156#define MSR_IA32_THERM_STATUS 0x0000019c
157#define MSR_IA32_MISC_ENABLE 0x000001a0
158
159/* Intel Model 6 */
160#define MSR_P6_EVNTSEL0 0x00000186
161#define MSR_P6_EVNTSEL1 0x00000187
162
163/* P4/Xeon+ specific */
164#define MSR_IA32_MCG_EAX 0x00000180
165#define MSR_IA32_MCG_EBX 0x00000181
166#define MSR_IA32_MCG_ECX 0x00000182
167#define MSR_IA32_MCG_EDX 0x00000183
168#define MSR_IA32_MCG_ESI 0x00000184
169#define MSR_IA32_MCG_EDI 0x00000185
170#define MSR_IA32_MCG_EBP 0x00000186
171#define MSR_IA32_MCG_ESP 0x00000187
172#define MSR_IA32_MCG_EFLAGS 0x00000188
173#define MSR_IA32_MCG_EIP 0x00000189
174#define MSR_IA32_MCG_RESERVED 0x0000018a
175
176/* Pentium IV performance counter MSRs */
177#define MSR_P4_BPU_PERFCTR0 0x00000300
178#define MSR_P4_BPU_PERFCTR1 0x00000301
179#define MSR_P4_BPU_PERFCTR2 0x00000302
180#define MSR_P4_BPU_PERFCTR3 0x00000303
181#define MSR_P4_MS_PERFCTR0 0x00000304
182#define MSR_P4_MS_PERFCTR1 0x00000305
183#define MSR_P4_MS_PERFCTR2 0x00000306
184#define MSR_P4_MS_PERFCTR3 0x00000307
185#define MSR_P4_FLAME_PERFCTR0 0x00000308
186#define MSR_P4_FLAME_PERFCTR1 0x00000309
187#define MSR_P4_FLAME_PERFCTR2 0x0000030a
188#define MSR_P4_FLAME_PERFCTR3 0x0000030b
189#define MSR_P4_IQ_PERFCTR0 0x0000030c
190#define MSR_P4_IQ_PERFCTR1 0x0000030d
191#define MSR_P4_IQ_PERFCTR2 0x0000030e
192#define MSR_P4_IQ_PERFCTR3 0x0000030f
193#define MSR_P4_IQ_PERFCTR4 0x00000310
194#define MSR_P4_IQ_PERFCTR5 0x00000311
195#define MSR_P4_BPU_CCCR0 0x00000360
196#define MSR_P4_BPU_CCCR1 0x00000361
197#define MSR_P4_BPU_CCCR2 0x00000362
198#define MSR_P4_BPU_CCCR3 0x00000363
199#define MSR_P4_MS_CCCR0 0x00000364
200#define MSR_P4_MS_CCCR1 0x00000365
201#define MSR_P4_MS_CCCR2 0x00000366
202#define MSR_P4_MS_CCCR3 0x00000367
203#define MSR_P4_FLAME_CCCR0 0x00000368
204#define MSR_P4_FLAME_CCCR1 0x00000369
205#define MSR_P4_FLAME_CCCR2 0x0000036a
206#define MSR_P4_FLAME_CCCR3 0x0000036b
207#define MSR_P4_IQ_CCCR0 0x0000036c
208#define MSR_P4_IQ_CCCR1 0x0000036d
209#define MSR_P4_IQ_CCCR2 0x0000036e
210#define MSR_P4_IQ_CCCR3 0x0000036f
211#define MSR_P4_IQ_CCCR4 0x00000370
212#define MSR_P4_IQ_CCCR5 0x00000371
213#define MSR_P4_ALF_ESCR0 0x000003ca
214#define MSR_P4_ALF_ESCR1 0x000003cb
215#define MSR_P4_BPU_ESCR0 0x000003b2
216#define MSR_P4_BPU_ESCR1 0x000003b3
217#define MSR_P4_BSU_ESCR0 0x000003a0
218#define MSR_P4_BSU_ESCR1 0x000003a1
219#define MSR_P4_CRU_ESCR0 0x000003b8
220#define MSR_P4_CRU_ESCR1 0x000003b9
221#define MSR_P4_CRU_ESCR2 0x000003cc
222#define MSR_P4_CRU_ESCR3 0x000003cd
223#define MSR_P4_CRU_ESCR4 0x000003e0
224#define MSR_P4_CRU_ESCR5 0x000003e1
225#define MSR_P4_DAC_ESCR0 0x000003a8
226#define MSR_P4_DAC_ESCR1 0x000003a9
227#define MSR_P4_FIRM_ESCR0 0x000003a4
228#define MSR_P4_FIRM_ESCR1 0x000003a5
229#define MSR_P4_FLAME_ESCR0 0x000003a6
230#define MSR_P4_FLAME_ESCR1 0x000003a7
231#define MSR_P4_FSB_ESCR0 0x000003a2
232#define MSR_P4_FSB_ESCR1 0x000003a3
233#define MSR_P4_IQ_ESCR0 0x000003ba
234#define MSR_P4_IQ_ESCR1 0x000003bb
235#define MSR_P4_IS_ESCR0 0x000003b4
236#define MSR_P4_IS_ESCR1 0x000003b5
237#define MSR_P4_ITLB_ESCR0 0x000003b6
238#define MSR_P4_ITLB_ESCR1 0x000003b7
239#define MSR_P4_IX_ESCR0 0x000003c8
240#define MSR_P4_IX_ESCR1 0x000003c9
241#define MSR_P4_MOB_ESCR0 0x000003aa
242#define MSR_P4_MOB_ESCR1 0x000003ab
243#define MSR_P4_MS_ESCR0 0x000003c0
244#define MSR_P4_MS_ESCR1 0x000003c1
245#define MSR_P4_PMH_ESCR0 0x000003ac
246#define MSR_P4_PMH_ESCR1 0x000003ad
247#define MSR_P4_RAT_ESCR0 0x000003bc
248#define MSR_P4_RAT_ESCR1 0x000003bd
249#define MSR_P4_SAAT_ESCR0 0x000003ae
250#define MSR_P4_SAAT_ESCR1 0x000003af
251#define MSR_P4_SSU_ESCR0 0x000003be
252#define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */
253
254#define MSR_P4_TBPU_ESCR0 0x000003c2
255#define MSR_P4_TBPU_ESCR1 0x000003c3
256#define MSR_P4_TC_ESCR0 0x000003c4
257#define MSR_P4_TC_ESCR1 0x000003c5
258#define MSR_P4_U2L_ESCR0 0x000003b0
259#define MSR_P4_U2L_ESCR1 0x000003b1
260
261/* Intel Core-based CPU performance counters */
262#define MSR_CORE_PERF_FIXED_CTR0 0x00000309
263#define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
264#define MSR_CORE_PERF_FIXED_CTR2 0x0000030b
265#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d
266#define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e
267#define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f
268#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390
269
270/* Geode defined MSRs */
271#define MSR_GEODE_BUSCONT_CONF0 0x00001900
272
273#endif /* __ASM_MSR_INDEX_H */