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authorStephane Eranian <eranian@hpl.hp.com>2006-12-06 20:14:01 -0500
committerAndi Kleen <andi@basil.nowhere.org>2006-12-06 20:14:01 -0500
commitd7731c0ff69dc3f18ea020257e627dae4d214fdb (patch)
tree869f8889f40246eb347b3e666d162b173bc9c177 /include/asm-i386/cpufeature.h
parentd8cebe65ea5179e3293c38427d71f4d73c795d39 (diff)
[PATCH] i386: i386 rename X86_FEATURE_DTES to X86_FEATURE_DS
Here is a patch (used by perfmon2) that renames X86_FEATURE_DTES to X86_FEATURE_DS to match Intel's documentation for the Debug Store save area on i386. The patch also adds cpu_has_ds. - rename X86_FEATURE_DTES to X86_FEATURE_DS to match documentation - adds cpu_has_ds to test for X86_FEATURE_DS Signed-off-by: stephane eranian <eranian@hpl.hp.com> Signed-off-by: Andi Kleen <ak@suse.de> Cc: Andi Kleen <ak@suse.de> Signed-off-by: Andrew Morton <akpm@osdl.org>
Diffstat (limited to 'include/asm-i386/cpufeature.h')
-rw-r--r--include/asm-i386/cpufeature.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/include/asm-i386/cpufeature.h b/include/asm-i386/cpufeature.h
index d314ebb3d59e..69ce35049a07 100644
--- a/include/asm-i386/cpufeature.h
+++ b/include/asm-i386/cpufeature.h
@@ -31,7 +31,7 @@
31#define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */ 31#define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */
32#define X86_FEATURE_PN (0*32+18) /* Processor serial number */ 32#define X86_FEATURE_PN (0*32+18) /* Processor serial number */
33#define X86_FEATURE_CLFLSH (0*32+19) /* Supports the CLFLUSH instruction */ 33#define X86_FEATURE_CLFLSH (0*32+19) /* Supports the CLFLUSH instruction */
34#define X86_FEATURE_DTES (0*32+21) /* Debug Trace Store */ 34#define X86_FEATURE_DS (0*32+21) /* Debug Store */
35#define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */ 35#define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */
36#define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */ 36#define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */
37#define X86_FEATURE_FXSR (0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */ 37#define X86_FEATURE_FXSR (0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */
@@ -134,6 +134,7 @@
134#define cpu_has_phe_enabled boot_cpu_has(X86_FEATURE_PHE_EN) 134#define cpu_has_phe_enabled boot_cpu_has(X86_FEATURE_PHE_EN)
135#define cpu_has_pmm boot_cpu_has(X86_FEATURE_PMM) 135#define cpu_has_pmm boot_cpu_has(X86_FEATURE_PMM)
136#define cpu_has_pmm_enabled boot_cpu_has(X86_FEATURE_PMM_EN) 136#define cpu_has_pmm_enabled boot_cpu_has(X86_FEATURE_PMM_EN)
137#define cpu_has_ds boot_cpu_has(X86_FEATURE_DS)
137 138
138#endif /* __ASM_I386_CPUFEATURE_H */ 139#endif /* __ASM_I386_CPUFEATURE_H */
139 140