diff options
author | H. Peter Anvin <hpa@zytor.com> | 2007-07-11 15:18:29 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-07-12 13:55:54 -0400 |
commit | ec481536b15eb0520d8f0204b0294480050fe1f8 (patch) | |
tree | 3f959a26ca58477734ea1e4d5370b2d3a33a1680 /include/asm-i386/cpufeature.h | |
parent | f8c09377d754f35a135454181b869ab527cc0757 (diff) |
Unify the CPU features vectors between i386 and x86-64
Unify the handling of the CPU features vectors between i386 and x86-64.
This also adopts the collapsing of features which are required at
compile-time into constant tests from x86-64 to i386.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'include/asm-i386/cpufeature.h')
-rw-r--r-- | include/asm-i386/cpufeature.h | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/include/asm-i386/cpufeature.h b/include/asm-i386/cpufeature.h index f514e906643a..7ea5f4a6706f 100644 --- a/include/asm-i386/cpufeature.h +++ b/include/asm-i386/cpufeature.h | |||
@@ -81,6 +81,7 @@ | |||
81 | #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ | 81 | #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ |
82 | #define X86_FEATURE_LAPIC_TIMER_BROKEN (3*32+ 14) /* lapic timer broken in C1 */ | 82 | #define X86_FEATURE_LAPIC_TIMER_BROKEN (3*32+ 14) /* lapic timer broken in C1 */ |
83 | #define X86_FEATURE_SYNC_RDTSC (3*32+15) /* RDTSC synchronizes the CPU */ | 83 | #define X86_FEATURE_SYNC_RDTSC (3*32+15) /* RDTSC synchronizes the CPU */ |
84 | #define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */ | ||
84 | 85 | ||
85 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ | 86 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ |
86 | #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ | 87 | #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ |
@@ -108,11 +109,17 @@ | |||
108 | #define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */ | 109 | #define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */ |
109 | #define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */ | 110 | #define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */ |
110 | 111 | ||
111 | #define cpu_has(c, bit) \ | 112 | #define cpu_has(c, bit) \ |
112 | ((__builtin_constant_p(bit) && (bit) < 32 && \ | 113 | (__builtin_constant_p(bit) && \ |
113 | (1UL << (bit)) & REQUIRED_MASK1) ? \ | 114 | ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) || \ |
114 | 1 : \ | 115 | (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) || \ |
115 | test_bit(bit, (c)->x86_capability)) | 116 | (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) || \ |
117 | (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) || \ | ||
118 | (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) || \ | ||
119 | (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) || \ | ||
120 | (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) ) \ | ||
121 | ? 1 : \ | ||
122 | test_bit(bit, (c)->x86_capability)) | ||
116 | #define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit) | 123 | #define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit) |
117 | 124 | ||
118 | #define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU) | 125 | #define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU) |