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authorLen Brown <len.brown@intel.com>2006-01-07 03:50:18 -0500
committerLen Brown <len.brown@intel.com>2006-01-07 03:50:18 -0500
commited03f430cdc8c802652467e9097606fedc2c7abc (patch)
tree30941ec1e6f93e99358fefe18175e5dd800a4379 /include/asm-i386/bugs.h
parented349a8a0a780ed27e2a765f16cee54d9b63bfee (diff)
parent6f957eaf79356a32e838f5f262ee9a60544b1d5b (diff)
Pull pnpacpi into acpica branch
Diffstat (limited to 'include/asm-i386/bugs.h')
-rw-r--r--include/asm-i386/bugs.h23
1 files changed, 1 insertions, 22 deletions
diff --git a/include/asm-i386/bugs.h b/include/asm-i386/bugs.h
index ea54540638d2..50233e0345fb 100644
--- a/include/asm-i386/bugs.h
+++ b/include/asm-i386/bugs.h
@@ -8,9 +8,6 @@
8 * <rreilova@ececs.uc.edu> 8 * <rreilova@ececs.uc.edu>
9 * - Channing Corn (tests & fixes), 9 * - Channing Corn (tests & fixes),
10 * - Andrew D. Balsa (code cleanup). 10 * - Andrew D. Balsa (code cleanup).
11 *
12 * Pentium III FXSR, SSE support
13 * Gareth Hughes <gareth@valinux.com>, May 2000
14 */ 11 */
15 12
16/* 13/*
@@ -76,25 +73,7 @@ static void __init check_fpu(void)
76 return; 73 return;
77 } 74 }
78 75
79/* Enable FXSR and company _before_ testing for FP problems. */ 76/* trap_init() enabled FXSR and company _before_ testing for FP problems here. */
80 /*
81 * Verify that the FXSAVE/FXRSTOR data will be 16-byte aligned.
82 */
83 if (offsetof(struct task_struct, thread.i387.fxsave) & 15) {
84 extern void __buggy_fxsr_alignment(void);
85 __buggy_fxsr_alignment();
86 }
87 if (cpu_has_fxsr) {
88 printk(KERN_INFO "Enabling fast FPU save and restore... ");
89 set_in_cr4(X86_CR4_OSFXSR);
90 printk("done.\n");
91 }
92 if (cpu_has_xmm) {
93 printk(KERN_INFO "Enabling unmasked SIMD FPU exception support... ");
94 set_in_cr4(X86_CR4_OSXMMEXCPT);
95 printk("done.\n");
96 }
97
98 /* Test for the divl bug.. */ 77 /* Test for the divl bug.. */
99 __asm__("fninit\n\t" 78 __asm__("fninit\n\t"
100 "fldl %1\n\t" 79 "fldl %1\n\t"