diff options
author | Bjorn Helgaas <bhelgaas@google.com> | 2012-04-30 17:21:02 -0400 |
---|---|---|
committer | Bjorn Helgaas <bhelgaas@google.com> | 2012-04-30 17:21:02 -0400 |
commit | 284f5f9dbac170b054c1e386ef92cbf654e91bba (patch) | |
tree | 74cacc94070d5590378c368fa7378d37319d07be /include/asm-generic | |
parent | 66f75a5d028beaf67c931435fdc3e7823125730c (diff) |
PCI: work around Stratus ftServer broken PCIe hierarchy
A PCIe downstream port is a P2P bridge. Its secondary interface is
a link that should lead only to device 0 (unless ARI is enabled)[1], so
we don't probe for non-zero device numbers.
Some Stratus ftServer systems have a PCIe downstream port (02:00.0) that
leads to both an upstream port (03:00.0) and a downstream port (03:01.0),
and 03:01.0 has important devices below it:
[0000:02]-+-00.0-[03-3c]--+-00.0-[04-09]--...
\-01.0-[0a-0d]--+-[USB]
+-[NIC]
+-...
Previously, we didn't enumerate device 03:01.0, so USB and the network
didn't work. This patch adds a DMI quirk to scan all device numbers,
not just 0, below a downstream port.
Based on a patch by Prarit Bhargava.
[1] PCIe spec r3.0, sec 7.3.1
CC: Myron Stowe <mstowe@redhat.com>
CC: Don Dutile <ddutile@redhat.com>
CC: James Paradis <james.paradis@stratus.com>
CC: Matthew Wilcox <matthew.r.wilcox@intel.com>
CC: Jesse Barnes <jbarnes@virtuousgeek.org>
CC: Prarit Bhargava <prarit@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'include/asm-generic')
-rw-r--r-- | include/asm-generic/pci-bridge.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/asm-generic/pci-bridge.h b/include/asm-generic/pci-bridge.h index a5b5d5a89a4f..20db2e5a0a69 100644 --- a/include/asm-generic/pci-bridge.h +++ b/include/asm-generic/pci-bridge.h | |||
@@ -30,6 +30,12 @@ enum { | |||
30 | PCI_ENABLE_PROC_DOMAINS = 0x00000010, | 30 | PCI_ENABLE_PROC_DOMAINS = 0x00000010, |
31 | /* ... except for domain 0 */ | 31 | /* ... except for domain 0 */ |
32 | PCI_COMPAT_DOMAIN_0 = 0x00000020, | 32 | PCI_COMPAT_DOMAIN_0 = 0x00000020, |
33 | |||
34 | /* PCIe downstream ports are bridges that normally lead to only a | ||
35 | * device 0, but if this is set, we scan all possible devices, not | ||
36 | * just device 0. | ||
37 | */ | ||
38 | PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, | ||
33 | }; | 39 | }; |
34 | 40 | ||
35 | #ifdef CONFIG_PCI | 41 | #ifdef CONFIG_PCI |