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authorAndi Kleen <ak@suse.de>2005-09-12 12:49:24 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2005-09-12 13:49:58 -0400
commit2b4a08150e0ce2f6eb5d0987fdfe3524ec799313 (patch)
treeae4d69033fa3e1e64485433bec8e496fc498ca8f /include/asm-generic/tlb.h
parent165aeb82848c81ee1774f8defc74df4341e9184b (diff)
[PATCH] x86-64: Increase TLB flush array size
The generic TLB flush functions kept upto 506 pages per CPU to avoid too frequent IPIs. This value was done for the L1 cache of older x86 CPUs, but with modern CPUs it does not make much sense anymore. TLB flushing is slow enough that using the L2 cache is fine. This patch increases the flush array on x86-64 to cache 5350 pages. That is roughly 20MB with 4K pages. It speeds up large munmaps in multithreaded processes on SMP considerably. The cost is roughly 42k of memory per CPU, which is reasonable. I only increased it on x86-64 for now, but it would probably make sense to increase it everywhere. Embedded architectures with SMP may keep it smaller to save some memory per CPU. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-generic/tlb.h')
-rw-r--r--include/asm-generic/tlb.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/include/asm-generic/tlb.h b/include/asm-generic/tlb.h
index faff403e1061..7d0298347ee7 100644
--- a/include/asm-generic/tlb.h
+++ b/include/asm-generic/tlb.h
@@ -23,7 +23,11 @@
23 * and page free order so much.. 23 * and page free order so much..
24 */ 24 */
25#ifdef CONFIG_SMP 25#ifdef CONFIG_SMP
26 #define FREE_PTE_NR 506 26 #ifdef ARCH_FREE_PTR_NR
27 #define FREE_PTR_NR ARCH_FREE_PTR_NR
28 #else
29 #define FREE_PTE_NR 506
30 #endif
27 #define tlb_fast_mode(tlb) ((tlb)->nr == ~0U) 31 #define tlb_fast_mode(tlb) ((tlb)->nr == ~0U)
28#else 32#else
29 #define FREE_PTE_NR 1 33 #define FREE_PTE_NR 1