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authorDavid Howells <dhowells@redhat.com>2006-02-14 16:53:20 -0500
committerLinus Torvalds <torvalds@g5.osdl.org>2006-02-14 19:09:35 -0500
commit28baebae73c3ea8b75c7cae225a7db817ab825a9 (patch)
tree940476b4d03b96480d451b7b5b6f3df3f0ff18dc /include/asm-frv
parent68f624fc8b9fa50de9cc0ebd612ef7b7b9fa32d0 (diff)
[PATCH] FRV: Use virtual interrupt disablement
Make the FRV arch use virtual interrupt disablement because accesses to the processor status register (PSR) are relatively slow and because we will soon have the need to deal with multiple interrupt controls at the same time (separate h/w and inter-core interrupts). The way this is done is to dedicate one of the four integer condition code registers (ICC2) to maintaining a virtual interrupt disablement state whilst inside the kernel. This uses the ICC2.Z flag (Zero) to indicate whether the interrupts are virtually disabled and the ICC2.C flag (Carry) to indicate whether the interrupts are physically disabled. ICC2.Z is set to indicate interrupts are virtually disabled. ICC2.C is set to indicate interrupts are physically enabled. Under normal running conditions Z==0 and C==1. Disabling interrupts with local_irq_disable() doesn't then actually physically disable interrupts - it merely sets ICC2.Z to 1. Should an interrupt then happen, the exception prologue will note ICC2.Z is set and branch out of line using one instruction (an unlikely BEQ). Here it will physically disable interrupts and clear ICC2.C. When it comes time to enable interrupts (local_irq_enable()), this simply clears the ICC2.Z flag and invokes a trap #2 if both Z and C flags are clear (the HI integer condition). This can be done with the TIHI conditional trap instruction. The trap then physically reenables interrupts and sets ICC2.C again. Upon returning the interrupt will be taken as interrupts will then be enabled. Note that whilst processing the trap, the whole exceptions system is disabled, and so an interrupt can't happen till it returns. If no pending interrupt had happened, ICC2.C would still be set, the HI condition would not be fulfilled, and no trap will happen. Saving interrupts (local_irq_save) is simply a matter of pulling the ICC2.Z flag out of the CCR register, shifting it down and masking it off. This gives a result of 0 if interrupts were enabled and 1 if they weren't. Restoring interrupts (local_irq_restore) is then a matter of taking the saved value mentioned previously and XOR'ing it against 1. If it was one, the result will be zero, and if it was zero the result will be non-zero. This result is then used to affect the ICC2.Z flag directly (it is a condition code flag after all). An XOR instruction does not affect the Carry flag, and so that bit of state is unchanged. The two flags can then be sampled to see if they're both zero using the trap (TIHI) as for the unconditional reenablement (local_irq_enable). This patch also: (1) Modifies the debugging stub (break.S) to handle single-stepping crossing into the trap #2 handler and into virtually disabled interrupts. (2) Removes superseded fixup pointers from the second instructions in the trap tables (there's no a separate fixup table for this). (3) Declares the trap #3 vector for use in .org directives in the trap table. (4) Moves irq_enter() and irq_exit() in do_IRQ() to avoid problems with virtual interrupt handling, and removes the duplicate code that has now been folded into irq_exit() (softirq and preemption handling). (5) Tells the compiler in the arch Makefile that ICC2 is now reserved. (6) Documents the in-kernel ABI, including the virtual interrupts. (7) Renames the old irq management functions to different names. Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-frv')
-rw-r--r--include/asm-frv/spr-regs.h1
-rw-r--r--include/asm-frv/system.h88
2 files changed, 83 insertions, 6 deletions
diff --git a/include/asm-frv/spr-regs.h b/include/asm-frv/spr-regs.h
index ef472f058d9c..c2a541ef828d 100644
--- a/include/asm-frv/spr-regs.h
+++ b/include/asm-frv/spr-regs.h
@@ -98,6 +98,7 @@
98#define TBR_TT_TRAP0 (0x80 << 4) 98#define TBR_TT_TRAP0 (0x80 << 4)
99#define TBR_TT_TRAP1 (0x81 << 4) 99#define TBR_TT_TRAP1 (0x81 << 4)
100#define TBR_TT_TRAP2 (0x82 << 4) 100#define TBR_TT_TRAP2 (0x82 << 4)
101#define TBR_TT_TRAP3 (0x83 << 4)
101#define TBR_TT_TRAP126 (0xfe << 4) 102#define TBR_TT_TRAP126 (0xfe << 4)
102#define TBR_TT_BREAK (0xff << 4) 103#define TBR_TT_BREAK (0xff << 4)
103 104
diff --git a/include/asm-frv/system.h b/include/asm-frv/system.h
index d2aea70a5f64..f72ff0c4dc0b 100644
--- a/include/asm-frv/system.h
+++ b/include/asm-frv/system.h
@@ -40,8 +40,84 @@ do { \
40 40
41/* 41/*
42 * interrupt flag manipulation 42 * interrupt flag manipulation
43 * - use virtual interrupt management since touching the PSR is slow
44 * - ICC2.Z: T if interrupts virtually disabled
45 * - ICC2.C: F if interrupts really disabled
46 * - if Z==1 upon interrupt:
47 * - C is set to 0
48 * - interrupts are really disabled
49 * - entry.S returns immediately
50 * - uses TIHI (TRAP if Z==0 && C==0) #2 to really reenable interrupts
51 * - if taken, the trap:
52 * - sets ICC2.C
53 * - enables interrupts
43 */ 54 */
44#define local_irq_disable() \ 55#define local_irq_disable() \
56do { \
57 /* set Z flag, but don't change the C flag */ \
58 asm volatile(" andcc gr0,gr0,gr0,icc2 \n" \
59 : \
60 : \
61 : "memory", "icc2" \
62 ); \
63} while(0)
64
65#define local_irq_enable() \
66do { \
67 /* clear Z flag and then test the C flag */ \
68 asm volatile(" oricc gr0,#1,gr0,icc2 \n" \
69 " tihi icc2,gr0,#2 \n" \
70 : \
71 : \
72 : "memory", "icc2" \
73 ); \
74} while(0)
75
76#define local_save_flags(flags) \
77do { \
78 typecheck(unsigned long, flags); \
79 asm volatile("movsg ccr,%0" \
80 : "=r"(flags) \
81 : \
82 : "memory"); \
83 \
84 /* shift ICC2.Z to bit 0 */ \
85 flags >>= 26; \
86 \
87 /* make flags 1 if interrupts disabled, 0 otherwise */ \
88 flags &= 1UL; \
89} while(0)
90
91#define irqs_disabled() \
92 ({unsigned long flags; local_save_flags(flags); flags; })
93
94#define local_irq_save(flags) \
95do { \
96 typecheck(unsigned long, flags); \
97 local_save_flags(flags); \
98 local_irq_disable(); \
99} while(0)
100
101#define local_irq_restore(flags) \
102do { \
103 typecheck(unsigned long, flags); \
104 \
105 /* load the Z flag by turning 1 if disabled into 0 if disabled \
106 * and thus setting the Z flag but not the C flag */ \
107 asm volatile(" xoricc %0,#1,gr0,icc2 \n" \
108 /* then test Z=0 and C=0 */ \
109 " tihi icc2,gr0,#2 \n" \
110 : \
111 : "r"(flags) \
112 : "memory", "icc2" \
113 ); \
114 \
115} while(0)
116
117/*
118 * real interrupt flag manipulation
119 */
120#define __local_irq_disable() \
45do { \ 121do { \
46 unsigned long psr; \ 122 unsigned long psr; \
47 asm volatile(" movsg psr,%0 \n" \ 123 asm volatile(" movsg psr,%0 \n" \
@@ -53,7 +129,7 @@ do { \
53 : "memory"); \ 129 : "memory"); \
54} while(0) 130} while(0)
55 131
56#define local_irq_enable() \ 132#define __local_irq_enable() \
57do { \ 133do { \
58 unsigned long psr; \ 134 unsigned long psr; \
59 asm volatile(" movsg psr,%0 \n" \ 135 asm volatile(" movsg psr,%0 \n" \
@@ -64,7 +140,7 @@ do { \
64 : "memory"); \ 140 : "memory"); \
65} while(0) 141} while(0)
66 142
67#define local_save_flags(flags) \ 143#define __local_save_flags(flags) \
68do { \ 144do { \
69 typecheck(unsigned long, flags); \ 145 typecheck(unsigned long, flags); \
70 asm("movsg psr,%0" \ 146 asm("movsg psr,%0" \
@@ -73,7 +149,7 @@ do { \
73 : "memory"); \ 149 : "memory"); \
74} while(0) 150} while(0)
75 151
76#define local_irq_save(flags) \ 152#define __local_irq_save(flags) \
77do { \ 153do { \
78 unsigned long npsr; \ 154 unsigned long npsr; \
79 typecheck(unsigned long, flags); \ 155 typecheck(unsigned long, flags); \
@@ -86,7 +162,7 @@ do { \
86 : "memory"); \ 162 : "memory"); \
87} while(0) 163} while(0)
88 164
89#define local_irq_restore(flags) \ 165#define __local_irq_restore(flags) \
90do { \ 166do { \
91 typecheck(unsigned long, flags); \ 167 typecheck(unsigned long, flags); \
92 asm volatile(" movgs %0,psr \n" \ 168 asm volatile(" movgs %0,psr \n" \
@@ -95,7 +171,7 @@ do { \
95 : "memory"); \ 171 : "memory"); \
96} while(0) 172} while(0)
97 173
98#define irqs_disabled() \ 174#define __irqs_disabled() \
99 ((__get_PSR() & PSR_PIL) >= PSR_PIL_14) 175 ((__get_PSR() & PSR_PIL) >= PSR_PIL_14)
100 176
101/* 177/*