diff options
| author | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
| commit | 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch) | |
| tree | 0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-cris | |
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
Diffstat (limited to 'include/asm-cris')
110 files changed, 14616 insertions, 0 deletions
diff --git a/include/asm-cris/a.out.h b/include/asm-cris/a.out.h new file mode 100644 index 000000000000..770734ce54a6 --- /dev/null +++ b/include/asm-cris/a.out.h | |||
| @@ -0,0 +1,31 @@ | |||
| 1 | #ifndef __CRIS_A_OUT_H__ | ||
| 2 | #define __CRIS_A_OUT_H__ | ||
| 3 | |||
| 4 | /* we don't support a.out binaries on Linux/CRIS anyway, so this is | ||
| 5 | * not really used but still needed because binfmt_elf.c for some reason | ||
| 6 | * wants to know about a.out even if there is no interpreter available... | ||
| 7 | */ | ||
| 8 | |||
| 9 | /* grabbed from the intel stuff */ | ||
| 10 | #define STACK_TOP TASK_SIZE | ||
| 11 | |||
| 12 | |||
| 13 | struct exec | ||
| 14 | { | ||
| 15 | unsigned long a_info; /* Use macros N_MAGIC, etc for access */ | ||
| 16 | unsigned a_text; /* length of text, in bytes */ | ||
| 17 | unsigned a_data; /* length of data, in bytes */ | ||
| 18 | unsigned a_bss; /* length of uninitialized data area for file, in bytes */ | ||
| 19 | unsigned a_syms; /* length of symbol table data in file, in bytes */ | ||
| 20 | unsigned a_entry; /* start address */ | ||
| 21 | unsigned a_trsize; /* length of relocation info for text, in bytes */ | ||
| 22 | unsigned a_drsize; /* length of relocation info for data, in bytes */ | ||
| 23 | }; | ||
| 24 | |||
| 25 | |||
| 26 | #define N_TRSIZE(a) ((a).a_trsize) | ||
| 27 | #define N_DRSIZE(a) ((a).a_drsize) | ||
| 28 | #define N_SYMSIZE(a) ((a).a_syms) | ||
| 29 | |||
| 30 | |||
| 31 | #endif | ||
diff --git a/include/asm-cris/arch-v10/bitops.h b/include/asm-cris/arch-v10/bitops.h new file mode 100644 index 000000000000..21b7ae8c9bb3 --- /dev/null +++ b/include/asm-cris/arch-v10/bitops.h | |||
| @@ -0,0 +1,73 @@ | |||
| 1 | /* asm/arch/bitops.h for Linux/CRISv10 */ | ||
| 2 | |||
| 3 | #ifndef _CRIS_ARCH_BITOPS_H | ||
| 4 | #define _CRIS_ARCH_BITOPS_H | ||
| 5 | |||
| 6 | /* | ||
| 7 | * Helper functions for the core of the ff[sz] functions, wrapping the | ||
| 8 | * syntactically awkward asms. The asms compute the number of leading | ||
| 9 | * zeroes of a bits-in-byte and byte-in-word and word-in-dword-swapped | ||
| 10 | * number. They differ in that the first function also inverts all bits | ||
| 11 | * in the input. | ||
| 12 | */ | ||
| 13 | extern inline unsigned long cris_swapnwbrlz(unsigned long w) | ||
| 14 | { | ||
| 15 | /* Let's just say we return the result in the same register as the | ||
| 16 | input. Saying we clobber the input but can return the result | ||
| 17 | in another register: | ||
| 18 | ! __asm__ ("swapnwbr %2\n\tlz %2,%0" | ||
| 19 | ! : "=r,r" (res), "=r,X" (dummy) : "1,0" (w)); | ||
| 20 | confuses gcc (sched.c, gcc from cris-dist-1.14). */ | ||
| 21 | |||
| 22 | unsigned long res; | ||
| 23 | __asm__ ("swapnwbr %0 \n\t" | ||
| 24 | "lz %0,%0" | ||
| 25 | : "=r" (res) : "0" (w)); | ||
| 26 | return res; | ||
| 27 | } | ||
| 28 | |||
| 29 | extern inline unsigned long cris_swapwbrlz(unsigned long w) | ||
| 30 | { | ||
| 31 | unsigned res; | ||
| 32 | __asm__ ("swapwbr %0 \n\t" | ||
| 33 | "lz %0,%0" | ||
| 34 | : "=r" (res) | ||
| 35 | : "0" (w)); | ||
| 36 | return res; | ||
| 37 | } | ||
| 38 | |||
| 39 | /* | ||
| 40 | * ffz = Find First Zero in word. Undefined if no zero exists, | ||
| 41 | * so code should check against ~0UL first.. | ||
| 42 | */ | ||
| 43 | extern inline unsigned long ffz(unsigned long w) | ||
| 44 | { | ||
| 45 | return cris_swapnwbrlz(w); | ||
| 46 | } | ||
| 47 | |||
| 48 | /** | ||
| 49 | * __ffs - find first bit in word. | ||
| 50 | * @word: The word to search | ||
| 51 | * | ||
| 52 | * Undefined if no bit exists, so code should check against 0 first. | ||
| 53 | */ | ||
| 54 | extern __inline__ unsigned long __ffs(unsigned long word) | ||
| 55 | { | ||
| 56 | return cris_swapnwbrlz(~word); | ||
| 57 | } | ||
| 58 | |||
| 59 | /** | ||
| 60 | * ffs - find first bit set | ||
| 61 | * @x: the word to search | ||
| 62 | * | ||
| 63 | * This is defined the same way as | ||
| 64 | * the libc and compiler builtin ffs routines, therefore | ||
| 65 | * differs in spirit from the above ffz (man ffs). | ||
| 66 | */ | ||
| 67 | |||
| 68 | extern inline unsigned long kernel_ffs(unsigned long w) | ||
| 69 | { | ||
| 70 | return w ? cris_swapwbrlz (w) + 1 : 0; | ||
| 71 | } | ||
| 72 | |||
| 73 | #endif | ||
diff --git a/include/asm-cris/arch-v10/byteorder.h b/include/asm-cris/arch-v10/byteorder.h new file mode 100644 index 000000000000..e24465d1f40d --- /dev/null +++ b/include/asm-cris/arch-v10/byteorder.h | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | #ifndef _CRIS_ARCH_BYTEORDER_H | ||
| 2 | #define _CRIS_ARCH_BYTEORDER_H | ||
| 3 | |||
| 4 | #include <asm/types.h> | ||
| 5 | #include <linux/compiler.h> | ||
| 6 | |||
| 7 | /* we just define these two (as we can do the swap in a single | ||
| 8 | * asm instruction in CRIS) and the arch-independent files will put | ||
| 9 | * them together into ntohl etc. | ||
| 10 | */ | ||
| 11 | |||
| 12 | extern __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) | ||
| 13 | { | ||
| 14 | __asm__ ("swapwb %0" : "=r" (x) : "0" (x)); | ||
| 15 | |||
| 16 | return(x); | ||
| 17 | } | ||
| 18 | |||
| 19 | extern __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) | ||
| 20 | { | ||
| 21 | __asm__ ("swapb %0" : "=r" (x) : "0" (x)); | ||
| 22 | |||
| 23 | return(x); | ||
| 24 | } | ||
| 25 | |||
| 26 | #endif | ||
diff --git a/include/asm-cris/arch-v10/cache.h b/include/asm-cris/arch-v10/cache.h new file mode 100644 index 000000000000..1d1d1ba65b1a --- /dev/null +++ b/include/asm-cris/arch-v10/cache.h | |||
| @@ -0,0 +1,9 @@ | |||
| 1 | #ifndef _ASM_ARCH_CACHE_H | ||
| 2 | #define _ASM_ARCH_CACHE_H | ||
| 3 | |||
| 4 | /* Etrax 100LX have 32-byte cache-lines. */ | ||
| 5 | #define L1_CACHE_BYTES 32 | ||
| 6 | #define L1_CACHE_SHIFT 5 | ||
| 7 | #define L1_CACHE_SHIFT_MAX 5 | ||
| 8 | |||
| 9 | #endif /* _ASM_ARCH_CACHE_H */ | ||
diff --git a/include/asm-cris/arch-v10/checksum.h b/include/asm-cris/arch-v10/checksum.h new file mode 100644 index 000000000000..fde1d00aaa90 --- /dev/null +++ b/include/asm-cris/arch-v10/checksum.h | |||
| @@ -0,0 +1,29 @@ | |||
| 1 | #ifndef _CRIS_ARCH_CHECKSUM_H | ||
| 2 | #define _CRIS_ARCH_CHECKSUM_H | ||
| 3 | |||
| 4 | /* Checksum some values used in TCP/UDP headers. | ||
| 5 | * | ||
| 6 | * The gain by doing this in asm is that C will not generate carry-additions | ||
| 7 | * for the 32-bit components of the checksum, so otherwise we would have had | ||
| 8 | * to split all of those into 16-bit components, then add. | ||
| 9 | */ | ||
| 10 | |||
| 11 | extern inline unsigned int | ||
| 12 | csum_tcpudp_nofold(unsigned long saddr, unsigned long daddr, unsigned short len, | ||
| 13 | unsigned short proto, unsigned int sum) | ||
| 14 | { | ||
| 15 | int res; | ||
| 16 | __asm__ ("add.d %2, %0\n\t" | ||
| 17 | "ax\n\t" | ||
| 18 | "add.d %3, %0\n\t" | ||
| 19 | "ax\n\t" | ||
| 20 | "add.d %4, %0\n\t" | ||
| 21 | "ax\n\t" | ||
| 22 | "addq 0, %0\n" | ||
| 23 | : "=r" (res) | ||
| 24 | : "0" (sum), "r" (daddr), "r" (saddr), "r" ((ntohs(len) << 16) + (proto << 8))); | ||
| 25 | |||
| 26 | return res; | ||
| 27 | } | ||
| 28 | |||
| 29 | #endif | ||
diff --git a/include/asm-cris/arch-v10/delay.h b/include/asm-cris/arch-v10/delay.h new file mode 100644 index 000000000000..cfedae0d2f53 --- /dev/null +++ b/include/asm-cris/arch-v10/delay.h | |||
| @@ -0,0 +1,20 @@ | |||
| 1 | #ifndef _CRIS_ARCH_DELAY_H | ||
| 2 | #define _CRIS_ARCH_DELAY_H | ||
| 3 | |||
| 4 | extern __inline__ void __delay(int loops) | ||
| 5 | { | ||
| 6 | __asm__ __volatile__ ( | ||
| 7 | "move.d %0,$r9\n\t" | ||
| 8 | "beq 2f\n\t" | ||
| 9 | "subq 1,$r9\n\t" | ||
| 10 | "1:\n\t" | ||
| 11 | "bne 1b\n\t" | ||
| 12 | "subq 1,$r9\n" | ||
| 13 | "2:" | ||
| 14 | : : "g" (loops) : "r9"); | ||
| 15 | } | ||
| 16 | |||
| 17 | #endif /* defined(_CRIS_ARCH_DELAY_H) */ | ||
| 18 | |||
| 19 | |||
| 20 | |||
diff --git a/include/asm-cris/arch-v10/dma.h b/include/asm-cris/arch-v10/dma.h new file mode 100644 index 000000000000..9e078b9bc934 --- /dev/null +++ b/include/asm-cris/arch-v10/dma.h | |||
| @@ -0,0 +1,46 @@ | |||
| 1 | /* Defines for using and allocating dma channels. */ | ||
| 2 | |||
| 3 | #ifndef _ASM_ARCH_DMA_H | ||
| 4 | #define _ASM_ARCH_DMA_H | ||
| 5 | |||
| 6 | #define MAX_DMA_CHANNELS 10 | ||
| 7 | |||
| 8 | /* dma0 and dma1 used for network (ethernet) */ | ||
| 9 | #define NETWORK_TX_DMA_NBR 0 | ||
| 10 | #define NETWORK_RX_DMA_NBR 1 | ||
| 11 | |||
| 12 | /* dma2 and dma3 shared by par0, scsi0, ser2 and ata */ | ||
| 13 | #define PAR0_TX_DMA_NBR 2 | ||
| 14 | #define PAR0_RX_DMA_NBR 3 | ||
| 15 | #define SCSI0_TX_DMA_NBR 2 | ||
| 16 | #define SCSI0_RX_DMA_NBR 3 | ||
| 17 | #define SER2_TX_DMA_NBR 2 | ||
| 18 | #define SER2_RX_DMA_NBR 3 | ||
| 19 | #define ATA_TX_DMA_NBR 2 | ||
| 20 | #define ATA_RX_DMA_NBR 3 | ||
| 21 | |||
| 22 | /* dma4 and dma5 shared by par1, scsi1, ser3 and extdma0 */ | ||
| 23 | #define PAR1_TX_DMA_NBR 4 | ||
| 24 | #define PAR1_RX_DMA_NBR 5 | ||
| 25 | #define SCSI1_TX_DMA_NBR 4 | ||
| 26 | #define SCSI1_RX_DMA_NBR 5 | ||
| 27 | #define SER3_TX_DMA_NBR 4 | ||
| 28 | #define SER3_RX_DMA_NBR 5 | ||
| 29 | #define EXTDMA0_TX_DMA_NBR 4 | ||
| 30 | #define EXTDMA0_RX_DMA_NBR 5 | ||
| 31 | |||
| 32 | /* dma6 and dma7 shared by ser0, extdma1 and mem2mem */ | ||
| 33 | #define SER0_TX_DMA_NBR 6 | ||
| 34 | #define SER0_RX_DMA_NBR 7 | ||
| 35 | #define EXTDMA1_TX_DMA_NBR 6 | ||
| 36 | #define EXTDMA1_RX_DMA_NBR 7 | ||
| 37 | #define MEM2MEM_TX_DMA_NBR 6 | ||
| 38 | #define MEM2MEM_RX_DMA_NBR 7 | ||
| 39 | |||
| 40 | /* dma8 and dma9 shared by ser1 and usb */ | ||
| 41 | #define SER1_TX_DMA_NBR 8 | ||
| 42 | #define SER1_RX_DMA_NBR 9 | ||
| 43 | #define USB_TX_DMA_NBR 8 | ||
| 44 | #define USB_RX_DMA_NBR 9 | ||
| 45 | |||
| 46 | #endif | ||
diff --git a/include/asm-cris/arch-v10/elf.h b/include/asm-cris/arch-v10/elf.h new file mode 100644 index 000000000000..2a2201ca538e --- /dev/null +++ b/include/asm-cris/arch-v10/elf.h | |||
| @@ -0,0 +1,71 @@ | |||
| 1 | #ifndef __ASMCRIS_ARCH_ELF_H | ||
| 2 | #define __ASMCRIS_ARCH_ELF_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * ELF register definitions.. | ||
| 6 | */ | ||
| 7 | |||
| 8 | #include <asm/ptrace.h> | ||
| 9 | |||
| 10 | /* SVR4/i386 ABI (pages 3-31, 3-32) says that when the program | ||
| 11 | starts (a register; assume first param register for CRIS) | ||
| 12 | contains a pointer to a function which might be | ||
| 13 | registered using `atexit'. This provides a mean for the | ||
| 14 | dynamic linker to call DT_FINI functions for shared libraries | ||
| 15 | that have been loaded before the code runs. | ||
| 16 | |||
| 17 | A value of 0 tells we have no such handler. */ | ||
| 18 | |||
| 19 | /* Explicitly set registers to 0 to increase determinism. */ | ||
| 20 | #define ELF_PLAT_INIT(_r, load_addr) do { \ | ||
| 21 | (_r)->r13 = 0; (_r)->r12 = 0; (_r)->r11 = 0; (_r)->r10 = 0; \ | ||
| 22 | (_r)->r9 = 0; (_r)->r8 = 0; (_r)->r7 = 0; (_r)->r6 = 0; \ | ||
| 23 | (_r)->r5 = 0; (_r)->r4 = 0; (_r)->r3 = 0; (_r)->r2 = 0; \ | ||
| 24 | (_r)->r1 = 0; (_r)->r0 = 0; (_r)->mof = 0; (_r)->srp = 0; \ | ||
| 25 | } while (0) | ||
| 26 | |||
| 27 | /* The additional layer below is because the stack pointer is missing in | ||
| 28 | the pt_regs struct, but needed in a core dump. pr_reg is a elf_gregset_t, | ||
| 29 | and should be filled in according to the layout of the user_regs_struct | ||
| 30 | struct; regs is a pt_regs struct. We dump all registers, though several are | ||
| 31 | obviously unnecessary. That way there's less need for intelligence at | ||
| 32 | the receiving end (i.e. gdb). */ | ||
| 33 | #define ELF_CORE_COPY_REGS(pr_reg, regs) \ | ||
| 34 | pr_reg[0] = regs->r0; \ | ||
| 35 | pr_reg[1] = regs->r1; \ | ||
| 36 | pr_reg[2] = regs->r2; \ | ||
| 37 | pr_reg[3] = regs->r3; \ | ||
| 38 | pr_reg[4] = regs->r4; \ | ||
| 39 | pr_reg[5] = regs->r5; \ | ||
| 40 | pr_reg[6] = regs->r6; \ | ||
| 41 | pr_reg[7] = regs->r7; \ | ||
| 42 | pr_reg[8] = regs->r8; \ | ||
| 43 | pr_reg[9] = regs->r9; \ | ||
| 44 | pr_reg[10] = regs->r10; \ | ||
| 45 | pr_reg[11] = regs->r11; \ | ||
| 46 | pr_reg[12] = regs->r12; \ | ||
| 47 | pr_reg[13] = regs->r13; \ | ||
| 48 | pr_reg[14] = rdusp(); /* sp */ \ | ||
| 49 | pr_reg[15] = regs->irp; /* pc */ \ | ||
| 50 | pr_reg[16] = 0; /* p0 */ \ | ||
| 51 | pr_reg[17] = rdvr(); /* vr */ \ | ||
| 52 | pr_reg[18] = 0; /* p2 */ \ | ||
| 53 | pr_reg[19] = 0; /* p3 */ \ | ||
| 54 | pr_reg[20] = 0; /* p4 */ \ | ||
| 55 | pr_reg[21] = (regs->dccr & 0xffff); /* ccr */ \ | ||
| 56 | pr_reg[22] = 0; /* p6 */ \ | ||
| 57 | pr_reg[23] = regs->mof; /* mof */ \ | ||
| 58 | pr_reg[24] = 0; /* p8 */ \ | ||
| 59 | pr_reg[25] = 0; /* ibr */ \ | ||
| 60 | pr_reg[26] = 0; /* irp */ \ | ||
| 61 | pr_reg[27] = regs->srp; /* srp */ \ | ||
| 62 | pr_reg[28] = 0; /* bar */ \ | ||
| 63 | pr_reg[29] = regs->dccr; /* dccr */ \ | ||
| 64 | pr_reg[30] = 0; /* brp */ \ | ||
| 65 | pr_reg[31] = rdusp(); /* usp */ \ | ||
| 66 | pr_reg[32] = 0; /* csrinstr */ \ | ||
| 67 | pr_reg[33] = 0; /* csraddr */ \ | ||
| 68 | pr_reg[34] = 0; /* csrdata */ | ||
| 69 | |||
| 70 | |||
| 71 | #endif | ||
diff --git a/include/asm-cris/arch-v10/io.h b/include/asm-cris/arch-v10/io.h new file mode 100644 index 000000000000..0bc38a0313c1 --- /dev/null +++ b/include/asm-cris/arch-v10/io.h | |||
| @@ -0,0 +1,193 @@ | |||
| 1 | #ifndef _ASM_ARCH_CRIS_IO_H | ||
| 2 | #define _ASM_ARCH_CRIS_IO_H | ||
| 3 | |||
| 4 | #include <asm/arch/svinto.h> | ||
| 5 | #include <linux/config.h> | ||
| 6 | |||
| 7 | /* Etrax shadow registers - which live in arch/cris/kernel/shadows.c */ | ||
| 8 | |||
| 9 | extern unsigned long port_g_data_shadow; | ||
| 10 | extern unsigned char port_pa_dir_shadow; | ||
| 11 | extern unsigned char port_pa_data_shadow; | ||
| 12 | extern unsigned char port_pb_i2c_shadow; | ||
| 13 | extern unsigned char port_pb_config_shadow; | ||
| 14 | extern unsigned char port_pb_dir_shadow; | ||
| 15 | extern unsigned char port_pb_data_shadow; | ||
| 16 | extern unsigned long r_timer_ctrl_shadow; | ||
| 17 | |||
| 18 | extern unsigned long port_cse1_shadow; | ||
| 19 | extern unsigned long port_csp0_shadow; | ||
| 20 | extern unsigned long port_csp4_shadow; | ||
| 21 | |||
| 22 | extern volatile unsigned long *port_cse1_addr; | ||
| 23 | extern volatile unsigned long *port_csp0_addr; | ||
| 24 | extern volatile unsigned long *port_csp4_addr; | ||
| 25 | |||
| 26 | /* macro for setting regs through a shadow - | ||
| 27 | * r = register name (like R_PORT_PA_DATA) | ||
| 28 | * s = shadow name (like port_pa_data_shadow) | ||
| 29 | * b = bit number | ||
| 30 | * v = value (0 or 1) | ||
| 31 | */ | ||
| 32 | |||
| 33 | #define REG_SHADOW_SET(r,s,b,v) *r = s = (s & ~(1 << (b))) | ((v) << (b)) | ||
| 34 | |||
| 35 | /* The LED's on various Etrax-based products are set differently. */ | ||
| 36 | |||
| 37 | #if defined(CONFIG_ETRAX_NO_LEDS) || defined(CONFIG_SVINTO_SIM) | ||
| 38 | #undef CONFIG_ETRAX_PA_LEDS | ||
| 39 | #undef CONFIG_ETRAX_PB_LEDS | ||
| 40 | #undef CONFIG_ETRAX_CSP0_LEDS | ||
| 41 | #define LED_NETWORK_SET_G(x) | ||
| 42 | #define LED_NETWORK_SET_R(x) | ||
| 43 | #define LED_ACTIVE_SET_G(x) | ||
| 44 | #define LED_ACTIVE_SET_R(x) | ||
| 45 | #define LED_DISK_WRITE(x) | ||
| 46 | #define LED_DISK_READ(x) | ||
| 47 | #endif | ||
| 48 | |||
| 49 | #if !defined(CONFIG_ETRAX_CSP0_LEDS) | ||
| 50 | #define LED_BIT_SET(x) | ||
| 51 | #define LED_BIT_CLR(x) | ||
| 52 | #endif | ||
| 53 | |||
| 54 | #define LED_OFF 0x00 | ||
| 55 | #define LED_GREEN 0x01 | ||
| 56 | #define LED_RED 0x02 | ||
| 57 | #define LED_ORANGE (LED_GREEN | LED_RED) | ||
| 58 | |||
| 59 | #if CONFIG_ETRAX_LED1G == CONFIG_ETRAX_LED1R | ||
| 60 | #define LED_NETWORK_SET(x) \ | ||
| 61 | do { \ | ||
| 62 | LED_NETWORK_SET_G((x) & LED_GREEN); \ | ||
| 63 | } while (0) | ||
| 64 | #else | ||
| 65 | #define LED_NETWORK_SET(x) \ | ||
| 66 | do { \ | ||
| 67 | LED_NETWORK_SET_G((x) & LED_GREEN); \ | ||
| 68 | LED_NETWORK_SET_R((x) & LED_RED); \ | ||
| 69 | } while (0) | ||
| 70 | #endif | ||
| 71 | #if CONFIG_ETRAX_LED2G == CONFIG_ETRAX_LED2R | ||
| 72 | #define LED_ACTIVE_SET(x) \ | ||
| 73 | do { \ | ||
| 74 | LED_ACTIVE_SET_G((x) & LED_GREEN); \ | ||
| 75 | } while (0) | ||
| 76 | #else | ||
| 77 | #define LED_ACTIVE_SET(x) \ | ||
| 78 | do { \ | ||
| 79 | LED_ACTIVE_SET_G((x) & LED_GREEN); \ | ||
| 80 | LED_ACTIVE_SET_R((x) & LED_RED); \ | ||
| 81 | } while (0) | ||
| 82 | #endif | ||
| 83 | |||
| 84 | #ifdef CONFIG_ETRAX_PA_LEDS | ||
| 85 | #define LED_NETWORK_SET_G(x) \ | ||
| 86 | REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED1G, !(x)) | ||
| 87 | #define LED_NETWORK_SET_R(x) \ | ||
| 88 | REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED1R, !(x)) | ||
| 89 | #define LED_ACTIVE_SET_G(x) \ | ||
| 90 | REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED2G, !(x)) | ||
| 91 | #define LED_ACTIVE_SET_R(x) \ | ||
| 92 | REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED2R, !(x)) | ||
| 93 | #define LED_DISK_WRITE(x) \ | ||
| 94 | do{\ | ||
| 95 | REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3G, !(x));\ | ||
| 96 | REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3R, !(x));\ | ||
| 97 | }while(0) | ||
| 98 | #define LED_DISK_READ(x) \ | ||
| 99 | REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3G, !(x)) | ||
| 100 | #endif | ||
| 101 | |||
| 102 | #ifdef CONFIG_ETRAX_PB_LEDS | ||
| 103 | #define LED_NETWORK_SET_G(x) \ | ||
| 104 | REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED1G, !(x)) | ||
| 105 | #define LED_NETWORK_SET_R(x) \ | ||
| 106 | REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED1R, !(x)) | ||
| 107 | #define LED_ACTIVE_SET_G(x) \ | ||
| 108 | REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED2G, !(x)) | ||
| 109 | #define LED_ACTIVE_SET_R(x) \ | ||
| 110 | REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED2R, !(x)) | ||
| 111 | #define LED_DISK_WRITE(x) \ | ||
| 112 | do{\ | ||
| 113 | REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3G, !(x));\ | ||
| 114 | REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3R, !(x));\ | ||
| 115 | }while(0) | ||
| 116 | #define LED_DISK_READ(x) \ | ||
| 117 | REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3G, !(x)) | ||
| 118 | #endif | ||
| 119 | |||
| 120 | #ifdef CONFIG_ETRAX_CSP0_LEDS | ||
| 121 | #define CONFIGURABLE_LEDS\ | ||
| 122 | ((1 << CONFIG_ETRAX_LED1G ) | (1 << CONFIG_ETRAX_LED1R ) |\ | ||
| 123 | (1 << CONFIG_ETRAX_LED2G ) | (1 << CONFIG_ETRAX_LED2R ) |\ | ||
| 124 | (1 << CONFIG_ETRAX_LED3G ) | (1 << CONFIG_ETRAX_LED3R ) |\ | ||
| 125 | (1 << CONFIG_ETRAX_LED4G ) | (1 << CONFIG_ETRAX_LED4R ) |\ | ||
| 126 | (1 << CONFIG_ETRAX_LED5G ) | (1 << CONFIG_ETRAX_LED5R ) |\ | ||
| 127 | (1 << CONFIG_ETRAX_LED6G ) | (1 << CONFIG_ETRAX_LED6R ) |\ | ||
| 128 | (1 << CONFIG_ETRAX_LED7G ) | (1 << CONFIG_ETRAX_LED7R ) |\ | ||
| 129 | (1 << CONFIG_ETRAX_LED8Y ) | (1 << CONFIG_ETRAX_LED9Y ) |\ | ||
| 130 | (1 << CONFIG_ETRAX_LED10Y ) |(1 << CONFIG_ETRAX_LED11Y )|\ | ||
| 131 | (1 << CONFIG_ETRAX_LED12R )) | ||
| 132 | |||
| 133 | #define LED_NETWORK_SET_G(x) \ | ||
| 134 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED1G, !(x)) | ||
| 135 | #define LED_NETWORK_SET_R(x) \ | ||
| 136 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED1R, !(x)) | ||
| 137 | #define LED_ACTIVE_SET_G(x) \ | ||
| 138 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED2G, !(x)) | ||
| 139 | #define LED_ACTIVE_SET_R(x) \ | ||
| 140 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED2R, !(x)) | ||
| 141 | #define LED_DISK_WRITE(x) \ | ||
| 142 | do{\ | ||
| 143 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3G, !(x));\ | ||
| 144 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3R, !(x));\ | ||
| 145 | }while(0) | ||
| 146 | #define LED_DISK_READ(x) \ | ||
| 147 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3G, !(x)) | ||
| 148 | #define LED_BIT_SET(x)\ | ||
| 149 | do{\ | ||
| 150 | if((( 1 << x) & CONFIGURABLE_LEDS) != 0)\ | ||
| 151 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, x, 1);\ | ||
| 152 | }while(0) | ||
| 153 | #define LED_BIT_CLR(x)\ | ||
| 154 | do{\ | ||
| 155 | if((( 1 << x) & CONFIGURABLE_LEDS) != 0)\ | ||
| 156 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, x, 0);\ | ||
| 157 | }while(0) | ||
| 158 | #endif | ||
| 159 | |||
| 160 | # | ||
| 161 | #ifdef CONFIG_ETRAX_SOFT_SHUTDOWN | ||
| 162 | #define SOFT_SHUTDOWN() \ | ||
| 163 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_SHUTDOWN_BIT, 1) | ||
| 164 | #else | ||
| 165 | #define SOFT_SHUTDOWN() | ||
| 166 | #endif | ||
| 167 | |||
| 168 | /* Console I/O for simulated etrax100. Use #ifdef so erroneous | ||
| 169 | use will be evident. */ | ||
| 170 | #ifdef CONFIG_SVINTO_SIM | ||
| 171 | /* Let's use the ucsim interface since it lets us do write(2, ...) */ | ||
| 172 | #define SIMCOUT(s,len) \ | ||
| 173 | asm ("moveq 4,$r9 \n\t" \ | ||
| 174 | "moveq 2,$r10 \n\t" \ | ||
| 175 | "move.d %0,$r11 \n\t" \ | ||
| 176 | "move.d %1,$r12 \n\t" \ | ||
| 177 | "push $irp \n\t" \ | ||
| 178 | "move 0f,$irp \n\t" \ | ||
| 179 | "jump -6809 \n" \ | ||
| 180 | "0: \n\t" \ | ||
| 181 | "pop $irp" \ | ||
| 182 | : : "rm" (s), "rm" (len) : "r9","r10","r11","r12","memory") | ||
| 183 | #define TRACE_ON() __extension__ \ | ||
| 184 | ({ int _Foofoo; __asm__ volatile ("bmod [%0],%0" : "=r" (_Foofoo) : "0" \ | ||
| 185 | (255)); _Foofoo; }) | ||
| 186 | |||
| 187 | #define TRACE_OFF() do { __asm__ volatile ("bmod [%0],%0" :: "r" (254)); } while (0) | ||
| 188 | #define SIM_END() do { __asm__ volatile ("bmod [%0],%0" :: "r" (28)); } while (0) | ||
| 189 | #define CRIS_CYCLES() __extension__ \ | ||
| 190 | ({ unsigned long c; asm ("bmod [%1],%0" : "=r" (c) : "r" (27)); c;}) | ||
| 191 | #endif /* ! defined CONFIG_SVINTO_SIM */ | ||
| 192 | |||
| 193 | #endif | ||
diff --git a/include/asm-cris/arch-v10/irq.h b/include/asm-cris/arch-v10/irq.h new file mode 100644 index 000000000000..a2a6e1533ea0 --- /dev/null +++ b/include/asm-cris/arch-v10/irq.h | |||
| @@ -0,0 +1,181 @@ | |||
| 1 | /* | ||
| 2 | * Interrupt handling assembler and defines for Linux/CRISv10 | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifndef _ASM_ARCH_IRQ_H | ||
| 6 | #define _ASM_ARCH_IRQ_H | ||
| 7 | |||
| 8 | #include <asm/arch/sv_addr_ag.h> | ||
| 9 | |||
| 10 | #define NR_IRQS 32 | ||
| 11 | |||
| 12 | /* The first vector number used for IRQs in v10 is really 0x20 */ | ||
| 13 | /* but all the code and constants are offseted to make 0 the first */ | ||
| 14 | #define FIRST_IRQ 0 | ||
| 15 | |||
| 16 | #define SOME_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, some) /* 0 ? */ | ||
| 17 | #define NMI_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, nmi) /* 1 */ | ||
| 18 | #define TIMER0_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, timer0) /* 2 */ | ||
| 19 | #define TIMER1_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, timer1) /* 3 */ | ||
| 20 | /* mio, ata, par0, scsi0 on 4 */ | ||
| 21 | /* par1, scsi1 on 5 */ | ||
| 22 | #define NETWORK_STATUS_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, network) /* 6 */ | ||
| 23 | |||
| 24 | #define SERIAL_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, serial) /* 8 */ | ||
| 25 | #define PA_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, pa) /* 11 */ | ||
| 26 | /* extdma0 and extdma1 is at irq 12 and 13 and/or same as dma5 and dma6 ? */ | ||
| 27 | #define EXTDMA0_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, ext_dma0) | ||
| 28 | #define EXTDMA1_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, ext_dma1) | ||
| 29 | |||
| 30 | /* dma0-9 is irq 16..25 */ | ||
| 31 | /* 16,17: network */ | ||
| 32 | #define DMA0_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma0) | ||
| 33 | #define DMA1_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma1) | ||
| 34 | #define NETWORK_DMA_TX_IRQ_NBR DMA0_TX_IRQ_NBR | ||
| 35 | #define NETWORK_DMA_RX_IRQ_NBR DMA1_RX_IRQ_NBR | ||
| 36 | |||
| 37 | /* 18,19: dma2 and dma3 shared by par0, scsi0, ser2 and ata */ | ||
| 38 | #define DMA2_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma2) | ||
| 39 | #define DMA3_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma3) | ||
| 40 | #define SER2_DMA_TX_IRQ_NBR DMA2_TX_IRQ_NBR | ||
| 41 | #define SER2_DMA_RX_IRQ_NBR DMA3_RX_IRQ_NBR | ||
| 42 | |||
| 43 | /* 20,21: dma4 and dma5 shared by par1, scsi1, ser3 and extdma0 */ | ||
| 44 | #define DMA4_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma4) | ||
| 45 | #define DMA5_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma5) | ||
| 46 | #define SER3_DMA_TX_IRQ_NBR DMA4_TX_IRQ_NBR | ||
| 47 | #define SER3_DMA_RX_IRQ_NBR DMA5_RX_IRQ_NBR | ||
| 48 | |||
| 49 | /* 22,23: dma6 and dma7 shared by ser0, extdma1 and mem2mem */ | ||
| 50 | #define DMA6_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma6) | ||
| 51 | #define DMA7_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma7) | ||
| 52 | #define SER0_DMA_TX_IRQ_NBR DMA6_TX_IRQ_NBR | ||
| 53 | #define SER0_DMA_RX_IRQ_NBR DMA7_RX_IRQ_NBR | ||
| 54 | #define MEM2MEM_DMA_TX_IRQ_NBR DMA6_TX_IRQ_NBR | ||
| 55 | #define MEM2MEM_DMA_RX_IRQ_NBR DMA7_RX_IRQ_NBR | ||
| 56 | |||
| 57 | /* 24,25: dma8 and dma9 shared by ser1 and usb */ | ||
| 58 | #define DMA8_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma8) | ||
| 59 | #define DMA9_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma9) | ||
| 60 | #define SER1_DMA_TX_IRQ_NBR DMA8_TX_IRQ_NBR | ||
| 61 | #define SER1_DMA_RX_IRQ_NBR DMA9_RX_IRQ_NBR | ||
| 62 | #define USB_DMA_TX_IRQ_NBR DMA8_TX_IRQ_NBR | ||
| 63 | #define USB_DMA_RX_IRQ_NBR DMA9_RX_IRQ_NBR | ||
| 64 | |||
| 65 | /* usb: controller at irq 31 + uses DMA8 and DMA9 */ | ||
| 66 | #define USB_HC_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, usb) | ||
| 67 | |||
| 68 | /* our fine, global, etrax irq vector! the pointer lives in the head.S file. */ | ||
| 69 | |||
| 70 | typedef void (*irqvectptr)(void); | ||
| 71 | |||
| 72 | struct etrax_interrupt_vector { | ||
| 73 | irqvectptr v[256]; | ||
| 74 | }; | ||
| 75 | |||
| 76 | extern struct etrax_interrupt_vector *etrax_irv; | ||
| 77 | void set_int_vector(int n, irqvectptr addr, irqvectptr saddr); | ||
| 78 | void set_break_vector(int n, irqvectptr addr); | ||
| 79 | |||
| 80 | #define mask_irq(irq_nr) (*R_VECT_MASK_CLR = 1 << (irq_nr)); | ||
| 81 | #define unmask_irq(irq_nr) (*R_VECT_MASK_SET = 1 << (irq_nr)); | ||
| 82 | |||
| 83 | #define __STR(x) #x | ||
| 84 | #define STR(x) __STR(x) | ||
| 85 | |||
| 86 | /* SAVE_ALL saves registers so they match pt_regs */ | ||
| 87 | |||
| 88 | #define SAVE_ALL \ | ||
| 89 | "move $irp,[$sp=$sp-16]\n\t" /* push instruction pointer and fake SBFS struct */ \ | ||
| 90 | "push $srp\n\t" /* push subroutine return pointer */ \ | ||
| 91 | "push $dccr\n\t" /* push condition codes */ \ | ||
| 92 | "push $mof\n\t" /* push multiply overflow reg */ \ | ||
| 93 | "di\n\t" /* need to disable irq's at this point */\ | ||
| 94 | "subq 14*4,$sp\n\t" /* make room for r0-r13 */ \ | ||
| 95 | "movem $r13,[$sp]\n\t" /* push the r0-r13 registers */ \ | ||
| 96 | "push $r10\n\t" /* push orig_r10 */ \ | ||
| 97 | "clear.d [$sp=$sp-4]\n\t" /* frametype - this is a normal stackframe */ | ||
| 98 | |||
| 99 | /* BLOCK_IRQ and UNBLOCK_IRQ do the same as mask_irq and unmask_irq */ | ||
| 100 | |||
| 101 | #define BLOCK_IRQ(mask,nr) \ | ||
| 102 | "move.d " #mask ",$r0\n\t" \ | ||
| 103 | "move.d $r0,[0xb00000d8]\n\t" | ||
| 104 | |||
| 105 | #define UNBLOCK_IRQ(mask) \ | ||
| 106 | "move.d " #mask ",$r0\n\t" \ | ||
| 107 | "move.d $r0,[0xb00000dc]\n\t" | ||
| 108 | |||
| 109 | #define IRQ_NAME2(nr) nr##_interrupt(void) | ||
| 110 | #define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr) | ||
| 111 | #define sIRQ_NAME(nr) IRQ_NAME2(sIRQ##nr) | ||
| 112 | #define BAD_IRQ_NAME(nr) IRQ_NAME2(bad_IRQ##nr) | ||
| 113 | |||
| 114 | /* the asm IRQ handler makes sure the causing IRQ is blocked, then it calls | ||
| 115 | * do_IRQ (with irq disabled still). after that it unblocks and jumps to | ||
| 116 | * ret_from_intr (entry.S) | ||
| 117 | * | ||
| 118 | * The reason the IRQ is blocked is to allow an sti() before the handler which | ||
| 119 | * will acknowledge the interrupt is run. | ||
| 120 | */ | ||
| 121 | |||
| 122 | #define BUILD_IRQ(nr,mask) \ | ||
| 123 | void IRQ_NAME(nr); \ | ||
| 124 | void sIRQ_NAME(nr); \ | ||
| 125 | void BAD_IRQ_NAME(nr); \ | ||
| 126 | __asm__ ( \ | ||
| 127 | ".text\n\t" \ | ||
| 128 | "IRQ" #nr "_interrupt:\n\t" \ | ||
| 129 | SAVE_ALL \ | ||
| 130 | "sIRQ" #nr "_interrupt:\n\t" /* shortcut for the multiple irq handler */ \ | ||
| 131 | BLOCK_IRQ(mask,nr) /* this must be done to prevent irq loops when we ei later */ \ | ||
| 132 | "moveq "#nr",$r10\n\t" \ | ||
| 133 | "move.d $sp,$r11\n\t" \ | ||
| 134 | "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \ | ||
| 135 | UNBLOCK_IRQ(mask) \ | ||
| 136 | "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \ | ||
| 137 | "jump ret_from_intr\n\t" \ | ||
| 138 | "bad_IRQ" #nr "_interrupt:\n\t" \ | ||
| 139 | "push $r0\n\t" \ | ||
| 140 | BLOCK_IRQ(mask,nr) \ | ||
| 141 | "pop $r0\n\t" \ | ||
| 142 | "reti\n\t" \ | ||
| 143 | "nop\n"); | ||
| 144 | |||
| 145 | /* This is subtle. The timer interrupt is crucial and it should not be disabled for | ||
| 146 | * too long. However, if it had been a normal interrupt as per BUILD_IRQ, it would | ||
| 147 | * have been BLOCK'ed, and then softirq's are run before we return here to UNBLOCK. | ||
| 148 | * If the softirq's take too much time to run, the timer irq won't run and the | ||
| 149 | * watchdog will kill us. | ||
| 150 | * | ||
| 151 | * Furthermore, if a lot of other irq's occur before we return here, the multiple_irq | ||
| 152 | * handler is run and it prioritizes the timer interrupt. However if we had BLOCK'ed | ||
| 153 | * it here, we would not get the multiple_irq at all. | ||
| 154 | * | ||
| 155 | * The non-blocking here is based on the knowledge that the timer interrupt is | ||
| 156 | * registred as a fast interrupt (SA_INTERRUPT) so that we _know_ there will not | ||
| 157 | * be an sti() before the timer irq handler is run to acknowledge the interrupt. | ||
| 158 | */ | ||
| 159 | |||
| 160 | #define BUILD_TIMER_IRQ(nr,mask) \ | ||
| 161 | void IRQ_NAME(nr); \ | ||
| 162 | void sIRQ_NAME(nr); \ | ||
| 163 | void BAD_IRQ_NAME(nr); \ | ||
| 164 | __asm__ ( \ | ||
| 165 | ".text\n\t" \ | ||
| 166 | "IRQ" #nr "_interrupt:\n\t" \ | ||
| 167 | SAVE_ALL \ | ||
| 168 | "sIRQ" #nr "_interrupt:\n\t" /* shortcut for the multiple irq handler */ \ | ||
| 169 | "moveq "#nr",$r10\n\t" \ | ||
| 170 | "move.d $sp,$r11\n\t" \ | ||
| 171 | "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \ | ||
| 172 | "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \ | ||
| 173 | "jump ret_from_intr\n\t" \ | ||
| 174 | "bad_IRQ" #nr "_interrupt:\n\t" \ | ||
| 175 | "push $r0\n\t" \ | ||
| 176 | BLOCK_IRQ(mask,nr) \ | ||
| 177 | "pop $r0\n\t" \ | ||
| 178 | "reti\n\t" \ | ||
| 179 | "nop\n"); | ||
| 180 | |||
| 181 | #endif | ||
diff --git a/include/asm-cris/arch-v10/mmu.h b/include/asm-cris/arch-v10/mmu.h new file mode 100644 index 000000000000..d18aa00e50bc --- /dev/null +++ b/include/asm-cris/arch-v10/mmu.h | |||
| @@ -0,0 +1,106 @@ | |||
| 1 | /* | ||
| 2 | * CRIS MMU constants and PTE layout | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifndef _CRIS_ARCH_MMU_H | ||
| 6 | #define _CRIS_ARCH_MMU_H | ||
| 7 | |||
| 8 | /* type used in struct mm to couple an MMU context to an active mm */ | ||
| 9 | |||
| 10 | typedef unsigned int mm_context_t; | ||
| 11 | |||
| 12 | /* kernel memory segments */ | ||
| 13 | |||
| 14 | #define KSEG_F 0xf0000000UL | ||
| 15 | #define KSEG_E 0xe0000000UL | ||
| 16 | #define KSEG_D 0xd0000000UL | ||
| 17 | #define KSEG_C 0xc0000000UL | ||
| 18 | #define KSEG_B 0xb0000000UL | ||
| 19 | #define KSEG_A 0xa0000000UL | ||
| 20 | #define KSEG_9 0x90000000UL | ||
| 21 | #define KSEG_8 0x80000000UL | ||
| 22 | #define KSEG_7 0x70000000UL | ||
| 23 | #define KSEG_6 0x60000000UL | ||
| 24 | #define KSEG_5 0x50000000UL | ||
| 25 | #define KSEG_4 0x40000000UL | ||
| 26 | #define KSEG_3 0x30000000UL | ||
| 27 | #define KSEG_2 0x20000000UL | ||
| 28 | #define KSEG_1 0x10000000UL | ||
| 29 | #define KSEG_0 0x00000000UL | ||
| 30 | |||
| 31 | /* CRIS PTE bits (see R_TLB_LO in the register description) | ||
| 32 | * | ||
| 33 | * Bit: 31-13 12-------4 3 2 1 0 | ||
| 34 | * ________________________________________________ | ||
| 35 | * | pfn | reserved | global | valid | kernel | we | | ||
| 36 | * |_____|__________|________|_______|________|_____| | ||
| 37 | * | ||
| 38 | * (pfn = physical frame number) | ||
| 39 | */ | ||
| 40 | |||
| 41 | /* Real HW-based PTE bits. We use some synonym names so that | ||
| 42 | * things become less confusing in combination with the SW-based | ||
| 43 | * bits further below. | ||
| 44 | * | ||
| 45 | */ | ||
| 46 | |||
| 47 | #define _PAGE_WE (1<<0) /* page is write-enabled */ | ||
| 48 | #define _PAGE_SILENT_WRITE (1<<0) /* synonym */ | ||
| 49 | #define _PAGE_KERNEL (1<<1) /* page is kernel only */ | ||
| 50 | #define _PAGE_VALID (1<<2) /* page is valid */ | ||
| 51 | #define _PAGE_SILENT_READ (1<<2) /* synonym */ | ||
| 52 | #define _PAGE_GLOBAL (1<<3) /* global page - context is ignored */ | ||
| 53 | |||
| 54 | /* Bits the HW doesn't care about but the kernel uses them in SW */ | ||
| 55 | |||
| 56 | #define _PAGE_PRESENT (1<<4) /* page present in memory */ | ||
| 57 | #define _PAGE_FILE (1<<5) /* set: pagecache, unset: swap (when !PRESENT) */ | ||
| 58 | #define _PAGE_ACCESSED (1<<5) /* simulated in software using valid bit */ | ||
| 59 | #define _PAGE_MODIFIED (1<<6) /* simulated in software using we bit */ | ||
| 60 | #define _PAGE_READ (1<<7) /* read-enabled */ | ||
| 61 | #define _PAGE_WRITE (1<<8) /* write-enabled */ | ||
| 62 | |||
| 63 | /* Define some higher level generic page attributes. */ | ||
| 64 | |||
| 65 | #define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) | ||
| 66 | #define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) | ||
| 67 | |||
| 68 | #define _PAGE_TABLE (_PAGE_PRESENT | __READABLE | __WRITEABLE) | ||
| 69 | #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED) | ||
| 70 | |||
| 71 | #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED) | ||
| 72 | #define PAGE_SHARED __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \ | ||
| 73 | _PAGE_ACCESSED) | ||
| 74 | #define PAGE_COPY __pgprot(_PAGE_PRESENT | __READABLE) // | _PAGE_COW | ||
| 75 | #define PAGE_READONLY __pgprot(_PAGE_PRESENT | __READABLE) | ||
| 76 | #define PAGE_KERNEL __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | \ | ||
| 77 | _PAGE_PRESENT | __READABLE | __WRITEABLE) | ||
| 78 | #define _KERNPG_TABLE (_PAGE_TABLE | _PAGE_KERNEL) | ||
| 79 | |||
| 80 | /* | ||
| 81 | * CRIS can't do page protection for execute, and considers read the same. | ||
| 82 | * Also, write permissions imply read permissions. This is the closest we can | ||
| 83 | * get.. | ||
| 84 | */ | ||
| 85 | |||
| 86 | #define __P000 PAGE_NONE | ||
| 87 | #define __P001 PAGE_READONLY | ||
| 88 | #define __P010 PAGE_COPY | ||
| 89 | #define __P011 PAGE_COPY | ||
| 90 | #define __P100 PAGE_READONLY | ||
| 91 | #define __P101 PAGE_READONLY | ||
| 92 | #define __P110 PAGE_COPY | ||
| 93 | #define __P111 PAGE_COPY | ||
| 94 | |||
| 95 | #define __S000 PAGE_NONE | ||
| 96 | #define __S001 PAGE_READONLY | ||
| 97 | #define __S010 PAGE_SHARED | ||
| 98 | #define __S011 PAGE_SHARED | ||
| 99 | #define __S100 PAGE_READONLY | ||
| 100 | #define __S101 PAGE_READONLY | ||
| 101 | #define __S110 PAGE_SHARED | ||
| 102 | #define __S111 PAGE_SHARED | ||
| 103 | |||
| 104 | #define PTE_FILE_MAX_BITS 26 | ||
| 105 | |||
| 106 | #endif | ||
diff --git a/include/asm-cris/arch-v10/offset.h b/include/asm-cris/arch-v10/offset.h new file mode 100644 index 000000000000..fcbd77eab281 --- /dev/null +++ b/include/asm-cris/arch-v10/offset.h | |||
| @@ -0,0 +1,33 @@ | |||
| 1 | #ifndef __ASM_OFFSETS_H__ | ||
| 2 | #define __ASM_OFFSETS_H__ | ||
| 3 | /* | ||
| 4 | * DO NOT MODIFY. | ||
| 5 | * | ||
| 6 | * This file was generated by arch/cris/Makefile | ||
| 7 | * | ||
| 8 | */ | ||
| 9 | |||
| 10 | #define PT_orig_r10 4 /* offsetof(struct pt_regs, orig_r10) */ | ||
| 11 | #define PT_r13 8 /* offsetof(struct pt_regs, r13) */ | ||
| 12 | #define PT_r12 12 /* offsetof(struct pt_regs, r12) */ | ||
| 13 | #define PT_r11 16 /* offsetof(struct pt_regs, r11) */ | ||
| 14 | #define PT_r10 20 /* offsetof(struct pt_regs, r10) */ | ||
| 15 | #define PT_r9 24 /* offsetof(struct pt_regs, r9) */ | ||
| 16 | #define PT_mof 64 /* offsetof(struct pt_regs, mof) */ | ||
| 17 | #define PT_dccr 68 /* offsetof(struct pt_regs, dccr) */ | ||
| 18 | #define PT_srp 72 /* offsetof(struct pt_regs, srp) */ | ||
| 19 | |||
| 20 | #define TI_task 0 /* offsetof(struct thread_info, task) */ | ||
| 21 | #define TI_flags 8 /* offsetof(struct thread_info, flags) */ | ||
| 22 | #define TI_preempt_count 16 /* offsetof(struct thread_info, preempt_count) */ | ||
| 23 | |||
| 24 | #define THREAD_ksp 0 /* offsetof(struct thread_struct, ksp) */ | ||
| 25 | #define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */ | ||
| 26 | #define THREAD_dccr 8 /* offsetof(struct thread_struct, dccr) */ | ||
| 27 | |||
| 28 | #define TASK_pid 133 /* offsetof(struct task_struct, pid) */ | ||
| 29 | |||
| 30 | #define LCLONE_VM 256 /* CLONE_VM */ | ||
| 31 | #define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */ | ||
| 32 | |||
| 33 | #endif | ||
diff --git a/include/asm-cris/arch-v10/page.h b/include/asm-cris/arch-v10/page.h new file mode 100644 index 000000000000..407e6e68f49e --- /dev/null +++ b/include/asm-cris/arch-v10/page.h | |||
| @@ -0,0 +1,31 @@ | |||
| 1 | #ifndef _CRIS_ARCH_PAGE_H | ||
| 2 | #define _CRIS_ARCH_PAGE_H | ||
| 3 | |||
| 4 | #include <linux/config.h> | ||
| 5 | |||
| 6 | #ifdef __KERNEL__ | ||
| 7 | |||
| 8 | /* This handles the memory map.. */ | ||
| 9 | #ifdef CONFIG_CRIS_LOW_MAP | ||
| 10 | #define PAGE_OFFSET KSEG_6 /* kseg_6 is mapped to physical ram */ | ||
| 11 | #else | ||
| 12 | #define PAGE_OFFSET KSEG_C /* kseg_c is mapped to physical ram */ | ||
| 13 | #endif | ||
| 14 | |||
| 15 | /* macros to convert between really physical and virtual addresses | ||
| 16 | * by stripping a selected bit, we can convert between KSEG_x and 0x40000000 where | ||
| 17 | * the DRAM really resides | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifdef CONFIG_CRIS_LOW_MAP | ||
| 21 | /* we have DRAM virtually at 0x6 */ | ||
| 22 | #define __pa(x) ((unsigned long)(x) & 0xdfffffff) | ||
| 23 | #define __va(x) ((void *)((unsigned long)(x) | 0x20000000)) | ||
| 24 | #else | ||
| 25 | /* we have DRAM virtually at 0xc */ | ||
| 26 | #define __pa(x) ((unsigned long)(x) & 0x7fffffff) | ||
| 27 | #define __va(x) ((void *)((unsigned long)(x) | 0x80000000)) | ||
| 28 | #endif | ||
| 29 | |||
| 30 | #endif | ||
| 31 | #endif | ||
diff --git a/include/asm-cris/arch-v10/pgtable.h b/include/asm-cris/arch-v10/pgtable.h new file mode 100644 index 000000000000..2a2576d1fc97 --- /dev/null +++ b/include/asm-cris/arch-v10/pgtable.h | |||
| @@ -0,0 +1,17 @@ | |||
| 1 | #ifndef _CRIS_ARCH_PGTABLE_H | ||
| 2 | #define _CRIS_ARCH_PGTABLE_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * Kernels own virtual memory area. | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifdef CONFIG_CRIS_LOW_MAP | ||
| 9 | #define VMALLOC_START KSEG_7 | ||
| 10 | #define VMALLOC_END KSEG_8 | ||
| 11 | #else | ||
| 12 | #define VMALLOC_START KSEG_D | ||
| 13 | #define VMALLOC_END KSEG_E | ||
| 14 | #endif | ||
| 15 | |||
| 16 | #endif | ||
| 17 | |||
diff --git a/include/asm-cris/arch-v10/processor.h b/include/asm-cris/arch-v10/processor.h new file mode 100644 index 000000000000..9355d8675a58 --- /dev/null +++ b/include/asm-cris/arch-v10/processor.h | |||
| @@ -0,0 +1,62 @@ | |||
| 1 | #ifndef __ASM_CRIS_ARCH_PROCESSOR_H | ||
| 2 | #define __ASM_CRIS_ARCH_PROCESSOR_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * Default implementation of macro that returns current | ||
| 6 | * instruction pointer ("program counter"). | ||
| 7 | */ | ||
| 8 | #define current_text_addr() ({void *pc; __asm__ ("move.d $pc,%0" : "=rm" (pc)); pc; }) | ||
| 9 | |||
| 10 | /* CRIS has no problems with write protection */ | ||
| 11 | #define wp_works_ok 1 | ||
| 12 | |||
| 13 | /* CRIS thread_struct. this really has nothing to do with the processor itself, since | ||
| 14 | * CRIS does not do any hardware task-switching, but it's here for legacy reasons. | ||
| 15 | * The thread_struct here is used when task-switching using _resume defined in entry.S. | ||
| 16 | * The offsets here are hardcoded into _resume - if you change this struct, you need to | ||
| 17 | * change them as well!!! | ||
| 18 | */ | ||
| 19 | |||
| 20 | struct thread_struct { | ||
| 21 | unsigned long ksp; /* kernel stack pointer */ | ||
| 22 | unsigned long usp; /* user stack pointer */ | ||
| 23 | unsigned long dccr; /* saved flag register */ | ||
| 24 | }; | ||
| 25 | |||
| 26 | /* | ||
| 27 | * User space process size. This is hardcoded into a few places, | ||
| 28 | * so don't change it unless you know what you are doing. | ||
| 29 | */ | ||
| 30 | |||
| 31 | #ifdef CONFIG_CRIS_LOW_MAP | ||
| 32 | #define TASK_SIZE (0x50000000UL) /* 1.25 GB */ | ||
| 33 | #else | ||
| 34 | #define TASK_SIZE (0xA0000000UL) /* 2.56 GB */ | ||
| 35 | #endif | ||
| 36 | |||
| 37 | #define INIT_THREAD { \ | ||
| 38 | 0, 0, 0x20 } /* ccr = int enable, nothing else */ | ||
| 39 | |||
| 40 | #define KSTK_EIP(tsk) \ | ||
| 41 | ({ \ | ||
| 42 | unsigned long eip = 0; \ | ||
| 43 | unsigned long regs = (unsigned long)user_regs(tsk); \ | ||
| 44 | if (regs > PAGE_SIZE && \ | ||
| 45 | virt_addr_valid(regs)) \ | ||
| 46 | eip = ((struct pt_regs *)regs)->irp; \ | ||
| 47 | eip; \ | ||
| 48 | }) | ||
| 49 | |||
| 50 | /* give the thread a program location | ||
| 51 | * set user-mode (The 'U' flag (User mode flag) is CCR/DCCR bit 8) | ||
| 52 | * switch user-stackpointer | ||
| 53 | */ | ||
| 54 | |||
| 55 | #define start_thread(regs, ip, usp) do { \ | ||
| 56 | set_fs(USER_DS); \ | ||
| 57 | regs->irp = ip; \ | ||
| 58 | regs->dccr |= 1 << U_DCCR_BITNR; \ | ||
| 59 | wrusp(usp); \ | ||
| 60 | } while(0) | ||
| 61 | |||
| 62 | #endif | ||
diff --git a/include/asm-cris/arch-v10/ptrace.h b/include/asm-cris/arch-v10/ptrace.h new file mode 100644 index 000000000000..fb14c5ee37f9 --- /dev/null +++ b/include/asm-cris/arch-v10/ptrace.h | |||
| @@ -0,0 +1,115 @@ | |||
| 1 | #ifndef _CRIS_ARCH_PTRACE_H | ||
| 2 | #define _CRIS_ARCH_PTRACE_H | ||
| 3 | |||
| 4 | /* Frame types */ | ||
| 5 | |||
| 6 | #define CRIS_FRAME_NORMAL 0 /* normal frame without SBFS stacking */ | ||
| 7 | #define CRIS_FRAME_BUSFAULT 1 /* frame stacked using SBFS, need RBF return | ||
| 8 | path */ | ||
| 9 | |||
| 10 | /* Register numbers in the ptrace system call interface */ | ||
| 11 | |||
| 12 | #define PT_FRAMETYPE 0 | ||
| 13 | #define PT_ORIG_R10 1 | ||
| 14 | #define PT_R13 2 | ||
| 15 | #define PT_R12 3 | ||
| 16 | #define PT_R11 4 | ||
| 17 | #define PT_R10 5 | ||
| 18 | #define PT_R9 6 | ||
| 19 | #define PT_R8 7 | ||
| 20 | #define PT_R7 8 | ||
| 21 | #define PT_R6 9 | ||
| 22 | #define PT_R5 10 | ||
| 23 | #define PT_R4 11 | ||
| 24 | #define PT_R3 12 | ||
| 25 | #define PT_R2 13 | ||
| 26 | #define PT_R1 14 | ||
| 27 | #define PT_R0 15 | ||
| 28 | #define PT_MOF 16 | ||
| 29 | #define PT_DCCR 17 | ||
| 30 | #define PT_SRP 18 | ||
| 31 | #define PT_IRP 19 /* This is actually the debugged process' PC */ | ||
| 32 | #define PT_CSRINSTR 20 /* CPU Status record remnants - | ||
| 33 | valid if frametype == busfault */ | ||
| 34 | #define PT_CSRADDR 21 | ||
| 35 | #define PT_CSRDATA 22 | ||
| 36 | #define PT_USP 23 /* special case - USP is not in the pt_regs */ | ||
| 37 | #define PT_MAX 23 | ||
| 38 | |||
| 39 | /* Condition code bit numbers. The same numbers apply to CCR of course, | ||
| 40 | but we use DCCR everywhere else, so let's try and be consistent. */ | ||
| 41 | #define C_DCCR_BITNR 0 | ||
| 42 | #define V_DCCR_BITNR 1 | ||
| 43 | #define Z_DCCR_BITNR 2 | ||
| 44 | #define N_DCCR_BITNR 3 | ||
| 45 | #define X_DCCR_BITNR 4 | ||
| 46 | #define I_DCCR_BITNR 5 | ||
| 47 | #define B_DCCR_BITNR 6 | ||
| 48 | #define M_DCCR_BITNR 7 | ||
| 49 | #define U_DCCR_BITNR 8 | ||
| 50 | #define P_DCCR_BITNR 9 | ||
| 51 | #define F_DCCR_BITNR 10 | ||
| 52 | |||
| 53 | /* pt_regs not only specifices the format in the user-struct during | ||
| 54 | * ptrace but is also the frame format used in the kernel prologue/epilogues | ||
| 55 | * themselves | ||
| 56 | */ | ||
| 57 | |||
| 58 | struct pt_regs { | ||
| 59 | unsigned long frametype; /* type of stackframe */ | ||
| 60 | unsigned long orig_r10; | ||
| 61 | /* pushed by movem r13, [sp] in SAVE_ALL, movem pushes backwards */ | ||
| 62 | unsigned long r13; | ||
| 63 | unsigned long r12; | ||
| 64 | unsigned long r11; | ||
| 65 | unsigned long r10; | ||
| 66 | unsigned long r9; | ||
| 67 | unsigned long r8; | ||
| 68 | unsigned long r7; | ||
| 69 | unsigned long r6; | ||
| 70 | unsigned long r5; | ||
| 71 | unsigned long r4; | ||
| 72 | unsigned long r3; | ||
| 73 | unsigned long r2; | ||
| 74 | unsigned long r1; | ||
| 75 | unsigned long r0; | ||
| 76 | unsigned long mof; | ||
| 77 | unsigned long dccr; | ||
| 78 | unsigned long srp; | ||
| 79 | unsigned long irp; /* This is actually the debugged process' PC */ | ||
| 80 | unsigned long csrinstr; | ||
| 81 | unsigned long csraddr; | ||
| 82 | unsigned long csrdata; | ||
| 83 | }; | ||
| 84 | |||
| 85 | /* switch_stack is the extra stuff pushed onto the stack in _resume (entry.S) | ||
| 86 | * when doing a context-switch. it is used (apart from in resume) when a new | ||
| 87 | * thread is made and we need to make _resume (which is starting it for the | ||
| 88 | * first time) realise what is going on. | ||
| 89 | * | ||
| 90 | * Actually, the use is very close to the thread struct (TSS) in that both the | ||
| 91 | * switch_stack and the TSS are used to keep thread stuff when switching in | ||
| 92 | * _resume. | ||
| 93 | */ | ||
| 94 | |||
| 95 | struct switch_stack { | ||
| 96 | unsigned long r9; | ||
| 97 | unsigned long r8; | ||
| 98 | unsigned long r7; | ||
| 99 | unsigned long r6; | ||
| 100 | unsigned long r5; | ||
| 101 | unsigned long r4; | ||
| 102 | unsigned long r3; | ||
| 103 | unsigned long r2; | ||
| 104 | unsigned long r1; | ||
| 105 | unsigned long r0; | ||
| 106 | unsigned long return_ip; /* ip that _resume will return to */ | ||
| 107 | }; | ||
| 108 | |||
| 109 | /* bit 8 is user-mode flag */ | ||
| 110 | #define user_mode(regs) (((regs)->dccr & 0x100) != 0) | ||
| 111 | #define instruction_pointer(regs) ((regs)->irp) | ||
| 112 | #define profile_pc(regs) instruction_pointer(regs) | ||
| 113 | extern void show_regs(struct pt_regs *); | ||
| 114 | |||
| 115 | #endif | ||
diff --git a/include/asm-cris/arch-v10/sv_addr.agh b/include/asm-cris/arch-v10/sv_addr.agh new file mode 100644 index 000000000000..6ac3a7bc9760 --- /dev/null +++ b/include/asm-cris/arch-v10/sv_addr.agh | |||
| @@ -0,0 +1,7306 @@ | |||
| 1 | /* | ||
| 2 | !* This file was automatically generated by /n/asic/bin/reg_macro_gen | ||
| 3 | !* from the file `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd'. | ||
| 4 | !* Editing within this file is thus not recommended, | ||
| 5 | !* make the changes in `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd' instead. | ||
| 6 | !*/ | ||
| 7 | |||
| 8 | |||
| 9 | /* | ||
| 10 | !* Bus interface configuration registers | ||
| 11 | !*/ | ||
| 12 | |||
| 13 | #define R_WAITSTATES (IO_TYPECAST_UDWORD 0xb0000000) | ||
| 14 | #define R_WAITSTATES__pcs4_7_zw__BITNR 30 | ||
| 15 | #define R_WAITSTATES__pcs4_7_zw__WIDTH 2 | ||
| 16 | #define R_WAITSTATES__pcs4_7_ew__BITNR 28 | ||
| 17 | #define R_WAITSTATES__pcs4_7_ew__WIDTH 2 | ||
| 18 | #define R_WAITSTATES__pcs4_7_lw__BITNR 24 | ||
| 19 | #define R_WAITSTATES__pcs4_7_lw__WIDTH 4 | ||
| 20 | #define R_WAITSTATES__pcs0_3_zw__BITNR 22 | ||
| 21 | #define R_WAITSTATES__pcs0_3_zw__WIDTH 2 | ||
| 22 | #define R_WAITSTATES__pcs0_3_ew__BITNR 20 | ||
| 23 | #define R_WAITSTATES__pcs0_3_ew__WIDTH 2 | ||
| 24 | #define R_WAITSTATES__pcs0_3_lw__BITNR 16 | ||
| 25 | #define R_WAITSTATES__pcs0_3_lw__WIDTH 4 | ||
| 26 | #define R_WAITSTATES__sram_zw__BITNR 14 | ||
| 27 | #define R_WAITSTATES__sram_zw__WIDTH 2 | ||
| 28 | #define R_WAITSTATES__sram_ew__BITNR 12 | ||
| 29 | #define R_WAITSTATES__sram_ew__WIDTH 2 | ||
| 30 | #define R_WAITSTATES__sram_lw__BITNR 8 | ||
| 31 | #define R_WAITSTATES__sram_lw__WIDTH 4 | ||
| 32 | #define R_WAITSTATES__flash_zw__BITNR 6 | ||
| 33 | #define R_WAITSTATES__flash_zw__WIDTH 2 | ||
| 34 | #define R_WAITSTATES__flash_ew__BITNR 4 | ||
| 35 | #define R_WAITSTATES__flash_ew__WIDTH 2 | ||
| 36 | #define R_WAITSTATES__flash_lw__BITNR 0 | ||
| 37 | #define R_WAITSTATES__flash_lw__WIDTH 4 | ||
| 38 | |||
| 39 | #define R_BUS_CONFIG (IO_TYPECAST_UDWORD 0xb0000004) | ||
| 40 | #define R_BUS_CONFIG__sram_type__BITNR 9 | ||
| 41 | #define R_BUS_CONFIG__sram_type__WIDTH 1 | ||
| 42 | #define R_BUS_CONFIG__sram_type__cwe 1 | ||
| 43 | #define R_BUS_CONFIG__sram_type__bwe 0 | ||
| 44 | #define R_BUS_CONFIG__dma_burst__BITNR 8 | ||
| 45 | #define R_BUS_CONFIG__dma_burst__WIDTH 1 | ||
| 46 | #define R_BUS_CONFIG__dma_burst__burst16 1 | ||
| 47 | #define R_BUS_CONFIG__dma_burst__burst32 0 | ||
| 48 | #define R_BUS_CONFIG__pcs4_7_wr__BITNR 7 | ||
| 49 | #define R_BUS_CONFIG__pcs4_7_wr__WIDTH 1 | ||
| 50 | #define R_BUS_CONFIG__pcs4_7_wr__ext 1 | ||
| 51 | #define R_BUS_CONFIG__pcs4_7_wr__norm 0 | ||
| 52 | #define R_BUS_CONFIG__pcs0_3_wr__BITNR 6 | ||
| 53 | #define R_BUS_CONFIG__pcs0_3_wr__WIDTH 1 | ||
| 54 | #define R_BUS_CONFIG__pcs0_3_wr__ext 1 | ||
| 55 | #define R_BUS_CONFIG__pcs0_3_wr__norm 0 | ||
| 56 | #define R_BUS_CONFIG__sram_wr__BITNR 5 | ||
| 57 | #define R_BUS_CONFIG__sram_wr__WIDTH 1 | ||
| 58 | #define R_BUS_CONFIG__sram_wr__ext 1 | ||
| 59 | #define R_BUS_CONFIG__sram_wr__norm 0 | ||
| 60 | #define R_BUS_CONFIG__flash_wr__BITNR 4 | ||
| 61 | #define R_BUS_CONFIG__flash_wr__WIDTH 1 | ||
| 62 | #define R_BUS_CONFIG__flash_wr__ext 1 | ||
| 63 | #define R_BUS_CONFIG__flash_wr__norm 0 | ||
| 64 | #define R_BUS_CONFIG__pcs4_7_bw__BITNR 3 | ||
| 65 | #define R_BUS_CONFIG__pcs4_7_bw__WIDTH 1 | ||
| 66 | #define R_BUS_CONFIG__pcs4_7_bw__bw32 1 | ||
| 67 | #define R_BUS_CONFIG__pcs4_7_bw__bw16 0 | ||
| 68 | #define R_BUS_CONFIG__pcs0_3_bw__BITNR 2 | ||
| 69 | #define R_BUS_CONFIG__pcs0_3_bw__WIDTH 1 | ||
| 70 | #define R_BUS_CONFIG__pcs0_3_bw__bw32 1 | ||
| 71 | #define R_BUS_CONFIG__pcs0_3_bw__bw16 0 | ||
| 72 | #define R_BUS_CONFIG__sram_bw__BITNR 1 | ||
| 73 | #define R_BUS_CONFIG__sram_bw__WIDTH 1 | ||
| 74 | #define R_BUS_CONFIG__sram_bw__bw32 1 | ||
| 75 | #define R_BUS_CONFIG__sram_bw__bw16 0 | ||
| 76 | #define R_BUS_CONFIG__flash_bw__BITNR 0 | ||
| 77 | #define R_BUS_CONFIG__flash_bw__WIDTH 1 | ||
| 78 | #define R_BUS_CONFIG__flash_bw__bw32 1 | ||
| 79 | #define R_BUS_CONFIG__flash_bw__bw16 0 | ||
| 80 | |||
| 81 | #define R_BUS_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000004) | ||
| 82 | #define R_BUS_STATUS__pll_lock_tm__BITNR 5 | ||
| 83 | #define R_BUS_STATUS__pll_lock_tm__WIDTH 1 | ||
| 84 | #define R_BUS_STATUS__pll_lock_tm__expired 0 | ||
| 85 | #define R_BUS_STATUS__pll_lock_tm__counting 1 | ||
| 86 | #define R_BUS_STATUS__both_faults__BITNR 4 | ||
| 87 | #define R_BUS_STATUS__both_faults__WIDTH 1 | ||
| 88 | #define R_BUS_STATUS__both_faults__no 0 | ||
| 89 | #define R_BUS_STATUS__both_faults__yes 1 | ||
| 90 | #define R_BUS_STATUS__bsen___BITNR 3 | ||
| 91 | #define R_BUS_STATUS__bsen___WIDTH 1 | ||
| 92 | #define R_BUS_STATUS__bsen___enable 0 | ||
| 93 | #define R_BUS_STATUS__bsen___disable 1 | ||
| 94 | #define R_BUS_STATUS__boot__BITNR 1 | ||
| 95 | #define R_BUS_STATUS__boot__WIDTH 2 | ||
| 96 | #define R_BUS_STATUS__boot__uncached 0 | ||
| 97 | #define R_BUS_STATUS__boot__serial 1 | ||
| 98 | #define R_BUS_STATUS__boot__network 2 | ||
| 99 | #define R_BUS_STATUS__boot__parallel 3 | ||
| 100 | #define R_BUS_STATUS__flashw__BITNR 0 | ||
| 101 | #define R_BUS_STATUS__flashw__WIDTH 1 | ||
| 102 | #define R_BUS_STATUS__flashw__bw32 1 | ||
| 103 | #define R_BUS_STATUS__flashw__bw16 0 | ||
| 104 | |||
| 105 | #define R_DRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008) | ||
| 106 | #define R_DRAM_TIMING__sdram__BITNR 31 | ||
| 107 | #define R_DRAM_TIMING__sdram__WIDTH 1 | ||
| 108 | #define R_DRAM_TIMING__sdram__enable 1 | ||
| 109 | #define R_DRAM_TIMING__sdram__disable 0 | ||
| 110 | #define R_DRAM_TIMING__ref__BITNR 14 | ||
| 111 | #define R_DRAM_TIMING__ref__WIDTH 2 | ||
| 112 | #define R_DRAM_TIMING__ref__e52us 0 | ||
| 113 | #define R_DRAM_TIMING__ref__e13us 1 | ||
| 114 | #define R_DRAM_TIMING__ref__e8700ns 2 | ||
| 115 | #define R_DRAM_TIMING__ref__disable 3 | ||
| 116 | #define R_DRAM_TIMING__rp__BITNR 12 | ||
| 117 | #define R_DRAM_TIMING__rp__WIDTH 2 | ||
| 118 | #define R_DRAM_TIMING__rs__BITNR 10 | ||
| 119 | #define R_DRAM_TIMING__rs__WIDTH 2 | ||
| 120 | #define R_DRAM_TIMING__rh__BITNR 8 | ||
| 121 | #define R_DRAM_TIMING__rh__WIDTH 2 | ||
| 122 | #define R_DRAM_TIMING__w__BITNR 7 | ||
| 123 | #define R_DRAM_TIMING__w__WIDTH 1 | ||
| 124 | #define R_DRAM_TIMING__w__norm 0 | ||
| 125 | #define R_DRAM_TIMING__w__ext 1 | ||
| 126 | #define R_DRAM_TIMING__c__BITNR 6 | ||
| 127 | #define R_DRAM_TIMING__c__WIDTH 1 | ||
| 128 | #define R_DRAM_TIMING__c__norm 0 | ||
| 129 | #define R_DRAM_TIMING__c__ext 1 | ||
| 130 | #define R_DRAM_TIMING__cz__BITNR 4 | ||
| 131 | #define R_DRAM_TIMING__cz__WIDTH 2 | ||
| 132 | #define R_DRAM_TIMING__cp__BITNR 2 | ||
| 133 | #define R_DRAM_TIMING__cp__WIDTH 2 | ||
| 134 | #define R_DRAM_TIMING__cw__BITNR 0 | ||
| 135 | #define R_DRAM_TIMING__cw__WIDTH 2 | ||
| 136 | |||
| 137 | #define R_SDRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008) | ||
| 138 | #define R_SDRAM_TIMING__sdram__BITNR 31 | ||
| 139 | #define R_SDRAM_TIMING__sdram__WIDTH 1 | ||
| 140 | #define R_SDRAM_TIMING__sdram__enable 1 | ||
| 141 | #define R_SDRAM_TIMING__sdram__disable 0 | ||
| 142 | #define R_SDRAM_TIMING__mrs_data__BITNR 16 | ||
| 143 | #define R_SDRAM_TIMING__mrs_data__WIDTH 15 | ||
| 144 | #define R_SDRAM_TIMING__ref__BITNR 14 | ||
| 145 | #define R_SDRAM_TIMING__ref__WIDTH 2 | ||
| 146 | #define R_SDRAM_TIMING__ref__e52us 0 | ||
| 147 | #define R_SDRAM_TIMING__ref__e13us 1 | ||
| 148 | #define R_SDRAM_TIMING__ref__e6500ns 2 | ||
| 149 | #define R_SDRAM_TIMING__ref__disable 3 | ||
| 150 | #define R_SDRAM_TIMING__ddr__BITNR 13 | ||
| 151 | #define R_SDRAM_TIMING__ddr__WIDTH 1 | ||
| 152 | #define R_SDRAM_TIMING__ddr__on 1 | ||
| 153 | #define R_SDRAM_TIMING__ddr__off 0 | ||
| 154 | #define R_SDRAM_TIMING__clk100__BITNR 12 | ||
| 155 | #define R_SDRAM_TIMING__clk100__WIDTH 1 | ||
| 156 | #define R_SDRAM_TIMING__clk100__on 1 | ||
| 157 | #define R_SDRAM_TIMING__clk100__off 0 | ||
| 158 | #define R_SDRAM_TIMING__ps__BITNR 11 | ||
| 159 | #define R_SDRAM_TIMING__ps__WIDTH 1 | ||
| 160 | #define R_SDRAM_TIMING__ps__on 1 | ||
| 161 | #define R_SDRAM_TIMING__ps__off 0 | ||
| 162 | #define R_SDRAM_TIMING__cmd__BITNR 9 | ||
| 163 | #define R_SDRAM_TIMING__cmd__WIDTH 2 | ||
| 164 | #define R_SDRAM_TIMING__cmd__pre 3 | ||
| 165 | #define R_SDRAM_TIMING__cmd__ref 2 | ||
| 166 | #define R_SDRAM_TIMING__cmd__mrs 1 | ||
| 167 | #define R_SDRAM_TIMING__cmd__nop 0 | ||
| 168 | #define R_SDRAM_TIMING__pde__BITNR 8 | ||
| 169 | #define R_SDRAM_TIMING__pde__WIDTH 1 | ||
| 170 | #define R_SDRAM_TIMING__rc__BITNR 6 | ||
| 171 | #define R_SDRAM_TIMING__rc__WIDTH 2 | ||
| 172 | #define R_SDRAM_TIMING__rp__BITNR 4 | ||
| 173 | #define R_SDRAM_TIMING__rp__WIDTH 2 | ||
| 174 | #define R_SDRAM_TIMING__rcd__BITNR 2 | ||
| 175 | #define R_SDRAM_TIMING__rcd__WIDTH 2 | ||
| 176 | #define R_SDRAM_TIMING__cl__BITNR 0 | ||
| 177 | #define R_SDRAM_TIMING__cl__WIDTH 2 | ||
| 178 | |||
| 179 | #define R_DRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c) | ||
| 180 | #define R_DRAM_CONFIG__wmm1__BITNR 31 | ||
| 181 | #define R_DRAM_CONFIG__wmm1__WIDTH 1 | ||
| 182 | #define R_DRAM_CONFIG__wmm1__wmm 1 | ||
| 183 | #define R_DRAM_CONFIG__wmm1__norm 0 | ||
| 184 | #define R_DRAM_CONFIG__wmm0__BITNR 30 | ||
| 185 | #define R_DRAM_CONFIG__wmm0__WIDTH 1 | ||
| 186 | #define R_DRAM_CONFIG__wmm0__wmm 1 | ||
| 187 | #define R_DRAM_CONFIG__wmm0__norm 0 | ||
| 188 | #define R_DRAM_CONFIG__sh1__BITNR 27 | ||
| 189 | #define R_DRAM_CONFIG__sh1__WIDTH 3 | ||
| 190 | #define R_DRAM_CONFIG__sh0__BITNR 24 | ||
| 191 | #define R_DRAM_CONFIG__sh0__WIDTH 3 | ||
| 192 | #define R_DRAM_CONFIG__w__BITNR 23 | ||
| 193 | #define R_DRAM_CONFIG__w__WIDTH 1 | ||
| 194 | #define R_DRAM_CONFIG__w__bw16 0 | ||
| 195 | #define R_DRAM_CONFIG__w__bw32 1 | ||
| 196 | #define R_DRAM_CONFIG__c__BITNR 22 | ||
| 197 | #define R_DRAM_CONFIG__c__WIDTH 1 | ||
| 198 | #define R_DRAM_CONFIG__c__byte 0 | ||
| 199 | #define R_DRAM_CONFIG__c__bank 1 | ||
| 200 | #define R_DRAM_CONFIG__e__BITNR 21 | ||
| 201 | #define R_DRAM_CONFIG__e__WIDTH 1 | ||
| 202 | #define R_DRAM_CONFIG__e__fast 0 | ||
| 203 | #define R_DRAM_CONFIG__e__edo 1 | ||
| 204 | #define R_DRAM_CONFIG__group_sel__BITNR 16 | ||
| 205 | #define R_DRAM_CONFIG__group_sel__WIDTH 5 | ||
| 206 | #define R_DRAM_CONFIG__group_sel__grp0 0 | ||
| 207 | #define R_DRAM_CONFIG__group_sel__grp1 1 | ||
| 208 | #define R_DRAM_CONFIG__group_sel__bit9 9 | ||
| 209 | #define R_DRAM_CONFIG__group_sel__bit10 10 | ||
| 210 | #define R_DRAM_CONFIG__group_sel__bit11 11 | ||
| 211 | #define R_DRAM_CONFIG__group_sel__bit12 12 | ||
| 212 | #define R_DRAM_CONFIG__group_sel__bit13 13 | ||
| 213 | #define R_DRAM_CONFIG__group_sel__bit14 14 | ||
| 214 | #define R_DRAM_CONFIG__group_sel__bit15 15 | ||
| 215 | #define R_DRAM_CONFIG__group_sel__bit16 16 | ||
| 216 | #define R_DRAM_CONFIG__group_sel__bit17 17 | ||
| 217 | #define R_DRAM_CONFIG__group_sel__bit18 18 | ||
| 218 | #define R_DRAM_CONFIG__group_sel__bit19 19 | ||
| 219 | #define R_DRAM_CONFIG__group_sel__bit20 20 | ||
| 220 | #define R_DRAM_CONFIG__group_sel__bit21 21 | ||
| 221 | #define R_DRAM_CONFIG__group_sel__bit22 22 | ||
| 222 | #define R_DRAM_CONFIG__group_sel__bit23 23 | ||
| 223 | #define R_DRAM_CONFIG__group_sel__bit24 24 | ||
| 224 | #define R_DRAM_CONFIG__group_sel__bit25 25 | ||
| 225 | #define R_DRAM_CONFIG__group_sel__bit26 26 | ||
| 226 | #define R_DRAM_CONFIG__group_sel__bit27 27 | ||
| 227 | #define R_DRAM_CONFIG__group_sel__bit28 28 | ||
| 228 | #define R_DRAM_CONFIG__group_sel__bit29 29 | ||
| 229 | #define R_DRAM_CONFIG__ca1__BITNR 13 | ||
| 230 | #define R_DRAM_CONFIG__ca1__WIDTH 3 | ||
| 231 | #define R_DRAM_CONFIG__bank23sel__BITNR 8 | ||
| 232 | #define R_DRAM_CONFIG__bank23sel__WIDTH 5 | ||
| 233 | #define R_DRAM_CONFIG__bank23sel__bank0 0 | ||
| 234 | #define R_DRAM_CONFIG__bank23sel__bank1 1 | ||
| 235 | #define R_DRAM_CONFIG__bank23sel__bit9 9 | ||
| 236 | #define R_DRAM_CONFIG__bank23sel__bit10 10 | ||
| 237 | #define R_DRAM_CONFIG__bank23sel__bit11 11 | ||
| 238 | #define R_DRAM_CONFIG__bank23sel__bit12 12 | ||
| 239 | #define R_DRAM_CONFIG__bank23sel__bit13 13 | ||
| 240 | #define R_DRAM_CONFIG__bank23sel__bit14 14 | ||
| 241 | #define R_DRAM_CONFIG__bank23sel__bit15 15 | ||
| 242 | #define R_DRAM_CONFIG__bank23sel__bit16 16 | ||
| 243 | #define R_DRAM_CONFIG__bank23sel__bit17 17 | ||
| 244 | #define R_DRAM_CONFIG__bank23sel__bit18 18 | ||
| 245 | #define R_DRAM_CONFIG__bank23sel__bit19 19 | ||
| 246 | #define R_DRAM_CONFIG__bank23sel__bit20 20 | ||
| 247 | #define R_DRAM_CONFIG__bank23sel__bit21 21 | ||
| 248 | #define R_DRAM_CONFIG__bank23sel__bit22 22 | ||
| 249 | #define R_DRAM_CONFIG__bank23sel__bit23 23 | ||
| 250 | #define R_DRAM_CONFIG__bank23sel__bit24 24 | ||
| 251 | #define R_DRAM_CONFIG__bank23sel__bit25 25 | ||
| 252 | #define R_DRAM_CONFIG__bank23sel__bit26 26 | ||
| 253 | #define R_DRAM_CONFIG__bank23sel__bit27 27 | ||
| 254 | #define R_DRAM_CONFIG__bank23sel__bit28 28 | ||
| 255 | #define R_DRAM_CONFIG__bank23sel__bit29 29 | ||
| 256 | #define R_DRAM_CONFIG__ca0__BITNR 5 | ||
| 257 | #define R_DRAM_CONFIG__ca0__WIDTH 3 | ||
| 258 | #define R_DRAM_CONFIG__bank01sel__BITNR 0 | ||
| 259 | #define R_DRAM_CONFIG__bank01sel__WIDTH 5 | ||
| 260 | #define R_DRAM_CONFIG__bank01sel__bank0 0 | ||
| 261 | #define R_DRAM_CONFIG__bank01sel__bank1 1 | ||
| 262 | #define R_DRAM_CONFIG__bank01sel__bit9 9 | ||
| 263 | #define R_DRAM_CONFIG__bank01sel__bit10 10 | ||
| 264 | #define R_DRAM_CONFIG__bank01sel__bit11 11 | ||
| 265 | #define R_DRAM_CONFIG__bank01sel__bit12 12 | ||
| 266 | #define R_DRAM_CONFIG__bank01sel__bit13 13 | ||
| 267 | #define R_DRAM_CONFIG__bank01sel__bit14 14 | ||
| 268 | #define R_DRAM_CONFIG__bank01sel__bit15 15 | ||
| 269 | #define R_DRAM_CONFIG__bank01sel__bit16 16 | ||
| 270 | #define R_DRAM_CONFIG__bank01sel__bit17 17 | ||
| 271 | #define R_DRAM_CONFIG__bank01sel__bit18 18 | ||
| 272 | #define R_DRAM_CONFIG__bank01sel__bit19 19 | ||
| 273 | #define R_DRAM_CONFIG__bank01sel__bit20 20 | ||
| 274 | #define R_DRAM_CONFIG__bank01sel__bit21 21 | ||
| 275 | #define R_DRAM_CONFIG__bank01sel__bit22 22 | ||
| 276 | #define R_DRAM_CONFIG__bank01sel__bit23 23 | ||
| 277 | #define R_DRAM_CONFIG__bank01sel__bit24 24 | ||
| 278 | #define R_DRAM_CONFIG__bank01sel__bit25 25 | ||
| 279 | #define R_DRAM_CONFIG__bank01sel__bit26 26 | ||
| 280 | #define R_DRAM_CONFIG__bank01sel__bit27 27 | ||
| 281 | #define R_DRAM_CONFIG__bank01sel__bit28 28 | ||
| 282 | #define R_DRAM_CONFIG__bank01sel__bit29 29 | ||
| 283 | |||
| 284 | #define R_SDRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c) | ||
| 285 | #define R_SDRAM_CONFIG__wmm1__BITNR 31 | ||
| 286 | #define R_SDRAM_CONFIG__wmm1__WIDTH 1 | ||
| 287 | #define R_SDRAM_CONFIG__wmm1__wmm 1 | ||
| 288 | #define R_SDRAM_CONFIG__wmm1__norm 0 | ||
| 289 | #define R_SDRAM_CONFIG__wmm0__BITNR 30 | ||
| 290 | #define R_SDRAM_CONFIG__wmm0__WIDTH 1 | ||
| 291 | #define R_SDRAM_CONFIG__wmm0__wmm 1 | ||
| 292 | #define R_SDRAM_CONFIG__wmm0__norm 0 | ||
| 293 | #define R_SDRAM_CONFIG__sh1__BITNR 27 | ||
| 294 | #define R_SDRAM_CONFIG__sh1__WIDTH 3 | ||
| 295 | #define R_SDRAM_CONFIG__sh0__BITNR 24 | ||
| 296 | #define R_SDRAM_CONFIG__sh0__WIDTH 3 | ||
| 297 | #define R_SDRAM_CONFIG__w__BITNR 23 | ||
| 298 | #define R_SDRAM_CONFIG__w__WIDTH 1 | ||
| 299 | #define R_SDRAM_CONFIG__w__bw16 0 | ||
| 300 | #define R_SDRAM_CONFIG__w__bw32 1 | ||
| 301 | #define R_SDRAM_CONFIG__type1__BITNR 22 | ||
| 302 | #define R_SDRAM_CONFIG__type1__WIDTH 1 | ||
| 303 | #define R_SDRAM_CONFIG__type1__bank2 0 | ||
| 304 | #define R_SDRAM_CONFIG__type1__bank4 1 | ||
| 305 | #define R_SDRAM_CONFIG__type0__BITNR 21 | ||
| 306 | #define R_SDRAM_CONFIG__type0__WIDTH 1 | ||
| 307 | #define R_SDRAM_CONFIG__type0__bank2 0 | ||
| 308 | #define R_SDRAM_CONFIG__type0__bank4 1 | ||
| 309 | #define R_SDRAM_CONFIG__group_sel__BITNR 16 | ||
| 310 | #define R_SDRAM_CONFIG__group_sel__WIDTH 5 | ||
| 311 | #define R_SDRAM_CONFIG__group_sel__grp0 0 | ||
| 312 | #define R_SDRAM_CONFIG__group_sel__grp1 1 | ||
| 313 | #define R_SDRAM_CONFIG__group_sel__bit9 9 | ||
| 314 | #define R_SDRAM_CONFIG__group_sel__bit10 10 | ||
| 315 | #define R_SDRAM_CONFIG__group_sel__bit11 11 | ||
| 316 | #define R_SDRAM_CONFIG__group_sel__bit12 12 | ||
| 317 | #define R_SDRAM_CONFIG__group_sel__bit13 13 | ||
| 318 | #define R_SDRAM_CONFIG__group_sel__bit14 14 | ||
| 319 | #define R_SDRAM_CONFIG__group_sel__bit15 15 | ||
| 320 | #define R_SDRAM_CONFIG__group_sel__bit16 16 | ||
| 321 | #define R_SDRAM_CONFIG__group_sel__bit17 17 | ||
| 322 | #define R_SDRAM_CONFIG__group_sel__bit18 18 | ||
| 323 | #define R_SDRAM_CONFIG__group_sel__bit19 19 | ||
| 324 | #define R_SDRAM_CONFIG__group_sel__bit20 20 | ||
| 325 | #define R_SDRAM_CONFIG__group_sel__bit21 21 | ||
| 326 | #define R_SDRAM_CONFIG__group_sel__bit22 22 | ||
| 327 | #define R_SDRAM_CONFIG__group_sel__bit23 23 | ||
| 328 | #define R_SDRAM_CONFIG__group_sel__bit24 24 | ||
| 329 | #define R_SDRAM_CONFIG__group_sel__bit25 25 | ||
| 330 | #define R_SDRAM_CONFIG__group_sel__bit26 26 | ||
| 331 | #define R_SDRAM_CONFIG__group_sel__bit27 27 | ||
| 332 | #define R_SDRAM_CONFIG__group_sel__bit28 28 | ||
| 333 | #define R_SDRAM_CONFIG__group_sel__bit29 29 | ||
| 334 | #define R_SDRAM_CONFIG__ca1__BITNR 13 | ||
| 335 | #define R_SDRAM_CONFIG__ca1__WIDTH 3 | ||
| 336 | #define R_SDRAM_CONFIG__bank_sel1__BITNR 8 | ||
| 337 | #define R_SDRAM_CONFIG__bank_sel1__WIDTH 5 | ||
| 338 | #define R_SDRAM_CONFIG__bank_sel1__bit9 9 | ||
| 339 | #define R_SDRAM_CONFIG__bank_sel1__bit10 10 | ||
| 340 | #define R_SDRAM_CONFIG__bank_sel1__bit11 11 | ||
| 341 | #define R_SDRAM_CONFIG__bank_sel1__bit12 12 | ||
| 342 | #define R_SDRAM_CONFIG__bank_sel1__bit13 13 | ||
| 343 | #define R_SDRAM_CONFIG__bank_sel1__bit14 14 | ||
| 344 | #define R_SDRAM_CONFIG__bank_sel1__bit15 15 | ||
| 345 | #define R_SDRAM_CONFIG__bank_sel1__bit16 16 | ||
| 346 | #define R_SDRAM_CONFIG__bank_sel1__bit17 17 | ||
| 347 | #define R_SDRAM_CONFIG__bank_sel1__bit18 18 | ||
| 348 | #define R_SDRAM_CONFIG__bank_sel1__bit19 19 | ||
| 349 | #define R_SDRAM_CONFIG__bank_sel1__bit20 20 | ||
| 350 | #define R_SDRAM_CONFIG__bank_sel1__bit21 21 | ||
| 351 | #define R_SDRAM_CONFIG__bank_sel1__bit22 22 | ||
| 352 | #define R_SDRAM_CONFIG__bank_sel1__bit23 23 | ||
| 353 | #define R_SDRAM_CONFIG__bank_sel1__bit24 24 | ||
| 354 | #define R_SDRAM_CONFIG__bank_sel1__bit25 25 | ||
| 355 | #define R_SDRAM_CONFIG__bank_sel1__bit26 26 | ||
| 356 | #define R_SDRAM_CONFIG__bank_sel1__bit27 27 | ||
| 357 | #define R_SDRAM_CONFIG__bank_sel1__bit28 28 | ||
| 358 | #define R_SDRAM_CONFIG__bank_sel1__bit29 29 | ||
| 359 | #define R_SDRAM_CONFIG__ca0__BITNR 5 | ||
| 360 | #define R_SDRAM_CONFIG__ca0__WIDTH 3 | ||
| 361 | #define R_SDRAM_CONFIG__bank_sel0__BITNR 0 | ||
| 362 | #define R_SDRAM_CONFIG__bank_sel0__WIDTH 5 | ||
| 363 | #define R_SDRAM_CONFIG__bank_sel0__bit9 9 | ||
| 364 | #define R_SDRAM_CONFIG__bank_sel0__bit10 10 | ||
| 365 | #define R_SDRAM_CONFIG__bank_sel0__bit11 11 | ||
| 366 | #define R_SDRAM_CONFIG__bank_sel0__bit12 12 | ||
| 367 | #define R_SDRAM_CONFIG__bank_sel0__bit13 13 | ||
| 368 | #define R_SDRAM_CONFIG__bank_sel0__bit14 14 | ||
| 369 | #define R_SDRAM_CONFIG__bank_sel0__bit15 15 | ||
| 370 | #define R_SDRAM_CONFIG__bank_sel0__bit16 16 | ||
| 371 | #define R_SDRAM_CONFIG__bank_sel0__bit17 17 | ||
| 372 | #define R_SDRAM_CONFIG__bank_sel0__bit18 18 | ||
| 373 | #define R_SDRAM_CONFIG__bank_sel0__bit19 19 | ||
| 374 | #define R_SDRAM_CONFIG__bank_sel0__bit20 20 | ||
| 375 | #define R_SDRAM_CONFIG__bank_sel0__bit21 21 | ||
| 376 | #define R_SDRAM_CONFIG__bank_sel0__bit22 22 | ||
| 377 | #define R_SDRAM_CONFIG__bank_sel0__bit23 23 | ||
| 378 | #define R_SDRAM_CONFIG__bank_sel0__bit24 24 | ||
| 379 | #define R_SDRAM_CONFIG__bank_sel0__bit25 25 | ||
| 380 | #define R_SDRAM_CONFIG__bank_sel0__bit26 26 | ||
| 381 | #define R_SDRAM_CONFIG__bank_sel0__bit27 27 | ||
| 382 | #define R_SDRAM_CONFIG__bank_sel0__bit28 28 | ||
| 383 | #define R_SDRAM_CONFIG__bank_sel0__bit29 29 | ||
| 384 | |||
| 385 | /* | ||
| 386 | !* External DMA registers | ||
| 387 | !*/ | ||
| 388 | |||
| 389 | #define R_EXT_DMA_0_CMD (IO_TYPECAST_UDWORD 0xb0000010) | ||
| 390 | #define R_EXT_DMA_0_CMD__cnt__BITNR 23 | ||
| 391 | #define R_EXT_DMA_0_CMD__cnt__WIDTH 1 | ||
| 392 | #define R_EXT_DMA_0_CMD__cnt__enable 1 | ||
| 393 | #define R_EXT_DMA_0_CMD__cnt__disable 0 | ||
| 394 | #define R_EXT_DMA_0_CMD__rqpol__BITNR 22 | ||
| 395 | #define R_EXT_DMA_0_CMD__rqpol__WIDTH 1 | ||
| 396 | #define R_EXT_DMA_0_CMD__rqpol__ahigh 0 | ||
| 397 | #define R_EXT_DMA_0_CMD__rqpol__alow 1 | ||
| 398 | #define R_EXT_DMA_0_CMD__apol__BITNR 21 | ||
| 399 | #define R_EXT_DMA_0_CMD__apol__WIDTH 1 | ||
| 400 | #define R_EXT_DMA_0_CMD__apol__ahigh 0 | ||
| 401 | #define R_EXT_DMA_0_CMD__apol__alow 1 | ||
| 402 | #define R_EXT_DMA_0_CMD__rq_ack__BITNR 20 | ||
| 403 | #define R_EXT_DMA_0_CMD__rq_ack__WIDTH 1 | ||
| 404 | #define R_EXT_DMA_0_CMD__rq_ack__burst 0 | ||
| 405 | #define R_EXT_DMA_0_CMD__rq_ack__handsh 1 | ||
| 406 | #define R_EXT_DMA_0_CMD__wid__BITNR 18 | ||
| 407 | #define R_EXT_DMA_0_CMD__wid__WIDTH 2 | ||
| 408 | #define R_EXT_DMA_0_CMD__wid__byte 0 | ||
| 409 | #define R_EXT_DMA_0_CMD__wid__word 1 | ||
| 410 | #define R_EXT_DMA_0_CMD__wid__dword 2 | ||
| 411 | #define R_EXT_DMA_0_CMD__dir__BITNR 17 | ||
| 412 | #define R_EXT_DMA_0_CMD__dir__WIDTH 1 | ||
| 413 | #define R_EXT_DMA_0_CMD__dir__input 0 | ||
| 414 | #define R_EXT_DMA_0_CMD__dir__output 1 | ||
| 415 | #define R_EXT_DMA_0_CMD__run__BITNR 16 | ||
| 416 | #define R_EXT_DMA_0_CMD__run__WIDTH 1 | ||
| 417 | #define R_EXT_DMA_0_CMD__run__start 1 | ||
| 418 | #define R_EXT_DMA_0_CMD__run__stop 0 | ||
| 419 | #define R_EXT_DMA_0_CMD__trf_count__BITNR 0 | ||
| 420 | #define R_EXT_DMA_0_CMD__trf_count__WIDTH 16 | ||
| 421 | |||
| 422 | #define R_EXT_DMA_0_STAT (IO_TYPECAST_RO_UDWORD 0xb0000010) | ||
| 423 | #define R_EXT_DMA_0_STAT__run__BITNR 16 | ||
| 424 | #define R_EXT_DMA_0_STAT__run__WIDTH 1 | ||
| 425 | #define R_EXT_DMA_0_STAT__run__start 1 | ||
| 426 | #define R_EXT_DMA_0_STAT__run__stop 0 | ||
| 427 | #define R_EXT_DMA_0_STAT__trf_count__BITNR 0 | ||
| 428 | #define R_EXT_DMA_0_STAT__trf_count__WIDTH 16 | ||
| 429 | |||
| 430 | #define R_EXT_DMA_0_ADDR (IO_TYPECAST_UDWORD 0xb0000014) | ||
| 431 | #define R_EXT_DMA_0_ADDR__ext0_addr__BITNR 2 | ||
| 432 | #define R_EXT_DMA_0_ADDR__ext0_addr__WIDTH 28 | ||
| 433 | |||
| 434 | #define R_EXT_DMA_1_CMD (IO_TYPECAST_UDWORD 0xb0000018) | ||
| 435 | #define R_EXT_DMA_1_CMD__cnt__BITNR 23 | ||
| 436 | #define R_EXT_DMA_1_CMD__cnt__WIDTH 1 | ||
| 437 | #define R_EXT_DMA_1_CMD__cnt__enable 1 | ||
| 438 | #define R_EXT_DMA_1_CMD__cnt__disable 0 | ||
| 439 | #define R_EXT_DMA_1_CMD__rqpol__BITNR 22 | ||
| 440 | #define R_EXT_DMA_1_CMD__rqpol__WIDTH 1 | ||
| 441 | #define R_EXT_DMA_1_CMD__rqpol__ahigh 0 | ||
| 442 | #define R_EXT_DMA_1_CMD__rqpol__alow 1 | ||
| 443 | #define R_EXT_DMA_1_CMD__apol__BITNR 21 | ||
| 444 | #define R_EXT_DMA_1_CMD__apol__WIDTH 1 | ||
| 445 | #define R_EXT_DMA_1_CMD__apol__ahigh 0 | ||
| 446 | #define R_EXT_DMA_1_CMD__apol__alow 1 | ||
| 447 | #define R_EXT_DMA_1_CMD__rq_ack__BITNR 20 | ||
| 448 | #define R_EXT_DMA_1_CMD__rq_ack__WIDTH 1 | ||
| 449 | #define R_EXT_DMA_1_CMD__rq_ack__burst 0 | ||
| 450 | #define R_EXT_DMA_1_CMD__rq_ack__handsh 1 | ||
| 451 | #define R_EXT_DMA_1_CMD__wid__BITNR 18 | ||
| 452 | #define R_EXT_DMA_1_CMD__wid__WIDTH 2 | ||
| 453 | #define R_EXT_DMA_1_CMD__wid__byte 0 | ||
| 454 | #define R_EXT_DMA_1_CMD__wid__word 1 | ||
| 455 | #define R_EXT_DMA_1_CMD__wid__dword 2 | ||
| 456 | #define R_EXT_DMA_1_CMD__dir__BITNR 17 | ||
| 457 | #define R_EXT_DMA_1_CMD__dir__WIDTH 1 | ||
| 458 | #define R_EXT_DMA_1_CMD__dir__input 0 | ||
| 459 | #define R_EXT_DMA_1_CMD__dir__output 1 | ||
| 460 | #define R_EXT_DMA_1_CMD__run__BITNR 16 | ||
| 461 | #define R_EXT_DMA_1_CMD__run__WIDTH 1 | ||
| 462 | #define R_EXT_DMA_1_CMD__run__start 1 | ||
| 463 | #define R_EXT_DMA_1_CMD__run__stop 0 | ||
| 464 | #define R_EXT_DMA_1_CMD__trf_count__BITNR 0 | ||
| 465 | #define R_EXT_DMA_1_CMD__trf_count__WIDTH 16 | ||
| 466 | |||
| 467 | #define R_EXT_DMA_1_STAT (IO_TYPECAST_RO_UDWORD 0xb0000018) | ||
| 468 | #define R_EXT_DMA_1_STAT__run__BITNR 16 | ||
| 469 | #define R_EXT_DMA_1_STAT__run__WIDTH 1 | ||
| 470 | #define R_EXT_DMA_1_STAT__run__start 1 | ||
| 471 | #define R_EXT_DMA_1_STAT__run__stop 0 | ||
| 472 | #define R_EXT_DMA_1_STAT__trf_count__BITNR 0 | ||
| 473 | #define R_EXT_DMA_1_STAT__trf_count__WIDTH 16 | ||
| 474 | |||
| 475 | #define R_EXT_DMA_1_ADDR (IO_TYPECAST_UDWORD 0xb000001c) | ||
| 476 | #define R_EXT_DMA_1_ADDR__ext0_addr__BITNR 2 | ||
| 477 | #define R_EXT_DMA_1_ADDR__ext0_addr__WIDTH 28 | ||
| 478 | |||
| 479 | /* | ||
| 480 | !* Timer registers | ||
| 481 | !*/ | ||
| 482 | |||
| 483 | #define R_TIMER_CTRL (IO_TYPECAST_UDWORD 0xb0000020) | ||
| 484 | #define R_TIMER_CTRL__timerdiv1__BITNR 24 | ||
| 485 | #define R_TIMER_CTRL__timerdiv1__WIDTH 8 | ||
| 486 | #define R_TIMER_CTRL__timerdiv0__BITNR 16 | ||
| 487 | #define R_TIMER_CTRL__timerdiv0__WIDTH 8 | ||
| 488 | #define R_TIMER_CTRL__presc_timer1__BITNR 15 | ||
| 489 | #define R_TIMER_CTRL__presc_timer1__WIDTH 1 | ||
| 490 | #define R_TIMER_CTRL__presc_timer1__normal 0 | ||
| 491 | #define R_TIMER_CTRL__presc_timer1__prescale 1 | ||
| 492 | #define R_TIMER_CTRL__i1__BITNR 14 | ||
| 493 | #define R_TIMER_CTRL__i1__WIDTH 1 | ||
| 494 | #define R_TIMER_CTRL__i1__clr 1 | ||
| 495 | #define R_TIMER_CTRL__i1__nop 0 | ||
| 496 | #define R_TIMER_CTRL__tm1__BITNR 12 | ||
| 497 | #define R_TIMER_CTRL__tm1__WIDTH 2 | ||
| 498 | #define R_TIMER_CTRL__tm1__stop_ld 0 | ||
| 499 | #define R_TIMER_CTRL__tm1__freeze 1 | ||
| 500 | #define R_TIMER_CTRL__tm1__run 2 | ||
| 501 | #define R_TIMER_CTRL__tm1__reserved 3 | ||
| 502 | #define R_TIMER_CTRL__clksel1__BITNR 8 | ||
| 503 | #define R_TIMER_CTRL__clksel1__WIDTH 4 | ||
| 504 | #define R_TIMER_CTRL__clksel1__c300Hz 0 | ||
| 505 | #define R_TIMER_CTRL__clksel1__c600Hz 1 | ||
| 506 | #define R_TIMER_CTRL__clksel1__c1200Hz 2 | ||
| 507 | #define R_TIMER_CTRL__clksel1__c2400Hz 3 | ||
| 508 | #define R_TIMER_CTRL__clksel1__c4800Hz 4 | ||
| 509 | #define R_TIMER_CTRL__clksel1__c9600Hz 5 | ||
| 510 | #define R_TIMER_CTRL__clksel1__c19k2Hz 6 | ||
| 511 | #define R_TIMER_CTRL__clksel1__c38k4Hz 7 | ||
| 512 | #define R_TIMER_CTRL__clksel1__c57k6Hz 8 | ||
| 513 | #define R_TIMER_CTRL__clksel1__c115k2Hz 9 | ||
| 514 | #define R_TIMER_CTRL__clksel1__c230k4Hz 10 | ||
| 515 | #define R_TIMER_CTRL__clksel1__c460k8Hz 11 | ||
| 516 | #define R_TIMER_CTRL__clksel1__c921k6Hz 12 | ||
| 517 | #define R_TIMER_CTRL__clksel1__c1843k2Hz 13 | ||
| 518 | #define R_TIMER_CTRL__clksel1__c6250kHz 14 | ||
| 519 | #define R_TIMER_CTRL__clksel1__cascade0 15 | ||
| 520 | #define R_TIMER_CTRL__presc_ext__BITNR 7 | ||
| 521 | #define R_TIMER_CTRL__presc_ext__WIDTH 1 | ||
| 522 | #define R_TIMER_CTRL__presc_ext__prescale 0 | ||
| 523 | #define R_TIMER_CTRL__presc_ext__external 1 | ||
| 524 | #define R_TIMER_CTRL__i0__BITNR 6 | ||
| 525 | #define R_TIMER_CTRL__i0__WIDTH 1 | ||
| 526 | #define R_TIMER_CTRL__i0__clr 1 | ||
| 527 | #define R_TIMER_CTRL__i0__nop 0 | ||
| 528 | #define R_TIMER_CTRL__tm0__BITNR 4 | ||
| 529 | #define R_TIMER_CTRL__tm0__WIDTH 2 | ||
| 530 | #define R_TIMER_CTRL__tm0__stop_ld 0 | ||
| 531 | #define R_TIMER_CTRL__tm0__freeze 1 | ||
| 532 | #define R_TIMER_CTRL__tm0__run 2 | ||
| 533 | #define R_TIMER_CTRL__tm0__reserved 3 | ||
| 534 | #define R_TIMER_CTRL__clksel0__BITNR 0 | ||
| 535 | #define R_TIMER_CTRL__clksel0__WIDTH 4 | ||
| 536 | #define R_TIMER_CTRL__clksel0__c300Hz 0 | ||
| 537 | #define R_TIMER_CTRL__clksel0__c600Hz 1 | ||
| 538 | #define R_TIMER_CTRL__clksel0__c1200Hz 2 | ||
| 539 | #define R_TIMER_CTRL__clksel0__c2400Hz 3 | ||
| 540 | #define R_TIMER_CTRL__clksel0__c4800Hz 4 | ||
| 541 | #define R_TIMER_CTRL__clksel0__c9600Hz 5 | ||
| 542 | #define R_TIMER_CTRL__clksel0__c19k2Hz 6 | ||
| 543 | #define R_TIMER_CTRL__clksel0__c38k4Hz 7 | ||
| 544 | #define R_TIMER_CTRL__clksel0__c57k6Hz 8 | ||
| 545 | #define R_TIMER_CTRL__clksel0__c115k2Hz 9 | ||
| 546 | #define R_TIMER_CTRL__clksel0__c230k4Hz 10 | ||
| 547 | #define R_TIMER_CTRL__clksel0__c460k8Hz 11 | ||
| 548 | #define R_TIMER_CTRL__clksel0__c921k6Hz 12 | ||
| 549 | #define R_TIMER_CTRL__clksel0__c1843k2Hz 13 | ||
| 550 | #define R_TIMER_CTRL__clksel0__c6250kHz 14 | ||
| 551 | #define R_TIMER_CTRL__clksel0__flexible 15 | ||
| 552 | |||
| 553 | #define R_TIMER_DATA (IO_TYPECAST_RO_UDWORD 0xb0000020) | ||
| 554 | #define R_TIMER_DATA__timer1__BITNR 24 | ||
| 555 | #define R_TIMER_DATA__timer1__WIDTH 8 | ||
| 556 | #define R_TIMER_DATA__timer0__BITNR 16 | ||
| 557 | #define R_TIMER_DATA__timer0__WIDTH 8 | ||
| 558 | #define R_TIMER_DATA__clkdiv_high__BITNR 8 | ||
| 559 | #define R_TIMER_DATA__clkdiv_high__WIDTH 8 | ||
| 560 | #define R_TIMER_DATA__clkdiv_low__BITNR 0 | ||
| 561 | #define R_TIMER_DATA__clkdiv_low__WIDTH 8 | ||
| 562 | |||
| 563 | #define R_TIMER01_DATA (IO_TYPECAST_RO_UWORD 0xb0000022) | ||
| 564 | #define R_TIMER01_DATA__count__BITNR 0 | ||
| 565 | #define R_TIMER01_DATA__count__WIDTH 16 | ||
| 566 | |||
| 567 | #define R_TIMER0_DATA (IO_TYPECAST_RO_BYTE 0xb0000022) | ||
| 568 | #define R_TIMER0_DATA__count__BITNR 0 | ||
| 569 | #define R_TIMER0_DATA__count__WIDTH 8 | ||
| 570 | |||
| 571 | #define R_TIMER1_DATA (IO_TYPECAST_RO_BYTE 0xb0000023) | ||
| 572 | #define R_TIMER1_DATA__count__BITNR 0 | ||
| 573 | #define R_TIMER1_DATA__count__WIDTH 8 | ||
| 574 | |||
| 575 | #define R_WATCHDOG (IO_TYPECAST_UDWORD 0xb0000024) | ||
| 576 | #define R_WATCHDOG__key__BITNR 1 | ||
| 577 | #define R_WATCHDOG__key__WIDTH 3 | ||
| 578 | #define R_WATCHDOG__enable__BITNR 0 | ||
| 579 | #define R_WATCHDOG__enable__WIDTH 1 | ||
| 580 | #define R_WATCHDOG__enable__stop 0 | ||
| 581 | #define R_WATCHDOG__enable__start 1 | ||
| 582 | |||
| 583 | #define R_CLOCK_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f0) | ||
| 584 | #define R_CLOCK_PRESCALE__ser_presc__BITNR 16 | ||
| 585 | #define R_CLOCK_PRESCALE__ser_presc__WIDTH 16 | ||
| 586 | #define R_CLOCK_PRESCALE__tim_presc__BITNR 0 | ||
| 587 | #define R_CLOCK_PRESCALE__tim_presc__WIDTH 16 | ||
| 588 | |||
| 589 | #define R_SERIAL_PRESCALE (IO_TYPECAST_UWORD 0xb00000f2) | ||
| 590 | #define R_SERIAL_PRESCALE__ser_presc__BITNR 0 | ||
| 591 | #define R_SERIAL_PRESCALE__ser_presc__WIDTH 16 | ||
| 592 | |||
| 593 | #define R_TIMER_PRESCALE (IO_TYPECAST_UWORD 0xb00000f0) | ||
| 594 | #define R_TIMER_PRESCALE__tim_presc__BITNR 0 | ||
| 595 | #define R_TIMER_PRESCALE__tim_presc__WIDTH 16 | ||
| 596 | |||
| 597 | #define R_PRESCALE_STATUS (IO_TYPECAST_RO_UDWORD 0xb00000f0) | ||
| 598 | #define R_PRESCALE_STATUS__ser_status__BITNR 16 | ||
| 599 | #define R_PRESCALE_STATUS__ser_status__WIDTH 16 | ||
| 600 | #define R_PRESCALE_STATUS__tim_status__BITNR 0 | ||
| 601 | #define R_PRESCALE_STATUS__tim_status__WIDTH 16 | ||
| 602 | |||
| 603 | #define R_SER_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f2) | ||
| 604 | #define R_SER_PRESC_STATUS__ser_status__BITNR 0 | ||
| 605 | #define R_SER_PRESC_STATUS__ser_status__WIDTH 16 | ||
| 606 | |||
| 607 | #define R_TIM_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f0) | ||
| 608 | #define R_TIM_PRESC_STATUS__tim_status__BITNR 0 | ||
| 609 | #define R_TIM_PRESC_STATUS__tim_status__WIDTH 16 | ||
| 610 | |||
| 611 | #define R_SYNC_SERIAL_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f4) | ||
| 612 | #define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__BITNR 23 | ||
| 613 | #define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__WIDTH 1 | ||
| 614 | #define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__codec 0 | ||
| 615 | #define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__baudrate 1 | ||
| 616 | #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__BITNR 22 | ||
| 617 | #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__WIDTH 1 | ||
| 618 | #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__external 0 | ||
| 619 | #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__internal 1 | ||
| 620 | #define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__BITNR 21 | ||
| 621 | #define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__WIDTH 1 | ||
| 622 | #define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__codec 0 | ||
| 623 | #define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__baudrate 1 | ||
| 624 | #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__BITNR 20 | ||
| 625 | #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__WIDTH 1 | ||
| 626 | #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__external 0 | ||
| 627 | #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__internal 1 | ||
| 628 | #define R_SYNC_SERIAL_PRESCALE__prescaler__BITNR 16 | ||
| 629 | #define R_SYNC_SERIAL_PRESCALE__prescaler__WIDTH 3 | ||
| 630 | #define R_SYNC_SERIAL_PRESCALE__prescaler__div1 0 | ||
| 631 | #define R_SYNC_SERIAL_PRESCALE__prescaler__div2 1 | ||
| 632 | #define R_SYNC_SERIAL_PRESCALE__prescaler__div4 2 | ||
| 633 | #define R_SYNC_SERIAL_PRESCALE__prescaler__div8 3 | ||
| 634 | #define R_SYNC_SERIAL_PRESCALE__prescaler__div16 4 | ||
| 635 | #define R_SYNC_SERIAL_PRESCALE__prescaler__div32 5 | ||
| 636 | #define R_SYNC_SERIAL_PRESCALE__prescaler__div64 6 | ||
| 637 | #define R_SYNC_SERIAL_PRESCALE__prescaler__div128 7 | ||
| 638 | #define R_SYNC_SERIAL_PRESCALE__warp_mode__BITNR 15 | ||
| 639 | #define R_SYNC_SERIAL_PRESCALE__warp_mode__WIDTH 1 | ||
| 640 | #define R_SYNC_SERIAL_PRESCALE__warp_mode__normal 0 | ||
| 641 | #define R_SYNC_SERIAL_PRESCALE__warp_mode__enabled 1 | ||
| 642 | #define R_SYNC_SERIAL_PRESCALE__frame_rate__BITNR 11 | ||
| 643 | #define R_SYNC_SERIAL_PRESCALE__frame_rate__WIDTH 4 | ||
| 644 | #define R_SYNC_SERIAL_PRESCALE__word_rate__BITNR 0 | ||
| 645 | #define R_SYNC_SERIAL_PRESCALE__word_rate__WIDTH 10 | ||
| 646 | |||
| 647 | /* | ||
| 648 | !* Shared RAM interface registers | ||
| 649 | !*/ | ||
| 650 | |||
| 651 | #define R_SHARED_RAM_CONFIG (IO_TYPECAST_UDWORD 0xb0000040) | ||
| 652 | #define R_SHARED_RAM_CONFIG__width__BITNR 3 | ||
| 653 | #define R_SHARED_RAM_CONFIG__width__WIDTH 1 | ||
| 654 | #define R_SHARED_RAM_CONFIG__width__byte 0 | ||
| 655 | #define R_SHARED_RAM_CONFIG__width__word 1 | ||
| 656 | #define R_SHARED_RAM_CONFIG__enable__BITNR 2 | ||
| 657 | #define R_SHARED_RAM_CONFIG__enable__WIDTH 1 | ||
| 658 | #define R_SHARED_RAM_CONFIG__enable__yes 1 | ||
| 659 | #define R_SHARED_RAM_CONFIG__enable__no 0 | ||
| 660 | #define R_SHARED_RAM_CONFIG__pint__BITNR 1 | ||
| 661 | #define R_SHARED_RAM_CONFIG__pint__WIDTH 1 | ||
| 662 | #define R_SHARED_RAM_CONFIG__pint__int 1 | ||
| 663 | #define R_SHARED_RAM_CONFIG__pint__nop 0 | ||
| 664 | #define R_SHARED_RAM_CONFIG__clri__BITNR 0 | ||
| 665 | #define R_SHARED_RAM_CONFIG__clri__WIDTH 1 | ||
| 666 | #define R_SHARED_RAM_CONFIG__clri__clr 1 | ||
| 667 | #define R_SHARED_RAM_CONFIG__clri__nop 0 | ||
| 668 | |||
| 669 | #define R_SHARED_RAM_ADDR (IO_TYPECAST_UDWORD 0xb0000044) | ||
| 670 | #define R_SHARED_RAM_ADDR__base_addr__BITNR 8 | ||
| 671 | #define R_SHARED_RAM_ADDR__base_addr__WIDTH 22 | ||
| 672 | |||
| 673 | /* | ||
| 674 | !* General config registers | ||
| 675 | !*/ | ||
| 676 | |||
| 677 | #define R_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb000002c) | ||
| 678 | #define R_GEN_CONFIG__par_w__BITNR 31 | ||
| 679 | #define R_GEN_CONFIG__par_w__WIDTH 1 | ||
| 680 | #define R_GEN_CONFIG__par_w__select 1 | ||
| 681 | #define R_GEN_CONFIG__par_w__disable 0 | ||
| 682 | #define R_GEN_CONFIG__usb2__BITNR 30 | ||
| 683 | #define R_GEN_CONFIG__usb2__WIDTH 1 | ||
| 684 | #define R_GEN_CONFIG__usb2__select 1 | ||
| 685 | #define R_GEN_CONFIG__usb2__disable 0 | ||
| 686 | #define R_GEN_CONFIG__usb1__BITNR 29 | ||
| 687 | #define R_GEN_CONFIG__usb1__WIDTH 1 | ||
| 688 | #define R_GEN_CONFIG__usb1__select 1 | ||
| 689 | #define R_GEN_CONFIG__usb1__disable 0 | ||
| 690 | #define R_GEN_CONFIG__g24dir__BITNR 27 | ||
| 691 | #define R_GEN_CONFIG__g24dir__WIDTH 1 | ||
| 692 | #define R_GEN_CONFIG__g24dir__in 0 | ||
| 693 | #define R_GEN_CONFIG__g24dir__out 1 | ||
| 694 | #define R_GEN_CONFIG__g16_23dir__BITNR 26 | ||
| 695 | #define R_GEN_CONFIG__g16_23dir__WIDTH 1 | ||
| 696 | #define R_GEN_CONFIG__g16_23dir__in 0 | ||
| 697 | #define R_GEN_CONFIG__g16_23dir__out 1 | ||
| 698 | #define R_GEN_CONFIG__g8_15dir__BITNR 25 | ||
| 699 | #define R_GEN_CONFIG__g8_15dir__WIDTH 1 | ||
| 700 | #define R_GEN_CONFIG__g8_15dir__in 0 | ||
| 701 | #define R_GEN_CONFIG__g8_15dir__out 1 | ||
| 702 | #define R_GEN_CONFIG__g0dir__BITNR 24 | ||
| 703 | #define R_GEN_CONFIG__g0dir__WIDTH 1 | ||
| 704 | #define R_GEN_CONFIG__g0dir__in 0 | ||
| 705 | #define R_GEN_CONFIG__g0dir__out 1 | ||
| 706 | #define R_GEN_CONFIG__dma9__BITNR 23 | ||
| 707 | #define R_GEN_CONFIG__dma9__WIDTH 1 | ||
| 708 | #define R_GEN_CONFIG__dma9__usb 0 | ||
| 709 | #define R_GEN_CONFIG__dma9__serial1 1 | ||
| 710 | #define R_GEN_CONFIG__dma8__BITNR 22 | ||
| 711 | #define R_GEN_CONFIG__dma8__WIDTH 1 | ||
| 712 | #define R_GEN_CONFIG__dma8__usb 0 | ||
| 713 | #define R_GEN_CONFIG__dma8__serial1 1 | ||
| 714 | #define R_GEN_CONFIG__dma7__BITNR 20 | ||
| 715 | #define R_GEN_CONFIG__dma7__WIDTH 2 | ||
| 716 | #define R_GEN_CONFIG__dma7__unused 0 | ||
| 717 | #define R_GEN_CONFIG__dma7__serial0 1 | ||
| 718 | #define R_GEN_CONFIG__dma7__extdma1 2 | ||
| 719 | #define R_GEN_CONFIG__dma7__intdma6 3 | ||
| 720 | #define R_GEN_CONFIG__dma6__BITNR 18 | ||
| 721 | #define R_GEN_CONFIG__dma6__WIDTH 2 | ||
| 722 | #define R_GEN_CONFIG__dma6__unused 0 | ||
| 723 | #define R_GEN_CONFIG__dma6__serial0 1 | ||
| 724 | #define R_GEN_CONFIG__dma6__extdma1 2 | ||
| 725 | #define R_GEN_CONFIG__dma6__intdma7 3 | ||
| 726 | #define R_GEN_CONFIG__dma5__BITNR 16 | ||
| 727 | #define R_GEN_CONFIG__dma5__WIDTH 2 | ||
| 728 | #define R_GEN_CONFIG__dma5__par1 0 | ||
| 729 | #define R_GEN_CONFIG__dma5__scsi1 1 | ||
| 730 | #define R_GEN_CONFIG__dma5__serial3 2 | ||
| 731 | #define R_GEN_CONFIG__dma5__extdma0 3 | ||
| 732 | #define R_GEN_CONFIG__dma4__BITNR 14 | ||
| 733 | #define R_GEN_CONFIG__dma4__WIDTH 2 | ||
| 734 | #define R_GEN_CONFIG__dma4__par1 0 | ||
| 735 | #define R_GEN_CONFIG__dma4__scsi1 1 | ||
| 736 | #define R_GEN_CONFIG__dma4__serial3 2 | ||
| 737 | #define R_GEN_CONFIG__dma4__extdma0 3 | ||
| 738 | #define R_GEN_CONFIG__dma3__BITNR 12 | ||
| 739 | #define R_GEN_CONFIG__dma3__WIDTH 2 | ||
| 740 | #define R_GEN_CONFIG__dma3__par0 0 | ||
| 741 | #define R_GEN_CONFIG__dma3__scsi0 1 | ||
| 742 | #define R_GEN_CONFIG__dma3__serial2 2 | ||
| 743 | #define R_GEN_CONFIG__dma3__ata 3 | ||
| 744 | #define R_GEN_CONFIG__dma2__BITNR 10 | ||
| 745 | #define R_GEN_CONFIG__dma2__WIDTH 2 | ||
| 746 | #define R_GEN_CONFIG__dma2__par0 0 | ||
| 747 | #define R_GEN_CONFIG__dma2__scsi0 1 | ||
| 748 | #define R_GEN_CONFIG__dma2__serial2 2 | ||
| 749 | #define R_GEN_CONFIG__dma2__ata 3 | ||
| 750 | #define R_GEN_CONFIG__mio_w__BITNR 9 | ||
| 751 | #define R_GEN_CONFIG__mio_w__WIDTH 1 | ||
| 752 | #define R_GEN_CONFIG__mio_w__select 1 | ||
| 753 | #define R_GEN_CONFIG__mio_w__disable 0 | ||
| 754 | #define R_GEN_CONFIG__ser3__BITNR 8 | ||
| 755 | #define R_GEN_CONFIG__ser3__WIDTH 1 | ||
| 756 | #define R_GEN_CONFIG__ser3__select 1 | ||
| 757 | #define R_GEN_CONFIG__ser3__disable 0 | ||
| 758 | #define R_GEN_CONFIG__par1__BITNR 7 | ||
| 759 | #define R_GEN_CONFIG__par1__WIDTH 1 | ||
| 760 | #define R_GEN_CONFIG__par1__select 1 | ||
| 761 | #define R_GEN_CONFIG__par1__disable 0 | ||
| 762 | #define R_GEN_CONFIG__scsi0w__BITNR 6 | ||
| 763 | #define R_GEN_CONFIG__scsi0w__WIDTH 1 | ||
| 764 | #define R_GEN_CONFIG__scsi0w__select 1 | ||
| 765 | #define R_GEN_CONFIG__scsi0w__disable 0 | ||
| 766 | #define R_GEN_CONFIG__scsi1__BITNR 5 | ||
| 767 | #define R_GEN_CONFIG__scsi1__WIDTH 1 | ||
| 768 | #define R_GEN_CONFIG__scsi1__select 1 | ||
| 769 | #define R_GEN_CONFIG__scsi1__disable 0 | ||
| 770 | #define R_GEN_CONFIG__mio__BITNR 4 | ||
| 771 | #define R_GEN_CONFIG__mio__WIDTH 1 | ||
| 772 | #define R_GEN_CONFIG__mio__select 1 | ||
| 773 | #define R_GEN_CONFIG__mio__disable 0 | ||
| 774 | #define R_GEN_CONFIG__ser2__BITNR 3 | ||
| 775 | #define R_GEN_CONFIG__ser2__WIDTH 1 | ||
| 776 | #define R_GEN_CONFIG__ser2__select 1 | ||
| 777 | #define R_GEN_CONFIG__ser2__disable 0 | ||
| 778 | #define R_GEN_CONFIG__par0__BITNR 2 | ||
| 779 | #define R_GEN_CONFIG__par0__WIDTH 1 | ||
| 780 | #define R_GEN_CONFIG__par0__select 1 | ||
| 781 | #define R_GEN_CONFIG__par0__disable 0 | ||
| 782 | #define R_GEN_CONFIG__ata__BITNR 1 | ||
| 783 | #define R_GEN_CONFIG__ata__WIDTH 1 | ||
| 784 | #define R_GEN_CONFIG__ata__select 1 | ||
| 785 | #define R_GEN_CONFIG__ata__disable 0 | ||
| 786 | #define R_GEN_CONFIG__scsi0__BITNR 0 | ||
| 787 | #define R_GEN_CONFIG__scsi0__WIDTH 1 | ||
| 788 | #define R_GEN_CONFIG__scsi0__select 1 | ||
| 789 | #define R_GEN_CONFIG__scsi0__disable 0 | ||
| 790 | |||
| 791 | #define R_GEN_CONFIG_II (IO_TYPECAST_UDWORD 0xb0000034) | ||
| 792 | #define R_GEN_CONFIG_II__sermode3__BITNR 6 | ||
| 793 | #define R_GEN_CONFIG_II__sermode3__WIDTH 1 | ||
| 794 | #define R_GEN_CONFIG_II__sermode3__async 0 | ||
| 795 | #define R_GEN_CONFIG_II__sermode3__sync 1 | ||
| 796 | #define R_GEN_CONFIG_II__sermode1__BITNR 4 | ||
| 797 | #define R_GEN_CONFIG_II__sermode1__WIDTH 1 | ||
| 798 | #define R_GEN_CONFIG_II__sermode1__async 0 | ||
| 799 | #define R_GEN_CONFIG_II__sermode1__sync 1 | ||
| 800 | #define R_GEN_CONFIG_II__ext_clk__BITNR 2 | ||
| 801 | #define R_GEN_CONFIG_II__ext_clk__WIDTH 1 | ||
| 802 | #define R_GEN_CONFIG_II__ext_clk__select 1 | ||
| 803 | #define R_GEN_CONFIG_II__ext_clk__disable 0 | ||
| 804 | #define R_GEN_CONFIG_II__ser2__BITNR 1 | ||
| 805 | #define R_GEN_CONFIG_II__ser2__WIDTH 1 | ||
| 806 | #define R_GEN_CONFIG_II__ser2__select 1 | ||
| 807 | #define R_GEN_CONFIG_II__ser2__disable 0 | ||
| 808 | #define R_GEN_CONFIG_II__ser3__BITNR 0 | ||
| 809 | #define R_GEN_CONFIG_II__ser3__WIDTH 1 | ||
| 810 | #define R_GEN_CONFIG_II__ser3__select 1 | ||
| 811 | #define R_GEN_CONFIG_II__ser3__disable 0 | ||
| 812 | |||
| 813 | #define R_PORT_G_DATA (IO_TYPECAST_UDWORD 0xb0000028) | ||
| 814 | #define R_PORT_G_DATA__data__BITNR 0 | ||
| 815 | #define R_PORT_G_DATA__data__WIDTH 32 | ||
| 816 | |||
| 817 | /* | ||
| 818 | !* General port configuration registers | ||
| 819 | !*/ | ||
| 820 | |||
| 821 | #define R_PORT_PA_SET (IO_TYPECAST_UDWORD 0xb0000030) | ||
| 822 | #define R_PORT_PA_SET__dir7__BITNR 15 | ||
| 823 | #define R_PORT_PA_SET__dir7__WIDTH 1 | ||
| 824 | #define R_PORT_PA_SET__dir7__input 0 | ||
| 825 | #define R_PORT_PA_SET__dir7__output 1 | ||
| 826 | #define R_PORT_PA_SET__dir6__BITNR 14 | ||
| 827 | #define R_PORT_PA_SET__dir6__WIDTH 1 | ||
| 828 | #define R_PORT_PA_SET__dir6__input 0 | ||
| 829 | #define R_PORT_PA_SET__dir6__output 1 | ||
| 830 | #define R_PORT_PA_SET__dir5__BITNR 13 | ||
| 831 | #define R_PORT_PA_SET__dir5__WIDTH 1 | ||
| 832 | #define R_PORT_PA_SET__dir5__input 0 | ||
| 833 | #define R_PORT_PA_SET__dir5__output 1 | ||
| 834 | #define R_PORT_PA_SET__dir4__BITNR 12 | ||
| 835 | #define R_PORT_PA_SET__dir4__WIDTH 1 | ||
| 836 | #define R_PORT_PA_SET__dir4__input 0 | ||
| 837 | #define R_PORT_PA_SET__dir4__output 1 | ||
| 838 | #define R_PORT_PA_SET__dir3__BITNR 11 | ||
| 839 | #define R_PORT_PA_SET__dir3__WIDTH 1 | ||
| 840 | #define R_PORT_PA_SET__dir3__input 0 | ||
| 841 | #define R_PORT_PA_SET__dir3__output 1 | ||
| 842 | #define R_PORT_PA_SET__dir2__BITNR 10 | ||
| 843 | #define R_PORT_PA_SET__dir2__WIDTH 1 | ||
| 844 | #define R_PORT_PA_SET__dir2__input 0 | ||
| 845 | #define R_PORT_PA_SET__dir2__output 1 | ||
| 846 | #define R_PORT_PA_SET__dir1__BITNR 9 | ||
| 847 | #define R_PORT_PA_SET__dir1__WIDTH 1 | ||
| 848 | #define R_PORT_PA_SET__dir1__input 0 | ||
| 849 | #define R_PORT_PA_SET__dir1__output 1 | ||
| 850 | #define R_PORT_PA_SET__dir0__BITNR 8 | ||
| 851 | #define R_PORT_PA_SET__dir0__WIDTH 1 | ||
| 852 | #define R_PORT_PA_SET__dir0__input 0 | ||
| 853 | #define R_PORT_PA_SET__dir0__output 1 | ||
| 854 | #define R_PORT_PA_SET__data_out__BITNR 0 | ||
| 855 | #define R_PORT_PA_SET__data_out__WIDTH 8 | ||
| 856 | |||
| 857 | #define R_PORT_PA_DATA (IO_TYPECAST_BYTE 0xb0000030) | ||
| 858 | #define R_PORT_PA_DATA__data_out__BITNR 0 | ||
| 859 | #define R_PORT_PA_DATA__data_out__WIDTH 8 | ||
| 860 | |||
| 861 | #define R_PORT_PA_DIR (IO_TYPECAST_BYTE 0xb0000031) | ||
| 862 | #define R_PORT_PA_DIR__dir7__BITNR 7 | ||
| 863 | #define R_PORT_PA_DIR__dir7__WIDTH 1 | ||
| 864 | #define R_PORT_PA_DIR__dir7__input 0 | ||
| 865 | #define R_PORT_PA_DIR__dir7__output 1 | ||
| 866 | #define R_PORT_PA_DIR__dir6__BITNR 6 | ||
| 867 | #define R_PORT_PA_DIR__dir6__WIDTH 1 | ||
| 868 | #define R_PORT_PA_DIR__dir6__input 0 | ||
| 869 | #define R_PORT_PA_DIR__dir6__output 1 | ||
| 870 | #define R_PORT_PA_DIR__dir5__BITNR 5 | ||
| 871 | #define R_PORT_PA_DIR__dir5__WIDTH 1 | ||
| 872 | #define R_PORT_PA_DIR__dir5__input 0 | ||
| 873 | #define R_PORT_PA_DIR__dir5__output 1 | ||
| 874 | #define R_PORT_PA_DIR__dir4__BITNR 4 | ||
| 875 | #define R_PORT_PA_DIR__dir4__WIDTH 1 | ||
| 876 | #define R_PORT_PA_DIR__dir4__input 0 | ||
| 877 | #define R_PORT_PA_DIR__dir4__output 1 | ||
| 878 | #define R_PORT_PA_DIR__dir3__BITNR 3 | ||
| 879 | #define R_PORT_PA_DIR__dir3__WIDTH 1 | ||
| 880 | #define R_PORT_PA_DIR__dir3__input 0 | ||
| 881 | #define R_PORT_PA_DIR__dir3__output 1 | ||
| 882 | #define R_PORT_PA_DIR__dir2__BITNR 2 | ||
| 883 | #define R_PORT_PA_DIR__dir2__WIDTH 1 | ||
| 884 | #define R_PORT_PA_DIR__dir2__input 0 | ||
| 885 | #define R_PORT_PA_DIR__dir2__output 1 | ||
| 886 | #define R_PORT_PA_DIR__dir1__BITNR 1 | ||
| 887 | #define R_PORT_PA_DIR__dir1__WIDTH 1 | ||
| 888 | #define R_PORT_PA_DIR__dir1__input 0 | ||
| 889 | #define R_PORT_PA_DIR__dir1__output 1 | ||
| 890 | #define R_PORT_PA_DIR__dir0__BITNR 0 | ||
| 891 | #define R_PORT_PA_DIR__dir0__WIDTH 1 | ||
| 892 | #define R_PORT_PA_DIR__dir0__input 0 | ||
| 893 | #define R_PORT_PA_DIR__dir0__output 1 | ||
| 894 | |||
| 895 | #define R_PORT_PA_READ (IO_TYPECAST_RO_UDWORD 0xb0000030) | ||
| 896 | #define R_PORT_PA_READ__data_in__BITNR 0 | ||
| 897 | #define R_PORT_PA_READ__data_in__WIDTH 8 | ||
| 898 | |||
| 899 | #define R_PORT_PB_SET (IO_TYPECAST_UDWORD 0xb0000038) | ||
| 900 | #define R_PORT_PB_SET__syncser3__BITNR 29 | ||
| 901 | #define R_PORT_PB_SET__syncser3__WIDTH 1 | ||
| 902 | #define R_PORT_PB_SET__syncser3__port_cs 0 | ||
| 903 | #define R_PORT_PB_SET__syncser3__ss3extra 1 | ||
| 904 | #define R_PORT_PB_SET__syncser1__BITNR 28 | ||
| 905 | #define R_PORT_PB_SET__syncser1__WIDTH 1 | ||
| 906 | #define R_PORT_PB_SET__syncser1__port_cs 0 | ||
| 907 | #define R_PORT_PB_SET__syncser1__ss1extra 1 | ||
| 908 | #define R_PORT_PB_SET__i2c_en__BITNR 27 | ||
| 909 | #define R_PORT_PB_SET__i2c_en__WIDTH 1 | ||
| 910 | #define R_PORT_PB_SET__i2c_en__off 0 | ||
| 911 | #define R_PORT_PB_SET__i2c_en__on 1 | ||
| 912 | #define R_PORT_PB_SET__i2c_d__BITNR 26 | ||
| 913 | #define R_PORT_PB_SET__i2c_d__WIDTH 1 | ||
| 914 | #define R_PORT_PB_SET__i2c_clk__BITNR 25 | ||
| 915 | #define R_PORT_PB_SET__i2c_clk__WIDTH 1 | ||
| 916 | #define R_PORT_PB_SET__i2c_oe___BITNR 24 | ||
| 917 | #define R_PORT_PB_SET__i2c_oe___WIDTH 1 | ||
| 918 | #define R_PORT_PB_SET__i2c_oe___enable 0 | ||
| 919 | #define R_PORT_PB_SET__i2c_oe___disable 1 | ||
| 920 | #define R_PORT_PB_SET__cs7__BITNR 23 | ||
| 921 | #define R_PORT_PB_SET__cs7__WIDTH 1 | ||
| 922 | #define R_PORT_PB_SET__cs7__port 0 | ||
| 923 | #define R_PORT_PB_SET__cs7__cs 1 | ||
| 924 | #define R_PORT_PB_SET__cs6__BITNR 22 | ||
| 925 | #define R_PORT_PB_SET__cs6__WIDTH 1 | ||
| 926 | #define R_PORT_PB_SET__cs6__port 0 | ||
| 927 | #define R_PORT_PB_SET__cs6__cs 1 | ||
| 928 | #define R_PORT_PB_SET__cs5__BITNR 21 | ||
| 929 | #define R_PORT_PB_SET__cs5__WIDTH 1 | ||
| 930 | #define R_PORT_PB_SET__cs5__port 0 | ||
| 931 | #define R_PORT_PB_SET__cs5__cs 1 | ||
| 932 | #define R_PORT_PB_SET__cs4__BITNR 20 | ||
| 933 | #define R_PORT_PB_SET__cs4__WIDTH 1 | ||
| 934 | #define R_PORT_PB_SET__cs4__port 0 | ||
| 935 | #define R_PORT_PB_SET__cs4__cs 1 | ||
| 936 | #define R_PORT_PB_SET__cs3__BITNR 19 | ||
| 937 | #define R_PORT_PB_SET__cs3__WIDTH 1 | ||
| 938 | #define R_PORT_PB_SET__cs3__port 0 | ||
| 939 | #define R_PORT_PB_SET__cs3__cs 1 | ||
| 940 | #define R_PORT_PB_SET__cs2__BITNR 18 | ||
| 941 | #define R_PORT_PB_SET__cs2__WIDTH 1 | ||
| 942 | #define R_PORT_PB_SET__cs2__port 0 | ||
| 943 | #define R_PORT_PB_SET__cs2__cs 1 | ||
| 944 | #define R_PORT_PB_SET__scsi1__BITNR 17 | ||
| 945 | #define R_PORT_PB_SET__scsi1__WIDTH 1 | ||
| 946 | #define R_PORT_PB_SET__scsi1__port_cs 0 | ||
| 947 | #define R_PORT_PB_SET__scsi1__enph 1 | ||
| 948 | #define R_PORT_PB_SET__scsi0__BITNR 16 | ||
| 949 | #define R_PORT_PB_SET__scsi0__WIDTH 1 | ||
| 950 | #define R_PORT_PB_SET__scsi0__port_cs 0 | ||
| 951 | #define R_PORT_PB_SET__scsi0__enph 1 | ||
| 952 | #define R_PORT_PB_SET__dir7__BITNR 15 | ||
| 953 | #define R_PORT_PB_SET__dir7__WIDTH 1 | ||
| 954 | #define R_PORT_PB_SET__dir7__input 0 | ||
| 955 | #define R_PORT_PB_SET__dir7__output 1 | ||
| 956 | #define R_PORT_PB_SET__dir6__BITNR 14 | ||
| 957 | #define R_PORT_PB_SET__dir6__WIDTH 1 | ||
| 958 | #define R_PORT_PB_SET__dir6__input 0 | ||
| 959 | #define R_PORT_PB_SET__dir6__output 1 | ||
| 960 | #define R_PORT_PB_SET__dir5__BITNR 13 | ||
| 961 | #define R_PORT_PB_SET__dir5__WIDTH 1 | ||
| 962 | #define R_PORT_PB_SET__dir5__input 0 | ||
| 963 | #define R_PORT_PB_SET__dir5__output 1 | ||
| 964 | #define R_PORT_PB_SET__dir4__BITNR 12 | ||
| 965 | #define R_PORT_PB_SET__dir4__WIDTH 1 | ||
| 966 | #define R_PORT_PB_SET__dir4__input 0 | ||
| 967 | #define R_PORT_PB_SET__dir4__output 1 | ||
| 968 | #define R_PORT_PB_SET__dir3__BITNR 11 | ||
| 969 | #define R_PORT_PB_SET__dir3__WIDTH 1 | ||
| 970 | #define R_PORT_PB_SET__dir3__input 0 | ||
| 971 | #define R_PORT_PB_SET__dir3__output 1 | ||
| 972 | #define R_PORT_PB_SET__dir2__BITNR 10 | ||
| 973 | #define R_PORT_PB_SET__dir2__WIDTH 1 | ||
| 974 | #define R_PORT_PB_SET__dir2__input 0 | ||
| 975 | #define R_PORT_PB_SET__dir2__output 1 | ||
| 976 | #define R_PORT_PB_SET__dir1__BITNR 9 | ||
| 977 | #define R_PORT_PB_SET__dir1__WIDTH 1 | ||
| 978 | #define R_PORT_PB_SET__dir1__input 0 | ||
| 979 | #define R_PORT_PB_SET__dir1__output 1 | ||
| 980 | #define R_PORT_PB_SET__dir0__BITNR 8 | ||
| 981 | #define R_PORT_PB_SET__dir0__WIDTH 1 | ||
| 982 | #define R_PORT_PB_SET__dir0__input 0 | ||
| 983 | #define R_PORT_PB_SET__dir0__output 1 | ||
| 984 | #define R_PORT_PB_SET__data_out__BITNR 0 | ||
| 985 | #define R_PORT_PB_SET__data_out__WIDTH 8 | ||
| 986 | |||
| 987 | #define R_PORT_PB_DATA (IO_TYPECAST_BYTE 0xb0000038) | ||
| 988 | #define R_PORT_PB_DATA__data_out__BITNR 0 | ||
| 989 | #define R_PORT_PB_DATA__data_out__WIDTH 8 | ||
| 990 | |||
| 991 | #define R_PORT_PB_DIR (IO_TYPECAST_BYTE 0xb0000039) | ||
| 992 | #define R_PORT_PB_DIR__dir7__BITNR 7 | ||
| 993 | #define R_PORT_PB_DIR__dir7__WIDTH 1 | ||
| 994 | #define R_PORT_PB_DIR__dir7__input 0 | ||
| 995 | #define R_PORT_PB_DIR__dir7__output 1 | ||
| 996 | #define R_PORT_PB_DIR__dir6__BITNR 6 | ||
| 997 | #define R_PORT_PB_DIR__dir6__WIDTH 1 | ||
| 998 | #define R_PORT_PB_DIR__dir6__input 0 | ||
| 999 | #define R_PORT_PB_DIR__dir6__output 1 | ||
| 1000 | #define R_PORT_PB_DIR__dir5__BITNR 5 | ||
| 1001 | #define R_PORT_PB_DIR__dir5__WIDTH 1 | ||
| 1002 | #define R_PORT_PB_DIR__dir5__input 0 | ||
| 1003 | #define R_PORT_PB_DIR__dir5__output 1 | ||
| 1004 | #define R_PORT_PB_DIR__dir4__BITNR 4 | ||
| 1005 | #define R_PORT_PB_DIR__dir4__WIDTH 1 | ||
| 1006 | #define R_PORT_PB_DIR__dir4__input 0 | ||
| 1007 | #define R_PORT_PB_DIR__dir4__output 1 | ||
| 1008 | #define R_PORT_PB_DIR__dir3__BITNR 3 | ||
| 1009 | #define R_PORT_PB_DIR__dir3__WIDTH 1 | ||
| 1010 | #define R_PORT_PB_DIR__dir3__input 0 | ||
| 1011 | #define R_PORT_PB_DIR__dir3__output 1 | ||
| 1012 | #define R_PORT_PB_DIR__dir2__BITNR 2 | ||
| 1013 | #define R_PORT_PB_DIR__dir2__WIDTH 1 | ||
| 1014 | #define R_PORT_PB_DIR__dir2__input 0 | ||
| 1015 | #define R_PORT_PB_DIR__dir2__output 1 | ||
| 1016 | #define R_PORT_PB_DIR__dir1__BITNR 1 | ||
| 1017 | #define R_PORT_PB_DIR__dir1__WIDTH 1 | ||
| 1018 | #define R_PORT_PB_DIR__dir1__input 0 | ||
| 1019 | #define R_PORT_PB_DIR__dir1__output 1 | ||
| 1020 | #define R_PORT_PB_DIR__dir0__BITNR 0 | ||
| 1021 | #define R_PORT_PB_DIR__dir0__WIDTH 1 | ||
| 1022 | #define R_PORT_PB_DIR__dir0__input 0 | ||
| 1023 | #define R_PORT_PB_DIR__dir0__output 1 | ||
| 1024 | |||
| 1025 | #define R_PORT_PB_CONFIG (IO_TYPECAST_BYTE 0xb000003a) | ||
| 1026 | #define R_PORT_PB_CONFIG__cs7__BITNR 7 | ||
| 1027 | #define R_PORT_PB_CONFIG__cs7__WIDTH 1 | ||
| 1028 | #define R_PORT_PB_CONFIG__cs7__port 0 | ||
| 1029 | #define R_PORT_PB_CONFIG__cs7__cs 1 | ||
| 1030 | #define R_PORT_PB_CONFIG__cs6__BITNR 6 | ||
| 1031 | #define R_PORT_PB_CONFIG__cs6__WIDTH 1 | ||
| 1032 | #define R_PORT_PB_CONFIG__cs6__port 0 | ||
| 1033 | #define R_PORT_PB_CONFIG__cs6__cs 1 | ||
| 1034 | #define R_PORT_PB_CONFIG__cs5__BITNR 5 | ||
| 1035 | #define R_PORT_PB_CONFIG__cs5__WIDTH 1 | ||
| 1036 | #define R_PORT_PB_CONFIG__cs5__port 0 | ||
| 1037 | #define R_PORT_PB_CONFIG__cs5__cs 1 | ||
| 1038 | #define R_PORT_PB_CONFIG__cs4__BITNR 4 | ||
| 1039 | #define R_PORT_PB_CONFIG__cs4__WIDTH 1 | ||
| 1040 | #define R_PORT_PB_CONFIG__cs4__port 0 | ||
| 1041 | #define R_PORT_PB_CONFIG__cs4__cs 1 | ||
| 1042 | #define R_PORT_PB_CONFIG__cs3__BITNR 3 | ||
| 1043 | #define R_PORT_PB_CONFIG__cs3__WIDTH 1 | ||
| 1044 | #define R_PORT_PB_CONFIG__cs3__port 0 | ||
| 1045 | #define R_PORT_PB_CONFIG__cs3__cs 1 | ||
| 1046 | #define R_PORT_PB_CONFIG__cs2__BITNR 2 | ||
| 1047 | #define R_PORT_PB_CONFIG__cs2__WIDTH 1 | ||
| 1048 | #define R_PORT_PB_CONFIG__cs2__port 0 | ||
| 1049 | #define R_PORT_PB_CONFIG__cs2__cs 1 | ||
| 1050 | #define R_PORT_PB_CONFIG__scsi1__BITNR 1 | ||
| 1051 | #define R_PORT_PB_CONFIG__scsi1__WIDTH 1 | ||
| 1052 | #define R_PORT_PB_CONFIG__scsi1__port_cs 0 | ||
| 1053 | #define R_PORT_PB_CONFIG__scsi1__enph 1 | ||
| 1054 | #define R_PORT_PB_CONFIG__scsi0__BITNR 0 | ||
| 1055 | #define R_PORT_PB_CONFIG__scsi0__WIDTH 1 | ||
| 1056 | #define R_PORT_PB_CONFIG__scsi0__port_cs 0 | ||
| 1057 | #define R_PORT_PB_CONFIG__scsi0__enph 1 | ||
| 1058 | |||
| 1059 | #define R_PORT_PB_I2C (IO_TYPECAST_BYTE 0xb000003b) | ||
| 1060 | #define R_PORT_PB_I2C__syncser3__BITNR 5 | ||
| 1061 | #define R_PORT_PB_I2C__syncser3__WIDTH 1 | ||
| 1062 | #define R_PORT_PB_I2C__syncser3__port_cs 0 | ||
| 1063 | #define R_PORT_PB_I2C__syncser3__ss3extra 1 | ||
| 1064 | #define R_PORT_PB_I2C__syncser1__BITNR 4 | ||
| 1065 | #define R_PORT_PB_I2C__syncser1__WIDTH 1 | ||
| 1066 | #define R_PORT_PB_I2C__syncser1__port_cs 0 | ||
| 1067 | #define R_PORT_PB_I2C__syncser1__ss1extra 1 | ||
| 1068 | #define R_PORT_PB_I2C__i2c_en__BITNR 3 | ||
| 1069 | #define R_PORT_PB_I2C__i2c_en__WIDTH 1 | ||
| 1070 | #define R_PORT_PB_I2C__i2c_en__off 0 | ||
| 1071 | #define R_PORT_PB_I2C__i2c_en__on 1 | ||
| 1072 | #define R_PORT_PB_I2C__i2c_d__BITNR 2 | ||
| 1073 | #define R_PORT_PB_I2C__i2c_d__WIDTH 1 | ||
| 1074 | #define R_PORT_PB_I2C__i2c_clk__BITNR 1 | ||
| 1075 | #define R_PORT_PB_I2C__i2c_clk__WIDTH 1 | ||
| 1076 | #define R_PORT_PB_I2C__i2c_oe___BITNR 0 | ||
| 1077 | #define R_PORT_PB_I2C__i2c_oe___WIDTH 1 | ||
| 1078 | #define R_PORT_PB_I2C__i2c_oe___enable 0 | ||
| 1079 | #define R_PORT_PB_I2C__i2c_oe___disable 1 | ||
| 1080 | |||
| 1081 | #define R_PORT_PB_READ (IO_TYPECAST_RO_UDWORD 0xb0000038) | ||
| 1082 | #define R_PORT_PB_READ__data_in__BITNR 0 | ||
| 1083 | #define R_PORT_PB_READ__data_in__WIDTH 8 | ||
| 1084 | |||
| 1085 | /* | ||
| 1086 | !* Serial port registers | ||
| 1087 | !*/ | ||
| 1088 | |||
| 1089 | #define R_SERIAL0_CTRL (IO_TYPECAST_UDWORD 0xb0000060) | ||
| 1090 | #define R_SERIAL0_CTRL__tr_baud__BITNR 28 | ||
| 1091 | #define R_SERIAL0_CTRL__tr_baud__WIDTH 4 | ||
| 1092 | #define R_SERIAL0_CTRL__tr_baud__c300Hz 0 | ||
| 1093 | #define R_SERIAL0_CTRL__tr_baud__c600Hz 1 | ||
| 1094 | #define R_SERIAL0_CTRL__tr_baud__c1200Hz 2 | ||
| 1095 | #define R_SERIAL0_CTRL__tr_baud__c2400Hz 3 | ||
| 1096 | #define R_SERIAL0_CTRL__tr_baud__c4800Hz 4 | ||
| 1097 | #define R_SERIAL0_CTRL__tr_baud__c9600Hz 5 | ||
| 1098 | #define R_SERIAL0_CTRL__tr_baud__c19k2Hz 6 | ||
| 1099 | #define R_SERIAL0_CTRL__tr_baud__c38k4Hz 7 | ||
| 1100 | #define R_SERIAL0_CTRL__tr_baud__c57k6Hz 8 | ||
| 1101 | #define R_SERIAL0_CTRL__tr_baud__c115k2Hz 9 | ||
| 1102 | #define R_SERIAL0_CTRL__tr_baud__c230k4Hz 10 | ||
| 1103 | #define R_SERIAL0_CTRL__tr_baud__c460k8Hz 11 | ||
| 1104 | #define R_SERIAL0_CTRL__tr_baud__c921k6Hz 12 | ||
| 1105 | #define R_SERIAL0_CTRL__tr_baud__c1843k2Hz 13 | ||
| 1106 | #define R_SERIAL0_CTRL__tr_baud__c6250kHz 14 | ||
| 1107 | #define R_SERIAL0_CTRL__tr_baud__reserved 15 | ||
| 1108 | #define R_SERIAL0_CTRL__rec_baud__BITNR 24 | ||
| 1109 | #define R_SERIAL0_CTRL__rec_baud__WIDTH 4 | ||
| 1110 | #define R_SERIAL0_CTRL__rec_baud__c300Hz 0 | ||
| 1111 | #define R_SERIAL0_CTRL__rec_baud__c600Hz 1 | ||
| 1112 | #define R_SERIAL0_CTRL__rec_baud__c1200Hz 2 | ||
| 1113 | #define R_SERIAL0_CTRL__rec_baud__c2400Hz 3 | ||
| 1114 | #define R_SERIAL0_CTRL__rec_baud__c4800Hz 4 | ||
| 1115 | #define R_SERIAL0_CTRL__rec_baud__c9600Hz 5 | ||
| 1116 | #define R_SERIAL0_CTRL__rec_baud__c19k2Hz 6 | ||
| 1117 | #define R_SERIAL0_CTRL__rec_baud__c38k4Hz 7 | ||
| 1118 | #define R_SERIAL0_CTRL__rec_baud__c57k6Hz 8 | ||
| 1119 | #define R_SERIAL0_CTRL__rec_baud__c115k2Hz 9 | ||
| 1120 | #define R_SERIAL0_CTRL__rec_baud__c230k4Hz 10 | ||
| 1121 | #define R_SERIAL0_CTRL__rec_baud__c460k8Hz 11 | ||
| 1122 | #define R_SERIAL0_CTRL__rec_baud__c921k6Hz 12 | ||
| 1123 | #define R_SERIAL0_CTRL__rec_baud__c1843k2Hz 13 | ||
| 1124 | #define R_SERIAL0_CTRL__rec_baud__c6250kHz 14 | ||
| 1125 | #define R_SERIAL0_CTRL__rec_baud__reserved 15 | ||
| 1126 | #define R_SERIAL0_CTRL__dma_err__BITNR 23 | ||
| 1127 | #define R_SERIAL0_CTRL__dma_err__WIDTH 1 | ||
| 1128 | #define R_SERIAL0_CTRL__dma_err__stop 0 | ||
| 1129 | #define R_SERIAL0_CTRL__dma_err__ignore 1 | ||
| 1130 | #define R_SERIAL0_CTRL__rec_enable__BITNR 22 | ||
| 1131 | #define R_SERIAL0_CTRL__rec_enable__WIDTH 1 | ||
| 1132 | #define R_SERIAL0_CTRL__rec_enable__disable 0 | ||
| 1133 | #define R_SERIAL0_CTRL__rec_enable__enable 1 | ||
| 1134 | #define R_SERIAL0_CTRL__rts___BITNR 21 | ||
| 1135 | #define R_SERIAL0_CTRL__rts___WIDTH 1 | ||
| 1136 | #define R_SERIAL0_CTRL__rts___active 0 | ||
| 1137 | #define R_SERIAL0_CTRL__rts___inactive 1 | ||
| 1138 | #define R_SERIAL0_CTRL__sampling__BITNR 20 | ||
| 1139 | #define R_SERIAL0_CTRL__sampling__WIDTH 1 | ||
| 1140 | #define R_SERIAL0_CTRL__sampling__middle 0 | ||
| 1141 | #define R_SERIAL0_CTRL__sampling__majority 1 | ||
| 1142 | #define R_SERIAL0_CTRL__rec_stick_par__BITNR 19 | ||
| 1143 | #define R_SERIAL0_CTRL__rec_stick_par__WIDTH 1 | ||
| 1144 | #define R_SERIAL0_CTRL__rec_stick_par__normal 0 | ||
| 1145 | #define R_SERIAL0_CTRL__rec_stick_par__stick 1 | ||
| 1146 | #define R_SERIAL0_CTRL__rec_par__BITNR 18 | ||
| 1147 | #define R_SERIAL0_CTRL__rec_par__WIDTH 1 | ||
| 1148 | #define R_SERIAL0_CTRL__rec_par__even 0 | ||
| 1149 | #define R_SERIAL0_CTRL__rec_par__odd 1 | ||
| 1150 | #define R_SERIAL0_CTRL__rec_par_en__BITNR 17 | ||
| 1151 | #define R_SERIAL0_CTRL__rec_par_en__WIDTH 1 | ||
| 1152 | #define R_SERIAL0_CTRL__rec_par_en__disable 0 | ||
| 1153 | #define R_SERIAL0_CTRL__rec_par_en__enable 1 | ||
| 1154 | #define R_SERIAL0_CTRL__rec_bitnr__BITNR 16 | ||
| 1155 | #define R_SERIAL0_CTRL__rec_bitnr__WIDTH 1 | ||
| 1156 | #define R_SERIAL0_CTRL__rec_bitnr__rec_8bit 0 | ||
| 1157 | #define R_SERIAL0_CTRL__rec_bitnr__rec_7bit 1 | ||
| 1158 | #define R_SERIAL0_CTRL__txd__BITNR 15 | ||
| 1159 | #define R_SERIAL0_CTRL__txd__WIDTH 1 | ||
| 1160 | #define R_SERIAL0_CTRL__tr_enable__BITNR 14 | ||
| 1161 | #define R_SERIAL0_CTRL__tr_enable__WIDTH 1 | ||
| 1162 | #define R_SERIAL0_CTRL__tr_enable__disable 0 | ||
| 1163 | #define R_SERIAL0_CTRL__tr_enable__enable 1 | ||
| 1164 | #define R_SERIAL0_CTRL__auto_cts__BITNR 13 | ||
| 1165 | #define R_SERIAL0_CTRL__auto_cts__WIDTH 1 | ||
| 1166 | #define R_SERIAL0_CTRL__auto_cts__disabled 0 | ||
| 1167 | #define R_SERIAL0_CTRL__auto_cts__active 1 | ||
| 1168 | #define R_SERIAL0_CTRL__stop_bits__BITNR 12 | ||
| 1169 | #define R_SERIAL0_CTRL__stop_bits__WIDTH 1 | ||
| 1170 | #define R_SERIAL0_CTRL__stop_bits__one_bit 0 | ||
| 1171 | #define R_SERIAL0_CTRL__stop_bits__two_bits 1 | ||
| 1172 | #define R_SERIAL0_CTRL__tr_stick_par__BITNR 11 | ||
| 1173 | #define R_SERIAL0_CTRL__tr_stick_par__WIDTH 1 | ||
| 1174 | #define R_SERIAL0_CTRL__tr_stick_par__normal 0 | ||
| 1175 | #define R_SERIAL0_CTRL__tr_stick_par__stick 1 | ||
| 1176 | #define R_SERIAL0_CTRL__tr_par__BITNR 10 | ||
| 1177 | #define R_SERIAL0_CTRL__tr_par__WIDTH 1 | ||
| 1178 | #define R_SERIAL0_CTRL__tr_par__even 0 | ||
| 1179 | #define R_SERIAL0_CTRL__tr_par__odd 1 | ||
| 1180 | #define R_SERIAL0_CTRL__tr_par_en__BITNR 9 | ||
| 1181 | #define R_SERIAL0_CTRL__tr_par_en__WIDTH 1 | ||
| 1182 | #define R_SERIAL0_CTRL__tr_par_en__disable 0 | ||
| 1183 | #define R_SERIAL0_CTRL__tr_par_en__enable 1 | ||
| 1184 | #define R_SERIAL0_CTRL__tr_bitnr__BITNR 8 | ||
| 1185 | #define R_SERIAL0_CTRL__tr_bitnr__WIDTH 1 | ||
| 1186 | #define R_SERIAL0_CTRL__tr_bitnr__tr_8bit 0 | ||
| 1187 | #define R_SERIAL0_CTRL__tr_bitnr__tr_7bit 1 | ||
| 1188 | #define R_SERIAL0_CTRL__data_out__BITNR 0 | ||
| 1189 | #define R_SERIAL0_CTRL__data_out__WIDTH 8 | ||
| 1190 | |||
| 1191 | #define R_SERIAL0_BAUD (IO_TYPECAST_BYTE 0xb0000063) | ||
| 1192 | #define R_SERIAL0_BAUD__tr_baud__BITNR 4 | ||
| 1193 | #define R_SERIAL0_BAUD__tr_baud__WIDTH 4 | ||
| 1194 | #define R_SERIAL0_BAUD__tr_baud__c300Hz 0 | ||
| 1195 | #define R_SERIAL0_BAUD__tr_baud__c600Hz 1 | ||
| 1196 | #define R_SERIAL0_BAUD__tr_baud__c1200Hz 2 | ||
| 1197 | #define R_SERIAL0_BAUD__tr_baud__c2400Hz 3 | ||
| 1198 | #define R_SERIAL0_BAUD__tr_baud__c4800Hz 4 | ||
| 1199 | #define R_SERIAL0_BAUD__tr_baud__c9600Hz 5 | ||
| 1200 | #define R_SERIAL0_BAUD__tr_baud__c19k2Hz 6 | ||
| 1201 | #define R_SERIAL0_BAUD__tr_baud__c38k4Hz 7 | ||
| 1202 | #define R_SERIAL0_BAUD__tr_baud__c57k6Hz 8 | ||
| 1203 | #define R_SERIAL0_BAUD__tr_baud__c115k2Hz 9 | ||
| 1204 | #define R_SERIAL0_BAUD__tr_baud__c230k4Hz 10 | ||
| 1205 | #define R_SERIAL0_BAUD__tr_baud__c460k8Hz 11 | ||
| 1206 | #define R_SERIAL0_BAUD__tr_baud__c921k6Hz 12 | ||
| 1207 | #define R_SERIAL0_BAUD__tr_baud__c1843k2Hz 13 | ||
| 1208 | #define R_SERIAL0_BAUD__tr_baud__c6250kHz 14 | ||
| 1209 | #define R_SERIAL0_BAUD__tr_baud__reserved 15 | ||
| 1210 | #define R_SERIAL0_BAUD__rec_baud__BITNR 0 | ||
| 1211 | #define R_SERIAL0_BAUD__rec_baud__WIDTH 4 | ||
| 1212 | #define R_SERIAL0_BAUD__rec_baud__c300Hz 0 | ||
| 1213 | #define R_SERIAL0_BAUD__rec_baud__c600Hz 1 | ||
| 1214 | #define R_SERIAL0_BAUD__rec_baud__c1200Hz 2 | ||
| 1215 | #define R_SERIAL0_BAUD__rec_baud__c2400Hz 3 | ||
| 1216 | #define R_SERIAL0_BAUD__rec_baud__c4800Hz 4 | ||
| 1217 | #define R_SERIAL0_BAUD__rec_baud__c9600Hz 5 | ||
| 1218 | #define R_SERIAL0_BAUD__rec_baud__c19k2Hz 6 | ||
| 1219 | #define R_SERIAL0_BAUD__rec_baud__c38k4Hz 7 | ||
| 1220 | #define R_SERIAL0_BAUD__rec_baud__c57k6Hz 8 | ||
| 1221 | #define R_SERIAL0_BAUD__rec_baud__c115k2Hz 9 | ||
| 1222 | #define R_SERIAL0_BAUD__rec_baud__c230k4Hz 10 | ||
| 1223 | #define R_SERIAL0_BAUD__rec_baud__c460k8Hz 11 | ||
| 1224 | #define R_SERIAL0_BAUD__rec_baud__c921k6Hz 12 | ||
| 1225 | #define R_SERIAL0_BAUD__rec_baud__c1843k2Hz 13 | ||
| 1226 | #define R_SERIAL0_BAUD__rec_baud__c6250kHz 14 | ||
| 1227 | #define R_SERIAL0_BAUD__rec_baud__reserved 15 | ||
| 1228 | |||
| 1229 | #define R_SERIAL0_REC_CTRL (IO_TYPECAST_BYTE 0xb0000062) | ||
| 1230 | #define R_SERIAL0_REC_CTRL__dma_err__BITNR 7 | ||
| 1231 | #define R_SERIAL0_REC_CTRL__dma_err__WIDTH 1 | ||
| 1232 | #define R_SERIAL0_REC_CTRL__dma_err__stop 0 | ||
| 1233 | #define R_SERIAL0_REC_CTRL__dma_err__ignore 1 | ||
| 1234 | #define R_SERIAL0_REC_CTRL__rec_enable__BITNR 6 | ||
| 1235 | #define R_SERIAL0_REC_CTRL__rec_enable__WIDTH 1 | ||
| 1236 | #define R_SERIAL0_REC_CTRL__rec_enable__disable 0 | ||
| 1237 | #define R_SERIAL0_REC_CTRL__rec_enable__enable 1 | ||
| 1238 | #define R_SERIAL0_REC_CTRL__rts___BITNR 5 | ||
| 1239 | #define R_SERIAL0_REC_CTRL__rts___WIDTH 1 | ||
| 1240 | #define R_SERIAL0_REC_CTRL__rts___active 0 | ||
| 1241 | #define R_SERIAL0_REC_CTRL__rts___inactive 1 | ||
| 1242 | #define R_SERIAL0_REC_CTRL__sampling__BITNR 4 | ||
| 1243 | #define R_SERIAL0_REC_CTRL__sampling__WIDTH 1 | ||
| 1244 | #define R_SERIAL0_REC_CTRL__sampling__middle 0 | ||
| 1245 | #define R_SERIAL0_REC_CTRL__sampling__majority 1 | ||
| 1246 | #define R_SERIAL0_REC_CTRL__rec_stick_par__BITNR 3 | ||
| 1247 | #define R_SERIAL0_REC_CTRL__rec_stick_par__WIDTH 1 | ||
| 1248 | #define R_SERIAL0_REC_CTRL__rec_stick_par__normal 0 | ||
| 1249 | #define R_SERIAL0_REC_CTRL__rec_stick_par__stick 1 | ||
| 1250 | #define R_SERIAL0_REC_CTRL__rec_par__BITNR 2 | ||
| 1251 | #define R_SERIAL0_REC_CTRL__rec_par__WIDTH 1 | ||
| 1252 | #define R_SERIAL0_REC_CTRL__rec_par__even 0 | ||
| 1253 | #define R_SERIAL0_REC_CTRL__rec_par__odd 1 | ||
| 1254 | #define R_SERIAL0_REC_CTRL__rec_par_en__BITNR 1 | ||
| 1255 | #define R_SERIAL0_REC_CTRL__rec_par_en__WIDTH 1 | ||
| 1256 | #define R_SERIAL0_REC_CTRL__rec_par_en__disable 0 | ||
| 1257 | #define R_SERIAL0_REC_CTRL__rec_par_en__enable 1 | ||
| 1258 | #define R_SERIAL0_REC_CTRL__rec_bitnr__BITNR 0 | ||
| 1259 | #define R_SERIAL0_REC_CTRL__rec_bitnr__WIDTH 1 | ||
| 1260 | #define R_SERIAL0_REC_CTRL__rec_bitnr__rec_8bit 0 | ||
| 1261 | #define R_SERIAL0_REC_CTRL__rec_bitnr__rec_7bit 1 | ||
| 1262 | |||
| 1263 | #define R_SERIAL0_TR_CTRL (IO_TYPECAST_BYTE 0xb0000061) | ||
| 1264 | #define R_SERIAL0_TR_CTRL__txd__BITNR 7 | ||
| 1265 | #define R_SERIAL0_TR_CTRL__txd__WIDTH 1 | ||
| 1266 | #define R_SERIAL0_TR_CTRL__tr_enable__BITNR 6 | ||
| 1267 | #define R_SERIAL0_TR_CTRL__tr_enable__WIDTH 1 | ||
| 1268 | #define R_SERIAL0_TR_CTRL__tr_enable__disable 0 | ||
| 1269 | #define R_SERIAL0_TR_CTRL__tr_enable__enable 1 | ||
| 1270 | #define R_SERIAL0_TR_CTRL__auto_cts__BITNR 5 | ||
| 1271 | #define R_SERIAL0_TR_CTRL__auto_cts__WIDTH 1 | ||
| 1272 | #define R_SERIAL0_TR_CTRL__auto_cts__disabled 0 | ||
| 1273 | #define R_SERIAL0_TR_CTRL__auto_cts__active 1 | ||
| 1274 | #define R_SERIAL0_TR_CTRL__stop_bits__BITNR 4 | ||
| 1275 | #define R_SERIAL0_TR_CTRL__stop_bits__WIDTH 1 | ||
| 1276 | #define R_SERIAL0_TR_CTRL__stop_bits__one_bit 0 | ||
| 1277 | #define R_SERIAL0_TR_CTRL__stop_bits__two_bits 1 | ||
| 1278 | #define R_SERIAL0_TR_CTRL__tr_stick_par__BITNR 3 | ||
| 1279 | #define R_SERIAL0_TR_CTRL__tr_stick_par__WIDTH 1 | ||
| 1280 | #define R_SERIAL0_TR_CTRL__tr_stick_par__normal 0 | ||
| 1281 | #define R_SERIAL0_TR_CTRL__tr_stick_par__stick 1 | ||
| 1282 | #define R_SERIAL0_TR_CTRL__tr_par__BITNR 2 | ||
| 1283 | #define R_SERIAL0_TR_CTRL__tr_par__WIDTH 1 | ||
| 1284 | #define R_SERIAL0_TR_CTRL__tr_par__even 0 | ||
| 1285 | #define R_SERIAL0_TR_CTRL__tr_par__odd 1 | ||
| 1286 | #define R_SERIAL0_TR_CTRL__tr_par_en__BITNR 1 | ||
| 1287 | #define R_SERIAL0_TR_CTRL__tr_par_en__WIDTH 1 | ||
| 1288 | #define R_SERIAL0_TR_CTRL__tr_par_en__disable 0 | ||
| 1289 | #define R_SERIAL0_TR_CTRL__tr_par_en__enable 1 | ||
| 1290 | #define R_SERIAL0_TR_CTRL__tr_bitnr__BITNR 0 | ||
| 1291 | #define R_SERIAL0_TR_CTRL__tr_bitnr__WIDTH 1 | ||
| 1292 | #define R_SERIAL0_TR_CTRL__tr_bitnr__tr_8bit 0 | ||
| 1293 | #define R_SERIAL0_TR_CTRL__tr_bitnr__tr_7bit 1 | ||
| 1294 | |||
| 1295 | #define R_SERIAL0_TR_DATA (IO_TYPECAST_BYTE 0xb0000060) | ||
| 1296 | #define R_SERIAL0_TR_DATA__data_out__BITNR 0 | ||
| 1297 | #define R_SERIAL0_TR_DATA__data_out__WIDTH 8 | ||
| 1298 | |||
| 1299 | #define R_SERIAL0_READ (IO_TYPECAST_RO_UDWORD 0xb0000060) | ||
| 1300 | #define R_SERIAL0_READ__xoff_detect__BITNR 15 | ||
| 1301 | #define R_SERIAL0_READ__xoff_detect__WIDTH 1 | ||
| 1302 | #define R_SERIAL0_READ__xoff_detect__no_xoff 0 | ||
| 1303 | #define R_SERIAL0_READ__xoff_detect__xoff 1 | ||
| 1304 | #define R_SERIAL0_READ__cts___BITNR 14 | ||
| 1305 | #define R_SERIAL0_READ__cts___WIDTH 1 | ||
| 1306 | #define R_SERIAL0_READ__cts___active 0 | ||
| 1307 | #define R_SERIAL0_READ__cts___inactive 1 | ||
| 1308 | #define R_SERIAL0_READ__tr_ready__BITNR 13 | ||
| 1309 | #define R_SERIAL0_READ__tr_ready__WIDTH 1 | ||
| 1310 | #define R_SERIAL0_READ__tr_ready__full 0 | ||
| 1311 | #define R_SERIAL0_READ__tr_ready__ready 1 | ||
| 1312 | #define R_SERIAL0_READ__rxd__BITNR 12 | ||
| 1313 | #define R_SERIAL0_READ__rxd__WIDTH 1 | ||
| 1314 | #define R_SERIAL0_READ__overrun__BITNR 11 | ||
| 1315 | #define R_SERIAL0_READ__overrun__WIDTH 1 | ||
| 1316 | #define R_SERIAL0_READ__overrun__no 0 | ||
| 1317 | #define R_SERIAL0_READ__overrun__yes 1 | ||
| 1318 | #define R_SERIAL0_READ__par_err__BITNR 10 | ||
| 1319 | #define R_SERIAL0_READ__par_err__WIDTH 1 | ||
| 1320 | #define R_SERIAL0_READ__par_err__no 0 | ||
| 1321 | #define R_SERIAL0_READ__par_err__yes 1 | ||
| 1322 | #define R_SERIAL0_READ__framing_err__BITNR 9 | ||
| 1323 | #define R_SERIAL0_READ__framing_err__WIDTH 1 | ||
| 1324 | #define R_SERIAL0_READ__framing_err__no 0 | ||
| 1325 | #define R_SERIAL0_READ__framing_err__yes 1 | ||
| 1326 | #define R_SERIAL0_READ__data_avail__BITNR 8 | ||
| 1327 | #define R_SERIAL0_READ__data_avail__WIDTH 1 | ||
| 1328 | #define R_SERIAL0_READ__data_avail__no 0 | ||
| 1329 | #define R_SERIAL0_READ__data_avail__yes 1 | ||
| 1330 | #define R_SERIAL0_READ__data_in__BITNR 0 | ||
| 1331 | #define R_SERIAL0_READ__data_in__WIDTH 8 | ||
| 1332 | |||
| 1333 | #define R_SERIAL0_STATUS (IO_TYPECAST_RO_BYTE 0xb0000061) | ||
| 1334 | #define R_SERIAL0_STATUS__xoff_detect__BITNR 7 | ||
| 1335 | #define R_SERIAL0_STATUS__xoff_detect__WIDTH 1 | ||
| 1336 | #define R_SERIAL0_STATUS__xoff_detect__no_xoff 0 | ||
| 1337 | #define R_SERIAL0_STATUS__xoff_detect__xoff 1 | ||
| 1338 | #define R_SERIAL0_STATUS__cts___BITNR 6 | ||
| 1339 | #define R_SERIAL0_STATUS__cts___WIDTH 1 | ||
| 1340 | #define R_SERIAL0_STATUS__cts___active 0 | ||
| 1341 | #define R_SERIAL0_STATUS__cts___inactive 1 | ||
| 1342 | #define R_SERIAL0_STATUS__tr_ready__BITNR 5 | ||
| 1343 | #define R_SERIAL0_STATUS__tr_ready__WIDTH 1 | ||
| 1344 | #define R_SERIAL0_STATUS__tr_ready__full 0 | ||
| 1345 | #define R_SERIAL0_STATUS__tr_ready__ready 1 | ||
| 1346 | #define R_SERIAL0_STATUS__rxd__BITNR 4 | ||
| 1347 | #define R_SERIAL0_STATUS__rxd__WIDTH 1 | ||
| 1348 | #define R_SERIAL0_STATUS__overrun__BITNR 3 | ||
| 1349 | #define R_SERIAL0_STATUS__overrun__WIDTH 1 | ||
| 1350 | #define R_SERIAL0_STATUS__overrun__no 0 | ||
| 1351 | #define R_SERIAL0_STATUS__overrun__yes 1 | ||
| 1352 | #define R_SERIAL0_STATUS__par_err__BITNR 2 | ||
| 1353 | #define R_SERIAL0_STATUS__par_err__WIDTH 1 | ||
| 1354 | #define R_SERIAL0_STATUS__par_err__no 0 | ||
| 1355 | #define R_SERIAL0_STATUS__par_err__yes 1 | ||
| 1356 | #define R_SERIAL0_STATUS__framing_err__BITNR 1 | ||
| 1357 | #define R_SERIAL0_STATUS__framing_err__WIDTH 1 | ||
| 1358 | #define R_SERIAL0_STATUS__framing_err__no 0 | ||
| 1359 | #define R_SERIAL0_STATUS__framing_err__yes 1 | ||
| 1360 | #define R_SERIAL0_STATUS__data_avail__BITNR 0 | ||
| 1361 | #define R_SERIAL0_STATUS__data_avail__WIDTH 1 | ||
| 1362 | #define R_SERIAL0_STATUS__data_avail__no 0 | ||
| 1363 | #define R_SERIAL0_STATUS__data_avail__yes 1 | ||
| 1364 | |||
| 1365 | #define R_SERIAL0_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000060) | ||
| 1366 | #define R_SERIAL0_REC_DATA__data_in__BITNR 0 | ||
| 1367 | #define R_SERIAL0_REC_DATA__data_in__WIDTH 8 | ||
| 1368 | |||
| 1369 | #define R_SERIAL0_XOFF (IO_TYPECAST_UDWORD 0xb0000064) | ||
| 1370 | #define R_SERIAL0_XOFF__tx_stop__BITNR 9 | ||
| 1371 | #define R_SERIAL0_XOFF__tx_stop__WIDTH 1 | ||
| 1372 | #define R_SERIAL0_XOFF__tx_stop__enable 0 | ||
| 1373 | #define R_SERIAL0_XOFF__tx_stop__stop 1 | ||
| 1374 | #define R_SERIAL0_XOFF__auto_xoff__BITNR 8 | ||
| 1375 | #define R_SERIAL0_XOFF__auto_xoff__WIDTH 1 | ||
| 1376 | #define R_SERIAL0_XOFF__auto_xoff__disable 0 | ||
| 1377 | #define R_SERIAL0_XOFF__auto_xoff__enable 1 | ||
| 1378 | #define R_SERIAL0_XOFF__xoff_char__BITNR 0 | ||
| 1379 | #define R_SERIAL0_XOFF__xoff_char__WIDTH 8 | ||
| 1380 | |||
| 1381 | #define R_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068) | ||
| 1382 | #define R_SERIAL1_CTRL__tr_baud__BITNR 28 | ||
| 1383 | #define R_SERIAL1_CTRL__tr_baud__WIDTH 4 | ||
| 1384 | #define R_SERIAL1_CTRL__tr_baud__c300Hz 0 | ||
| 1385 | #define R_SERIAL1_CTRL__tr_baud__c600Hz 1 | ||
| 1386 | #define R_SERIAL1_CTRL__tr_baud__c1200Hz 2 | ||
| 1387 | #define R_SERIAL1_CTRL__tr_baud__c2400Hz 3 | ||
| 1388 | #define R_SERIAL1_CTRL__tr_baud__c4800Hz 4 | ||
| 1389 | #define R_SERIAL1_CTRL__tr_baud__c9600Hz 5 | ||
| 1390 | #define R_SERIAL1_CTRL__tr_baud__c19k2Hz 6 | ||
| 1391 | #define R_SERIAL1_CTRL__tr_baud__c38k4Hz 7 | ||
| 1392 | #define R_SERIAL1_CTRL__tr_baud__c57k6Hz 8 | ||
| 1393 | #define R_SERIAL1_CTRL__tr_baud__c115k2Hz 9 | ||
| 1394 | #define R_SERIAL1_CTRL__tr_baud__c230k4Hz 10 | ||
| 1395 | #define R_SERIAL1_CTRL__tr_baud__c460k8Hz 11 | ||
| 1396 | #define R_SERIAL1_CTRL__tr_baud__c921k6Hz 12 | ||
| 1397 | #define R_SERIAL1_CTRL__tr_baud__c1843k2Hz 13 | ||
| 1398 | #define R_SERIAL1_CTRL__tr_baud__c6250kHz 14 | ||
| 1399 | #define R_SERIAL1_CTRL__tr_baud__reserved 15 | ||
| 1400 | #define R_SERIAL1_CTRL__rec_baud__BITNR 24 | ||
| 1401 | #define R_SERIAL1_CTRL__rec_baud__WIDTH 4 | ||
| 1402 | #define R_SERIAL1_CTRL__rec_baud__c300Hz 0 | ||
| 1403 | #define R_SERIAL1_CTRL__rec_baud__c600Hz 1 | ||
| 1404 | #define R_SERIAL1_CTRL__rec_baud__c1200Hz 2 | ||
| 1405 | #define R_SERIAL1_CTRL__rec_baud__c2400Hz 3 | ||
| 1406 | #define R_SERIAL1_CTRL__rec_baud__c4800Hz 4 | ||
| 1407 | #define R_SERIAL1_CTRL__rec_baud__c9600Hz 5 | ||
| 1408 | #define R_SERIAL1_CTRL__rec_baud__c19k2Hz 6 | ||
| 1409 | #define R_SERIAL1_CTRL__rec_baud__c38k4Hz 7 | ||
| 1410 | #define R_SERIAL1_CTRL__rec_baud__c57k6Hz 8 | ||
| 1411 | #define R_SERIAL1_CTRL__rec_baud__c115k2Hz 9 | ||
| 1412 | #define R_SERIAL1_CTRL__rec_baud__c230k4Hz 10 | ||
| 1413 | #define R_SERIAL1_CTRL__rec_baud__c460k8Hz 11 | ||
| 1414 | #define R_SERIAL1_CTRL__rec_baud__c921k6Hz 12 | ||
| 1415 | #define R_SERIAL1_CTRL__rec_baud__c1843k2Hz 13 | ||
| 1416 | #define R_SERIAL1_CTRL__rec_baud__c6250kHz 14 | ||
| 1417 | #define R_SERIAL1_CTRL__rec_baud__reserved 15 | ||
| 1418 | #define R_SERIAL1_CTRL__dma_err__BITNR 23 | ||
| 1419 | #define R_SERIAL1_CTRL__dma_err__WIDTH 1 | ||
| 1420 | #define R_SERIAL1_CTRL__dma_err__stop 0 | ||
| 1421 | #define R_SERIAL1_CTRL__dma_err__ignore 1 | ||
| 1422 | #define R_SERIAL1_CTRL__rec_enable__BITNR 22 | ||
| 1423 | #define R_SERIAL1_CTRL__rec_enable__WIDTH 1 | ||
| 1424 | #define R_SERIAL1_CTRL__rec_enable__disable 0 | ||
| 1425 | #define R_SERIAL1_CTRL__rec_enable__enable 1 | ||
| 1426 | #define R_SERIAL1_CTRL__rts___BITNR 21 | ||
| 1427 | #define R_SERIAL1_CTRL__rts___WIDTH 1 | ||
| 1428 | #define R_SERIAL1_CTRL__rts___active 0 | ||
| 1429 | #define R_SERIAL1_CTRL__rts___inactive 1 | ||
| 1430 | #define R_SERIAL1_CTRL__sampling__BITNR 20 | ||
| 1431 | #define R_SERIAL1_CTRL__sampling__WIDTH 1 | ||
| 1432 | #define R_SERIAL1_CTRL__sampling__middle 0 | ||
| 1433 | #define R_SERIAL1_CTRL__sampling__majority 1 | ||
| 1434 | #define R_SERIAL1_CTRL__rec_stick_par__BITNR 19 | ||
| 1435 | #define R_SERIAL1_CTRL__rec_stick_par__WIDTH 1 | ||
| 1436 | #define R_SERIAL1_CTRL__rec_stick_par__normal 0 | ||
| 1437 | #define R_SERIAL1_CTRL__rec_stick_par__stick 1 | ||
| 1438 | #define R_SERIAL1_CTRL__rec_par__BITNR 18 | ||
| 1439 | #define R_SERIAL1_CTRL__rec_par__WIDTH 1 | ||
| 1440 | #define R_SERIAL1_CTRL__rec_par__even 0 | ||
| 1441 | #define R_SERIAL1_CTRL__rec_par__odd 1 | ||
| 1442 | #define R_SERIAL1_CTRL__rec_par_en__BITNR 17 | ||
| 1443 | #define R_SERIAL1_CTRL__rec_par_en__WIDTH 1 | ||
| 1444 | #define R_SERIAL1_CTRL__rec_par_en__disable 0 | ||
| 1445 | #define R_SERIAL1_CTRL__rec_par_en__enable 1 | ||
| 1446 | #define R_SERIAL1_CTRL__rec_bitnr__BITNR 16 | ||
| 1447 | #define R_SERIAL1_CTRL__rec_bitnr__WIDTH 1 | ||
| 1448 | #define R_SERIAL1_CTRL__rec_bitnr__rec_8bit 0 | ||
| 1449 | #define R_SERIAL1_CTRL__rec_bitnr__rec_7bit 1 | ||
| 1450 | #define R_SERIAL1_CTRL__txd__BITNR 15 | ||
| 1451 | #define R_SERIAL1_CTRL__txd__WIDTH 1 | ||
| 1452 | #define R_SERIAL1_CTRL__tr_enable__BITNR 14 | ||
| 1453 | #define R_SERIAL1_CTRL__tr_enable__WIDTH 1 | ||
| 1454 | #define R_SERIAL1_CTRL__tr_enable__disable 0 | ||
| 1455 | #define R_SERIAL1_CTRL__tr_enable__enable 1 | ||
| 1456 | #define R_SERIAL1_CTRL__auto_cts__BITNR 13 | ||
| 1457 | #define R_SERIAL1_CTRL__auto_cts__WIDTH 1 | ||
| 1458 | #define R_SERIAL1_CTRL__auto_cts__disabled 0 | ||
| 1459 | #define R_SERIAL1_CTRL__auto_cts__active 1 | ||
| 1460 | #define R_SERIAL1_CTRL__stop_bits__BITNR 12 | ||
| 1461 | #define R_SERIAL1_CTRL__stop_bits__WIDTH 1 | ||
| 1462 | #define R_SERIAL1_CTRL__stop_bits__one_bit 0 | ||
| 1463 | #define R_SERIAL1_CTRL__stop_bits__two_bits 1 | ||
| 1464 | #define R_SERIAL1_CTRL__tr_stick_par__BITNR 11 | ||
| 1465 | #define R_SERIAL1_CTRL__tr_stick_par__WIDTH 1 | ||
| 1466 | #define R_SERIAL1_CTRL__tr_stick_par__normal 0 | ||
| 1467 | #define R_SERIAL1_CTRL__tr_stick_par__stick 1 | ||
| 1468 | #define R_SERIAL1_CTRL__tr_par__BITNR 10 | ||
| 1469 | #define R_SERIAL1_CTRL__tr_par__WIDTH 1 | ||
| 1470 | #define R_SERIAL1_CTRL__tr_par__even 0 | ||
| 1471 | #define R_SERIAL1_CTRL__tr_par__odd 1 | ||
| 1472 | #define R_SERIAL1_CTRL__tr_par_en__BITNR 9 | ||
| 1473 | #define R_SERIAL1_CTRL__tr_par_en__WIDTH 1 | ||
| 1474 | #define R_SERIAL1_CTRL__tr_par_en__disable 0 | ||
| 1475 | #define R_SERIAL1_CTRL__tr_par_en__enable 1 | ||
| 1476 | #define R_SERIAL1_CTRL__tr_bitnr__BITNR 8 | ||
| 1477 | #define R_SERIAL1_CTRL__tr_bitnr__WIDTH 1 | ||
| 1478 | #define R_SERIAL1_CTRL__tr_bitnr__tr_8bit 0 | ||
| 1479 | #define R_SERIAL1_CTRL__tr_bitnr__tr_7bit 1 | ||
| 1480 | #define R_SERIAL1_CTRL__data_out__BITNR 0 | ||
| 1481 | #define R_SERIAL1_CTRL__data_out__WIDTH 8 | ||
| 1482 | |||
| 1483 | #define R_SERIAL1_BAUD (IO_TYPECAST_BYTE 0xb000006b) | ||
| 1484 | #define R_SERIAL1_BAUD__tr_baud__BITNR 4 | ||
| 1485 | #define R_SERIAL1_BAUD__tr_baud__WIDTH 4 | ||
| 1486 | #define R_SERIAL1_BAUD__tr_baud__c300Hz 0 | ||
| 1487 | #define R_SERIAL1_BAUD__tr_baud__c600Hz 1 | ||
| 1488 | #define R_SERIAL1_BAUD__tr_baud__c1200Hz 2 | ||
| 1489 | #define R_SERIAL1_BAUD__tr_baud__c2400Hz 3 | ||
| 1490 | #define R_SERIAL1_BAUD__tr_baud__c4800Hz 4 | ||
| 1491 | #define R_SERIAL1_BAUD__tr_baud__c9600Hz 5 | ||
| 1492 | #define R_SERIAL1_BAUD__tr_baud__c19k2Hz 6 | ||
| 1493 | #define R_SERIAL1_BAUD__tr_baud__c38k4Hz 7 | ||
| 1494 | #define R_SERIAL1_BAUD__tr_baud__c57k6Hz 8 | ||
| 1495 | #define R_SERIAL1_BAUD__tr_baud__c115k2Hz 9 | ||
| 1496 | #define R_SERIAL1_BAUD__tr_baud__c230k4Hz 10 | ||
| 1497 | #define R_SERIAL1_BAUD__tr_baud__c460k8Hz 11 | ||
| 1498 | #define R_SERIAL1_BAUD__tr_baud__c921k6Hz 12 | ||
| 1499 | #define R_SERIAL1_BAUD__tr_baud__c1843k2Hz 13 | ||
| 1500 | #define R_SERIAL1_BAUD__tr_baud__c6250kHz 14 | ||
| 1501 | #define R_SERIAL1_BAUD__tr_baud__reserved 15 | ||
| 1502 | #define R_SERIAL1_BAUD__rec_baud__BITNR 0 | ||
| 1503 | #define R_SERIAL1_BAUD__rec_baud__WIDTH 4 | ||
| 1504 | #define R_SERIAL1_BAUD__rec_baud__c300Hz 0 | ||
| 1505 | #define R_SERIAL1_BAUD__rec_baud__c600Hz 1 | ||
| 1506 | #define R_SERIAL1_BAUD__rec_baud__c1200Hz 2 | ||
| 1507 | #define R_SERIAL1_BAUD__rec_baud__c2400Hz 3 | ||
| 1508 | #define R_SERIAL1_BAUD__rec_baud__c4800Hz 4 | ||
| 1509 | #define R_SERIAL1_BAUD__rec_baud__c9600Hz 5 | ||
| 1510 | #define R_SERIAL1_BAUD__rec_baud__c19k2Hz 6 | ||
| 1511 | #define R_SERIAL1_BAUD__rec_baud__c38k4Hz 7 | ||
| 1512 | #define R_SERIAL1_BAUD__rec_baud__c57k6Hz 8 | ||
| 1513 | #define R_SERIAL1_BAUD__rec_baud__c115k2Hz 9 | ||
| 1514 | #define R_SERIAL1_BAUD__rec_baud__c230k4Hz 10 | ||
| 1515 | #define R_SERIAL1_BAUD__rec_baud__c460k8Hz 11 | ||
| 1516 | #define R_SERIAL1_BAUD__rec_baud__c921k6Hz 12 | ||
| 1517 | #define R_SERIAL1_BAUD__rec_baud__c1843k2Hz 13 | ||
| 1518 | #define R_SERIAL1_BAUD__rec_baud__c6250kHz 14 | ||
| 1519 | #define R_SERIAL1_BAUD__rec_baud__reserved 15 | ||
| 1520 | |||
| 1521 | #define R_SERIAL1_REC_CTRL (IO_TYPECAST_BYTE 0xb000006a) | ||
| 1522 | #define R_SERIAL1_REC_CTRL__dma_err__BITNR 7 | ||
| 1523 | #define R_SERIAL1_REC_CTRL__dma_err__WIDTH 1 | ||
| 1524 | #define R_SERIAL1_REC_CTRL__dma_err__stop 0 | ||
| 1525 | #define R_SERIAL1_REC_CTRL__dma_err__ignore 1 | ||
| 1526 | #define R_SERIAL1_REC_CTRL__rec_enable__BITNR 6 | ||
| 1527 | #define R_SERIAL1_REC_CTRL__rec_enable__WIDTH 1 | ||
| 1528 | #define R_SERIAL1_REC_CTRL__rec_enable__disable 0 | ||
| 1529 | #define R_SERIAL1_REC_CTRL__rec_enable__enable 1 | ||
| 1530 | #define R_SERIAL1_REC_CTRL__rts___BITNR 5 | ||
| 1531 | #define R_SERIAL1_REC_CTRL__rts___WIDTH 1 | ||
| 1532 | #define R_SERIAL1_REC_CTRL__rts___active 0 | ||
| 1533 | #define R_SERIAL1_REC_CTRL__rts___inactive 1 | ||
| 1534 | #define R_SERIAL1_REC_CTRL__sampling__BITNR 4 | ||
| 1535 | #define R_SERIAL1_REC_CTRL__sampling__WIDTH 1 | ||
| 1536 | #define R_SERIAL1_REC_CTRL__sampling__middle 0 | ||
| 1537 | #define R_SERIAL1_REC_CTRL__sampling__majority 1 | ||
| 1538 | #define R_SERIAL1_REC_CTRL__rec_stick_par__BITNR 3 | ||
| 1539 | #define R_SERIAL1_REC_CTRL__rec_stick_par__WIDTH 1 | ||
| 1540 | #define R_SERIAL1_REC_CTRL__rec_stick_par__normal 0 | ||
| 1541 | #define R_SERIAL1_REC_CTRL__rec_stick_par__stick 1 | ||
| 1542 | #define R_SERIAL1_REC_CTRL__rec_par__BITNR 2 | ||
| 1543 | #define R_SERIAL1_REC_CTRL__rec_par__WIDTH 1 | ||
| 1544 | #define R_SERIAL1_REC_CTRL__rec_par__even 0 | ||
| 1545 | #define R_SERIAL1_REC_CTRL__rec_par__odd 1 | ||
| 1546 | #define R_SERIAL1_REC_CTRL__rec_par_en__BITNR 1 | ||
| 1547 | #define R_SERIAL1_REC_CTRL__rec_par_en__WIDTH 1 | ||
| 1548 | #define R_SERIAL1_REC_CTRL__rec_par_en__disable 0 | ||
| 1549 | #define R_SERIAL1_REC_CTRL__rec_par_en__enable 1 | ||
| 1550 | #define R_SERIAL1_REC_CTRL__rec_bitnr__BITNR 0 | ||
| 1551 | #define R_SERIAL1_REC_CTRL__rec_bitnr__WIDTH 1 | ||
| 1552 | #define R_SERIAL1_REC_CTRL__rec_bitnr__rec_8bit 0 | ||
| 1553 | #define R_SERIAL1_REC_CTRL__rec_bitnr__rec_7bit 1 | ||
| 1554 | |||
| 1555 | #define R_SERIAL1_TR_CTRL (IO_TYPECAST_BYTE 0xb0000069) | ||
| 1556 | #define R_SERIAL1_TR_CTRL__txd__BITNR 7 | ||
| 1557 | #define R_SERIAL1_TR_CTRL__txd__WIDTH 1 | ||
| 1558 | #define R_SERIAL1_TR_CTRL__tr_enable__BITNR 6 | ||
| 1559 | #define R_SERIAL1_TR_CTRL__tr_enable__WIDTH 1 | ||
| 1560 | #define R_SERIAL1_TR_CTRL__tr_enable__disable 0 | ||
| 1561 | #define R_SERIAL1_TR_CTRL__tr_enable__enable 1 | ||
| 1562 | #define R_SERIAL1_TR_CTRL__auto_cts__BITNR 5 | ||
| 1563 | #define R_SERIAL1_TR_CTRL__auto_cts__WIDTH 1 | ||
| 1564 | #define R_SERIAL1_TR_CTRL__auto_cts__disabled 0 | ||
| 1565 | #define R_SERIAL1_TR_CTRL__auto_cts__active 1 | ||
| 1566 | #define R_SERIAL1_TR_CTRL__stop_bits__BITNR 4 | ||
| 1567 | #define R_SERIAL1_TR_CTRL__stop_bits__WIDTH 1 | ||
| 1568 | #define R_SERIAL1_TR_CTRL__stop_bits__one_bit 0 | ||
| 1569 | #define R_SERIAL1_TR_CTRL__stop_bits__two_bits 1 | ||
| 1570 | #define R_SERIAL1_TR_CTRL__tr_stick_par__BITNR 3 | ||
| 1571 | #define R_SERIAL1_TR_CTRL__tr_stick_par__WIDTH 1 | ||
| 1572 | #define R_SERIAL1_TR_CTRL__tr_stick_par__normal 0 | ||
| 1573 | #define R_SERIAL1_TR_CTRL__tr_stick_par__stick 1 | ||
| 1574 | #define R_SERIAL1_TR_CTRL__tr_par__BITNR 2 | ||
| 1575 | #define R_SERIAL1_TR_CTRL__tr_par__WIDTH 1 | ||
| 1576 | #define R_SERIAL1_TR_CTRL__tr_par__even 0 | ||
| 1577 | #define R_SERIAL1_TR_CTRL__tr_par__odd 1 | ||
| 1578 | #define R_SERIAL1_TR_CTRL__tr_par_en__BITNR 1 | ||
| 1579 | #define R_SERIAL1_TR_CTRL__tr_par_en__WIDTH 1 | ||
| 1580 | #define R_SERIAL1_TR_CTRL__tr_par_en__disable 0 | ||
| 1581 | #define R_SERIAL1_TR_CTRL__tr_par_en__enable 1 | ||
| 1582 | #define R_SERIAL1_TR_CTRL__tr_bitnr__BITNR 0 | ||
| 1583 | #define R_SERIAL1_TR_CTRL__tr_bitnr__WIDTH 1 | ||
| 1584 | #define R_SERIAL1_TR_CTRL__tr_bitnr__tr_8bit 0 | ||
| 1585 | #define R_SERIAL1_TR_CTRL__tr_bitnr__tr_7bit 1 | ||
| 1586 | |||
| 1587 | #define R_SERIAL1_TR_DATA (IO_TYPECAST_BYTE 0xb0000068) | ||
| 1588 | #define R_SERIAL1_TR_DATA__data_out__BITNR 0 | ||
| 1589 | #define R_SERIAL1_TR_DATA__data_out__WIDTH 8 | ||
| 1590 | |||
| 1591 | #define R_SERIAL1_READ (IO_TYPECAST_RO_UDWORD 0xb0000068) | ||
| 1592 | #define R_SERIAL1_READ__xoff_detect__BITNR 15 | ||
| 1593 | #define R_SERIAL1_READ__xoff_detect__WIDTH 1 | ||
| 1594 | #define R_SERIAL1_READ__xoff_detect__no_xoff 0 | ||
| 1595 | #define R_SERIAL1_READ__xoff_detect__xoff 1 | ||
| 1596 | #define R_SERIAL1_READ__cts___BITNR 14 | ||
| 1597 | #define R_SERIAL1_READ__cts___WIDTH 1 | ||
| 1598 | #define R_SERIAL1_READ__cts___active 0 | ||
| 1599 | #define R_SERIAL1_READ__cts___inactive 1 | ||
| 1600 | #define R_SERIAL1_READ__tr_ready__BITNR 13 | ||
| 1601 | #define R_SERIAL1_READ__tr_ready__WIDTH 1 | ||
| 1602 | #define R_SERIAL1_READ__tr_ready__full 0 | ||
| 1603 | #define R_SERIAL1_READ__tr_ready__ready 1 | ||
| 1604 | #define R_SERIAL1_READ__rxd__BITNR 12 | ||
| 1605 | #define R_SERIAL1_READ__rxd__WIDTH 1 | ||
| 1606 | #define R_SERIAL1_READ__overrun__BITNR 11 | ||
| 1607 | #define R_SERIAL1_READ__overrun__WIDTH 1 | ||
| 1608 | #define R_SERIAL1_READ__overrun__no 0 | ||
| 1609 | #define R_SERIAL1_READ__overrun__yes 1 | ||
| 1610 | #define R_SERIAL1_READ__par_err__BITNR 10 | ||
| 1611 | #define R_SERIAL1_READ__par_err__WIDTH 1 | ||
| 1612 | #define R_SERIAL1_READ__par_err__no 0 | ||
| 1613 | #define R_SERIAL1_READ__par_err__yes 1 | ||
| 1614 | #define R_SERIAL1_READ__framing_err__BITNR 9 | ||
| 1615 | #define R_SERIAL1_READ__framing_err__WIDTH 1 | ||
| 1616 | #define R_SERIAL1_READ__framing_err__no 0 | ||
| 1617 | #define R_SERIAL1_READ__framing_err__yes 1 | ||
| 1618 | #define R_SERIAL1_READ__data_avail__BITNR 8 | ||
| 1619 | #define R_SERIAL1_READ__data_avail__WIDTH 1 | ||
| 1620 | #define R_SERIAL1_READ__data_avail__no 0 | ||
| 1621 | #define R_SERIAL1_READ__data_avail__yes 1 | ||
| 1622 | #define R_SERIAL1_READ__data_in__BITNR 0 | ||
| 1623 | #define R_SERIAL1_READ__data_in__WIDTH 8 | ||
| 1624 | |||
| 1625 | #define R_SERIAL1_STATUS (IO_TYPECAST_RO_BYTE 0xb0000069) | ||
| 1626 | #define R_SERIAL1_STATUS__xoff_detect__BITNR 7 | ||
| 1627 | #define R_SERIAL1_STATUS__xoff_detect__WIDTH 1 | ||
| 1628 | #define R_SERIAL1_STATUS__xoff_detect__no_xoff 0 | ||
| 1629 | #define R_SERIAL1_STATUS__xoff_detect__xoff 1 | ||
| 1630 | #define R_SERIAL1_STATUS__cts___BITNR 6 | ||
| 1631 | #define R_SERIAL1_STATUS__cts___WIDTH 1 | ||
| 1632 | #define R_SERIAL1_STATUS__cts___active 0 | ||
| 1633 | #define R_SERIAL1_STATUS__cts___inactive 1 | ||
| 1634 | #define R_SERIAL1_STATUS__tr_ready__BITNR 5 | ||
| 1635 | #define R_SERIAL1_STATUS__tr_ready__WIDTH 1 | ||
| 1636 | #define R_SERIAL1_STATUS__tr_ready__full 0 | ||
| 1637 | #define R_SERIAL1_STATUS__tr_ready__ready 1 | ||
| 1638 | #define R_SERIAL1_STATUS__rxd__BITNR 4 | ||
| 1639 | #define R_SERIAL1_STATUS__rxd__WIDTH 1 | ||
| 1640 | #define R_SERIAL1_STATUS__overrun__BITNR 3 | ||
| 1641 | #define R_SERIAL1_STATUS__overrun__WIDTH 1 | ||
| 1642 | #define R_SERIAL1_STATUS__overrun__no 0 | ||
| 1643 | #define R_SERIAL1_STATUS__overrun__yes 1 | ||
| 1644 | #define R_SERIAL1_STATUS__par_err__BITNR 2 | ||
| 1645 | #define R_SERIAL1_STATUS__par_err__WIDTH 1 | ||
| 1646 | #define R_SERIAL1_STATUS__par_err__no 0 | ||
| 1647 | #define R_SERIAL1_STATUS__par_err__yes 1 | ||
| 1648 | #define R_SERIAL1_STATUS__framing_err__BITNR 1 | ||
| 1649 | #define R_SERIAL1_STATUS__framing_err__WIDTH 1 | ||
| 1650 | #define R_SERIAL1_STATUS__framing_err__no 0 | ||
| 1651 | #define R_SERIAL1_STATUS__framing_err__yes 1 | ||
| 1652 | #define R_SERIAL1_STATUS__data_avail__BITNR 0 | ||
| 1653 | #define R_SERIAL1_STATUS__data_avail__WIDTH 1 | ||
| 1654 | #define R_SERIAL1_STATUS__data_avail__no 0 | ||
| 1655 | #define R_SERIAL1_STATUS__data_avail__yes 1 | ||
| 1656 | |||
| 1657 | #define R_SERIAL1_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000068) | ||
| 1658 | #define R_SERIAL1_REC_DATA__data_in__BITNR 0 | ||
| 1659 | #define R_SERIAL1_REC_DATA__data_in__WIDTH 8 | ||
| 1660 | |||
| 1661 | #define R_SERIAL1_XOFF (IO_TYPECAST_UDWORD 0xb000006c) | ||
| 1662 | #define R_SERIAL1_XOFF__tx_stop__BITNR 9 | ||
| 1663 | #define R_SERIAL1_XOFF__tx_stop__WIDTH 1 | ||
| 1664 | #define R_SERIAL1_XOFF__tx_stop__enable 0 | ||
| 1665 | #define R_SERIAL1_XOFF__tx_stop__stop 1 | ||
| 1666 | #define R_SERIAL1_XOFF__auto_xoff__BITNR 8 | ||
| 1667 | #define R_SERIAL1_XOFF__auto_xoff__WIDTH 1 | ||
| 1668 | #define R_SERIAL1_XOFF__auto_xoff__disable 0 | ||
| 1669 | #define R_SERIAL1_XOFF__auto_xoff__enable 1 | ||
| 1670 | #define R_SERIAL1_XOFF__xoff_char__BITNR 0 | ||
| 1671 | #define R_SERIAL1_XOFF__xoff_char__WIDTH 8 | ||
| 1672 | |||
| 1673 | #define R_SERIAL2_CTRL (IO_TYPECAST_UDWORD 0xb0000070) | ||
| 1674 | #define R_SERIAL2_CTRL__tr_baud__BITNR 28 | ||
| 1675 | #define R_SERIAL2_CTRL__tr_baud__WIDTH 4 | ||
| 1676 | #define R_SERIAL2_CTRL__tr_baud__c300Hz 0 | ||
| 1677 | #define R_SERIAL2_CTRL__tr_baud__c600Hz 1 | ||
| 1678 | #define R_SERIAL2_CTRL__tr_baud__c1200Hz 2 | ||
| 1679 | #define R_SERIAL2_CTRL__tr_baud__c2400Hz 3 | ||
| 1680 | #define R_SERIAL2_CTRL__tr_baud__c4800Hz 4 | ||
| 1681 | #define R_SERIAL2_CTRL__tr_baud__c9600Hz 5 | ||
| 1682 | #define R_SERIAL2_CTRL__tr_baud__c19k2Hz 6 | ||
| 1683 | #define R_SERIAL2_CTRL__tr_baud__c38k4Hz 7 | ||
| 1684 | #define R_SERIAL2_CTRL__tr_baud__c57k6Hz 8 | ||
| 1685 | #define R_SERIAL2_CTRL__tr_baud__c115k2Hz 9 | ||
| 1686 | #define R_SERIAL2_CTRL__tr_baud__c230k4Hz 10 | ||
| 1687 | #define R_SERIAL2_CTRL__tr_baud__c460k8Hz 11 | ||
| 1688 | #define R_SERIAL2_CTRL__tr_baud__c921k6Hz 12 | ||
| 1689 | #define R_SERIAL2_CTRL__tr_baud__c1843k2Hz 13 | ||
| 1690 | #define R_SERIAL2_CTRL__tr_baud__c6250kHz 14 | ||
| 1691 | #define R_SERIAL2_CTRL__tr_baud__reserved 15 | ||
| 1692 | #define R_SERIAL2_CTRL__rec_baud__BITNR 24 | ||
| 1693 | #define R_SERIAL2_CTRL__rec_baud__WIDTH 4 | ||
| 1694 | #define R_SERIAL2_CTRL__rec_baud__c300Hz 0 | ||
| 1695 | #define R_SERIAL2_CTRL__rec_baud__c600Hz 1 | ||
| 1696 | #define R_SERIAL2_CTRL__rec_baud__c1200Hz 2 | ||
| 1697 | #define R_SERIAL2_CTRL__rec_baud__c2400Hz 3 | ||
| 1698 | #define R_SERIAL2_CTRL__rec_baud__c4800Hz 4 | ||
| 1699 | #define R_SERIAL2_CTRL__rec_baud__c9600Hz 5 | ||
| 1700 | #define R_SERIAL2_CTRL__rec_baud__c19k2Hz 6 | ||
| 1701 | #define R_SERIAL2_CTRL__rec_baud__c38k4Hz 7 | ||
| 1702 | #define R_SERIAL2_CTRL__rec_baud__c57k6Hz 8 | ||
| 1703 | #define R_SERIAL2_CTRL__rec_baud__c115k2Hz 9 | ||
| 1704 | #define R_SERIAL2_CTRL__rec_baud__c230k4Hz 10 | ||
| 1705 | #define R_SERIAL2_CTRL__rec_baud__c460k8Hz 11 | ||
| 1706 | #define R_SERIAL2_CTRL__rec_baud__c921k6Hz 12 | ||
| 1707 | #define R_SERIAL2_CTRL__rec_baud__c1843k2Hz 13 | ||
| 1708 | #define R_SERIAL2_CTRL__rec_baud__c6250kHz 14 | ||
| 1709 | #define R_SERIAL2_CTRL__rec_baud__reserved 15 | ||
| 1710 | #define R_SERIAL2_CTRL__dma_err__BITNR 23 | ||
| 1711 | #define R_SERIAL2_CTRL__dma_err__WIDTH 1 | ||
| 1712 | #define R_SERIAL2_CTRL__dma_err__stop 0 | ||
| 1713 | #define R_SERIAL2_CTRL__dma_err__ignore 1 | ||
| 1714 | #define R_SERIAL2_CTRL__rec_enable__BITNR 22 | ||
| 1715 | #define R_SERIAL2_CTRL__rec_enable__WIDTH 1 | ||
| 1716 | #define R_SERIAL2_CTRL__rec_enable__disable 0 | ||
| 1717 | #define R_SERIAL2_CTRL__rec_enable__enable 1 | ||
| 1718 | #define R_SERIAL2_CTRL__rts___BITNR 21 | ||
| 1719 | #define R_SERIAL2_CTRL__rts___WIDTH 1 | ||
| 1720 | #define R_SERIAL2_CTRL__rts___active 0 | ||
| 1721 | #define R_SERIAL2_CTRL__rts___inactive 1 | ||
| 1722 | #define R_SERIAL2_CTRL__sampling__BITNR 20 | ||
| 1723 | #define R_SERIAL2_CTRL__sampling__WIDTH 1 | ||
| 1724 | #define R_SERIAL2_CTRL__sampling__middle 0 | ||
| 1725 | #define R_SERIAL2_CTRL__sampling__majority 1 | ||
| 1726 | #define R_SERIAL2_CTRL__rec_stick_par__BITNR 19 | ||
| 1727 | #define R_SERIAL2_CTRL__rec_stick_par__WIDTH 1 | ||
| 1728 | #define R_SERIAL2_CTRL__rec_stick_par__normal 0 | ||
| 1729 | #define R_SERIAL2_CTRL__rec_stick_par__stick 1 | ||
| 1730 | #define R_SERIAL2_CTRL__rec_par__BITNR 18 | ||
| 1731 | #define R_SERIAL2_CTRL__rec_par__WIDTH 1 | ||
| 1732 | #define R_SERIAL2_CTRL__rec_par__even 0 | ||
| 1733 | #define R_SERIAL2_CTRL__rec_par__odd 1 | ||
| 1734 | #define R_SERIAL2_CTRL__rec_par_en__BITNR 17 | ||
| 1735 | #define R_SERIAL2_CTRL__rec_par_en__WIDTH 1 | ||
| 1736 | #define R_SERIAL2_CTRL__rec_par_en__disable 0 | ||
| 1737 | #define R_SERIAL2_CTRL__rec_par_en__enable 1 | ||
| 1738 | #define R_SERIAL2_CTRL__rec_bitnr__BITNR 16 | ||
| 1739 | #define R_SERIAL2_CTRL__rec_bitnr__WIDTH 1 | ||
| 1740 | #define R_SERIAL2_CTRL__rec_bitnr__rec_8bit 0 | ||
| 1741 | #define R_SERIAL2_CTRL__rec_bitnr__rec_7bit 1 | ||
| 1742 | #define R_SERIAL2_CTRL__txd__BITNR 15 | ||
| 1743 | #define R_SERIAL2_CTRL__txd__WIDTH 1 | ||
| 1744 | #define R_SERIAL2_CTRL__tr_enable__BITNR 14 | ||
| 1745 | #define R_SERIAL2_CTRL__tr_enable__WIDTH 1 | ||
| 1746 | #define R_SERIAL2_CTRL__tr_enable__disable 0 | ||
| 1747 | #define R_SERIAL2_CTRL__tr_enable__enable 1 | ||
| 1748 | #define R_SERIAL2_CTRL__auto_cts__BITNR 13 | ||
| 1749 | #define R_SERIAL2_CTRL__auto_cts__WIDTH 1 | ||
| 1750 | #define R_SERIAL2_CTRL__auto_cts__disabled 0 | ||
| 1751 | #define R_SERIAL2_CTRL__auto_cts__active 1 | ||
| 1752 | #define R_SERIAL2_CTRL__stop_bits__BITNR 12 | ||
| 1753 | #define R_SERIAL2_CTRL__stop_bits__WIDTH 1 | ||
| 1754 | #define R_SERIAL2_CTRL__stop_bits__one_bit 0 | ||
| 1755 | #define R_SERIAL2_CTRL__stop_bits__two_bits 1 | ||
| 1756 | #define R_SERIAL2_CTRL__tr_stick_par__BITNR 11 | ||
| 1757 | #define R_SERIAL2_CTRL__tr_stick_par__WIDTH 1 | ||
| 1758 | #define R_SERIAL2_CTRL__tr_stick_par__normal 0 | ||
| 1759 | #define R_SERIAL2_CTRL__tr_stick_par__stick 1 | ||
| 1760 | #define R_SERIAL2_CTRL__tr_par__BITNR 10 | ||
| 1761 | #define R_SERIAL2_CTRL__tr_par__WIDTH 1 | ||
| 1762 | #define R_SERIAL2_CTRL__tr_par__even 0 | ||
| 1763 | #define R_SERIAL2_CTRL__tr_par__odd 1 | ||
| 1764 | #define R_SERIAL2_CTRL__tr_par_en__BITNR 9 | ||
| 1765 | #define R_SERIAL2_CTRL__tr_par_en__WIDTH 1 | ||
| 1766 | #define R_SERIAL2_CTRL__tr_par_en__disable 0 | ||
| 1767 | #define R_SERIAL2_CTRL__tr_par_en__enable 1 | ||
| 1768 | #define R_SERIAL2_CTRL__tr_bitnr__BITNR 8 | ||
| 1769 | #define R_SERIAL2_CTRL__tr_bitnr__WIDTH 1 | ||
| 1770 | #define R_SERIAL2_CTRL__tr_bitnr__tr_8bit 0 | ||
| 1771 | #define R_SERIAL2_CTRL__tr_bitnr__tr_7bit 1 | ||
| 1772 | #define R_SERIAL2_CTRL__data_out__BITNR 0 | ||
| 1773 | #define R_SERIAL2_CTRL__data_out__WIDTH 8 | ||
| 1774 | |||
| 1775 | #define R_SERIAL2_BAUD (IO_TYPECAST_BYTE 0xb0000073) | ||
| 1776 | #define R_SERIAL2_BAUD__tr_baud__BITNR 4 | ||
| 1777 | #define R_SERIAL2_BAUD__tr_baud__WIDTH 4 | ||
| 1778 | #define R_SERIAL2_BAUD__tr_baud__c300Hz 0 | ||
| 1779 | #define R_SERIAL2_BAUD__tr_baud__c600Hz 1 | ||
| 1780 | #define R_SERIAL2_BAUD__tr_baud__c1200Hz 2 | ||
| 1781 | #define R_SERIAL2_BAUD__tr_baud__c2400Hz 3 | ||
| 1782 | #define R_SERIAL2_BAUD__tr_baud__c4800Hz 4 | ||
| 1783 | #define R_SERIAL2_BAUD__tr_baud__c9600Hz 5 | ||
| 1784 | #define R_SERIAL2_BAUD__tr_baud__c19k2Hz 6 | ||
| 1785 | #define R_SERIAL2_BAUD__tr_baud__c38k4Hz 7 | ||
| 1786 | #define R_SERIAL2_BAUD__tr_baud__c57k6Hz 8 | ||
| 1787 | #define R_SERIAL2_BAUD__tr_baud__c115k2Hz 9 | ||
| 1788 | #define R_SERIAL2_BAUD__tr_baud__c230k4Hz 10 | ||
| 1789 | #define R_SERIAL2_BAUD__tr_baud__c460k8Hz 11 | ||
| 1790 | #define R_SERIAL2_BAUD__tr_baud__c921k6Hz 12 | ||
| 1791 | #define R_SERIAL2_BAUD__tr_baud__c1843k2Hz 13 | ||
| 1792 | #define R_SERIAL2_BAUD__tr_baud__c6250kHz 14 | ||
| 1793 | #define R_SERIAL2_BAUD__tr_baud__reserved 15 | ||
| 1794 | #define R_SERIAL2_BAUD__rec_baud__BITNR 0 | ||
| 1795 | #define R_SERIAL2_BAUD__rec_baud__WIDTH 4 | ||
| 1796 | #define R_SERIAL2_BAUD__rec_baud__c300Hz 0 | ||
| 1797 | #define R_SERIAL2_BAUD__rec_baud__c600Hz 1 | ||
| 1798 | #define R_SERIAL2_BAUD__rec_baud__c1200Hz 2 | ||
| 1799 | #define R_SERIAL2_BAUD__rec_baud__c2400Hz 3 | ||
| 1800 | #define R_SERIAL2_BAUD__rec_baud__c4800Hz 4 | ||
| 1801 | #define R_SERIAL2_BAUD__rec_baud__c9600Hz 5 | ||
| 1802 | #define R_SERIAL2_BAUD__rec_baud__c19k2Hz 6 | ||
| 1803 | #define R_SERIAL2_BAUD__rec_baud__c38k4Hz 7 | ||
| 1804 | #define R_SERIAL2_BAUD__rec_baud__c57k6Hz 8 | ||
| 1805 | #define R_SERIAL2_BAUD__rec_baud__c115k2Hz 9 | ||
| 1806 | #define R_SERIAL2_BAUD__rec_baud__c230k4Hz 10 | ||
| 1807 | #define R_SERIAL2_BAUD__rec_baud__c460k8Hz 11 | ||
| 1808 | #define R_SERIAL2_BAUD__rec_baud__c921k6Hz 12 | ||
| 1809 | #define R_SERIAL2_BAUD__rec_baud__c1843k2Hz 13 | ||
| 1810 | #define R_SERIAL2_BAUD__rec_baud__c6250kHz 14 | ||
| 1811 | #define R_SERIAL2_BAUD__rec_baud__reserved 15 | ||
| 1812 | |||
| 1813 | #define R_SERIAL2_REC_CTRL (IO_TYPECAST_BYTE 0xb0000072) | ||
| 1814 | #define R_SERIAL2_REC_CTRL__dma_err__BITNR 7 | ||
| 1815 | #define R_SERIAL2_REC_CTRL__dma_err__WIDTH 1 | ||
| 1816 | #define R_SERIAL2_REC_CTRL__dma_err__stop 0 | ||
| 1817 | #define R_SERIAL2_REC_CTRL__dma_err__ignore 1 | ||
| 1818 | #define R_SERIAL2_REC_CTRL__rec_enable__BITNR 6 | ||
| 1819 | #define R_SERIAL2_REC_CTRL__rec_enable__WIDTH 1 | ||
| 1820 | #define R_SERIAL2_REC_CTRL__rec_enable__disable 0 | ||
| 1821 | #define R_SERIAL2_REC_CTRL__rec_enable__enable 1 | ||
| 1822 | #define R_SERIAL2_REC_CTRL__rts___BITNR 5 | ||
| 1823 | #define R_SERIAL2_REC_CTRL__rts___WIDTH 1 | ||
| 1824 | #define R_SERIAL2_REC_CTRL__rts___active 0 | ||
| 1825 | #define R_SERIAL2_REC_CTRL__rts___inactive 1 | ||
| 1826 | #define R_SERIAL2_REC_CTRL__sampling__BITNR 4 | ||
| 1827 | #define R_SERIAL2_REC_CTRL__sampling__WIDTH 1 | ||
| 1828 | #define R_SERIAL2_REC_CTRL__sampling__middle 0 | ||
| 1829 | #define R_SERIAL2_REC_CTRL__sampling__majority 1 | ||
| 1830 | #define R_SERIAL2_REC_CTRL__rec_stick_par__BITNR 3 | ||
| 1831 | #define R_SERIAL2_REC_CTRL__rec_stick_par__WIDTH 1 | ||
| 1832 | #define R_SERIAL2_REC_CTRL__rec_stick_par__normal 0 | ||
| 1833 | #define R_SERIAL2_REC_CTRL__rec_stick_par__stick 1 | ||
| 1834 | #define R_SERIAL2_REC_CTRL__rec_par__BITNR 2 | ||
| 1835 | #define R_SERIAL2_REC_CTRL__rec_par__WIDTH 1 | ||
| 1836 | #define R_SERIAL2_REC_CTRL__rec_par__even 0 | ||
| 1837 | #define R_SERIAL2_REC_CTRL__rec_par__odd 1 | ||
| 1838 | #define R_SERIAL2_REC_CTRL__rec_par_en__BITNR 1 | ||
| 1839 | #define R_SERIAL2_REC_CTRL__rec_par_en__WIDTH 1 | ||
| 1840 | #define R_SERIAL2_REC_CTRL__rec_par_en__disable 0 | ||
| 1841 | #define R_SERIAL2_REC_CTRL__rec_par_en__enable 1 | ||
| 1842 | #define R_SERIAL2_REC_CTRL__rec_bitnr__BITNR 0 | ||
| 1843 | #define R_SERIAL2_REC_CTRL__rec_bitnr__WIDTH 1 | ||
| 1844 | #define R_SERIAL2_REC_CTRL__rec_bitnr__rec_8bit 0 | ||
| 1845 | #define R_SERIAL2_REC_CTRL__rec_bitnr__rec_7bit 1 | ||
| 1846 | |||
| 1847 | #define R_SERIAL2_TR_CTRL (IO_TYPECAST_BYTE 0xb0000071) | ||
| 1848 | #define R_SERIAL2_TR_CTRL__txd__BITNR 7 | ||
| 1849 | #define R_SERIAL2_TR_CTRL__txd__WIDTH 1 | ||
| 1850 | #define R_SERIAL2_TR_CTRL__tr_enable__BITNR 6 | ||
| 1851 | #define R_SERIAL2_TR_CTRL__tr_enable__WIDTH 1 | ||
| 1852 | #define R_SERIAL2_TR_CTRL__tr_enable__disable 0 | ||
| 1853 | #define R_SERIAL2_TR_CTRL__tr_enable__enable 1 | ||
| 1854 | #define R_SERIAL2_TR_CTRL__auto_cts__BITNR 5 | ||
| 1855 | #define R_SERIAL2_TR_CTRL__auto_cts__WIDTH 1 | ||
| 1856 | #define R_SERIAL2_TR_CTRL__auto_cts__disabled 0 | ||
| 1857 | #define R_SERIAL2_TR_CTRL__auto_cts__active 1 | ||
| 1858 | #define R_SERIAL2_TR_CTRL__stop_bits__BITNR 4 | ||
| 1859 | #define R_SERIAL2_TR_CTRL__stop_bits__WIDTH 1 | ||
| 1860 | #define R_SERIAL2_TR_CTRL__stop_bits__one_bit 0 | ||
| 1861 | #define R_SERIAL2_TR_CTRL__stop_bits__two_bits 1 | ||
| 1862 | #define R_SERIAL2_TR_CTRL__tr_stick_par__BITNR 3 | ||
| 1863 | #define R_SERIAL2_TR_CTRL__tr_stick_par__WIDTH 1 | ||
| 1864 | #define R_SERIAL2_TR_CTRL__tr_stick_par__normal 0 | ||
| 1865 | #define R_SERIAL2_TR_CTRL__tr_stick_par__stick 1 | ||
| 1866 | #define R_SERIAL2_TR_CTRL__tr_par__BITNR 2 | ||
| 1867 | #define R_SERIAL2_TR_CTRL__tr_par__WIDTH 1 | ||
| 1868 | #define R_SERIAL2_TR_CTRL__tr_par__even 0 | ||
| 1869 | #define R_SERIAL2_TR_CTRL__tr_par__odd 1 | ||
| 1870 | #define R_SERIAL2_TR_CTRL__tr_par_en__BITNR 1 | ||
| 1871 | #define R_SERIAL2_TR_CTRL__tr_par_en__WIDTH 1 | ||
| 1872 | #define R_SERIAL2_TR_CTRL__tr_par_en__disable 0 | ||
| 1873 | #define R_SERIAL2_TR_CTRL__tr_par_en__enable 1 | ||
| 1874 | #define R_SERIAL2_TR_CTRL__tr_bitnr__BITNR 0 | ||
| 1875 | #define R_SERIAL2_TR_CTRL__tr_bitnr__WIDTH 1 | ||
| 1876 | #define R_SERIAL2_TR_CTRL__tr_bitnr__tr_8bit 0 | ||
| 1877 | #define R_SERIAL2_TR_CTRL__tr_bitnr__tr_7bit 1 | ||
| 1878 | |||
| 1879 | #define R_SERIAL2_TR_DATA (IO_TYPECAST_BYTE 0xb0000070) | ||
| 1880 | #define R_SERIAL2_TR_DATA__data_out__BITNR 0 | ||
| 1881 | #define R_SERIAL2_TR_DATA__data_out__WIDTH 8 | ||
| 1882 | |||
| 1883 | #define R_SERIAL2_READ (IO_TYPECAST_RO_UDWORD 0xb0000070) | ||
| 1884 | #define R_SERIAL2_READ__xoff_detect__BITNR 15 | ||
| 1885 | #define R_SERIAL2_READ__xoff_detect__WIDTH 1 | ||
| 1886 | #define R_SERIAL2_READ__xoff_detect__no_xoff 0 | ||
| 1887 | #define R_SERIAL2_READ__xoff_detect__xoff 1 | ||
| 1888 | #define R_SERIAL2_READ__cts___BITNR 14 | ||
| 1889 | #define R_SERIAL2_READ__cts___WIDTH 1 | ||
| 1890 | #define R_SERIAL2_READ__cts___active 0 | ||
| 1891 | #define R_SERIAL2_READ__cts___inactive 1 | ||
| 1892 | #define R_SERIAL2_READ__tr_ready__BITNR 13 | ||
| 1893 | #define R_SERIAL2_READ__tr_ready__WIDTH 1 | ||
| 1894 | #define R_SERIAL2_READ__tr_ready__full 0 | ||
| 1895 | #define R_SERIAL2_READ__tr_ready__ready 1 | ||
| 1896 | #define R_SERIAL2_READ__rxd__BITNR 12 | ||
| 1897 | #define R_SERIAL2_READ__rxd__WIDTH 1 | ||
| 1898 | #define R_SERIAL2_READ__overrun__BITNR 11 | ||
| 1899 | #define R_SERIAL2_READ__overrun__WIDTH 1 | ||
| 1900 | #define R_SERIAL2_READ__overrun__no 0 | ||
| 1901 | #define R_SERIAL2_READ__overrun__yes 1 | ||
| 1902 | #define R_SERIAL2_READ__par_err__BITNR 10 | ||
| 1903 | #define R_SERIAL2_READ__par_err__WIDTH 1 | ||
| 1904 | #define R_SERIAL2_READ__par_err__no 0 | ||
| 1905 | #define R_SERIAL2_READ__par_err__yes 1 | ||
| 1906 | #define R_SERIAL2_READ__framing_err__BITNR 9 | ||
| 1907 | #define R_SERIAL2_READ__framing_err__WIDTH 1 | ||
| 1908 | #define R_SERIAL2_READ__framing_err__no 0 | ||
| 1909 | #define R_SERIAL2_READ__framing_err__yes 1 | ||
| 1910 | #define R_SERIAL2_READ__data_avail__BITNR 8 | ||
| 1911 | #define R_SERIAL2_READ__data_avail__WIDTH 1 | ||
| 1912 | #define R_SERIAL2_READ__data_avail__no 0 | ||
| 1913 | #define R_SERIAL2_READ__data_avail__yes 1 | ||
| 1914 | #define R_SERIAL2_READ__data_in__BITNR 0 | ||
| 1915 | #define R_SERIAL2_READ__data_in__WIDTH 8 | ||
| 1916 | |||
| 1917 | #define R_SERIAL2_STATUS (IO_TYPECAST_RO_BYTE 0xb0000071) | ||
| 1918 | #define R_SERIAL2_STATUS__xoff_detect__BITNR 7 | ||
| 1919 | #define R_SERIAL2_STATUS__xoff_detect__WIDTH 1 | ||
| 1920 | #define R_SERIAL2_STATUS__xoff_detect__no_xoff 0 | ||
| 1921 | #define R_SERIAL2_STATUS__xoff_detect__xoff 1 | ||
| 1922 | #define R_SERIAL2_STATUS__cts___BITNR 6 | ||
| 1923 | #define R_SERIAL2_STATUS__cts___WIDTH 1 | ||
| 1924 | #define R_SERIAL2_STATUS__cts___active 0 | ||
| 1925 | #define R_SERIAL2_STATUS__cts___inactive 1 | ||
| 1926 | #define R_SERIAL2_STATUS__tr_ready__BITNR 5 | ||
| 1927 | #define R_SERIAL2_STATUS__tr_ready__WIDTH 1 | ||
| 1928 | #define R_SERIAL2_STATUS__tr_ready__full 0 | ||
| 1929 | #define R_SERIAL2_STATUS__tr_ready__ready 1 | ||
| 1930 | #define R_SERIAL2_STATUS__rxd__BITNR 4 | ||
| 1931 | #define R_SERIAL2_STATUS__rxd__WIDTH 1 | ||
| 1932 | #define R_SERIAL2_STATUS__overrun__BITNR 3 | ||
| 1933 | #define R_SERIAL2_STATUS__overrun__WIDTH 1 | ||
| 1934 | #define R_SERIAL2_STATUS__overrun__no 0 | ||
| 1935 | #define R_SERIAL2_STATUS__overrun__yes 1 | ||
| 1936 | #define R_SERIAL2_STATUS__par_err__BITNR 2 | ||
| 1937 | #define R_SERIAL2_STATUS__par_err__WIDTH 1 | ||
| 1938 | #define R_SERIAL2_STATUS__par_err__no 0 | ||
| 1939 | #define R_SERIAL2_STATUS__par_err__yes 1 | ||
| 1940 | #define R_SERIAL2_STATUS__framing_err__BITNR 1 | ||
| 1941 | #define R_SERIAL2_STATUS__framing_err__WIDTH 1 | ||
| 1942 | #define R_SERIAL2_STATUS__framing_err__no 0 | ||
| 1943 | #define R_SERIAL2_STATUS__framing_err__yes 1 | ||
| 1944 | #define R_SERIAL2_STATUS__data_avail__BITNR 0 | ||
| 1945 | #define R_SERIAL2_STATUS__data_avail__WIDTH 1 | ||
| 1946 | #define R_SERIAL2_STATUS__data_avail__no 0 | ||
| 1947 | #define R_SERIAL2_STATUS__data_avail__yes 1 | ||
| 1948 | |||
| 1949 | #define R_SERIAL2_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000070) | ||
| 1950 | #define R_SERIAL2_REC_DATA__data_in__BITNR 0 | ||
| 1951 | #define R_SERIAL2_REC_DATA__data_in__WIDTH 8 | ||
| 1952 | |||
| 1953 | #define R_SERIAL2_XOFF (IO_TYPECAST_UDWORD 0xb0000074) | ||
| 1954 | #define R_SERIAL2_XOFF__tx_stop__BITNR 9 | ||
| 1955 | #define R_SERIAL2_XOFF__tx_stop__WIDTH 1 | ||
| 1956 | #define R_SERIAL2_XOFF__tx_stop__enable 0 | ||
| 1957 | #define R_SERIAL2_XOFF__tx_stop__stop 1 | ||
| 1958 | #define R_SERIAL2_XOFF__auto_xoff__BITNR 8 | ||
| 1959 | #define R_SERIAL2_XOFF__auto_xoff__WIDTH 1 | ||
| 1960 | #define R_SERIAL2_XOFF__auto_xoff__disable 0 | ||
| 1961 | #define R_SERIAL2_XOFF__auto_xoff__enable 1 | ||
| 1962 | #define R_SERIAL2_XOFF__xoff_char__BITNR 0 | ||
| 1963 | #define R_SERIAL2_XOFF__xoff_char__WIDTH 8 | ||
| 1964 | |||
| 1965 | #define R_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078) | ||
| 1966 | #define R_SERIAL3_CTRL__tr_baud__BITNR 28 | ||
| 1967 | #define R_SERIAL3_CTRL__tr_baud__WIDTH 4 | ||
| 1968 | #define R_SERIAL3_CTRL__tr_baud__c300Hz 0 | ||
| 1969 | #define R_SERIAL3_CTRL__tr_baud__c600Hz 1 | ||
| 1970 | #define R_SERIAL3_CTRL__tr_baud__c1200Hz 2 | ||
| 1971 | #define R_SERIAL3_CTRL__tr_baud__c2400Hz 3 | ||
| 1972 | #define R_SERIAL3_CTRL__tr_baud__c4800Hz 4 | ||
| 1973 | #define R_SERIAL3_CTRL__tr_baud__c9600Hz 5 | ||
| 1974 | #define R_SERIAL3_CTRL__tr_baud__c19k2Hz 6 | ||
| 1975 | #define R_SERIAL3_CTRL__tr_baud__c38k4Hz 7 | ||
| 1976 | #define R_SERIAL3_CTRL__tr_baud__c57k6Hz 8 | ||
| 1977 | #define R_SERIAL3_CTRL__tr_baud__c115k2Hz 9 | ||
| 1978 | #define R_SERIAL3_CTRL__tr_baud__c230k4Hz 10 | ||
| 1979 | #define R_SERIAL3_CTRL__tr_baud__c460k8Hz 11 | ||
| 1980 | #define R_SERIAL3_CTRL__tr_baud__c921k6Hz 12 | ||
| 1981 | #define R_SERIAL3_CTRL__tr_baud__c1843k2Hz 13 | ||
| 1982 | #define R_SERIAL3_CTRL__tr_baud__c6250kHz 14 | ||
| 1983 | #define R_SERIAL3_CTRL__tr_baud__reserved 15 | ||
| 1984 | #define R_SERIAL3_CTRL__rec_baud__BITNR 24 | ||
| 1985 | #define R_SERIAL3_CTRL__rec_baud__WIDTH 4 | ||
| 1986 | #define R_SERIAL3_CTRL__rec_baud__c300Hz 0 | ||
| 1987 | #define R_SERIAL3_CTRL__rec_baud__c600Hz 1 | ||
| 1988 | #define R_SERIAL3_CTRL__rec_baud__c1200Hz 2 | ||
| 1989 | #define R_SERIAL3_CTRL__rec_baud__c2400Hz 3 | ||
| 1990 | #define R_SERIAL3_CTRL__rec_baud__c4800Hz 4 | ||
| 1991 | #define R_SERIAL3_CTRL__rec_baud__c9600Hz 5 | ||
| 1992 | #define R_SERIAL3_CTRL__rec_baud__c19k2Hz 6 | ||
| 1993 | #define R_SERIAL3_CTRL__rec_baud__c38k4Hz 7 | ||
| 1994 | #define R_SERIAL3_CTRL__rec_baud__c57k6Hz 8 | ||
| 1995 | #define R_SERIAL3_CTRL__rec_baud__c115k2Hz 9 | ||
| 1996 | #define R_SERIAL3_CTRL__rec_baud__c230k4Hz 10 | ||
| 1997 | #define R_SERIAL3_CTRL__rec_baud__c460k8Hz 11 | ||
| 1998 | #define R_SERIAL3_CTRL__rec_baud__c921k6Hz 12 | ||
| 1999 | #define R_SERIAL3_CTRL__rec_baud__c1843k2Hz 13 | ||
| 2000 | #define R_SERIAL3_CTRL__rec_baud__c6250kHz 14 | ||
| 2001 | #define R_SERIAL3_CTRL__rec_baud__reserved 15 | ||
| 2002 | #define R_SERIAL3_CTRL__dma_err__BITNR 23 | ||
| 2003 | #define R_SERIAL3_CTRL__dma_err__WIDTH 1 | ||
| 2004 | #define R_SERIAL3_CTRL__dma_err__stop 0 | ||
| 2005 | #define R_SERIAL3_CTRL__dma_err__ignore 1 | ||
| 2006 | #define R_SERIAL3_CTRL__rec_enable__BITNR 22 | ||
| 2007 | #define R_SERIAL3_CTRL__rec_enable__WIDTH 1 | ||
| 2008 | #define R_SERIAL3_CTRL__rec_enable__disable 0 | ||
| 2009 | #define R_SERIAL3_CTRL__rec_enable__enable 1 | ||
| 2010 | #define R_SERIAL3_CTRL__rts___BITNR 21 | ||
| 2011 | #define R_SERIAL3_CTRL__rts___WIDTH 1 | ||
| 2012 | #define R_SERIAL3_CTRL__rts___active 0 | ||
| 2013 | #define R_SERIAL3_CTRL__rts___inactive 1 | ||
| 2014 | #define R_SERIAL3_CTRL__sampling__BITNR 20 | ||
| 2015 | #define R_SERIAL3_CTRL__sampling__WIDTH 1 | ||
| 2016 | #define R_SERIAL3_CTRL__sampling__middle 0 | ||
| 2017 | #define R_SERIAL3_CTRL__sampling__majority 1 | ||
| 2018 | #define R_SERIAL3_CTRL__rec_stick_par__BITNR 19 | ||
| 2019 | #define R_SERIAL3_CTRL__rec_stick_par__WIDTH 1 | ||
| 2020 | #define R_SERIAL3_CTRL__rec_stick_par__normal 0 | ||
| 2021 | #define R_SERIAL3_CTRL__rec_stick_par__stick 1 | ||
| 2022 | #define R_SERIAL3_CTRL__rec_par__BITNR 18 | ||
| 2023 | #define R_SERIAL3_CTRL__rec_par__WIDTH 1 | ||
| 2024 | #define R_SERIAL3_CTRL__rec_par__even 0 | ||
| 2025 | #define R_SERIAL3_CTRL__rec_par__odd 1 | ||
| 2026 | #define R_SERIAL3_CTRL__rec_par_en__BITNR 17 | ||
| 2027 | #define R_SERIAL3_CTRL__rec_par_en__WIDTH 1 | ||
| 2028 | #define R_SERIAL3_CTRL__rec_par_en__disable 0 | ||
| 2029 | #define R_SERIAL3_CTRL__rec_par_en__enable 1 | ||
| 2030 | #define R_SERIAL3_CTRL__rec_bitnr__BITNR 16 | ||
| 2031 | #define R_SERIAL3_CTRL__rec_bitnr__WIDTH 1 | ||
| 2032 | #define R_SERIAL3_CTRL__rec_bitnr__rec_8bit 0 | ||
| 2033 | #define R_SERIAL3_CTRL__rec_bitnr__rec_7bit 1 | ||
| 2034 | #define R_SERIAL3_CTRL__txd__BITNR 15 | ||
| 2035 | #define R_SERIAL3_CTRL__txd__WIDTH 1 | ||
| 2036 | #define R_SERIAL3_CTRL__tr_enable__BITNR 14 | ||
| 2037 | #define R_SERIAL3_CTRL__tr_enable__WIDTH 1 | ||
| 2038 | #define R_SERIAL3_CTRL__tr_enable__disable 0 | ||
| 2039 | #define R_SERIAL3_CTRL__tr_enable__enable 1 | ||
| 2040 | #define R_SERIAL3_CTRL__auto_cts__BITNR 13 | ||
| 2041 | #define R_SERIAL3_CTRL__auto_cts__WIDTH 1 | ||
| 2042 | #define R_SERIAL3_CTRL__auto_cts__disabled 0 | ||
| 2043 | #define R_SERIAL3_CTRL__auto_cts__active 1 | ||
| 2044 | #define R_SERIAL3_CTRL__stop_bits__BITNR 12 | ||
| 2045 | #define R_SERIAL3_CTRL__stop_bits__WIDTH 1 | ||
| 2046 | #define R_SERIAL3_CTRL__stop_bits__one_bit 0 | ||
| 2047 | #define R_SERIAL3_CTRL__stop_bits__two_bits 1 | ||
| 2048 | #define R_SERIAL3_CTRL__tr_stick_par__BITNR 11 | ||
| 2049 | #define R_SERIAL3_CTRL__tr_stick_par__WIDTH 1 | ||
| 2050 | #define R_SERIAL3_CTRL__tr_stick_par__normal 0 | ||
| 2051 | #define R_SERIAL3_CTRL__tr_stick_par__stick 1 | ||
| 2052 | #define R_SERIAL3_CTRL__tr_par__BITNR 10 | ||
| 2053 | #define R_SERIAL3_CTRL__tr_par__WIDTH 1 | ||
| 2054 | #define R_SERIAL3_CTRL__tr_par__even 0 | ||
| 2055 | #define R_SERIAL3_CTRL__tr_par__odd 1 | ||
| 2056 | #define R_SERIAL3_CTRL__tr_par_en__BITNR 9 | ||
| 2057 | #define R_SERIAL3_CTRL__tr_par_en__WIDTH 1 | ||
| 2058 | #define R_SERIAL3_CTRL__tr_par_en__disable 0 | ||
| 2059 | #define R_SERIAL3_CTRL__tr_par_en__enable 1 | ||
| 2060 | #define R_SERIAL3_CTRL__tr_bitnr__BITNR 8 | ||
| 2061 | #define R_SERIAL3_CTRL__tr_bitnr__WIDTH 1 | ||
| 2062 | #define R_SERIAL3_CTRL__tr_bitnr__tr_8bit 0 | ||
| 2063 | #define R_SERIAL3_CTRL__tr_bitnr__tr_7bit 1 | ||
| 2064 | #define R_SERIAL3_CTRL__data_out__BITNR 0 | ||
| 2065 | #define R_SERIAL3_CTRL__data_out__WIDTH 8 | ||
| 2066 | |||
| 2067 | #define R_SERIAL3_BAUD (IO_TYPECAST_BYTE 0xb000007b) | ||
| 2068 | #define R_SERIAL3_BAUD__tr_baud__BITNR 4 | ||
| 2069 | #define R_SERIAL3_BAUD__tr_baud__WIDTH 4 | ||
| 2070 | #define R_SERIAL3_BAUD__tr_baud__c300Hz 0 | ||
| 2071 | #define R_SERIAL3_BAUD__tr_baud__c600Hz 1 | ||
| 2072 | #define R_SERIAL3_BAUD__tr_baud__c1200Hz 2 | ||
| 2073 | #define R_SERIAL3_BAUD__tr_baud__c2400Hz 3 | ||
| 2074 | #define R_SERIAL3_BAUD__tr_baud__c4800Hz 4 | ||
| 2075 | #define R_SERIAL3_BAUD__tr_baud__c9600Hz 5 | ||
| 2076 | #define R_SERIAL3_BAUD__tr_baud__c19k2Hz 6 | ||
| 2077 | #define R_SERIAL3_BAUD__tr_baud__c38k4Hz 7 | ||
| 2078 | #define R_SERIAL3_BAUD__tr_baud__c57k6Hz 8 | ||
| 2079 | #define R_SERIAL3_BAUD__tr_baud__c115k2Hz 9 | ||
| 2080 | #define R_SERIAL3_BAUD__tr_baud__c230k4Hz 10 | ||
| 2081 | #define R_SERIAL3_BAUD__tr_baud__c460k8Hz 11 | ||
| 2082 | #define R_SERIAL3_BAUD__tr_baud__c921k6Hz 12 | ||
| 2083 | #define R_SERIAL3_BAUD__tr_baud__c1843k2Hz 13 | ||
| 2084 | #define R_SERIAL3_BAUD__tr_baud__c6250kHz 14 | ||
| 2085 | #define R_SERIAL3_BAUD__tr_baud__reserved 15 | ||
| 2086 | #define R_SERIAL3_BAUD__rec_baud__BITNR 0 | ||
| 2087 | #define R_SERIAL3_BAUD__rec_baud__WIDTH 4 | ||
| 2088 | #define R_SERIAL3_BAUD__rec_baud__c300Hz 0 | ||
| 2089 | #define R_SERIAL3_BAUD__rec_baud__c600Hz 1 | ||
| 2090 | #define R_SERIAL3_BAUD__rec_baud__c1200Hz 2 | ||
| 2091 | #define R_SERIAL3_BAUD__rec_baud__c2400Hz 3 | ||
| 2092 | #define R_SERIAL3_BAUD__rec_baud__c4800Hz 4 | ||
| 2093 | #define R_SERIAL3_BAUD__rec_baud__c9600Hz 5 | ||
| 2094 | #define R_SERIAL3_BAUD__rec_baud__c19k2Hz 6 | ||
| 2095 | #define R_SERIAL3_BAUD__rec_baud__c38k4Hz 7 | ||
| 2096 | #define R_SERIAL3_BAUD__rec_baud__c57k6Hz 8 | ||
| 2097 | #define R_SERIAL3_BAUD__rec_baud__c115k2Hz 9 | ||
| 2098 | #define R_SERIAL3_BAUD__rec_baud__c230k4Hz 10 | ||
| 2099 | #define R_SERIAL3_BAUD__rec_baud__c460k8Hz 11 | ||
| 2100 | #define R_SERIAL3_BAUD__rec_baud__c921k6Hz 12 | ||
| 2101 | #define R_SERIAL3_BAUD__rec_baud__c1843k2Hz 13 | ||
| 2102 | #define R_SERIAL3_BAUD__rec_baud__c6250kHz 14 | ||
| 2103 | #define R_SERIAL3_BAUD__rec_baud__reserved 15 | ||
| 2104 | |||
| 2105 | #define R_SERIAL3_REC_CTRL (IO_TYPECAST_BYTE 0xb000007a) | ||
| 2106 | #define R_SERIAL3_REC_CTRL__dma_err__BITNR 7 | ||
| 2107 | #define R_SERIAL3_REC_CTRL__dma_err__WIDTH 1 | ||
| 2108 | #define R_SERIAL3_REC_CTRL__dma_err__stop 0 | ||
| 2109 | #define R_SERIAL3_REC_CTRL__dma_err__ignore 1 | ||
| 2110 | #define R_SERIAL3_REC_CTRL__rec_enable__BITNR 6 | ||
| 2111 | #define R_SERIAL3_REC_CTRL__rec_enable__WIDTH 1 | ||
| 2112 | #define R_SERIAL3_REC_CTRL__rec_enable__disable 0 | ||
| 2113 | #define R_SERIAL3_REC_CTRL__rec_enable__enable 1 | ||
| 2114 | #define R_SERIAL3_REC_CTRL__rts___BITNR 5 | ||
| 2115 | #define R_SERIAL3_REC_CTRL__rts___WIDTH 1 | ||
| 2116 | #define R_SERIAL3_REC_CTRL__rts___active 0 | ||
| 2117 | #define R_SERIAL3_REC_CTRL__rts___inactive 1 | ||
| 2118 | #define R_SERIAL3_REC_CTRL__sampling__BITNR 4 | ||
| 2119 | #define R_SERIAL3_REC_CTRL__sampling__WIDTH 1 | ||
| 2120 | #define R_SERIAL3_REC_CTRL__sampling__middle 0 | ||
| 2121 | #define R_SERIAL3_REC_CTRL__sampling__majority 1 | ||
| 2122 | #define R_SERIAL3_REC_CTRL__rec_stick_par__BITNR 3 | ||
| 2123 | #define R_SERIAL3_REC_CTRL__rec_stick_par__WIDTH 1 | ||
| 2124 | #define R_SERIAL3_REC_CTRL__rec_stick_par__normal 0 | ||
| 2125 | #define R_SERIAL3_REC_CTRL__rec_stick_par__stick 1 | ||
| 2126 | #define R_SERIAL3_REC_CTRL__rec_par__BITNR 2 | ||
| 2127 | #define R_SERIAL3_REC_CTRL__rec_par__WIDTH 1 | ||
| 2128 | #define R_SERIAL3_REC_CTRL__rec_par__even 0 | ||
| 2129 | #define R_SERIAL3_REC_CTRL__rec_par__odd 1 | ||
| 2130 | #define R_SERIAL3_REC_CTRL__rec_par_en__BITNR 1 | ||
| 2131 | #define R_SERIAL3_REC_CTRL__rec_par_en__WIDTH 1 | ||
| 2132 | #define R_SERIAL3_REC_CTRL__rec_par_en__disable 0 | ||
| 2133 | #define R_SERIAL3_REC_CTRL__rec_par_en__enable 1 | ||
| 2134 | #define R_SERIAL3_REC_CTRL__rec_bitnr__BITNR 0 | ||
| 2135 | #define R_SERIAL3_REC_CTRL__rec_bitnr__WIDTH 1 | ||
| 2136 | #define R_SERIAL3_REC_CTRL__rec_bitnr__rec_8bit 0 | ||
| 2137 | #define R_SERIAL3_REC_CTRL__rec_bitnr__rec_7bit 1 | ||
| 2138 | |||
| 2139 | #define R_SERIAL3_TR_CTRL (IO_TYPECAST_BYTE 0xb0000079) | ||
| 2140 | #define R_SERIAL3_TR_CTRL__txd__BITNR 7 | ||
| 2141 | #define R_SERIAL3_TR_CTRL__txd__WIDTH 1 | ||
| 2142 | #define R_SERIAL3_TR_CTRL__tr_enable__BITNR 6 | ||
| 2143 | #define R_SERIAL3_TR_CTRL__tr_enable__WIDTH 1 | ||
| 2144 | #define R_SERIAL3_TR_CTRL__tr_enable__disable 0 | ||
| 2145 | #define R_SERIAL3_TR_CTRL__tr_enable__enable 1 | ||
| 2146 | #define R_SERIAL3_TR_CTRL__auto_cts__BITNR 5 | ||
| 2147 | #define R_SERIAL3_TR_CTRL__auto_cts__WIDTH 1 | ||
| 2148 | #define R_SERIAL3_TR_CTRL__auto_cts__disabled 0 | ||
| 2149 | #define R_SERIAL3_TR_CTRL__auto_cts__active 1 | ||
| 2150 | #define R_SERIAL3_TR_CTRL__stop_bits__BITNR 4 | ||
| 2151 | #define R_SERIAL3_TR_CTRL__stop_bits__WIDTH 1 | ||
| 2152 | #define R_SERIAL3_TR_CTRL__stop_bits__one_bit 0 | ||
| 2153 | #define R_SERIAL3_TR_CTRL__stop_bits__two_bits 1 | ||
| 2154 | #define R_SERIAL3_TR_CTRL__tr_stick_par__BITNR 3 | ||
| 2155 | #define R_SERIAL3_TR_CTRL__tr_stick_par__WIDTH 1 | ||
| 2156 | #define R_SERIAL3_TR_CTRL__tr_stick_par__normal 0 | ||
| 2157 | #define R_SERIAL3_TR_CTRL__tr_stick_par__stick 1 | ||
| 2158 | #define R_SERIAL3_TR_CTRL__tr_par__BITNR 2 | ||
| 2159 | #define R_SERIAL3_TR_CTRL__tr_par__WIDTH 1 | ||
| 2160 | #define R_SERIAL3_TR_CTRL__tr_par__even 0 | ||
| 2161 | #define R_SERIAL3_TR_CTRL__tr_par__odd 1 | ||
| 2162 | #define R_SERIAL3_TR_CTRL__tr_par_en__BITNR 1 | ||
| 2163 | #define R_SERIAL3_TR_CTRL__tr_par_en__WIDTH 1 | ||
| 2164 | #define R_SERIAL3_TR_CTRL__tr_par_en__disable 0 | ||
| 2165 | #define R_SERIAL3_TR_CTRL__tr_par_en__enable 1 | ||
| 2166 | #define R_SERIAL3_TR_CTRL__tr_bitnr__BITNR 0 | ||
| 2167 | #define R_SERIAL3_TR_CTRL__tr_bitnr__WIDTH 1 | ||
| 2168 | #define R_SERIAL3_TR_CTRL__tr_bitnr__tr_8bit 0 | ||
| 2169 | #define R_SERIAL3_TR_CTRL__tr_bitnr__tr_7bit 1 | ||
| 2170 | |||
| 2171 | #define R_SERIAL3_TR_DATA (IO_TYPECAST_BYTE 0xb0000078) | ||
| 2172 | #define R_SERIAL3_TR_DATA__data_out__BITNR 0 | ||
| 2173 | #define R_SERIAL3_TR_DATA__data_out__WIDTH 8 | ||
| 2174 | |||
| 2175 | #define R_SERIAL3_READ (IO_TYPECAST_RO_UDWORD 0xb0000078) | ||
| 2176 | #define R_SERIAL3_READ__xoff_detect__BITNR 15 | ||
| 2177 | #define R_SERIAL3_READ__xoff_detect__WIDTH 1 | ||
| 2178 | #define R_SERIAL3_READ__xoff_detect__no_xoff 0 | ||
| 2179 | #define R_SERIAL3_READ__xoff_detect__xoff 1 | ||
| 2180 | #define R_SERIAL3_READ__cts___BITNR 14 | ||
| 2181 | #define R_SERIAL3_READ__cts___WIDTH 1 | ||
| 2182 | #define R_SERIAL3_READ__cts___active 0 | ||
| 2183 | #define R_SERIAL3_READ__cts___inactive 1 | ||
| 2184 | #define R_SERIAL3_READ__tr_ready__BITNR 13 | ||
| 2185 | #define R_SERIAL3_READ__tr_ready__WIDTH 1 | ||
| 2186 | #define R_SERIAL3_READ__tr_ready__full 0 | ||
| 2187 | #define R_SERIAL3_READ__tr_ready__ready 1 | ||
| 2188 | #define R_SERIAL3_READ__rxd__BITNR 12 | ||
| 2189 | #define R_SERIAL3_READ__rxd__WIDTH 1 | ||
| 2190 | #define R_SERIAL3_READ__overrun__BITNR 11 | ||
| 2191 | #define R_SERIAL3_READ__overrun__WIDTH 1 | ||
| 2192 | #define R_SERIAL3_READ__overrun__no 0 | ||
| 2193 | #define R_SERIAL3_READ__overrun__yes 1 | ||
| 2194 | #define R_SERIAL3_READ__par_err__BITNR 10 | ||
| 2195 | #define R_SERIAL3_READ__par_err__WIDTH 1 | ||
| 2196 | #define R_SERIAL3_READ__par_err__no 0 | ||
| 2197 | #define R_SERIAL3_READ__par_err__yes 1 | ||
| 2198 | #define R_SERIAL3_READ__framing_err__BITNR 9 | ||
| 2199 | #define R_SERIAL3_READ__framing_err__WIDTH 1 | ||
| 2200 | #define R_SERIAL3_READ__framing_err__no 0 | ||
| 2201 | #define R_SERIAL3_READ__framing_err__yes 1 | ||
| 2202 | #define R_SERIAL3_READ__data_avail__BITNR 8 | ||
| 2203 | #define R_SERIAL3_READ__data_avail__WIDTH 1 | ||
| 2204 | #define R_SERIAL3_READ__data_avail__no 0 | ||
| 2205 | #define R_SERIAL3_READ__data_avail__yes 1 | ||
| 2206 | #define R_SERIAL3_READ__data_in__BITNR 0 | ||
| 2207 | #define R_SERIAL3_READ__data_in__WIDTH 8 | ||
| 2208 | |||
| 2209 | #define R_SERIAL3_STATUS (IO_TYPECAST_RO_BYTE 0xb0000079) | ||
| 2210 | #define R_SERIAL3_STATUS__xoff_detect__BITNR 7 | ||
| 2211 | #define R_SERIAL3_STATUS__xoff_detect__WIDTH 1 | ||
| 2212 | #define R_SERIAL3_STATUS__xoff_detect__no_xoff 0 | ||
| 2213 | #define R_SERIAL3_STATUS__xoff_detect__xoff 1 | ||
| 2214 | #define R_SERIAL3_STATUS__cts___BITNR 6 | ||
| 2215 | #define R_SERIAL3_STATUS__cts___WIDTH 1 | ||
| 2216 | #define R_SERIAL3_STATUS__cts___active 0 | ||
| 2217 | #define R_SERIAL3_STATUS__cts___inactive 1 | ||
| 2218 | #define R_SERIAL3_STATUS__tr_ready__BITNR 5 | ||
| 2219 | #define R_SERIAL3_STATUS__tr_ready__WIDTH 1 | ||
| 2220 | #define R_SERIAL3_STATUS__tr_ready__full 0 | ||
| 2221 | #define R_SERIAL3_STATUS__tr_ready__ready 1 | ||
| 2222 | #define R_SERIAL3_STATUS__rxd__BITNR 4 | ||
| 2223 | #define R_SERIAL3_STATUS__rxd__WIDTH 1 | ||
| 2224 | #define R_SERIAL3_STATUS__overrun__BITNR 3 | ||
| 2225 | #define R_SERIAL3_STATUS__overrun__WIDTH 1 | ||
| 2226 | #define R_SERIAL3_STATUS__overrun__no 0 | ||
| 2227 | #define R_SERIAL3_STATUS__overrun__yes 1 | ||
| 2228 | #define R_SERIAL3_STATUS__par_err__BITNR 2 | ||
| 2229 | #define R_SERIAL3_STATUS__par_err__WIDTH 1 | ||
| 2230 | #define R_SERIAL3_STATUS__par_err__no 0 | ||
| 2231 | #define R_SERIAL3_STATUS__par_err__yes 1 | ||
| 2232 | #define R_SERIAL3_STATUS__framing_err__BITNR 1 | ||
| 2233 | #define R_SERIAL3_STATUS__framing_err__WIDTH 1 | ||
| 2234 | #define R_SERIAL3_STATUS__framing_err__no 0 | ||
| 2235 | #define R_SERIAL3_STATUS__framing_err__yes 1 | ||
| 2236 | #define R_SERIAL3_STATUS__data_avail__BITNR 0 | ||
| 2237 | #define R_SERIAL3_STATUS__data_avail__WIDTH 1 | ||
| 2238 | #define R_SERIAL3_STATUS__data_avail__no 0 | ||
| 2239 | #define R_SERIAL3_STATUS__data_avail__yes 1 | ||
| 2240 | |||
| 2241 | #define R_SERIAL3_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000078) | ||
| 2242 | #define R_SERIAL3_REC_DATA__data_in__BITNR 0 | ||
| 2243 | #define R_SERIAL3_REC_DATA__data_in__WIDTH 8 | ||
| 2244 | |||
| 2245 | #define R_SERIAL3_XOFF (IO_TYPECAST_UDWORD 0xb000007c) | ||
| 2246 | #define R_SERIAL3_XOFF__tx_stop__BITNR 9 | ||
| 2247 | #define R_SERIAL3_XOFF__tx_stop__WIDTH 1 | ||
| 2248 | #define R_SERIAL3_XOFF__tx_stop__enable 0 | ||
| 2249 | #define R_SERIAL3_XOFF__tx_stop__stop 1 | ||
| 2250 | #define R_SERIAL3_XOFF__auto_xoff__BITNR 8 | ||
| 2251 | #define R_SERIAL3_XOFF__auto_xoff__WIDTH 1 | ||
| 2252 | #define R_SERIAL3_XOFF__auto_xoff__disable 0 | ||
| 2253 | #define R_SERIAL3_XOFF__auto_xoff__enable 1 | ||
| 2254 | #define R_SERIAL3_XOFF__xoff_char__BITNR 0 | ||
| 2255 | #define R_SERIAL3_XOFF__xoff_char__WIDTH 8 | ||
| 2256 | |||
| 2257 | #define R_ALT_SER_BAUDRATE (IO_TYPECAST_UDWORD 0xb000005c) | ||
| 2258 | #define R_ALT_SER_BAUDRATE__ser3_tr__BITNR 28 | ||
| 2259 | #define R_ALT_SER_BAUDRATE__ser3_tr__WIDTH 2 | ||
| 2260 | #define R_ALT_SER_BAUDRATE__ser3_tr__normal 0 | ||
| 2261 | #define R_ALT_SER_BAUDRATE__ser3_tr__prescale 1 | ||
| 2262 | #define R_ALT_SER_BAUDRATE__ser3_tr__extern 2 | ||
| 2263 | #define R_ALT_SER_BAUDRATE__ser3_tr__timer 3 | ||
| 2264 | #define R_ALT_SER_BAUDRATE__ser3_rec__BITNR 24 | ||
| 2265 | #define R_ALT_SER_BAUDRATE__ser3_rec__WIDTH 2 | ||
| 2266 | #define R_ALT_SER_BAUDRATE__ser3_rec__normal 0 | ||
| 2267 | #define R_ALT_SER_BAUDRATE__ser3_rec__prescale 1 | ||
| 2268 | #define R_ALT_SER_BAUDRATE__ser3_rec__extern 2 | ||
| 2269 | #define R_ALT_SER_BAUDRATE__ser3_rec__timer 3 | ||
| 2270 | #define R_ALT_SER_BAUDRATE__ser2_tr__BITNR 20 | ||
| 2271 | #define R_ALT_SER_BAUDRATE__ser2_tr__WIDTH 2 | ||
| 2272 | #define R_ALT_SER_BAUDRATE__ser2_tr__normal 0 | ||
| 2273 | #define R_ALT_SER_BAUDRATE__ser2_tr__prescale 1 | ||
| 2274 | #define R_ALT_SER_BAUDRATE__ser2_tr__extern 2 | ||
| 2275 | #define R_ALT_SER_BAUDRATE__ser2_tr__timer 3 | ||
| 2276 | #define R_ALT_SER_BAUDRATE__ser2_rec__BITNR 16 | ||
| 2277 | #define R_ALT_SER_BAUDRATE__ser2_rec__WIDTH 2 | ||
| 2278 | #define R_ALT_SER_BAUDRATE__ser2_rec__normal 0 | ||
| 2279 | #define R_ALT_SER_BAUDRATE__ser2_rec__prescale 1 | ||
| 2280 | #define R_ALT_SER_BAUDRATE__ser2_rec__extern 2 | ||
| 2281 | #define R_ALT_SER_BAUDRATE__ser2_rec__timer 3 | ||
| 2282 | #define R_ALT_SER_BAUDRATE__ser1_tr__BITNR 12 | ||
| 2283 | #define R_ALT_SER_BAUDRATE__ser1_tr__WIDTH 2 | ||
| 2284 | #define R_ALT_SER_BAUDRATE__ser1_tr__normal 0 | ||
| 2285 | #define R_ALT_SER_BAUDRATE__ser1_tr__prescale 1 | ||
| 2286 | #define R_ALT_SER_BAUDRATE__ser1_tr__extern 2 | ||
| 2287 | #define R_ALT_SER_BAUDRATE__ser1_tr__timer 3 | ||
| 2288 | #define R_ALT_SER_BAUDRATE__ser1_rec__BITNR 8 | ||
| 2289 | #define R_ALT_SER_BAUDRATE__ser1_rec__WIDTH 2 | ||
| 2290 | #define R_ALT_SER_BAUDRATE__ser1_rec__normal 0 | ||
| 2291 | #define R_ALT_SER_BAUDRATE__ser1_rec__prescale 1 | ||
| 2292 | #define R_ALT_SER_BAUDRATE__ser1_rec__extern 2 | ||
| 2293 | #define R_ALT_SER_BAUDRATE__ser1_rec__timer 3 | ||
| 2294 | #define R_ALT_SER_BAUDRATE__ser0_tr__BITNR 4 | ||
| 2295 | #define R_ALT_SER_BAUDRATE__ser0_tr__WIDTH 2 | ||
| 2296 | #define R_ALT_SER_BAUDRATE__ser0_tr__normal 0 | ||
| 2297 | #define R_ALT_SER_BAUDRATE__ser0_tr__prescale 1 | ||
| 2298 | #define R_ALT_SER_BAUDRATE__ser0_tr__extern 2 | ||
| 2299 | #define R_ALT_SER_BAUDRATE__ser0_tr__timer 3 | ||
| 2300 | #define R_ALT_SER_BAUDRATE__ser0_rec__BITNR 0 | ||
| 2301 | #define R_ALT_SER_BAUDRATE__ser0_rec__WIDTH 2 | ||
| 2302 | #define R_ALT_SER_BAUDRATE__ser0_rec__normal 0 | ||
| 2303 | #define R_ALT_SER_BAUDRATE__ser0_rec__prescale 1 | ||
| 2304 | #define R_ALT_SER_BAUDRATE__ser0_rec__extern 2 | ||
| 2305 | #define R_ALT_SER_BAUDRATE__ser0_rec__timer 3 | ||
| 2306 | |||
| 2307 | /* | ||
| 2308 | !* Network interface registers | ||
| 2309 | !*/ | ||
| 2310 | |||
| 2311 | #define R_NETWORK_SA_0 (IO_TYPECAST_UDWORD 0xb0000080) | ||
| 2312 | #define R_NETWORK_SA_0__ma0_low__BITNR 0 | ||
| 2313 | #define R_NETWORK_SA_0__ma0_low__WIDTH 32 | ||
| 2314 | |||
| 2315 | #define R_NETWORK_SA_1 (IO_TYPECAST_UDWORD 0xb0000084) | ||
| 2316 | #define R_NETWORK_SA_1__ma1_low__BITNR 16 | ||
| 2317 | #define R_NETWORK_SA_1__ma1_low__WIDTH 16 | ||
| 2318 | #define R_NETWORK_SA_1__ma0_high__BITNR 0 | ||
| 2319 | #define R_NETWORK_SA_1__ma0_high__WIDTH 16 | ||
| 2320 | |||
| 2321 | #define R_NETWORK_SA_2 (IO_TYPECAST_UDWORD 0xb0000088) | ||
| 2322 | #define R_NETWORK_SA_2__ma1_high__BITNR 0 | ||
| 2323 | #define R_NETWORK_SA_2__ma1_high__WIDTH 32 | ||
| 2324 | |||
| 2325 | #define R_NETWORK_GA_0 (IO_TYPECAST_UDWORD 0xb000008c) | ||
| 2326 | #define R_NETWORK_GA_0__ga_low__BITNR 0 | ||
| 2327 | #define R_NETWORK_GA_0__ga_low__WIDTH 32 | ||
| 2328 | |||
| 2329 | #define R_NETWORK_GA_1 (IO_TYPECAST_UDWORD 0xb0000090) | ||
| 2330 | #define R_NETWORK_GA_1__ga_high__BITNR 0 | ||
| 2331 | #define R_NETWORK_GA_1__ga_high__WIDTH 32 | ||
| 2332 | |||
| 2333 | #define R_NETWORK_REC_CONFIG (IO_TYPECAST_UDWORD 0xb0000094) | ||
| 2334 | #define R_NETWORK_REC_CONFIG__max_size__BITNR 10 | ||
| 2335 | #define R_NETWORK_REC_CONFIG__max_size__WIDTH 1 | ||
| 2336 | #define R_NETWORK_REC_CONFIG__max_size__size1518 0 | ||
| 2337 | #define R_NETWORK_REC_CONFIG__max_size__size1522 1 | ||
| 2338 | #define R_NETWORK_REC_CONFIG__duplex__BITNR 9 | ||
| 2339 | #define R_NETWORK_REC_CONFIG__duplex__WIDTH 1 | ||
| 2340 | #define R_NETWORK_REC_CONFIG__duplex__full 1 | ||
| 2341 | #define R_NETWORK_REC_CONFIG__duplex__half 0 | ||
| 2342 | #define R_NETWORK_REC_CONFIG__bad_crc__BITNR 8 | ||
| 2343 | #define R_NETWORK_REC_CONFIG__bad_crc__WIDTH 1 | ||
| 2344 | #define R_NETWORK_REC_CONFIG__bad_crc__receive 1 | ||
| 2345 | #define R_NETWORK_REC_CONFIG__bad_crc__discard 0 | ||
| 2346 | #define R_NETWORK_REC_CONFIG__oversize__BITNR 7 | ||
| 2347 | #define R_NETWORK_REC_CONFIG__oversize__WIDTH 1 | ||
| 2348 | #define R_NETWORK_REC_CONFIG__oversize__receive 1 | ||
| 2349 | #define R_NETWORK_REC_CONFIG__oversize__discard 0 | ||
| 2350 | #define R_NETWORK_REC_CONFIG__undersize__BITNR 6 | ||
| 2351 | #define R_NETWORK_REC_CONFIG__undersize__WIDTH 1 | ||
| 2352 | #define R_NETWORK_REC_CONFIG__undersize__receive 1 | ||
| 2353 | #define R_NETWORK_REC_CONFIG__undersize__discard 0 | ||
| 2354 | #define R_NETWORK_REC_CONFIG__all_roots__BITNR 5 | ||
| 2355 | #define R_NETWORK_REC_CONFIG__all_roots__WIDTH 1 | ||
| 2356 | #define R_NETWORK_REC_CONFIG__all_roots__receive 1 | ||
| 2357 | #define R_NETWORK_REC_CONFIG__all_roots__discard 0 | ||
| 2358 | #define R_NETWORK_REC_CONFIG__tr_broadcast__BITNR 4 | ||
| 2359 | #define R_NETWORK_REC_CONFIG__tr_broadcast__WIDTH 1 | ||
| 2360 | #define R_NETWORK_REC_CONFIG__tr_broadcast__receive 1 | ||
| 2361 | #define R_NETWORK_REC_CONFIG__tr_broadcast__discard 0 | ||
| 2362 | #define R_NETWORK_REC_CONFIG__broadcast__BITNR 3 | ||
| 2363 | #define R_NETWORK_REC_CONFIG__broadcast__WIDTH 1 | ||
| 2364 | #define R_NETWORK_REC_CONFIG__broadcast__receive 1 | ||
| 2365 | #define R_NETWORK_REC_CONFIG__broadcast__discard 0 | ||
| 2366 | #define R_NETWORK_REC_CONFIG__individual__BITNR 2 | ||
| 2367 | #define R_NETWORK_REC_CONFIG__individual__WIDTH 1 | ||
| 2368 | #define R_NETWORK_REC_CONFIG__individual__receive 1 | ||
| 2369 | #define R_NETWORK_REC_CONFIG__individual__discard 0 | ||
| 2370 | #define R_NETWORK_REC_CONFIG__ma1__BITNR 1 | ||
| 2371 | #define R_NETWORK_REC_CONFIG__ma1__WIDTH 1 | ||
| 2372 | #define R_NETWORK_REC_CONFIG__ma1__enable 1 | ||
| 2373 | #define R_NETWORK_REC_CONFIG__ma1__disable 0 | ||
| 2374 | #define R_NETWORK_REC_CONFIG__ma0__BITNR 0 | ||
| 2375 | #define R_NETWORK_REC_CONFIG__ma0__WIDTH 1 | ||
| 2376 | #define R_NETWORK_REC_CONFIG__ma0__enable 1 | ||
| 2377 | #define R_NETWORK_REC_CONFIG__ma0__disable 0 | ||
| 2378 | |||
| 2379 | #define R_NETWORK_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb0000098) | ||
| 2380 | #define R_NETWORK_GEN_CONFIG__loopback__BITNR 5 | ||
| 2381 | #define R_NETWORK_GEN_CONFIG__loopback__WIDTH 1 | ||
| 2382 | #define R_NETWORK_GEN_CONFIG__loopback__on 1 | ||
| 2383 | #define R_NETWORK_GEN_CONFIG__loopback__off 0 | ||
| 2384 | #define R_NETWORK_GEN_CONFIG__frame__BITNR 4 | ||
| 2385 | #define R_NETWORK_GEN_CONFIG__frame__WIDTH 1 | ||
| 2386 | #define R_NETWORK_GEN_CONFIG__frame__tokenr 1 | ||
| 2387 | #define R_NETWORK_GEN_CONFIG__frame__ether 0 | ||
| 2388 | #define R_NETWORK_GEN_CONFIG__vg__BITNR 3 | ||
| 2389 | #define R_NETWORK_GEN_CONFIG__vg__WIDTH 1 | ||
| 2390 | #define R_NETWORK_GEN_CONFIG__vg__on 1 | ||
| 2391 | #define R_NETWORK_GEN_CONFIG__vg__off 0 | ||
| 2392 | #define R_NETWORK_GEN_CONFIG__phy__BITNR 1 | ||
| 2393 | #define R_NETWORK_GEN_CONFIG__phy__WIDTH 2 | ||
| 2394 | #define R_NETWORK_GEN_CONFIG__phy__sni 0 | ||
| 2395 | #define R_NETWORK_GEN_CONFIG__phy__mii_clk 1 | ||
| 2396 | #define R_NETWORK_GEN_CONFIG__phy__mii_err 2 | ||
| 2397 | #define R_NETWORK_GEN_CONFIG__phy__mii_req 3 | ||
| 2398 | #define R_NETWORK_GEN_CONFIG__enable__BITNR 0 | ||
| 2399 | #define R_NETWORK_GEN_CONFIG__enable__WIDTH 1 | ||
| 2400 | #define R_NETWORK_GEN_CONFIG__enable__on 1 | ||
| 2401 | #define R_NETWORK_GEN_CONFIG__enable__off 0 | ||
| 2402 | |||
| 2403 | #define R_NETWORK_TR_CTRL (IO_TYPECAST_UDWORD 0xb000009c) | ||
| 2404 | #define R_NETWORK_TR_CTRL__clr_error__BITNR 8 | ||
| 2405 | #define R_NETWORK_TR_CTRL__clr_error__WIDTH 1 | ||
| 2406 | #define R_NETWORK_TR_CTRL__clr_error__clr 1 | ||
| 2407 | #define R_NETWORK_TR_CTRL__clr_error__nop 0 | ||
| 2408 | #define R_NETWORK_TR_CTRL__delay__BITNR 5 | ||
| 2409 | #define R_NETWORK_TR_CTRL__delay__WIDTH 1 | ||
| 2410 | #define R_NETWORK_TR_CTRL__delay__d2us 1 | ||
| 2411 | #define R_NETWORK_TR_CTRL__delay__none 0 | ||
| 2412 | #define R_NETWORK_TR_CTRL__cancel__BITNR 4 | ||
| 2413 | #define R_NETWORK_TR_CTRL__cancel__WIDTH 1 | ||
| 2414 | #define R_NETWORK_TR_CTRL__cancel__do 1 | ||
| 2415 | #define R_NETWORK_TR_CTRL__cancel__dont 0 | ||
| 2416 | #define R_NETWORK_TR_CTRL__cd__BITNR 3 | ||
| 2417 | #define R_NETWORK_TR_CTRL__cd__WIDTH 1 | ||
| 2418 | #define R_NETWORK_TR_CTRL__cd__enable 0 | ||
| 2419 | #define R_NETWORK_TR_CTRL__cd__disable 1 | ||
| 2420 | #define R_NETWORK_TR_CTRL__cd__ack_col 0 | ||
| 2421 | #define R_NETWORK_TR_CTRL__cd__ack_crs 1 | ||
| 2422 | #define R_NETWORK_TR_CTRL__retry__BITNR 2 | ||
| 2423 | #define R_NETWORK_TR_CTRL__retry__WIDTH 1 | ||
| 2424 | #define R_NETWORK_TR_CTRL__retry__enable 0 | ||
| 2425 | #define R_NETWORK_TR_CTRL__retry__disable 1 | ||
| 2426 | #define R_NETWORK_TR_CTRL__pad__BITNR 1 | ||
| 2427 | #define R_NETWORK_TR_CTRL__pad__WIDTH 1 | ||
| 2428 | #define R_NETWORK_TR_CTRL__pad__enable 1 | ||
| 2429 | #define R_NETWORK_TR_CTRL__pad__disable 0 | ||
| 2430 | #define R_NETWORK_TR_CTRL__crc__BITNR 0 | ||
| 2431 | #define R_NETWORK_TR_CTRL__crc__WIDTH 1 | ||
| 2432 | #define R_NETWORK_TR_CTRL__crc__enable 0 | ||
| 2433 | #define R_NETWORK_TR_CTRL__crc__disable 1 | ||
| 2434 | |||
| 2435 | #define R_NETWORK_MGM_CTRL (IO_TYPECAST_UDWORD 0xb00000a0) | ||
| 2436 | #define R_NETWORK_MGM_CTRL__txd_pins__BITNR 4 | ||
| 2437 | #define R_NETWORK_MGM_CTRL__txd_pins__WIDTH 4 | ||
| 2438 | #define R_NETWORK_MGM_CTRL__txer_pin__BITNR 3 | ||
| 2439 | #define R_NETWORK_MGM_CTRL__txer_pin__WIDTH 1 | ||
| 2440 | #define R_NETWORK_MGM_CTRL__mdck__BITNR 2 | ||
| 2441 | #define R_NETWORK_MGM_CTRL__mdck__WIDTH 1 | ||
| 2442 | #define R_NETWORK_MGM_CTRL__mdoe__BITNR 1 | ||
| 2443 | #define R_NETWORK_MGM_CTRL__mdoe__WIDTH 1 | ||
| 2444 | #define R_NETWORK_MGM_CTRL__mdoe__enable 1 | ||
| 2445 | #define R_NETWORK_MGM_CTRL__mdoe__disable 0 | ||
| 2446 | #define R_NETWORK_MGM_CTRL__mdio__BITNR 0 | ||
| 2447 | #define R_NETWORK_MGM_CTRL__mdio__WIDTH 1 | ||
| 2448 | |||
| 2449 | #define R_NETWORK_STAT (IO_TYPECAST_RO_UDWORD 0xb00000a0) | ||
| 2450 | #define R_NETWORK_STAT__rxd_pins__BITNR 4 | ||
| 2451 | #define R_NETWORK_STAT__rxd_pins__WIDTH 4 | ||
| 2452 | #define R_NETWORK_STAT__rxer__BITNR 3 | ||
| 2453 | #define R_NETWORK_STAT__rxer__WIDTH 1 | ||
| 2454 | #define R_NETWORK_STAT__underrun__BITNR 2 | ||
| 2455 | #define R_NETWORK_STAT__underrun__WIDTH 1 | ||
| 2456 | #define R_NETWORK_STAT__underrun__yes 1 | ||
| 2457 | #define R_NETWORK_STAT__underrun__no 0 | ||
| 2458 | #define R_NETWORK_STAT__exc_col__BITNR 1 | ||
| 2459 | #define R_NETWORK_STAT__exc_col__WIDTH 1 | ||
| 2460 | #define R_NETWORK_STAT__exc_col__yes 1 | ||
| 2461 | #define R_NETWORK_STAT__exc_col__no 0 | ||
| 2462 | #define R_NETWORK_STAT__mdio__BITNR 0 | ||
| 2463 | #define R_NETWORK_STAT__mdio__WIDTH 1 | ||
| 2464 | |||
| 2465 | #define R_REC_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a4) | ||
| 2466 | #define R_REC_COUNTERS__congestion__BITNR 24 | ||
| 2467 | #define R_REC_COUNTERS__congestion__WIDTH 8 | ||
| 2468 | #define R_REC_COUNTERS__oversize__BITNR 16 | ||
| 2469 | #define R_REC_COUNTERS__oversize__WIDTH 8 | ||
| 2470 | #define R_REC_COUNTERS__alignment_error__BITNR 8 | ||
| 2471 | #define R_REC_COUNTERS__alignment_error__WIDTH 8 | ||
| 2472 | #define R_REC_COUNTERS__crc_error__BITNR 0 | ||
| 2473 | #define R_REC_COUNTERS__crc_error__WIDTH 8 | ||
| 2474 | |||
| 2475 | #define R_TR_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a8) | ||
| 2476 | #define R_TR_COUNTERS__deferred__BITNR 24 | ||
| 2477 | #define R_TR_COUNTERS__deferred__WIDTH 8 | ||
| 2478 | #define R_TR_COUNTERS__late_col__BITNR 16 | ||
| 2479 | #define R_TR_COUNTERS__late_col__WIDTH 8 | ||
| 2480 | #define R_TR_COUNTERS__multiple_col__BITNR 8 | ||
| 2481 | #define R_TR_COUNTERS__multiple_col__WIDTH 8 | ||
| 2482 | #define R_TR_COUNTERS__single_col__BITNR 0 | ||
| 2483 | #define R_TR_COUNTERS__single_col__WIDTH 8 | ||
| 2484 | |||
| 2485 | #define R_PHY_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000ac) | ||
| 2486 | #define R_PHY_COUNTERS__sqe_test_error__BITNR 8 | ||
| 2487 | #define R_PHY_COUNTERS__sqe_test_error__WIDTH 8 | ||
| 2488 | #define R_PHY_COUNTERS__carrier_loss__BITNR 0 | ||
| 2489 | #define R_PHY_COUNTERS__carrier_loss__WIDTH 8 | ||
| 2490 | |||
| 2491 | /* | ||
| 2492 | !* Parallel printer port registers | ||
| 2493 | !*/ | ||
| 2494 | |||
| 2495 | #define R_PAR0_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040) | ||
| 2496 | #define R_PAR0_CTRL_DATA__peri_int__BITNR 24 | ||
| 2497 | #define R_PAR0_CTRL_DATA__peri_int__WIDTH 1 | ||
| 2498 | #define R_PAR0_CTRL_DATA__peri_int__ack 1 | ||
| 2499 | #define R_PAR0_CTRL_DATA__peri_int__nop 0 | ||
| 2500 | #define R_PAR0_CTRL_DATA__oe__BITNR 20 | ||
| 2501 | #define R_PAR0_CTRL_DATA__oe__WIDTH 1 | ||
| 2502 | #define R_PAR0_CTRL_DATA__oe__enable 1 | ||
| 2503 | #define R_PAR0_CTRL_DATA__oe__disable 0 | ||
| 2504 | #define R_PAR0_CTRL_DATA__seli__BITNR 19 | ||
| 2505 | #define R_PAR0_CTRL_DATA__seli__WIDTH 1 | ||
| 2506 | #define R_PAR0_CTRL_DATA__seli__active 1 | ||
| 2507 | #define R_PAR0_CTRL_DATA__seli__inactive 0 | ||
| 2508 | #define R_PAR0_CTRL_DATA__autofd__BITNR 18 | ||
| 2509 | #define R_PAR0_CTRL_DATA__autofd__WIDTH 1 | ||
| 2510 | #define R_PAR0_CTRL_DATA__autofd__active 1 | ||
| 2511 | #define R_PAR0_CTRL_DATA__autofd__inactive 0 | ||
| 2512 | #define R_PAR0_CTRL_DATA__strb__BITNR 17 | ||
| 2513 | #define R_PAR0_CTRL_DATA__strb__WIDTH 1 | ||
| 2514 | #define R_PAR0_CTRL_DATA__strb__active 1 | ||
| 2515 | #define R_PAR0_CTRL_DATA__strb__inactive 0 | ||
| 2516 | #define R_PAR0_CTRL_DATA__init__BITNR 16 | ||
| 2517 | #define R_PAR0_CTRL_DATA__init__WIDTH 1 | ||
| 2518 | #define R_PAR0_CTRL_DATA__init__active 1 | ||
| 2519 | #define R_PAR0_CTRL_DATA__init__inactive 0 | ||
| 2520 | #define R_PAR0_CTRL_DATA__ecp_cmd__BITNR 8 | ||
| 2521 | #define R_PAR0_CTRL_DATA__ecp_cmd__WIDTH 1 | ||
| 2522 | #define R_PAR0_CTRL_DATA__ecp_cmd__command 1 | ||
| 2523 | #define R_PAR0_CTRL_DATA__ecp_cmd__data 0 | ||
| 2524 | #define R_PAR0_CTRL_DATA__data__BITNR 0 | ||
| 2525 | #define R_PAR0_CTRL_DATA__data__WIDTH 8 | ||
| 2526 | |||
| 2527 | #define R_PAR0_CTRL (IO_TYPECAST_BYTE 0xb0000042) | ||
| 2528 | #define R_PAR0_CTRL__ctrl__BITNR 0 | ||
| 2529 | #define R_PAR0_CTRL__ctrl__WIDTH 5 | ||
| 2530 | |||
| 2531 | #define R_PAR0_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040) | ||
| 2532 | #define R_PAR0_STATUS_DATA__mode__BITNR 29 | ||
| 2533 | #define R_PAR0_STATUS_DATA__mode__WIDTH 3 | ||
| 2534 | #define R_PAR0_STATUS_DATA__mode__manual 0 | ||
| 2535 | #define R_PAR0_STATUS_DATA__mode__centronics 1 | ||
| 2536 | #define R_PAR0_STATUS_DATA__mode__fastbyte 2 | ||
| 2537 | #define R_PAR0_STATUS_DATA__mode__nibble 3 | ||
| 2538 | #define R_PAR0_STATUS_DATA__mode__byte 4 | ||
| 2539 | #define R_PAR0_STATUS_DATA__mode__ecp_fwd 5 | ||
| 2540 | #define R_PAR0_STATUS_DATA__mode__ecp_rev 6 | ||
| 2541 | #define R_PAR0_STATUS_DATA__mode__off 7 | ||
| 2542 | #define R_PAR0_STATUS_DATA__mode__epp_wr1 5 | ||
| 2543 | #define R_PAR0_STATUS_DATA__mode__epp_wr2 6 | ||
| 2544 | #define R_PAR0_STATUS_DATA__mode__epp_wr3 7 | ||
| 2545 | #define R_PAR0_STATUS_DATA__mode__epp_rd 0 | ||
| 2546 | #define R_PAR0_STATUS_DATA__perr__BITNR 28 | ||
| 2547 | #define R_PAR0_STATUS_DATA__perr__WIDTH 1 | ||
| 2548 | #define R_PAR0_STATUS_DATA__perr__active 1 | ||
| 2549 | #define R_PAR0_STATUS_DATA__perr__inactive 0 | ||
| 2550 | #define R_PAR0_STATUS_DATA__ack__BITNR 27 | ||
| 2551 | #define R_PAR0_STATUS_DATA__ack__WIDTH 1 | ||
| 2552 | #define R_PAR0_STATUS_DATA__ack__active 0 | ||
| 2553 | #define R_PAR0_STATUS_DATA__ack__inactive 1 | ||
| 2554 | #define R_PAR0_STATUS_DATA__busy__BITNR 26 | ||
| 2555 | #define R_PAR0_STATUS_DATA__busy__WIDTH 1 | ||
| 2556 | #define R_PAR0_STATUS_DATA__busy__active 1 | ||
| 2557 | #define R_PAR0_STATUS_DATA__busy__inactive 0 | ||
| 2558 | #define R_PAR0_STATUS_DATA__fault__BITNR 25 | ||
| 2559 | #define R_PAR0_STATUS_DATA__fault__WIDTH 1 | ||
| 2560 | #define R_PAR0_STATUS_DATA__fault__active 0 | ||
| 2561 | #define R_PAR0_STATUS_DATA__fault__inactive 1 | ||
| 2562 | #define R_PAR0_STATUS_DATA__sel__BITNR 24 | ||
| 2563 | #define R_PAR0_STATUS_DATA__sel__WIDTH 1 | ||
| 2564 | #define R_PAR0_STATUS_DATA__sel__active 1 | ||
| 2565 | #define R_PAR0_STATUS_DATA__sel__inactive 0 | ||
| 2566 | #define R_PAR0_STATUS_DATA__ext_mode__BITNR 23 | ||
| 2567 | #define R_PAR0_STATUS_DATA__ext_mode__WIDTH 1 | ||
| 2568 | #define R_PAR0_STATUS_DATA__ext_mode__enable 1 | ||
| 2569 | #define R_PAR0_STATUS_DATA__ext_mode__disable 0 | ||
| 2570 | #define R_PAR0_STATUS_DATA__ecp_16__BITNR 22 | ||
| 2571 | #define R_PAR0_STATUS_DATA__ecp_16__WIDTH 1 | ||
| 2572 | #define R_PAR0_STATUS_DATA__ecp_16__active 1 | ||
| 2573 | #define R_PAR0_STATUS_DATA__ecp_16__inactive 0 | ||
| 2574 | #define R_PAR0_STATUS_DATA__tr_rdy__BITNR 17 | ||
| 2575 | #define R_PAR0_STATUS_DATA__tr_rdy__WIDTH 1 | ||
| 2576 | #define R_PAR0_STATUS_DATA__tr_rdy__ready 1 | ||
| 2577 | #define R_PAR0_STATUS_DATA__tr_rdy__busy 0 | ||
| 2578 | #define R_PAR0_STATUS_DATA__dav__BITNR 16 | ||
| 2579 | #define R_PAR0_STATUS_DATA__dav__WIDTH 1 | ||
| 2580 | #define R_PAR0_STATUS_DATA__dav__data 1 | ||
| 2581 | #define R_PAR0_STATUS_DATA__dav__nodata 0 | ||
| 2582 | #define R_PAR0_STATUS_DATA__ecp_cmd__BITNR 8 | ||
| 2583 | #define R_PAR0_STATUS_DATA__ecp_cmd__WIDTH 1 | ||
| 2584 | #define R_PAR0_STATUS_DATA__ecp_cmd__command 1 | ||
| 2585 | #define R_PAR0_STATUS_DATA__ecp_cmd__data 0 | ||
| 2586 | #define R_PAR0_STATUS_DATA__data__BITNR 0 | ||
| 2587 | #define R_PAR0_STATUS_DATA__data__WIDTH 8 | ||
| 2588 | |||
| 2589 | #define R_PAR0_STATUS (IO_TYPECAST_RO_UWORD 0xb0000042) | ||
| 2590 | #define R_PAR0_STATUS__mode__BITNR 13 | ||
| 2591 | #define R_PAR0_STATUS__mode__WIDTH 3 | ||
| 2592 | #define R_PAR0_STATUS__mode__manual 0 | ||
| 2593 | #define R_PAR0_STATUS__mode__centronics 1 | ||
| 2594 | #define R_PAR0_STATUS__mode__fastbyte 2 | ||
| 2595 | #define R_PAR0_STATUS__mode__nibble 3 | ||
| 2596 | #define R_PAR0_STATUS__mode__byte 4 | ||
| 2597 | #define R_PAR0_STATUS__mode__ecp_fwd 5 | ||
| 2598 | #define R_PAR0_STATUS__mode__ecp_rev 6 | ||
| 2599 | #define R_PAR0_STATUS__mode__off 7 | ||
| 2600 | #define R_PAR0_STATUS__mode__epp_wr1 5 | ||
| 2601 | #define R_PAR0_STATUS__mode__epp_wr2 6 | ||
| 2602 | #define R_PAR0_STATUS__mode__epp_wr3 7 | ||
| 2603 | #define R_PAR0_STATUS__mode__epp_rd 0 | ||
| 2604 | #define R_PAR0_STATUS__perr__BITNR 12 | ||
| 2605 | #define R_PAR0_STATUS__perr__WIDTH 1 | ||
| 2606 | #define R_PAR0_STATUS__perr__active 1 | ||
| 2607 | #define R_PAR0_STATUS__perr__inactive 0 | ||
| 2608 | #define R_PAR0_STATUS__ack__BITNR 11 | ||
| 2609 | #define R_PAR0_STATUS__ack__WIDTH 1 | ||
| 2610 | #define R_PAR0_STATUS__ack__active 0 | ||
| 2611 | #define R_PAR0_STATUS__ack__inactive 1 | ||
| 2612 | #define R_PAR0_STATUS__busy__BITNR 10 | ||
| 2613 | #define R_PAR0_STATUS__busy__WIDTH 1 | ||
| 2614 | #define R_PAR0_STATUS__busy__active 1 | ||
| 2615 | #define R_PAR0_STATUS__busy__inactive 0 | ||
| 2616 | #define R_PAR0_STATUS__fault__BITNR 9 | ||
| 2617 | #define R_PAR0_STATUS__fault__WIDTH 1 | ||
| 2618 | #define R_PAR0_STATUS__fault__active 0 | ||
| 2619 | #define R_PAR0_STATUS__fault__inactive 1 | ||
| 2620 | #define R_PAR0_STATUS__sel__BITNR 8 | ||
| 2621 | #define R_PAR0_STATUS__sel__WIDTH 1 | ||
| 2622 | #define R_PAR0_STATUS__sel__active 1 | ||
| 2623 | #define R_PAR0_STATUS__sel__inactive 0 | ||
| 2624 | #define R_PAR0_STATUS__ext_mode__BITNR 7 | ||
| 2625 | #define R_PAR0_STATUS__ext_mode__WIDTH 1 | ||
| 2626 | #define R_PAR0_STATUS__ext_mode__enable 1 | ||
| 2627 | #define R_PAR0_STATUS__ext_mode__disable 0 | ||
| 2628 | #define R_PAR0_STATUS__ecp_16__BITNR 6 | ||
| 2629 | #define R_PAR0_STATUS__ecp_16__WIDTH 1 | ||
| 2630 | #define R_PAR0_STATUS__ecp_16__active 1 | ||
| 2631 | #define R_PAR0_STATUS__ecp_16__inactive 0 | ||
| 2632 | #define R_PAR0_STATUS__tr_rdy__BITNR 1 | ||
| 2633 | #define R_PAR0_STATUS__tr_rdy__WIDTH 1 | ||
| 2634 | #define R_PAR0_STATUS__tr_rdy__ready 1 | ||
| 2635 | #define R_PAR0_STATUS__tr_rdy__busy 0 | ||
| 2636 | #define R_PAR0_STATUS__dav__BITNR 0 | ||
| 2637 | #define R_PAR0_STATUS__dav__WIDTH 1 | ||
| 2638 | #define R_PAR0_STATUS__dav__data 1 | ||
| 2639 | #define R_PAR0_STATUS__dav__nodata 0 | ||
| 2640 | |||
| 2641 | #define R_PAR_ECP16_DATA (IO_TYPECAST_UWORD 0xb0000040) | ||
| 2642 | #define R_PAR_ECP16_DATA__data__BITNR 0 | ||
| 2643 | #define R_PAR_ECP16_DATA__data__WIDTH 16 | ||
| 2644 | |||
| 2645 | #define R_PAR0_CONFIG (IO_TYPECAST_UDWORD 0xb0000044) | ||
| 2646 | #define R_PAR0_CONFIG__ioe__BITNR 25 | ||
| 2647 | #define R_PAR0_CONFIG__ioe__WIDTH 1 | ||
| 2648 | #define R_PAR0_CONFIG__ioe__inv 1 | ||
| 2649 | #define R_PAR0_CONFIG__ioe__noninv 0 | ||
| 2650 | #define R_PAR0_CONFIG__iseli__BITNR 24 | ||
| 2651 | #define R_PAR0_CONFIG__iseli__WIDTH 1 | ||
| 2652 | #define R_PAR0_CONFIG__iseli__inv 1 | ||
| 2653 | #define R_PAR0_CONFIG__iseli__noninv 0 | ||
| 2654 | #define R_PAR0_CONFIG__iautofd__BITNR 23 | ||
| 2655 | #define R_PAR0_CONFIG__iautofd__WIDTH 1 | ||
| 2656 | #define R_PAR0_CONFIG__iautofd__inv 1 | ||
| 2657 | #define R_PAR0_CONFIG__iautofd__noninv 0 | ||
| 2658 | #define R_PAR0_CONFIG__istrb__BITNR 22 | ||
| 2659 | #define R_PAR0_CONFIG__istrb__WIDTH 1 | ||
| 2660 | #define R_PAR0_CONFIG__istrb__inv 1 | ||
| 2661 | #define R_PAR0_CONFIG__istrb__noninv 0 | ||
| 2662 | #define R_PAR0_CONFIG__iinit__BITNR 21 | ||
| 2663 | #define R_PAR0_CONFIG__iinit__WIDTH 1 | ||
| 2664 | #define R_PAR0_CONFIG__iinit__inv 1 | ||
| 2665 | #define R_PAR0_CONFIG__iinit__noninv 0 | ||
| 2666 | #define R_PAR0_CONFIG__iperr__BITNR 20 | ||
| 2667 | #define R_PAR0_CONFIG__iperr__WIDTH 1 | ||
| 2668 | #define R_PAR0_CONFIG__iperr__inv 1 | ||
| 2669 | #define R_PAR0_CONFIG__iperr__noninv 0 | ||
| 2670 | #define R_PAR0_CONFIG__iack__BITNR 19 | ||
| 2671 | #define R_PAR0_CONFIG__iack__WIDTH 1 | ||
| 2672 | #define R_PAR0_CONFIG__iack__inv 1 | ||
| 2673 | #define R_PAR0_CONFIG__iack__noninv 0 | ||
| 2674 | #define R_PAR0_CONFIG__ibusy__BITNR 18 | ||
| 2675 | #define R_PAR0_CONFIG__ibusy__WIDTH 1 | ||
| 2676 | #define R_PAR0_CONFIG__ibusy__inv 1 | ||
| 2677 | #define R_PAR0_CONFIG__ibusy__noninv 0 | ||
| 2678 | #define R_PAR0_CONFIG__ifault__BITNR 17 | ||
| 2679 | #define R_PAR0_CONFIG__ifault__WIDTH 1 | ||
| 2680 | #define R_PAR0_CONFIG__ifault__inv 1 | ||
| 2681 | #define R_PAR0_CONFIG__ifault__noninv 0 | ||
| 2682 | #define R_PAR0_CONFIG__isel__BITNR 16 | ||
| 2683 | #define R_PAR0_CONFIG__isel__WIDTH 1 | ||
| 2684 | #define R_PAR0_CONFIG__isel__inv 1 | ||
| 2685 | #define R_PAR0_CONFIG__isel__noninv 0 | ||
| 2686 | #define R_PAR0_CONFIG__ext_mode__BITNR 11 | ||
| 2687 | #define R_PAR0_CONFIG__ext_mode__WIDTH 1 | ||
| 2688 | #define R_PAR0_CONFIG__ext_mode__enable 1 | ||
| 2689 | #define R_PAR0_CONFIG__ext_mode__disable 0 | ||
| 2690 | #define R_PAR0_CONFIG__wide__BITNR 10 | ||
| 2691 | #define R_PAR0_CONFIG__wide__WIDTH 1 | ||
| 2692 | #define R_PAR0_CONFIG__wide__enable 1 | ||
| 2693 | #define R_PAR0_CONFIG__wide__disable 0 | ||
| 2694 | #define R_PAR0_CONFIG__dma__BITNR 9 | ||
| 2695 | #define R_PAR0_CONFIG__dma__WIDTH 1 | ||
| 2696 | #define R_PAR0_CONFIG__dma__enable 1 | ||
| 2697 | #define R_PAR0_CONFIG__dma__disable 0 | ||
| 2698 | #define R_PAR0_CONFIG__rle_in__BITNR 8 | ||
| 2699 | #define R_PAR0_CONFIG__rle_in__WIDTH 1 | ||
| 2700 | #define R_PAR0_CONFIG__rle_in__enable 1 | ||
| 2701 | #define R_PAR0_CONFIG__rle_in__disable 0 | ||
| 2702 | #define R_PAR0_CONFIG__rle_out__BITNR 7 | ||
| 2703 | #define R_PAR0_CONFIG__rle_out__WIDTH 1 | ||
| 2704 | #define R_PAR0_CONFIG__rle_out__enable 1 | ||
| 2705 | #define R_PAR0_CONFIG__rle_out__disable 0 | ||
| 2706 | #define R_PAR0_CONFIG__enable__BITNR 6 | ||
| 2707 | #define R_PAR0_CONFIG__enable__WIDTH 1 | ||
| 2708 | #define R_PAR0_CONFIG__enable__on 1 | ||
| 2709 | #define R_PAR0_CONFIG__enable__reset 0 | ||
| 2710 | #define R_PAR0_CONFIG__force__BITNR 5 | ||
| 2711 | #define R_PAR0_CONFIG__force__WIDTH 1 | ||
| 2712 | #define R_PAR0_CONFIG__force__on 1 | ||
| 2713 | #define R_PAR0_CONFIG__force__off 0 | ||
| 2714 | #define R_PAR0_CONFIG__ign_ack__BITNR 4 | ||
| 2715 | #define R_PAR0_CONFIG__ign_ack__WIDTH 1 | ||
| 2716 | #define R_PAR0_CONFIG__ign_ack__ignore 1 | ||
| 2717 | #define R_PAR0_CONFIG__ign_ack__wait 0 | ||
| 2718 | #define R_PAR0_CONFIG__oe_ack__BITNR 3 | ||
| 2719 | #define R_PAR0_CONFIG__oe_ack__WIDTH 1 | ||
| 2720 | #define R_PAR0_CONFIG__oe_ack__wait_oe 1 | ||
| 2721 | #define R_PAR0_CONFIG__oe_ack__dont_wait 0 | ||
| 2722 | #define R_PAR0_CONFIG__oe_ack__epp_addr 1 | ||
| 2723 | #define R_PAR0_CONFIG__oe_ack__epp_data 0 | ||
| 2724 | #define R_PAR0_CONFIG__epp_addr_data__BITNR 3 | ||
| 2725 | #define R_PAR0_CONFIG__epp_addr_data__WIDTH 1 | ||
| 2726 | #define R_PAR0_CONFIG__epp_addr_data__wait_oe 1 | ||
| 2727 | #define R_PAR0_CONFIG__epp_addr_data__dont_wait 0 | ||
| 2728 | #define R_PAR0_CONFIG__epp_addr_data__epp_addr 1 | ||
| 2729 | #define R_PAR0_CONFIG__epp_addr_data__epp_data 0 | ||
| 2730 | #define R_PAR0_CONFIG__mode__BITNR 0 | ||
| 2731 | #define R_PAR0_CONFIG__mode__WIDTH 3 | ||
| 2732 | #define R_PAR0_CONFIG__mode__manual 0 | ||
| 2733 | #define R_PAR0_CONFIG__mode__centronics 1 | ||
| 2734 | #define R_PAR0_CONFIG__mode__fastbyte 2 | ||
| 2735 | #define R_PAR0_CONFIG__mode__nibble 3 | ||
| 2736 | #define R_PAR0_CONFIG__mode__byte 4 | ||
| 2737 | #define R_PAR0_CONFIG__mode__ecp_fwd 5 | ||
| 2738 | #define R_PAR0_CONFIG__mode__ecp_rev 6 | ||
| 2739 | #define R_PAR0_CONFIG__mode__off 7 | ||
| 2740 | #define R_PAR0_CONFIG__mode__epp_wr1 5 | ||
| 2741 | #define R_PAR0_CONFIG__mode__epp_wr2 6 | ||
| 2742 | #define R_PAR0_CONFIG__mode__epp_wr3 7 | ||
| 2743 | #define R_PAR0_CONFIG__mode__epp_rd 0 | ||
| 2744 | |||
| 2745 | #define R_PAR0_DELAY (IO_TYPECAST_UDWORD 0xb0000048) | ||
| 2746 | #define R_PAR0_DELAY__fine_hold__BITNR 21 | ||
| 2747 | #define R_PAR0_DELAY__fine_hold__WIDTH 3 | ||
| 2748 | #define R_PAR0_DELAY__hold__BITNR 16 | ||
| 2749 | #define R_PAR0_DELAY__hold__WIDTH 5 | ||
| 2750 | #define R_PAR0_DELAY__fine_strb__BITNR 13 | ||
| 2751 | #define R_PAR0_DELAY__fine_strb__WIDTH 3 | ||
| 2752 | #define R_PAR0_DELAY__strobe__BITNR 8 | ||
| 2753 | #define R_PAR0_DELAY__strobe__WIDTH 5 | ||
| 2754 | #define R_PAR0_DELAY__fine_setup__BITNR 5 | ||
| 2755 | #define R_PAR0_DELAY__fine_setup__WIDTH 3 | ||
| 2756 | #define R_PAR0_DELAY__setup__BITNR 0 | ||
| 2757 | #define R_PAR0_DELAY__setup__WIDTH 5 | ||
| 2758 | |||
| 2759 | #define R_PAR1_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000050) | ||
| 2760 | #define R_PAR1_CTRL_DATA__peri_int__BITNR 24 | ||
| 2761 | #define R_PAR1_CTRL_DATA__peri_int__WIDTH 1 | ||
| 2762 | #define R_PAR1_CTRL_DATA__peri_int__ack 1 | ||
| 2763 | #define R_PAR1_CTRL_DATA__peri_int__nop 0 | ||
| 2764 | #define R_PAR1_CTRL_DATA__oe__BITNR 20 | ||
| 2765 | #define R_PAR1_CTRL_DATA__oe__WIDTH 1 | ||
| 2766 | #define R_PAR1_CTRL_DATA__oe__enable 1 | ||
| 2767 | #define R_PAR1_CTRL_DATA__oe__disable 0 | ||
| 2768 | #define R_PAR1_CTRL_DATA__seli__BITNR 19 | ||
| 2769 | #define R_PAR1_CTRL_DATA__seli__WIDTH 1 | ||
| 2770 | #define R_PAR1_CTRL_DATA__seli__active 1 | ||
| 2771 | #define R_PAR1_CTRL_DATA__seli__inactive 0 | ||
| 2772 | #define R_PAR1_CTRL_DATA__autofd__BITNR 18 | ||
| 2773 | #define R_PAR1_CTRL_DATA__autofd__WIDTH 1 | ||
| 2774 | #define R_PAR1_CTRL_DATA__autofd__active 1 | ||
| 2775 | #define R_PAR1_CTRL_DATA__autofd__inactive 0 | ||
| 2776 | #define R_PAR1_CTRL_DATA__strb__BITNR 17 | ||
| 2777 | #define R_PAR1_CTRL_DATA__strb__WIDTH 1 | ||
| 2778 | #define R_PAR1_CTRL_DATA__strb__active 1 | ||
| 2779 | #define R_PAR1_CTRL_DATA__strb__inactive 0 | ||
| 2780 | #define R_PAR1_CTRL_DATA__init__BITNR 16 | ||
| 2781 | #define R_PAR1_CTRL_DATA__init__WIDTH 1 | ||
| 2782 | #define R_PAR1_CTRL_DATA__init__active 1 | ||
| 2783 | #define R_PAR1_CTRL_DATA__init__inactive 0 | ||
| 2784 | #define R_PAR1_CTRL_DATA__ecp_cmd__BITNR 8 | ||
| 2785 | #define R_PAR1_CTRL_DATA__ecp_cmd__WIDTH 1 | ||
| 2786 | #define R_PAR1_CTRL_DATA__ecp_cmd__command 1 | ||
| 2787 | #define R_PAR1_CTRL_DATA__ecp_cmd__data 0 | ||
| 2788 | #define R_PAR1_CTRL_DATA__data__BITNR 0 | ||
| 2789 | #define R_PAR1_CTRL_DATA__data__WIDTH 8 | ||
| 2790 | |||
| 2791 | #define R_PAR1_CTRL (IO_TYPECAST_BYTE 0xb0000052) | ||
| 2792 | #define R_PAR1_CTRL__ctrl__BITNR 0 | ||
| 2793 | #define R_PAR1_CTRL__ctrl__WIDTH 5 | ||
| 2794 | |||
| 2795 | #define R_PAR1_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000050) | ||
| 2796 | #define R_PAR1_STATUS_DATA__mode__BITNR 29 | ||
| 2797 | #define R_PAR1_STATUS_DATA__mode__WIDTH 3 | ||
| 2798 | #define R_PAR1_STATUS_DATA__mode__manual 0 | ||
| 2799 | #define R_PAR1_STATUS_DATA__mode__centronics 1 | ||
| 2800 | #define R_PAR1_STATUS_DATA__mode__fastbyte 2 | ||
| 2801 | #define R_PAR1_STATUS_DATA__mode__nibble 3 | ||
| 2802 | #define R_PAR1_STATUS_DATA__mode__byte 4 | ||
| 2803 | #define R_PAR1_STATUS_DATA__mode__ecp_fwd 5 | ||
| 2804 | #define R_PAR1_STATUS_DATA__mode__ecp_rev 6 | ||
| 2805 | #define R_PAR1_STATUS_DATA__mode__off 7 | ||
| 2806 | #define R_PAR1_STATUS_DATA__mode__epp_wr1 5 | ||
| 2807 | #define R_PAR1_STATUS_DATA__mode__epp_wr2 6 | ||
| 2808 | #define R_PAR1_STATUS_DATA__mode__epp_wr3 7 | ||
| 2809 | #define R_PAR1_STATUS_DATA__mode__epp_rd 0 | ||
| 2810 | #define R_PAR1_STATUS_DATA__perr__BITNR 28 | ||
| 2811 | #define R_PAR1_STATUS_DATA__perr__WIDTH 1 | ||
| 2812 | #define R_PAR1_STATUS_DATA__perr__active 1 | ||
| 2813 | #define R_PAR1_STATUS_DATA__perr__inactive 0 | ||
| 2814 | #define R_PAR1_STATUS_DATA__ack__BITNR 27 | ||
| 2815 | #define R_PAR1_STATUS_DATA__ack__WIDTH 1 | ||
| 2816 | #define R_PAR1_STATUS_DATA__ack__active 0 | ||
| 2817 | #define R_PAR1_STATUS_DATA__ack__inactive 1 | ||
| 2818 | #define R_PAR1_STATUS_DATA__busy__BITNR 26 | ||
| 2819 | #define R_PAR1_STATUS_DATA__busy__WIDTH 1 | ||
| 2820 | #define R_PAR1_STATUS_DATA__busy__active 1 | ||
| 2821 | #define R_PAR1_STATUS_DATA__busy__inactive 0 | ||
| 2822 | #define R_PAR1_STATUS_DATA__fault__BITNR 25 | ||
| 2823 | #define R_PAR1_STATUS_DATA__fault__WIDTH 1 | ||
| 2824 | #define R_PAR1_STATUS_DATA__fault__active 0 | ||
| 2825 | #define R_PAR1_STATUS_DATA__fault__inactive 1 | ||
| 2826 | #define R_PAR1_STATUS_DATA__sel__BITNR 24 | ||
| 2827 | #define R_PAR1_STATUS_DATA__sel__WIDTH 1 | ||
| 2828 | #define R_PAR1_STATUS_DATA__sel__active 1 | ||
| 2829 | #define R_PAR1_STATUS_DATA__sel__inactive 0 | ||
| 2830 | #define R_PAR1_STATUS_DATA__ext_mode__BITNR 23 | ||
| 2831 | #define R_PAR1_STATUS_DATA__ext_mode__WIDTH 1 | ||
| 2832 | #define R_PAR1_STATUS_DATA__ext_mode__enable 1 | ||
| 2833 | #define R_PAR1_STATUS_DATA__ext_mode__disable 0 | ||
| 2834 | #define R_PAR1_STATUS_DATA__tr_rdy__BITNR 17 | ||
| 2835 | #define R_PAR1_STATUS_DATA__tr_rdy__WIDTH 1 | ||
| 2836 | #define R_PAR1_STATUS_DATA__tr_rdy__ready 1 | ||
| 2837 | #define R_PAR1_STATUS_DATA__tr_rdy__busy 0 | ||
| 2838 | #define R_PAR1_STATUS_DATA__dav__BITNR 16 | ||
| 2839 | #define R_PAR1_STATUS_DATA__dav__WIDTH 1 | ||
| 2840 | #define R_PAR1_STATUS_DATA__dav__data 1 | ||
| 2841 | #define R_PAR1_STATUS_DATA__dav__nodata 0 | ||
| 2842 | #define R_PAR1_STATUS_DATA__ecp_cmd__BITNR 8 | ||
| 2843 | #define R_PAR1_STATUS_DATA__ecp_cmd__WIDTH 1 | ||
| 2844 | #define R_PAR1_STATUS_DATA__ecp_cmd__command 1 | ||
| 2845 | #define R_PAR1_STATUS_DATA__ecp_cmd__data 0 | ||
| 2846 | #define R_PAR1_STATUS_DATA__data__BITNR 0 | ||
| 2847 | #define R_PAR1_STATUS_DATA__data__WIDTH 8 | ||
| 2848 | |||
| 2849 | #define R_PAR1_STATUS (IO_TYPECAST_RO_UWORD 0xb0000052) | ||
| 2850 | #define R_PAR1_STATUS__mode__BITNR 13 | ||
| 2851 | #define R_PAR1_STATUS__mode__WIDTH 3 | ||
| 2852 | #define R_PAR1_STATUS__mode__manual 0 | ||
| 2853 | #define R_PAR1_STATUS__mode__centronics 1 | ||
| 2854 | #define R_PAR1_STATUS__mode__fastbyte 2 | ||
| 2855 | #define R_PAR1_STATUS__mode__nibble 3 | ||
| 2856 | #define R_PAR1_STATUS__mode__byte 4 | ||
| 2857 | #define R_PAR1_STATUS__mode__ecp_fwd 5 | ||
| 2858 | #define R_PAR1_STATUS__mode__ecp_rev 6 | ||
| 2859 | #define R_PAR1_STATUS__mode__off 7 | ||
| 2860 | #define R_PAR1_STATUS__mode__epp_wr1 5 | ||
| 2861 | #define R_PAR1_STATUS__mode__epp_wr2 6 | ||
| 2862 | #define R_PAR1_STATUS__mode__epp_wr3 7 | ||
| 2863 | #define R_PAR1_STATUS__mode__epp_rd 0 | ||
| 2864 | #define R_PAR1_STATUS__perr__BITNR 12 | ||
| 2865 | #define R_PAR1_STATUS__perr__WIDTH 1 | ||
| 2866 | #define R_PAR1_STATUS__perr__active 1 | ||
| 2867 | #define R_PAR1_STATUS__perr__inactive 0 | ||
| 2868 | #define R_PAR1_STATUS__ack__BITNR 11 | ||
| 2869 | #define R_PAR1_STATUS__ack__WIDTH 1 | ||
| 2870 | #define R_PAR1_STATUS__ack__active 0 | ||
| 2871 | #define R_PAR1_STATUS__ack__inactive 1 | ||
| 2872 | #define R_PAR1_STATUS__busy__BITNR 10 | ||
| 2873 | #define R_PAR1_STATUS__busy__WIDTH 1 | ||
| 2874 | #define R_PAR1_STATUS__busy__active 1 | ||
| 2875 | #define R_PAR1_STATUS__busy__inactive 0 | ||
| 2876 | #define R_PAR1_STATUS__fault__BITNR 9 | ||
| 2877 | #define R_PAR1_STATUS__fault__WIDTH 1 | ||
| 2878 | #define R_PAR1_STATUS__fault__active 0 | ||
| 2879 | #define R_PAR1_STATUS__fault__inactive 1 | ||
| 2880 | #define R_PAR1_STATUS__sel__BITNR 8 | ||
| 2881 | #define R_PAR1_STATUS__sel__WIDTH 1 | ||
| 2882 | #define R_PAR1_STATUS__sel__active 1 | ||
| 2883 | #define R_PAR1_STATUS__sel__inactive 0 | ||
| 2884 | #define R_PAR1_STATUS__ext_mode__BITNR 7 | ||
| 2885 | #define R_PAR1_STATUS__ext_mode__WIDTH 1 | ||
| 2886 | #define R_PAR1_STATUS__ext_mode__enable 1 | ||
| 2887 | #define R_PAR1_STATUS__ext_mode__disable 0 | ||
| 2888 | #define R_PAR1_STATUS__tr_rdy__BITNR 1 | ||
| 2889 | #define R_PAR1_STATUS__tr_rdy__WIDTH 1 | ||
| 2890 | #define R_PAR1_STATUS__tr_rdy__ready 1 | ||
| 2891 | #define R_PAR1_STATUS__tr_rdy__busy 0 | ||
| 2892 | #define R_PAR1_STATUS__dav__BITNR 0 | ||
| 2893 | #define R_PAR1_STATUS__dav__WIDTH 1 | ||
| 2894 | #define R_PAR1_STATUS__dav__data 1 | ||
| 2895 | #define R_PAR1_STATUS__dav__nodata 0 | ||
| 2896 | |||
| 2897 | #define R_PAR1_CONFIG (IO_TYPECAST_UDWORD 0xb0000054) | ||
| 2898 | #define R_PAR1_CONFIG__ioe__BITNR 25 | ||
| 2899 | #define R_PAR1_CONFIG__ioe__WIDTH 1 | ||
| 2900 | #define R_PAR1_CONFIG__ioe__inv 1 | ||
| 2901 | #define R_PAR1_CONFIG__ioe__noninv 0 | ||
| 2902 | #define R_PAR1_CONFIG__iseli__BITNR 24 | ||
| 2903 | #define R_PAR1_CONFIG__iseli__WIDTH 1 | ||
| 2904 | #define R_PAR1_CONFIG__iseli__inv 1 | ||
| 2905 | #define R_PAR1_CONFIG__iseli__noninv 0 | ||
| 2906 | #define R_PAR1_CONFIG__iautofd__BITNR 23 | ||
| 2907 | #define R_PAR1_CONFIG__iautofd__WIDTH 1 | ||
| 2908 | #define R_PAR1_CONFIG__iautofd__inv 1 | ||
| 2909 | #define R_PAR1_CONFIG__iautofd__noninv 0 | ||
| 2910 | #define R_PAR1_CONFIG__istrb__BITNR 22 | ||
| 2911 | #define R_PAR1_CONFIG__istrb__WIDTH 1 | ||
| 2912 | #define R_PAR1_CONFIG__istrb__inv 1 | ||
| 2913 | #define R_PAR1_CONFIG__istrb__noninv 0 | ||
| 2914 | #define R_PAR1_CONFIG__iinit__BITNR 21 | ||
| 2915 | #define R_PAR1_CONFIG__iinit__WIDTH 1 | ||
| 2916 | #define R_PAR1_CONFIG__iinit__inv 1 | ||
| 2917 | #define R_PAR1_CONFIG__iinit__noninv 0 | ||
| 2918 | #define R_PAR1_CONFIG__iperr__BITNR 20 | ||
| 2919 | #define R_PAR1_CONFIG__iperr__WIDTH 1 | ||
| 2920 | #define R_PAR1_CONFIG__iperr__inv 1 | ||
| 2921 | #define R_PAR1_CONFIG__iperr__noninv 0 | ||
| 2922 | #define R_PAR1_CONFIG__iack__BITNR 19 | ||
| 2923 | #define R_PAR1_CONFIG__iack__WIDTH 1 | ||
| 2924 | #define R_PAR1_CONFIG__iack__inv 1 | ||
| 2925 | #define R_PAR1_CONFIG__iack__noninv 0 | ||
| 2926 | #define R_PAR1_CONFIG__ibusy__BITNR 18 | ||
| 2927 | #define R_PAR1_CONFIG__ibusy__WIDTH 1 | ||
| 2928 | #define R_PAR1_CONFIG__ibusy__inv 1 | ||
| 2929 | #define R_PAR1_CONFIG__ibusy__noninv 0 | ||
| 2930 | #define R_PAR1_CONFIG__ifault__BITNR 17 | ||
| 2931 | #define R_PAR1_CONFIG__ifault__WIDTH 1 | ||
| 2932 | #define R_PAR1_CONFIG__ifault__inv 1 | ||
| 2933 | #define R_PAR1_CONFIG__ifault__noninv 0 | ||
| 2934 | #define R_PAR1_CONFIG__isel__BITNR 16 | ||
| 2935 | #define R_PAR1_CONFIG__isel__WIDTH 1 | ||
| 2936 | #define R_PAR1_CONFIG__isel__inv 1 | ||
| 2937 | #define R_PAR1_CONFIG__isel__noninv 0 | ||
| 2938 | #define R_PAR1_CONFIG__ext_mode__BITNR 11 | ||
| 2939 | #define R_PAR1_CONFIG__ext_mode__WIDTH 1 | ||
| 2940 | #define R_PAR1_CONFIG__ext_mode__enable 1 | ||
| 2941 | #define R_PAR1_CONFIG__ext_mode__disable 0 | ||
| 2942 | #define R_PAR1_CONFIG__dma__BITNR 9 | ||
| 2943 | #define R_PAR1_CONFIG__dma__WIDTH 1 | ||
| 2944 | #define R_PAR1_CONFIG__dma__enable 1 | ||
| 2945 | #define R_PAR1_CONFIG__dma__disable 0 | ||
| 2946 | #define R_PAR1_CONFIG__rle_in__BITNR 8 | ||
| 2947 | #define R_PAR1_CONFIG__rle_in__WIDTH 1 | ||
| 2948 | #define R_PAR1_CONFIG__rle_in__enable 1 | ||
| 2949 | #define R_PAR1_CONFIG__rle_in__disable 0 | ||
| 2950 | #define R_PAR1_CONFIG__rle_out__BITNR 7 | ||
| 2951 | #define R_PAR1_CONFIG__rle_out__WIDTH 1 | ||
| 2952 | #define R_PAR1_CONFIG__rle_out__enable 1 | ||
| 2953 | #define R_PAR1_CONFIG__rle_out__disable 0 | ||
| 2954 | #define R_PAR1_CONFIG__enable__BITNR 6 | ||
| 2955 | #define R_PAR1_CONFIG__enable__WIDTH 1 | ||
| 2956 | #define R_PAR1_CONFIG__enable__on 1 | ||
| 2957 | #define R_PAR1_CONFIG__enable__reset 0 | ||
| 2958 | #define R_PAR1_CONFIG__force__BITNR 5 | ||
| 2959 | #define R_PAR1_CONFIG__force__WIDTH 1 | ||
| 2960 | #define R_PAR1_CONFIG__force__on 1 | ||
| 2961 | #define R_PAR1_CONFIG__force__off 0 | ||
| 2962 | #define R_PAR1_CONFIG__ign_ack__BITNR 4 | ||
| 2963 | #define R_PAR1_CONFIG__ign_ack__WIDTH 1 | ||
| 2964 | #define R_PAR1_CONFIG__ign_ack__ignore 1 | ||
| 2965 | #define R_PAR1_CONFIG__ign_ack__wait 0 | ||
| 2966 | #define R_PAR1_CONFIG__oe_ack__BITNR 3 | ||
| 2967 | #define R_PAR1_CONFIG__oe_ack__WIDTH 1 | ||
| 2968 | #define R_PAR1_CONFIG__oe_ack__wait_oe 1 | ||
| 2969 | #define R_PAR1_CONFIG__oe_ack__dont_wait 0 | ||
| 2970 | #define R_PAR1_CONFIG__oe_ack__epp_addr 1 | ||
| 2971 | #define R_PAR1_CONFIG__oe_ack__epp_data 0 | ||
| 2972 | #define R_PAR1_CONFIG__epp_addr_data__BITNR 3 | ||
| 2973 | #define R_PAR1_CONFIG__epp_addr_data__WIDTH 1 | ||
| 2974 | #define R_PAR1_CONFIG__epp_addr_data__wait_oe 1 | ||
| 2975 | #define R_PAR1_CONFIG__epp_addr_data__dont_wait 0 | ||
| 2976 | #define R_PAR1_CONFIG__epp_addr_data__epp_addr 1 | ||
| 2977 | #define R_PAR1_CONFIG__epp_addr_data__epp_data 0 | ||
| 2978 | #define R_PAR1_CONFIG__mode__BITNR 0 | ||
| 2979 | #define R_PAR1_CONFIG__mode__WIDTH 3 | ||
| 2980 | #define R_PAR1_CONFIG__mode__manual 0 | ||
| 2981 | #define R_PAR1_CONFIG__mode__centronics 1 | ||
| 2982 | #define R_PAR1_CONFIG__mode__fastbyte 2 | ||
| 2983 | #define R_PAR1_CONFIG__mode__nibble 3 | ||
| 2984 | #define R_PAR1_CONFIG__mode__byte 4 | ||
| 2985 | #define R_PAR1_CONFIG__mode__ecp_fwd 5 | ||
| 2986 | #define R_PAR1_CONFIG__mode__ecp_rev 6 | ||
| 2987 | #define R_PAR1_CONFIG__mode__off 7 | ||
| 2988 | #define R_PAR1_CONFIG__mode__epp_wr1 5 | ||
| 2989 | #define R_PAR1_CONFIG__mode__epp_wr2 6 | ||
| 2990 | #define R_PAR1_CONFIG__mode__epp_wr3 7 | ||
| 2991 | #define R_PAR1_CONFIG__mode__epp_rd 0 | ||
| 2992 | |||
| 2993 | #define R_PAR1_DELAY (IO_TYPECAST_UDWORD 0xb0000058) | ||
| 2994 | #define R_PAR1_DELAY__fine_hold__BITNR 21 | ||
| 2995 | #define R_PAR1_DELAY__fine_hold__WIDTH 3 | ||
| 2996 | #define R_PAR1_DELAY__hold__BITNR 16 | ||
| 2997 | #define R_PAR1_DELAY__hold__WIDTH 5 | ||
| 2998 | #define R_PAR1_DELAY__fine_strb__BITNR 13 | ||
| 2999 | #define R_PAR1_DELAY__fine_strb__WIDTH 3 | ||
| 3000 | #define R_PAR1_DELAY__strobe__BITNR 8 | ||
| 3001 | #define R_PAR1_DELAY__strobe__WIDTH 5 | ||
| 3002 | #define R_PAR1_DELAY__fine_setup__BITNR 5 | ||
| 3003 | #define R_PAR1_DELAY__fine_setup__WIDTH 3 | ||
| 3004 | #define R_PAR1_DELAY__setup__BITNR 0 | ||
| 3005 | #define R_PAR1_DELAY__setup__WIDTH 5 | ||
| 3006 | |||
| 3007 | /* | ||
| 3008 | !* ATA interface registers | ||
| 3009 | !*/ | ||
| 3010 | |||
| 3011 | #define R_ATA_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040) | ||
| 3012 | #define R_ATA_CTRL_DATA__sel__BITNR 30 | ||
| 3013 | #define R_ATA_CTRL_DATA__sel__WIDTH 2 | ||
| 3014 | #define R_ATA_CTRL_DATA__cs1__BITNR 29 | ||
| 3015 | #define R_ATA_CTRL_DATA__cs1__WIDTH 1 | ||
| 3016 | #define R_ATA_CTRL_DATA__cs1__active 1 | ||
| 3017 | #define R_ATA_CTRL_DATA__cs1__inactive 0 | ||
| 3018 | #define R_ATA_CTRL_DATA__cs0__BITNR 28 | ||
| 3019 | #define R_ATA_CTRL_DATA__cs0__WIDTH 1 | ||
| 3020 | #define R_ATA_CTRL_DATA__cs0__active 1 | ||
| 3021 | #define R_ATA_CTRL_DATA__cs0__inactive 0 | ||
| 3022 | #define R_ATA_CTRL_DATA__addr__BITNR 25 | ||
| 3023 | #define R_ATA_CTRL_DATA__addr__WIDTH 3 | ||
| 3024 | #define R_ATA_CTRL_DATA__rw__BITNR 24 | ||
| 3025 | #define R_ATA_CTRL_DATA__rw__WIDTH 1 | ||
| 3026 | #define R_ATA_CTRL_DATA__rw__read 1 | ||
| 3027 | #define R_ATA_CTRL_DATA__rw__write 0 | ||
| 3028 | #define R_ATA_CTRL_DATA__src_dst__BITNR 23 | ||
| 3029 | #define R_ATA_CTRL_DATA__src_dst__WIDTH 1 | ||
| 3030 | #define R_ATA_CTRL_DATA__src_dst__dma 1 | ||
| 3031 | #define R_ATA_CTRL_DATA__src_dst__register 0 | ||
| 3032 | #define R_ATA_CTRL_DATA__handsh__BITNR 22 | ||
| 3033 | #define R_ATA_CTRL_DATA__handsh__WIDTH 1 | ||
| 3034 | #define R_ATA_CTRL_DATA__handsh__dma 1 | ||
| 3035 | #define R_ATA_CTRL_DATA__handsh__pio 0 | ||
| 3036 | #define R_ATA_CTRL_DATA__multi__BITNR 21 | ||
| 3037 | #define R_ATA_CTRL_DATA__multi__WIDTH 1 | ||
| 3038 | #define R_ATA_CTRL_DATA__multi__on 1 | ||
| 3039 | #define R_ATA_CTRL_DATA__multi__off 0 | ||
| 3040 | #define R_ATA_CTRL_DATA__dma_size__BITNR 20 | ||
| 3041 | #define R_ATA_CTRL_DATA__dma_size__WIDTH 1 | ||
| 3042 | #define R_ATA_CTRL_DATA__dma_size__byte 1 | ||
| 3043 | #define R_ATA_CTRL_DATA__dma_size__word 0 | ||
| 3044 | #define R_ATA_CTRL_DATA__data__BITNR 0 | ||
| 3045 | #define R_ATA_CTRL_DATA__data__WIDTH 16 | ||
| 3046 | |||
| 3047 | #define R_ATA_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040) | ||
| 3048 | #define R_ATA_STATUS_DATA__busy__BITNR 18 | ||
| 3049 | #define R_ATA_STATUS_DATA__busy__WIDTH 1 | ||
| 3050 | #define R_ATA_STATUS_DATA__busy__yes 1 | ||
| 3051 | #define R_ATA_STATUS_DATA__busy__no 0 | ||
| 3052 | #define R_ATA_STATUS_DATA__tr_rdy__BITNR 17 | ||
| 3053 | #define R_ATA_STATUS_DATA__tr_rdy__WIDTH 1 | ||
| 3054 | #define R_ATA_STATUS_DATA__tr_rdy__ready 1 | ||
| 3055 | #define R_ATA_STATUS_DATA__tr_rdy__busy 0 | ||
| 3056 | #define R_ATA_STATUS_DATA__dav__BITNR 16 | ||
| 3057 | #define R_ATA_STATUS_DATA__dav__WIDTH 1 | ||
| 3058 | #define R_ATA_STATUS_DATA__dav__data 1 | ||
| 3059 | #define R_ATA_STATUS_DATA__dav__nodata 0 | ||
| 3060 | #define R_ATA_STATUS_DATA__data__BITNR 0 | ||
| 3061 | #define R_ATA_STATUS_DATA__data__WIDTH 16 | ||
| 3062 | |||
| 3063 | #define R_ATA_CONFIG (IO_TYPECAST_UDWORD 0xb0000044) | ||
| 3064 | #define R_ATA_CONFIG__enable__BITNR 25 | ||
| 3065 | #define R_ATA_CONFIG__enable__WIDTH 1 | ||
| 3066 | #define R_ATA_CONFIG__enable__on 1 | ||
| 3067 | #define R_ATA_CONFIG__enable__off 0 | ||
| 3068 | #define R_ATA_CONFIG__dma_strobe__BITNR 20 | ||
| 3069 | #define R_ATA_CONFIG__dma_strobe__WIDTH 5 | ||
| 3070 | #define R_ATA_CONFIG__dma_hold__BITNR 15 | ||
| 3071 | #define R_ATA_CONFIG__dma_hold__WIDTH 5 | ||
| 3072 | #define R_ATA_CONFIG__pio_setup__BITNR 10 | ||
| 3073 | #define R_ATA_CONFIG__pio_setup__WIDTH 5 | ||
| 3074 | #define R_ATA_CONFIG__pio_strobe__BITNR 5 | ||
| 3075 | #define R_ATA_CONFIG__pio_strobe__WIDTH 5 | ||
| 3076 | #define R_ATA_CONFIG__pio_hold__BITNR 0 | ||
| 3077 | #define R_ATA_CONFIG__pio_hold__WIDTH 5 | ||
| 3078 | |||
| 3079 | #define R_ATA_TRANSFER_CNT (IO_TYPECAST_UDWORD 0xb0000048) | ||
| 3080 | #define R_ATA_TRANSFER_CNT__count__BITNR 0 | ||
| 3081 | #define R_ATA_TRANSFER_CNT__count__WIDTH 17 | ||
| 3082 | |||
| 3083 | /* | ||
| 3084 | !* SCSI registers | ||
| 3085 | !*/ | ||
| 3086 | |||
| 3087 | #define R_SCSI0_CTRL (IO_TYPECAST_UDWORD 0xb0000044) | ||
| 3088 | #define R_SCSI0_CTRL__id_type__BITNR 31 | ||
| 3089 | #define R_SCSI0_CTRL__id_type__WIDTH 1 | ||
| 3090 | #define R_SCSI0_CTRL__id_type__software 1 | ||
| 3091 | #define R_SCSI0_CTRL__id_type__hardware 0 | ||
| 3092 | #define R_SCSI0_CTRL__sel_timeout__BITNR 24 | ||
| 3093 | #define R_SCSI0_CTRL__sel_timeout__WIDTH 7 | ||
| 3094 | #define R_SCSI0_CTRL__synch_per__BITNR 16 | ||
| 3095 | #define R_SCSI0_CTRL__synch_per__WIDTH 8 | ||
| 3096 | #define R_SCSI0_CTRL__rst__BITNR 15 | ||
| 3097 | #define R_SCSI0_CTRL__rst__WIDTH 1 | ||
| 3098 | #define R_SCSI0_CTRL__rst__yes 1 | ||
| 3099 | #define R_SCSI0_CTRL__rst__no 0 | ||
| 3100 | #define R_SCSI0_CTRL__atn__BITNR 14 | ||
| 3101 | #define R_SCSI0_CTRL__atn__WIDTH 1 | ||
| 3102 | #define R_SCSI0_CTRL__atn__yes 1 | ||
| 3103 | #define R_SCSI0_CTRL__atn__no 0 | ||
| 3104 | #define R_SCSI0_CTRL__my_id__BITNR 9 | ||
| 3105 | #define R_SCSI0_CTRL__my_id__WIDTH 4 | ||
| 3106 | #define R_SCSI0_CTRL__target_id__BITNR 4 | ||
| 3107 | #define R_SCSI0_CTRL__target_id__WIDTH 4 | ||
| 3108 | #define R_SCSI0_CTRL__fast_20__BITNR 3 | ||
| 3109 | #define R_SCSI0_CTRL__fast_20__WIDTH 1 | ||
| 3110 | #define R_SCSI0_CTRL__fast_20__yes 1 | ||
| 3111 | #define R_SCSI0_CTRL__fast_20__no 0 | ||
| 3112 | #define R_SCSI0_CTRL__bus_width__BITNR 2 | ||
| 3113 | #define R_SCSI0_CTRL__bus_width__WIDTH 1 | ||
| 3114 | #define R_SCSI0_CTRL__bus_width__wide 1 | ||
| 3115 | #define R_SCSI0_CTRL__bus_width__narrow 0 | ||
| 3116 | #define R_SCSI0_CTRL__synch__BITNR 1 | ||
| 3117 | #define R_SCSI0_CTRL__synch__WIDTH 1 | ||
| 3118 | #define R_SCSI0_CTRL__synch__synch 1 | ||
| 3119 | #define R_SCSI0_CTRL__synch__asynch 0 | ||
| 3120 | #define R_SCSI0_CTRL__enable__BITNR 0 | ||
| 3121 | #define R_SCSI0_CTRL__enable__WIDTH 1 | ||
| 3122 | #define R_SCSI0_CTRL__enable__on 1 | ||
| 3123 | #define R_SCSI0_CTRL__enable__off 0 | ||
| 3124 | |||
| 3125 | #define R_SCSI0_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000040) | ||
| 3126 | #define R_SCSI0_CMD_DATA__parity_in__BITNR 26 | ||
| 3127 | #define R_SCSI0_CMD_DATA__parity_in__WIDTH 1 | ||
| 3128 | #define R_SCSI0_CMD_DATA__parity_in__on 0 | ||
| 3129 | #define R_SCSI0_CMD_DATA__parity_in__off 1 | ||
| 3130 | #define R_SCSI0_CMD_DATA__skip__BITNR 25 | ||
| 3131 | #define R_SCSI0_CMD_DATA__skip__WIDTH 1 | ||
| 3132 | #define R_SCSI0_CMD_DATA__skip__on 1 | ||
| 3133 | #define R_SCSI0_CMD_DATA__skip__off 0 | ||
| 3134 | #define R_SCSI0_CMD_DATA__clr_status__BITNR 24 | ||
| 3135 | #define R_SCSI0_CMD_DATA__clr_status__WIDTH 1 | ||
| 3136 | #define R_SCSI0_CMD_DATA__clr_status__yes 1 | ||
| 3137 | #define R_SCSI0_CMD_DATA__clr_status__nop 0 | ||
| 3138 | #define R_SCSI0_CMD_DATA__asynch_setup__BITNR 20 | ||
| 3139 | #define R_SCSI0_CMD_DATA__asynch_setup__WIDTH 4 | ||
| 3140 | #define R_SCSI0_CMD_DATA__command__BITNR 16 | ||
| 3141 | #define R_SCSI0_CMD_DATA__command__WIDTH 4 | ||
| 3142 | #define R_SCSI0_CMD_DATA__command__full_din_1 0 | ||
| 3143 | #define R_SCSI0_CMD_DATA__command__full_dout_1 1 | ||
| 3144 | #define R_SCSI0_CMD_DATA__command__full_stat_1 2 | ||
| 3145 | #define R_SCSI0_CMD_DATA__command__resel_din 3 | ||
| 3146 | #define R_SCSI0_CMD_DATA__command__resel_dout 4 | ||
| 3147 | #define R_SCSI0_CMD_DATA__command__resel_stat 5 | ||
| 3148 | #define R_SCSI0_CMD_DATA__command__arb_only 6 | ||
| 3149 | #define R_SCSI0_CMD_DATA__command__full_din_3 8 | ||
| 3150 | #define R_SCSI0_CMD_DATA__command__full_dout_3 9 | ||
| 3151 | #define R_SCSI0_CMD_DATA__command__full_stat_3 10 | ||
| 3152 | #define R_SCSI0_CMD_DATA__command__man_data_in 11 | ||
| 3153 | #define R_SCSI0_CMD_DATA__command__man_data_out 12 | ||
| 3154 | #define R_SCSI0_CMD_DATA__command__man_rat 13 | ||
| 3155 | #define R_SCSI0_CMD_DATA__data_out__BITNR 0 | ||
| 3156 | #define R_SCSI0_CMD_DATA__data_out__WIDTH 16 | ||
| 3157 | |||
| 3158 | #define R_SCSI0_DATA (IO_TYPECAST_UWORD 0xb0000040) | ||
| 3159 | #define R_SCSI0_DATA__data_out__BITNR 0 | ||
| 3160 | #define R_SCSI0_DATA__data_out__WIDTH 16 | ||
| 3161 | |||
| 3162 | #define R_SCSI0_CMD (IO_TYPECAST_BYTE 0xb0000042) | ||
| 3163 | #define R_SCSI0_CMD__asynch_setup__BITNR 4 | ||
| 3164 | #define R_SCSI0_CMD__asynch_setup__WIDTH 4 | ||
| 3165 | #define R_SCSI0_CMD__command__BITNR 0 | ||
| 3166 | #define R_SCSI0_CMD__command__WIDTH 4 | ||
| 3167 | #define R_SCSI0_CMD__command__full_din_1 0 | ||
| 3168 | #define R_SCSI0_CMD__command__full_dout_1 1 | ||
| 3169 | #define R_SCSI0_CMD__command__full_stat_1 2 | ||
| 3170 | #define R_SCSI0_CMD__command__resel_din 3 | ||
| 3171 | #define R_SCSI0_CMD__command__resel_dout 4 | ||
| 3172 | #define R_SCSI0_CMD__command__resel_stat 5 | ||
| 3173 | #define R_SCSI0_CMD__command__arb_only 6 | ||
| 3174 | #define R_SCSI0_CMD__command__full_din_3 8 | ||
| 3175 | #define R_SCSI0_CMD__command__full_dout_3 9 | ||
| 3176 | #define R_SCSI0_CMD__command__full_stat_3 10 | ||
| 3177 | #define R_SCSI0_CMD__command__man_data_in 11 | ||
| 3178 | #define R_SCSI0_CMD__command__man_data_out 12 | ||
| 3179 | #define R_SCSI0_CMD__command__man_rat 13 | ||
| 3180 | |||
| 3181 | #define R_SCSI0_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000043) | ||
| 3182 | #define R_SCSI0_STATUS_CTRL__parity_in__BITNR 2 | ||
| 3183 | #define R_SCSI0_STATUS_CTRL__parity_in__WIDTH 1 | ||
| 3184 | #define R_SCSI0_STATUS_CTRL__parity_in__on 0 | ||
| 3185 | #define R_SCSI0_STATUS_CTRL__parity_in__off 1 | ||
| 3186 | #define R_SCSI0_STATUS_CTRL__skip__BITNR 1 | ||
| 3187 | #define R_SCSI0_STATUS_CTRL__skip__WIDTH 1 | ||
| 3188 | #define R_SCSI0_STATUS_CTRL__skip__on 1 | ||
| 3189 | #define R_SCSI0_STATUS_CTRL__skip__off 0 | ||
| 3190 | #define R_SCSI0_STATUS_CTRL__clr_status__BITNR 0 | ||
| 3191 | #define R_SCSI0_STATUS_CTRL__clr_status__WIDTH 1 | ||
| 3192 | #define R_SCSI0_STATUS_CTRL__clr_status__yes 1 | ||
| 3193 | #define R_SCSI0_STATUS_CTRL__clr_status__nop 0 | ||
| 3194 | |||
| 3195 | #define R_SCSI0_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000048) | ||
| 3196 | #define R_SCSI0_STATUS__tst_arb_won__BITNR 23 | ||
| 3197 | #define R_SCSI0_STATUS__tst_arb_won__WIDTH 1 | ||
| 3198 | #define R_SCSI0_STATUS__tst_resel__BITNR 22 | ||
| 3199 | #define R_SCSI0_STATUS__tst_resel__WIDTH 1 | ||
| 3200 | #define R_SCSI0_STATUS__parity_error__BITNR 21 | ||
| 3201 | #define R_SCSI0_STATUS__parity_error__WIDTH 1 | ||
| 3202 | #define R_SCSI0_STATUS__bus_reset__BITNR 20 | ||
| 3203 | #define R_SCSI0_STATUS__bus_reset__WIDTH 1 | ||
| 3204 | #define R_SCSI0_STATUS__bus_reset__yes 1 | ||
| 3205 | #define R_SCSI0_STATUS__bus_reset__no 0 | ||
| 3206 | #define R_SCSI0_STATUS__resel_target__BITNR 15 | ||
| 3207 | #define R_SCSI0_STATUS__resel_target__WIDTH 4 | ||
| 3208 | #define R_SCSI0_STATUS__resel__BITNR 14 | ||
| 3209 | #define R_SCSI0_STATUS__resel__WIDTH 1 | ||
| 3210 | #define R_SCSI0_STATUS__resel__yes 1 | ||
| 3211 | #define R_SCSI0_STATUS__resel__no 0 | ||
| 3212 | #define R_SCSI0_STATUS__curr_phase__BITNR 11 | ||
| 3213 | #define R_SCSI0_STATUS__curr_phase__WIDTH 3 | ||
| 3214 | #define R_SCSI0_STATUS__curr_phase__ph_undef 0 | ||
| 3215 | #define R_SCSI0_STATUS__curr_phase__ph_msg_in 7 | ||
| 3216 | #define R_SCSI0_STATUS__curr_phase__ph_msg_out 6 | ||
| 3217 | #define R_SCSI0_STATUS__curr_phase__ph_status 3 | ||
| 3218 | #define R_SCSI0_STATUS__curr_phase__ph_command 2 | ||
| 3219 | #define R_SCSI0_STATUS__curr_phase__ph_data_in 5 | ||
| 3220 | #define R_SCSI0_STATUS__curr_phase__ph_data_out 4 | ||
| 3221 | #define R_SCSI0_STATUS__curr_phase__ph_resel 1 | ||
| 3222 | #define R_SCSI0_STATUS__last_seq_step__BITNR 6 | ||
| 3223 | #define R_SCSI0_STATUS__last_seq_step__WIDTH 5 | ||
| 3224 | #define R_SCSI0_STATUS__last_seq_step__st_bus_free 24 | ||
| 3225 | #define R_SCSI0_STATUS__last_seq_step__st_arbitrate 8 | ||
| 3226 | #define R_SCSI0_STATUS__last_seq_step__st_resel_req 29 | ||
| 3227 | #define R_SCSI0_STATUS__last_seq_step__st_msg_1 2 | ||
| 3228 | #define R_SCSI0_STATUS__last_seq_step__st_manual 28 | ||
| 3229 | #define R_SCSI0_STATUS__last_seq_step__st_transf_cmd 30 | ||
| 3230 | #define R_SCSI0_STATUS__last_seq_step__st_msg_2 6 | ||
| 3231 | #define R_SCSI0_STATUS__last_seq_step__st_msg_3 22 | ||
| 3232 | #define R_SCSI0_STATUS__last_seq_step__st_answer 3 | ||
| 3233 | #define R_SCSI0_STATUS__last_seq_step__st_synch_din_perr 1 | ||
| 3234 | #define R_SCSI0_STATUS__last_seq_step__st_transfer_done 15 | ||
| 3235 | #define R_SCSI0_STATUS__last_seq_step__st_synch_dout 0 | ||
| 3236 | #define R_SCSI0_STATUS__last_seq_step__st_asynch_dout 25 | ||
| 3237 | #define R_SCSI0_STATUS__last_seq_step__st_synch_din 13 | ||
| 3238 | #define R_SCSI0_STATUS__last_seq_step__st_asynch_din 9 | ||
| 3239 | #define R_SCSI0_STATUS__last_seq_step__st_synch_dout_ack 4 | ||
| 3240 | #define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack 12 | ||
| 3241 | #define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack_perr 5 | ||
| 3242 | #define R_SCSI0_STATUS__last_seq_step__st_asynch_dout_end 11 | ||
| 3243 | #define R_SCSI0_STATUS__last_seq_step__st_iwr 27 | ||
| 3244 | #define R_SCSI0_STATUS__last_seq_step__st_wait_free_disc 21 | ||
| 3245 | #define R_SCSI0_STATUS__last_seq_step__st_sdp_disc 7 | ||
| 3246 | #define R_SCSI0_STATUS__last_seq_step__st_cc 31 | ||
| 3247 | #define R_SCSI0_STATUS__last_seq_step__st_iwr_good 14 | ||
| 3248 | #define R_SCSI0_STATUS__last_seq_step__st_iwr_cc 23 | ||
| 3249 | #define R_SCSI0_STATUS__last_seq_step__st_wait_free_iwr_cc 17 | ||
| 3250 | #define R_SCSI0_STATUS__last_seq_step__st_wait_free_cc 20 | ||
| 3251 | #define R_SCSI0_STATUS__last_seq_step__st_wait_free_sdp_disc 16 | ||
| 3252 | #define R_SCSI0_STATUS__last_seq_step__st_manual_req 10 | ||
| 3253 | #define R_SCSI0_STATUS__last_seq_step__st_manual_din_prot 18 | ||
| 3254 | #define R_SCSI0_STATUS__valid_status__BITNR 5 | ||
| 3255 | #define R_SCSI0_STATUS__valid_status__WIDTH 1 | ||
| 3256 | #define R_SCSI0_STATUS__valid_status__yes 1 | ||
| 3257 | #define R_SCSI0_STATUS__valid_status__no 0 | ||
| 3258 | #define R_SCSI0_STATUS__seq_status__BITNR 0 | ||
| 3259 | #define R_SCSI0_STATUS__seq_status__WIDTH 5 | ||
| 3260 | #define R_SCSI0_STATUS__seq_status__info_seq_complete 0 | ||
| 3261 | #define R_SCSI0_STATUS__seq_status__info_parity_error 1 | ||
| 3262 | #define R_SCSI0_STATUS__seq_status__info_unhandled_msg_in 2 | ||
| 3263 | #define R_SCSI0_STATUS__seq_status__info_unexp_ph_change 3 | ||
| 3264 | #define R_SCSI0_STATUS__seq_status__info_arb_lost 4 | ||
| 3265 | #define R_SCSI0_STATUS__seq_status__info_sel_timeout 5 | ||
| 3266 | #define R_SCSI0_STATUS__seq_status__info_unexp_bf 6 | ||
| 3267 | #define R_SCSI0_STATUS__seq_status__info_illegal_op 7 | ||
| 3268 | #define R_SCSI0_STATUS__seq_status__info_rec_recvd 8 | ||
| 3269 | #define R_SCSI0_STATUS__seq_status__info_reselected 9 | ||
| 3270 | #define R_SCSI0_STATUS__seq_status__info_unhandled_status 10 | ||
| 3271 | #define R_SCSI0_STATUS__seq_status__info_bus_reset 11 | ||
| 3272 | #define R_SCSI0_STATUS__seq_status__info_illegal_bf 12 | ||
| 3273 | #define R_SCSI0_STATUS__seq_status__info_bus_free 13 | ||
| 3274 | |||
| 3275 | #define R_SCSI0_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000040) | ||
| 3276 | #define R_SCSI0_DATA_IN__data_in__BITNR 0 | ||
| 3277 | #define R_SCSI0_DATA_IN__data_in__WIDTH 16 | ||
| 3278 | |||
| 3279 | #define R_SCSI1_CTRL (IO_TYPECAST_UDWORD 0xb0000054) | ||
| 3280 | #define R_SCSI1_CTRL__id_type__BITNR 31 | ||
| 3281 | #define R_SCSI1_CTRL__id_type__WIDTH 1 | ||
| 3282 | #define R_SCSI1_CTRL__id_type__software 1 | ||
| 3283 | #define R_SCSI1_CTRL__id_type__hardware 0 | ||
| 3284 | #define R_SCSI1_CTRL__sel_timeout__BITNR 24 | ||
| 3285 | #define R_SCSI1_CTRL__sel_timeout__WIDTH 7 | ||
| 3286 | #define R_SCSI1_CTRL__synch_per__BITNR 16 | ||
| 3287 | #define R_SCSI1_CTRL__synch_per__WIDTH 8 | ||
| 3288 | #define R_SCSI1_CTRL__rst__BITNR 15 | ||
| 3289 | #define R_SCSI1_CTRL__rst__WIDTH 1 | ||
| 3290 | #define R_SCSI1_CTRL__rst__yes 1 | ||
| 3291 | #define R_SCSI1_CTRL__rst__no 0 | ||
| 3292 | #define R_SCSI1_CTRL__atn__BITNR 14 | ||
| 3293 | #define R_SCSI1_CTRL__atn__WIDTH 1 | ||
| 3294 | #define R_SCSI1_CTRL__atn__yes 1 | ||
| 3295 | #define R_SCSI1_CTRL__atn__no 0 | ||
| 3296 | #define R_SCSI1_CTRL__my_id__BITNR 9 | ||
| 3297 | #define R_SCSI1_CTRL__my_id__WIDTH 4 | ||
| 3298 | #define R_SCSI1_CTRL__target_id__BITNR 4 | ||
| 3299 | #define R_SCSI1_CTRL__target_id__WIDTH 4 | ||
| 3300 | #define R_SCSI1_CTRL__fast_20__BITNR 3 | ||
| 3301 | #define R_SCSI1_CTRL__fast_20__WIDTH 1 | ||
| 3302 | #define R_SCSI1_CTRL__fast_20__yes 1 | ||
| 3303 | #define R_SCSI1_CTRL__fast_20__no 0 | ||
| 3304 | #define R_SCSI1_CTRL__bus_width__BITNR 2 | ||
| 3305 | #define R_SCSI1_CTRL__bus_width__WIDTH 1 | ||
| 3306 | #define R_SCSI1_CTRL__bus_width__wide 1 | ||
| 3307 | #define R_SCSI1_CTRL__bus_width__narrow 0 | ||
| 3308 | #define R_SCSI1_CTRL__synch__BITNR 1 | ||
| 3309 | #define R_SCSI1_CTRL__synch__WIDTH 1 | ||
| 3310 | #define R_SCSI1_CTRL__synch__synch 1 | ||
| 3311 | #define R_SCSI1_CTRL__synch__asynch 0 | ||
| 3312 | #define R_SCSI1_CTRL__enable__BITNR 0 | ||
| 3313 | #define R_SCSI1_CTRL__enable__WIDTH 1 | ||
| 3314 | #define R_SCSI1_CTRL__enable__on 1 | ||
| 3315 | #define R_SCSI1_CTRL__enable__off 0 | ||
| 3316 | |||
| 3317 | #define R_SCSI1_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000050) | ||
| 3318 | #define R_SCSI1_CMD_DATA__parity_in__BITNR 26 | ||
| 3319 | #define R_SCSI1_CMD_DATA__parity_in__WIDTH 1 | ||
| 3320 | #define R_SCSI1_CMD_DATA__parity_in__on 0 | ||
| 3321 | #define R_SCSI1_CMD_DATA__parity_in__off 1 | ||
| 3322 | #define R_SCSI1_CMD_DATA__skip__BITNR 25 | ||
| 3323 | #define R_SCSI1_CMD_DATA__skip__WIDTH 1 | ||
| 3324 | #define R_SCSI1_CMD_DATA__skip__on 1 | ||
| 3325 | #define R_SCSI1_CMD_DATA__skip__off 0 | ||
| 3326 | #define R_SCSI1_CMD_DATA__clr_status__BITNR 24 | ||
| 3327 | #define R_SCSI1_CMD_DATA__clr_status__WIDTH 1 | ||
| 3328 | #define R_SCSI1_CMD_DATA__clr_status__yes 1 | ||
| 3329 | #define R_SCSI1_CMD_DATA__clr_status__nop 0 | ||
| 3330 | #define R_SCSI1_CMD_DATA__asynch_setup__BITNR 20 | ||
| 3331 | #define R_SCSI1_CMD_DATA__asynch_setup__WIDTH 4 | ||
| 3332 | #define R_SCSI1_CMD_DATA__command__BITNR 16 | ||
| 3333 | #define R_SCSI1_CMD_DATA__command__WIDTH 4 | ||
| 3334 | #define R_SCSI1_CMD_DATA__command__full_din_1 0 | ||
| 3335 | #define R_SCSI1_CMD_DATA__command__full_dout_1 1 | ||
| 3336 | #define R_SCSI1_CMD_DATA__command__full_stat_1 2 | ||
| 3337 | #define R_SCSI1_CMD_DATA__command__resel_din 3 | ||
| 3338 | #define R_SCSI1_CMD_DATA__command__resel_dout 4 | ||
| 3339 | #define R_SCSI1_CMD_DATA__command__resel_stat 5 | ||
| 3340 | #define R_SCSI1_CMD_DATA__command__arb_only 6 | ||
| 3341 | #define R_SCSI1_CMD_DATA__command__full_din_3 8 | ||
| 3342 | #define R_SCSI1_CMD_DATA__command__full_dout_3 9 | ||
| 3343 | #define R_SCSI1_CMD_DATA__command__full_stat_3 10 | ||
| 3344 | #define R_SCSI1_CMD_DATA__command__man_data_in 11 | ||
| 3345 | #define R_SCSI1_CMD_DATA__command__man_data_out 12 | ||
| 3346 | #define R_SCSI1_CMD_DATA__command__man_rat 13 | ||
| 3347 | #define R_SCSI1_CMD_DATA__data_out__BITNR 0 | ||
| 3348 | #define R_SCSI1_CMD_DATA__data_out__WIDTH 16 | ||
| 3349 | |||
| 3350 | #define R_SCSI1_DATA (IO_TYPECAST_UWORD 0xb0000050) | ||
| 3351 | #define R_SCSI1_DATA__data_out__BITNR 0 | ||
| 3352 | #define R_SCSI1_DATA__data_out__WIDTH 16 | ||
| 3353 | |||
| 3354 | #define R_SCSI1_CMD (IO_TYPECAST_BYTE 0xb0000052) | ||
| 3355 | #define R_SCSI1_CMD__asynch_setup__BITNR 4 | ||
| 3356 | #define R_SCSI1_CMD__asynch_setup__WIDTH 4 | ||
| 3357 | #define R_SCSI1_CMD__command__BITNR 0 | ||
| 3358 | #define R_SCSI1_CMD__command__WIDTH 4 | ||
| 3359 | #define R_SCSI1_CMD__command__full_din_1 0 | ||
| 3360 | #define R_SCSI1_CMD__command__full_dout_1 1 | ||
| 3361 | #define R_SCSI1_CMD__command__full_stat_1 2 | ||
| 3362 | #define R_SCSI1_CMD__command__resel_din 3 | ||
| 3363 | #define R_SCSI1_CMD__command__resel_dout 4 | ||
| 3364 | #define R_SCSI1_CMD__command__resel_stat 5 | ||
| 3365 | #define R_SCSI1_CMD__command__arb_only 6 | ||
| 3366 | #define R_SCSI1_CMD__command__full_din_3 8 | ||
| 3367 | #define R_SCSI1_CMD__command__full_dout_3 9 | ||
| 3368 | #define R_SCSI1_CMD__command__full_stat_3 10 | ||
| 3369 | #define R_SCSI1_CMD__command__man_data_in 11 | ||
| 3370 | #define R_SCSI1_CMD__command__man_data_out 12 | ||
| 3371 | #define R_SCSI1_CMD__command__man_rat 13 | ||
| 3372 | |||
| 3373 | #define R_SCSI1_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000053) | ||
| 3374 | #define R_SCSI1_STATUS_CTRL__parity_in__BITNR 2 | ||
| 3375 | #define R_SCSI1_STATUS_CTRL__parity_in__WIDTH 1 | ||
| 3376 | #define R_SCSI1_STATUS_CTRL__parity_in__on 0 | ||
| 3377 | #define R_SCSI1_STATUS_CTRL__parity_in__off 1 | ||
| 3378 | #define R_SCSI1_STATUS_CTRL__skip__BITNR 1 | ||
| 3379 | #define R_SCSI1_STATUS_CTRL__skip__WIDTH 1 | ||
| 3380 | #define R_SCSI1_STATUS_CTRL__skip__on 1 | ||
| 3381 | #define R_SCSI1_STATUS_CTRL__skip__off 0 | ||
| 3382 | #define R_SCSI1_STATUS_CTRL__clr_status__BITNR 0 | ||
| 3383 | #define R_SCSI1_STATUS_CTRL__clr_status__WIDTH 1 | ||
| 3384 | #define R_SCSI1_STATUS_CTRL__clr_status__yes 1 | ||
| 3385 | #define R_SCSI1_STATUS_CTRL__clr_status__nop 0 | ||
| 3386 | |||
| 3387 | #define R_SCSI1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000058) | ||
| 3388 | #define R_SCSI1_STATUS__tst_arb_won__BITNR 23 | ||
| 3389 | #define R_SCSI1_STATUS__tst_arb_won__WIDTH 1 | ||
| 3390 | #define R_SCSI1_STATUS__tst_resel__BITNR 22 | ||
| 3391 | #define R_SCSI1_STATUS__tst_resel__WIDTH 1 | ||
| 3392 | #define R_SCSI1_STATUS__parity_error__BITNR 21 | ||
| 3393 | #define R_SCSI1_STATUS__parity_error__WIDTH 1 | ||
| 3394 | #define R_SCSI1_STATUS__bus_reset__BITNR 20 | ||
| 3395 | #define R_SCSI1_STATUS__bus_reset__WIDTH 1 | ||
| 3396 | #define R_SCSI1_STATUS__bus_reset__yes 1 | ||
| 3397 | #define R_SCSI1_STATUS__bus_reset__no 0 | ||
| 3398 | #define R_SCSI1_STATUS__resel_target__BITNR 15 | ||
| 3399 | #define R_SCSI1_STATUS__resel_target__WIDTH 4 | ||
| 3400 | #define R_SCSI1_STATUS__resel__BITNR 14 | ||
| 3401 | #define R_SCSI1_STATUS__resel__WIDTH 1 | ||
| 3402 | #define R_SCSI1_STATUS__resel__yes 1 | ||
| 3403 | #define R_SCSI1_STATUS__resel__no 0 | ||
| 3404 | #define R_SCSI1_STATUS__curr_phase__BITNR 11 | ||
| 3405 | #define R_SCSI1_STATUS__curr_phase__WIDTH 3 | ||
| 3406 | #define R_SCSI1_STATUS__curr_phase__ph_undef 0 | ||
| 3407 | #define R_SCSI1_STATUS__curr_phase__ph_msg_in 7 | ||
| 3408 | #define R_SCSI1_STATUS__curr_phase__ph_msg_out 6 | ||
| 3409 | #define R_SCSI1_STATUS__curr_phase__ph_status 3 | ||
| 3410 | #define R_SCSI1_STATUS__curr_phase__ph_command 2 | ||
| 3411 | #define R_SCSI1_STATUS__curr_phase__ph_data_in 5 | ||
| 3412 | #define R_SCSI1_STATUS__curr_phase__ph_data_out 4 | ||
| 3413 | #define R_SCSI1_STATUS__curr_phase__ph_resel 1 | ||
| 3414 | #define R_SCSI1_STATUS__last_seq_step__BITNR 6 | ||
| 3415 | #define R_SCSI1_STATUS__last_seq_step__WIDTH 5 | ||
| 3416 | #define R_SCSI1_STATUS__last_seq_step__st_bus_free 24 | ||
| 3417 | #define R_SCSI1_STATUS__last_seq_step__st_arbitrate 8 | ||
| 3418 | #define R_SCSI1_STATUS__last_seq_step__st_resel_req 29 | ||
| 3419 | #define R_SCSI1_STATUS__last_seq_step__st_msg_1 2 | ||
| 3420 | #define R_SCSI1_STATUS__last_seq_step__st_manual 28 | ||
| 3421 | #define R_SCSI1_STATUS__last_seq_step__st_transf_cmd 30 | ||
| 3422 | #define R_SCSI1_STATUS__last_seq_step__st_msg_2 6 | ||
| 3423 | #define R_SCSI1_STATUS__last_seq_step__st_msg_3 22 | ||
| 3424 | #define R_SCSI1_STATUS__last_seq_step__st_answer 3 | ||
| 3425 | #define R_SCSI1_STATUS__last_seq_step__st_synch_din_perr 1 | ||
| 3426 | #define R_SCSI1_STATUS__last_seq_step__st_transfer_done 15 | ||
| 3427 | #define R_SCSI1_STATUS__last_seq_step__st_synch_dout 0 | ||
| 3428 | #define R_SCSI1_STATUS__last_seq_step__st_asynch_dout 25 | ||
| 3429 | #define R_SCSI1_STATUS__last_seq_step__st_synch_din 13 | ||
| 3430 | #define R_SCSI1_STATUS__last_seq_step__st_asynch_din 9 | ||
| 3431 | #define R_SCSI1_STATUS__last_seq_step__st_synch_dout_ack 4 | ||
| 3432 | #define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack 12 | ||
| 3433 | #define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack_perr 5 | ||
| 3434 | #define R_SCSI1_STATUS__last_seq_step__st_asynch_dout_end 11 | ||
| 3435 | #define R_SCSI1_STATUS__last_seq_step__st_iwr 27 | ||
| 3436 | #define R_SCSI1_STATUS__last_seq_step__st_wait_free_disc 21 | ||
| 3437 | #define R_SCSI1_STATUS__last_seq_step__st_sdp_disc 7 | ||
| 3438 | #define R_SCSI1_STATUS__last_seq_step__st_cc 31 | ||
| 3439 | #define R_SCSI1_STATUS__last_seq_step__st_iwr_good 14 | ||
| 3440 | #define R_SCSI1_STATUS__last_seq_step__st_iwr_cc 23 | ||
| 3441 | #define R_SCSI1_STATUS__last_seq_step__st_wait_free_iwr_cc 17 | ||
| 3442 | #define R_SCSI1_STATUS__last_seq_step__st_wait_free_cc 20 | ||
| 3443 | #define R_SCSI1_STATUS__last_seq_step__st_wait_free_sdp_disc 16 | ||
| 3444 | #define R_SCSI1_STATUS__last_seq_step__st_manual_req 10 | ||
| 3445 | #define R_SCSI1_STATUS__last_seq_step__st_manual_din_prot 18 | ||
| 3446 | #define R_SCSI1_STATUS__valid_status__BITNR 5 | ||
| 3447 | #define R_SCSI1_STATUS__valid_status__WIDTH 1 | ||
| 3448 | #define R_SCSI1_STATUS__valid_status__yes 1 | ||
| 3449 | #define R_SCSI1_STATUS__valid_status__no 0 | ||
| 3450 | #define R_SCSI1_STATUS__seq_status__BITNR 0 | ||
| 3451 | #define R_SCSI1_STATUS__seq_status__WIDTH 5 | ||
| 3452 | #define R_SCSI1_STATUS__seq_status__info_seq_complete 0 | ||
| 3453 | #define R_SCSI1_STATUS__seq_status__info_parity_error 1 | ||
| 3454 | #define R_SCSI1_STATUS__seq_status__info_unhandled_msg_in 2 | ||
| 3455 | #define R_SCSI1_STATUS__seq_status__info_unexp_ph_change 3 | ||
| 3456 | #define R_SCSI1_STATUS__seq_status__info_arb_lost 4 | ||
| 3457 | #define R_SCSI1_STATUS__seq_status__info_sel_timeout 5 | ||
| 3458 | #define R_SCSI1_STATUS__seq_status__info_unexp_bf 6 | ||
| 3459 | #define R_SCSI1_STATUS__seq_status__info_illegal_op 7 | ||
| 3460 | #define R_SCSI1_STATUS__seq_status__info_rec_recvd 8 | ||
| 3461 | #define R_SCSI1_STATUS__seq_status__info_reselected 9 | ||
| 3462 | #define R_SCSI1_STATUS__seq_status__info_unhandled_status 10 | ||
| 3463 | #define R_SCSI1_STATUS__seq_status__info_bus_reset 11 | ||
| 3464 | #define R_SCSI1_STATUS__seq_status__info_illegal_bf 12 | ||
| 3465 | #define R_SCSI1_STATUS__seq_status__info_bus_free 13 | ||
| 3466 | |||
| 3467 | #define R_SCSI1_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000050) | ||
| 3468 | #define R_SCSI1_DATA_IN__data_in__BITNR 0 | ||
| 3469 | #define R_SCSI1_DATA_IN__data_in__WIDTH 16 | ||
| 3470 | |||
| 3471 | /* | ||
| 3472 | !* Interrupt mask and status registers | ||
| 3473 | !*/ | ||
| 3474 | |||
| 3475 | #define R_IRQ_MASK0_RD (IO_TYPECAST_RO_UDWORD 0xb00000c0) | ||
| 3476 | #define R_IRQ_MASK0_RD__nmi_pin__BITNR 31 | ||
| 3477 | #define R_IRQ_MASK0_RD__nmi_pin__WIDTH 1 | ||
| 3478 | #define R_IRQ_MASK0_RD__nmi_pin__active 1 | ||
| 3479 | #define R_IRQ_MASK0_RD__nmi_pin__inactive 0 | ||
| 3480 | #define R_IRQ_MASK0_RD__watchdog_nmi__BITNR 30 | ||
| 3481 | #define R_IRQ_MASK0_RD__watchdog_nmi__WIDTH 1 | ||
| 3482 | #define R_IRQ_MASK0_RD__watchdog_nmi__active 1 | ||
| 3483 | #define R_IRQ_MASK0_RD__watchdog_nmi__inactive 0 | ||
| 3484 | #define R_IRQ_MASK0_RD__sqe_test_error__BITNR 29 | ||
| 3485 | #define R_IRQ_MASK0_RD__sqe_test_error__WIDTH 1 | ||
| 3486 | #define R_IRQ_MASK0_RD__sqe_test_error__active 1 | ||
| 3487 | #define R_IRQ_MASK0_RD__sqe_test_error__inactive 0 | ||
| 3488 | #define R_IRQ_MASK0_RD__carrier_loss__BITNR 28 | ||
| 3489 | #define R_IRQ_MASK0_RD__carrier_loss__WIDTH 1 | ||
| 3490 | #define R_IRQ_MASK0_RD__carrier_loss__active 1 | ||
| 3491 | #define R_IRQ_MASK0_RD__carrier_loss__inactive 0 | ||
| 3492 | #define R_IRQ_MASK0_RD__deferred__BITNR 27 | ||
| 3493 | #define R_IRQ_MASK0_RD__deferred__WIDTH 1 | ||
| 3494 | #define R_IRQ_MASK0_RD__deferred__active 1 | ||
| 3495 | #define R_IRQ_MASK0_RD__deferred__inactive 0 | ||
| 3496 | #define R_IRQ_MASK0_RD__late_col__BITNR 26 | ||
| 3497 | #define R_IRQ_MASK0_RD__late_col__WIDTH 1 | ||
| 3498 | #define R_IRQ_MASK0_RD__late_col__active 1 | ||
| 3499 | #define R_IRQ_MASK0_RD__late_col__inactive 0 | ||
| 3500 | #define R_IRQ_MASK0_RD__multiple_col__BITNR 25 | ||
| 3501 | #define R_IRQ_MASK0_RD__multiple_col__WIDTH 1 | ||
| 3502 | #define R_IRQ_MASK0_RD__multiple_col__active 1 | ||
| 3503 | #define R_IRQ_MASK0_RD__multiple_col__inactive 0 | ||
| 3504 | #define R_IRQ_MASK0_RD__single_col__BITNR 24 | ||
| 3505 | #define R_IRQ_MASK0_RD__single_col__WIDTH 1 | ||
| 3506 | #define R_IRQ_MASK0_RD__single_col__active 1 | ||
| 3507 | #define R_IRQ_MASK0_RD__single_col__inactive 0 | ||
| 3508 | #define R_IRQ_MASK0_RD__congestion__BITNR 23 | ||
| 3509 | #define R_IRQ_MASK0_RD__congestion__WIDTH 1 | ||
| 3510 | #define R_IRQ_MASK0_RD__congestion__active 1 | ||
| 3511 | #define R_IRQ_MASK0_RD__congestion__inactive 0 | ||
| 3512 | #define R_IRQ_MASK0_RD__oversize__BITNR 22 | ||
| 3513 | #define R_IRQ_MASK0_RD__oversize__WIDTH 1 | ||
| 3514 | #define R_IRQ_MASK0_RD__oversize__active 1 | ||
| 3515 | #define R_IRQ_MASK0_RD__oversize__inactive 0 | ||
| 3516 | #define R_IRQ_MASK0_RD__alignment_error__BITNR 21 | ||
| 3517 | #define R_IRQ_MASK0_RD__alignment_error__WIDTH 1 | ||
| 3518 | #define R_IRQ_MASK0_RD__alignment_error__active 1 | ||
| 3519 | #define R_IRQ_MASK0_RD__alignment_error__inactive 0 | ||
| 3520 | #define R_IRQ_MASK0_RD__crc_error__BITNR 20 | ||
| 3521 | #define R_IRQ_MASK0_RD__crc_error__WIDTH 1 | ||
| 3522 | #define R_IRQ_MASK0_RD__crc_error__active 1 | ||
| 3523 | #define R_IRQ_MASK0_RD__crc_error__inactive 0 | ||
| 3524 | #define R_IRQ_MASK0_RD__overrun__BITNR 19 | ||
| 3525 | #define R_IRQ_MASK0_RD__overrun__WIDTH 1 | ||
| 3526 | #define R_IRQ_MASK0_RD__overrun__active 1 | ||
| 3527 | #define R_IRQ_MASK0_RD__overrun__inactive 0 | ||
| 3528 | #define R_IRQ_MASK0_RD__underrun__BITNR 18 | ||
| 3529 | #define R_IRQ_MASK0_RD__underrun__WIDTH 1 | ||
| 3530 | #define R_IRQ_MASK0_RD__underrun__active 1 | ||
| 3531 | #define R_IRQ_MASK0_RD__underrun__inactive 0 | ||
| 3532 | #define R_IRQ_MASK0_RD__excessive_col__BITNR 17 | ||
| 3533 | #define R_IRQ_MASK0_RD__excessive_col__WIDTH 1 | ||
| 3534 | #define R_IRQ_MASK0_RD__excessive_col__active 1 | ||
| 3535 | #define R_IRQ_MASK0_RD__excessive_col__inactive 0 | ||
| 3536 | #define R_IRQ_MASK0_RD__mdio__BITNR 16 | ||
| 3537 | #define R_IRQ_MASK0_RD__mdio__WIDTH 1 | ||
| 3538 | #define R_IRQ_MASK0_RD__mdio__active 1 | ||
| 3539 | #define R_IRQ_MASK0_RD__mdio__inactive 0 | ||
| 3540 | #define R_IRQ_MASK0_RD__ata_drq3__BITNR 15 | ||
| 3541 | #define R_IRQ_MASK0_RD__ata_drq3__WIDTH 1 | ||
| 3542 | #define R_IRQ_MASK0_RD__ata_drq3__active 1 | ||
| 3543 | #define R_IRQ_MASK0_RD__ata_drq3__inactive 0 | ||
| 3544 | #define R_IRQ_MASK0_RD__ata_drq2__BITNR 14 | ||
| 3545 | #define R_IRQ_MASK0_RD__ata_drq2__WIDTH 1 | ||
| 3546 | #define R_IRQ_MASK0_RD__ata_drq2__active 1 | ||
| 3547 | #define R_IRQ_MASK0_RD__ata_drq2__inactive 0 | ||
| 3548 | #define R_IRQ_MASK0_RD__ata_drq1__BITNR 13 | ||
| 3549 | #define R_IRQ_MASK0_RD__ata_drq1__WIDTH 1 | ||
| 3550 | #define R_IRQ_MASK0_RD__ata_drq1__active 1 | ||
| 3551 | #define R_IRQ_MASK0_RD__ata_drq1__inactive 0 | ||
| 3552 | #define R_IRQ_MASK0_RD__ata_drq0__BITNR 12 | ||
| 3553 | #define R_IRQ_MASK0_RD__ata_drq0__WIDTH 1 | ||
| 3554 | #define R_IRQ_MASK0_RD__ata_drq0__active 1 | ||
| 3555 | #define R_IRQ_MASK0_RD__ata_drq0__inactive 0 | ||
| 3556 | #define R_IRQ_MASK0_RD__par0_ecp_cmd__BITNR 11 | ||
| 3557 | #define R_IRQ_MASK0_RD__par0_ecp_cmd__WIDTH 1 | ||
| 3558 | #define R_IRQ_MASK0_RD__par0_ecp_cmd__active 1 | ||
| 3559 | #define R_IRQ_MASK0_RD__par0_ecp_cmd__inactive 0 | ||
| 3560 | #define R_IRQ_MASK0_RD__ata_irq3__BITNR 11 | ||
| 3561 | #define R_IRQ_MASK0_RD__ata_irq3__WIDTH 1 | ||
| 3562 | #define R_IRQ_MASK0_RD__ata_irq3__active 1 | ||
| 3563 | #define R_IRQ_MASK0_RD__ata_irq3__inactive 0 | ||
| 3564 | #define R_IRQ_MASK0_RD__par0_peri__BITNR 10 | ||
| 3565 | #define R_IRQ_MASK0_RD__par0_peri__WIDTH 1 | ||
| 3566 | #define R_IRQ_MASK0_RD__par0_peri__active 1 | ||
| 3567 | #define R_IRQ_MASK0_RD__par0_peri__inactive 0 | ||
| 3568 | #define R_IRQ_MASK0_RD__ata_irq2__BITNR 10 | ||
| 3569 | #define R_IRQ_MASK0_RD__ata_irq2__WIDTH 1 | ||
| 3570 | #define R_IRQ_MASK0_RD__ata_irq2__active 1 | ||
| 3571 | #define R_IRQ_MASK0_RD__ata_irq2__inactive 0 | ||
| 3572 | #define R_IRQ_MASK0_RD__par0_data__BITNR 9 | ||
| 3573 | #define R_IRQ_MASK0_RD__par0_data__WIDTH 1 | ||
| 3574 | #define R_IRQ_MASK0_RD__par0_data__active 1 | ||
| 3575 | #define R_IRQ_MASK0_RD__par0_data__inactive 0 | ||
| 3576 | #define R_IRQ_MASK0_RD__ata_irq1__BITNR 9 | ||
| 3577 | #define R_IRQ_MASK0_RD__ata_irq1__WIDTH 1 | ||
| 3578 | #define R_IRQ_MASK0_RD__ata_irq1__active 1 | ||
| 3579 | #define R_IRQ_MASK0_RD__ata_irq1__inactive 0 | ||
| 3580 | #define R_IRQ_MASK0_RD__par0_ready__BITNR 8 | ||
| 3581 | #define R_IRQ_MASK0_RD__par0_ready__WIDTH 1 | ||
| 3582 | #define R_IRQ_MASK0_RD__par0_ready__active 1 | ||
| 3583 | #define R_IRQ_MASK0_RD__par0_ready__inactive 0 | ||
| 3584 | #define R_IRQ_MASK0_RD__ata_irq0__BITNR 8 | ||
| 3585 | #define R_IRQ_MASK0_RD__ata_irq0__WIDTH 1 | ||
| 3586 | #define R_IRQ_MASK0_RD__ata_irq0__active 1 | ||
| 3587 | #define R_IRQ_MASK0_RD__ata_irq0__inactive 0 | ||
| 3588 | #define R_IRQ_MASK0_RD__mio__BITNR 8 | ||
| 3589 | #define R_IRQ_MASK0_RD__mio__WIDTH 1 | ||
| 3590 | #define R_IRQ_MASK0_RD__mio__active 1 | ||
| 3591 | #define R_IRQ_MASK0_RD__mio__inactive 0 | ||
| 3592 | #define R_IRQ_MASK0_RD__scsi0__BITNR 8 | ||
| 3593 | #define R_IRQ_MASK0_RD__scsi0__WIDTH 1 | ||
| 3594 | #define R_IRQ_MASK0_RD__scsi0__active 1 | ||
| 3595 | #define R_IRQ_MASK0_RD__scsi0__inactive 0 | ||
| 3596 | #define R_IRQ_MASK0_RD__ata_dmaend__BITNR 7 | ||
| 3597 | #define R_IRQ_MASK0_RD__ata_dmaend__WIDTH 1 | ||
| 3598 | #define R_IRQ_MASK0_RD__ata_dmaend__active 1 | ||
| 3599 | #define R_IRQ_MASK0_RD__ata_dmaend__inactive 0 | ||
| 3600 | #define R_IRQ_MASK0_RD__irq_ext_vector_nr__BITNR 5 | ||
| 3601 | #define R_IRQ_MASK0_RD__irq_ext_vector_nr__WIDTH 1 | ||
| 3602 | #define R_IRQ_MASK0_RD__irq_ext_vector_nr__active 1 | ||
| 3603 | #define R_IRQ_MASK0_RD__irq_ext_vector_nr__inactive 0 | ||
| 3604 | #define R_IRQ_MASK0_RD__irq_int_vector_nr__BITNR 4 | ||
| 3605 | #define R_IRQ_MASK0_RD__irq_int_vector_nr__WIDTH 1 | ||
| 3606 | #define R_IRQ_MASK0_RD__irq_int_vector_nr__active 1 | ||
| 3607 | #define R_IRQ_MASK0_RD__irq_int_vector_nr__inactive 0 | ||
| 3608 | #define R_IRQ_MASK0_RD__ext_dma1__BITNR 3 | ||
| 3609 | #define R_IRQ_MASK0_RD__ext_dma1__WIDTH 1 | ||
| 3610 | #define R_IRQ_MASK0_RD__ext_dma1__active 1 | ||
| 3611 | #define R_IRQ_MASK0_RD__ext_dma1__inactive 0 | ||
| 3612 | #define R_IRQ_MASK0_RD__ext_dma0__BITNR 2 | ||
| 3613 | #define R_IRQ_MASK0_RD__ext_dma0__WIDTH 1 | ||
| 3614 | #define R_IRQ_MASK0_RD__ext_dma0__active 1 | ||
| 3615 | #define R_IRQ_MASK0_RD__ext_dma0__inactive 0 | ||
| 3616 | #define R_IRQ_MASK0_RD__timer1__BITNR 1 | ||
| 3617 | #define R_IRQ_MASK0_RD__timer1__WIDTH 1 | ||
| 3618 | #define R_IRQ_MASK0_RD__timer1__active 1 | ||
| 3619 | #define R_IRQ_MASK0_RD__timer1__inactive 0 | ||
| 3620 | #define R_IRQ_MASK0_RD__timer0__BITNR 0 | ||
| 3621 | #define R_IRQ_MASK0_RD__timer0__WIDTH 1 | ||
| 3622 | #define R_IRQ_MASK0_RD__timer0__active 1 | ||
| 3623 | #define R_IRQ_MASK0_RD__timer0__inactive 0 | ||
| 3624 | |||
| 3625 | #define R_IRQ_MASK0_CLR (IO_TYPECAST_UDWORD 0xb00000c0) | ||
| 3626 | #define R_IRQ_MASK0_CLR__nmi_pin__BITNR 31 | ||
| 3627 | #define R_IRQ_MASK0_CLR__nmi_pin__WIDTH 1 | ||
| 3628 | #define R_IRQ_MASK0_CLR__nmi_pin__clr 1 | ||
| 3629 | #define R_IRQ_MASK0_CLR__nmi_pin__nop 0 | ||
| 3630 | #define R_IRQ_MASK0_CLR__watchdog_nmi__BITNR 30 | ||
| 3631 | #define R_IRQ_MASK0_CLR__watchdog_nmi__WIDTH 1 | ||
| 3632 | #define R_IRQ_MASK0_CLR__watchdog_nmi__clr 1 | ||
| 3633 | #define R_IRQ_MASK0_CLR__watchdog_nmi__nop 0 | ||
| 3634 | #define R_IRQ_MASK0_CLR__sqe_test_error__BITNR 29 | ||
| 3635 | #define R_IRQ_MASK0_CLR__sqe_test_error__WIDTH 1 | ||
| 3636 | #define R_IRQ_MASK0_CLR__sqe_test_error__clr 1 | ||
| 3637 | #define R_IRQ_MASK0_CLR__sqe_test_error__nop 0 | ||
| 3638 | #define R_IRQ_MASK0_CLR__carrier_loss__BITNR 28 | ||
| 3639 | #define R_IRQ_MASK0_CLR__carrier_loss__WIDTH 1 | ||
| 3640 | #define R_IRQ_MASK0_CLR__carrier_loss__clr 1 | ||
| 3641 | #define R_IRQ_MASK0_CLR__carrier_loss__nop 0 | ||
| 3642 | #define R_IRQ_MASK0_CLR__deferred__BITNR 27 | ||
| 3643 | #define R_IRQ_MASK0_CLR__deferred__WIDTH 1 | ||
| 3644 | #define R_IRQ_MASK0_CLR__deferred__clr 1 | ||
| 3645 | #define R_IRQ_MASK0_CLR__deferred__nop 0 | ||
| 3646 | #define R_IRQ_MASK0_CLR__late_col__BITNR 26 | ||
| 3647 | #define R_IRQ_MASK0_CLR__late_col__WIDTH 1 | ||
| 3648 | #define R_IRQ_MASK0_CLR__late_col__clr 1 | ||
| 3649 | #define R_IRQ_MASK0_CLR__late_col__nop 0 | ||
| 3650 | #define R_IRQ_MASK0_CLR__multiple_col__BITNR 25 | ||
| 3651 | #define R_IRQ_MASK0_CLR__multiple_col__WIDTH 1 | ||
| 3652 | #define R_IRQ_MASK0_CLR__multiple_col__clr 1 | ||
| 3653 | #define R_IRQ_MASK0_CLR__multiple_col__nop 0 | ||
| 3654 | #define R_IRQ_MASK0_CLR__single_col__BITNR 24 | ||
| 3655 | #define R_IRQ_MASK0_CLR__single_col__WIDTH 1 | ||
| 3656 | #define R_IRQ_MASK0_CLR__single_col__clr 1 | ||
| 3657 | #define R_IRQ_MASK0_CLR__single_col__nop 0 | ||
| 3658 | #define R_IRQ_MASK0_CLR__congestion__BITNR 23 | ||
| 3659 | #define R_IRQ_MASK0_CLR__congestion__WIDTH 1 | ||
| 3660 | #define R_IRQ_MASK0_CLR__congestion__clr 1 | ||
| 3661 | #define R_IRQ_MASK0_CLR__congestion__nop 0 | ||
| 3662 | #define R_IRQ_MASK0_CLR__oversize__BITNR 22 | ||
| 3663 | #define R_IRQ_MASK0_CLR__oversize__WIDTH 1 | ||
| 3664 | #define R_IRQ_MASK0_CLR__oversize__clr 1 | ||
| 3665 | #define R_IRQ_MASK0_CLR__oversize__nop 0 | ||
| 3666 | #define R_IRQ_MASK0_CLR__alignment_error__BITNR 21 | ||
| 3667 | #define R_IRQ_MASK0_CLR__alignment_error__WIDTH 1 | ||
| 3668 | #define R_IRQ_MASK0_CLR__alignment_error__clr 1 | ||
| 3669 | #define R_IRQ_MASK0_CLR__alignment_error__nop 0 | ||
| 3670 | #define R_IRQ_MASK0_CLR__crc_error__BITNR 20 | ||
| 3671 | #define R_IRQ_MASK0_CLR__crc_error__WIDTH 1 | ||
| 3672 | #define R_IRQ_MASK0_CLR__crc_error__clr 1 | ||
| 3673 | #define R_IRQ_MASK0_CLR__crc_error__nop 0 | ||
| 3674 | #define R_IRQ_MASK0_CLR__overrun__BITNR 19 | ||
| 3675 | #define R_IRQ_MASK0_CLR__overrun__WIDTH 1 | ||
| 3676 | #define R_IRQ_MASK0_CLR__overrun__clr 1 | ||
| 3677 | #define R_IRQ_MASK0_CLR__overrun__nop 0 | ||
| 3678 | #define R_IRQ_MASK0_CLR__underrun__BITNR 18 | ||
| 3679 | #define R_IRQ_MASK0_CLR__underrun__WIDTH 1 | ||
| 3680 | #define R_IRQ_MASK0_CLR__underrun__clr 1 | ||
| 3681 | #define R_IRQ_MASK0_CLR__underrun__nop 0 | ||
| 3682 | #define R_IRQ_MASK0_CLR__excessive_col__BITNR 17 | ||
| 3683 | #define R_IRQ_MASK0_CLR__excessive_col__WIDTH 1 | ||
| 3684 | #define R_IRQ_MASK0_CLR__excessive_col__clr 1 | ||
| 3685 | #define R_IRQ_MASK0_CLR__excessive_col__nop 0 | ||
| 3686 | #define R_IRQ_MASK0_CLR__mdio__BITNR 16 | ||
| 3687 | #define R_IRQ_MASK0_CLR__mdio__WIDTH 1 | ||
| 3688 | #define R_IRQ_MASK0_CLR__mdio__clr 1 | ||
| 3689 | #define R_IRQ_MASK0_CLR__mdio__nop 0 | ||
| 3690 | #define R_IRQ_MASK0_CLR__ata_drq3__BITNR 15 | ||
| 3691 | #define R_IRQ_MASK0_CLR__ata_drq3__WIDTH 1 | ||
| 3692 | #define R_IRQ_MASK0_CLR__ata_drq3__clr 1 | ||
| 3693 | #define R_IRQ_MASK0_CLR__ata_drq3__nop 0 | ||
| 3694 | #define R_IRQ_MASK0_CLR__ata_drq2__BITNR 14 | ||
| 3695 | #define R_IRQ_MASK0_CLR__ata_drq2__WIDTH 1 | ||
| 3696 | #define R_IRQ_MASK0_CLR__ata_drq2__clr 1 | ||
| 3697 | #define R_IRQ_MASK0_CLR__ata_drq2__nop 0 | ||
| 3698 | #define R_IRQ_MASK0_CLR__ata_drq1__BITNR 13 | ||
| 3699 | #define R_IRQ_MASK0_CLR__ata_drq1__WIDTH 1 | ||
| 3700 | #define R_IRQ_MASK0_CLR__ata_drq1__clr 1 | ||
| 3701 | #define R_IRQ_MASK0_CLR__ata_drq1__nop 0 | ||
| 3702 | #define R_IRQ_MASK0_CLR__ata_drq0__BITNR 12 | ||
| 3703 | #define R_IRQ_MASK0_CLR__ata_drq0__WIDTH 1 | ||
| 3704 | #define R_IRQ_MASK0_CLR__ata_drq0__clr 1 | ||
| 3705 | #define R_IRQ_MASK0_CLR__ata_drq0__nop 0 | ||
| 3706 | #define R_IRQ_MASK0_CLR__par0_ecp_cmd__BITNR 11 | ||
| 3707 | #define R_IRQ_MASK0_CLR__par0_ecp_cmd__WIDTH 1 | ||
| 3708 | #define R_IRQ_MASK0_CLR__par0_ecp_cmd__clr 1 | ||
| 3709 | #define R_IRQ_MASK0_CLR__par0_ecp_cmd__nop 0 | ||
| 3710 | #define R_IRQ_MASK0_CLR__ata_irq3__BITNR 11 | ||
| 3711 | #define R_IRQ_MASK0_CLR__ata_irq3__WIDTH 1 | ||
| 3712 | #define R_IRQ_MASK0_CLR__ata_irq3__clr 1 | ||
| 3713 | #define R_IRQ_MASK0_CLR__ata_irq3__nop 0 | ||
| 3714 | #define R_IRQ_MASK0_CLR__par0_peri__BITNR 10 | ||
| 3715 | #define R_IRQ_MASK0_CLR__par0_peri__WIDTH 1 | ||
| 3716 | #define R_IRQ_MASK0_CLR__par0_peri__clr 1 | ||
| 3717 | #define R_IRQ_MASK0_CLR__par0_peri__nop 0 | ||
| 3718 | #define R_IRQ_MASK0_CLR__ata_irq2__BITNR 10 | ||
| 3719 | #define R_IRQ_MASK0_CLR__ata_irq2__WIDTH 1 | ||
| 3720 | #define R_IRQ_MASK0_CLR__ata_irq2__clr 1 | ||
| 3721 | #define R_IRQ_MASK0_CLR__ata_irq2__nop 0 | ||
| 3722 | #define R_IRQ_MASK0_CLR__par0_data__BITNR 9 | ||
| 3723 | #define R_IRQ_MASK0_CLR__par0_data__WIDTH 1 | ||
| 3724 | #define R_IRQ_MASK0_CLR__par0_data__clr 1 | ||
| 3725 | #define R_IRQ_MASK0_CLR__par0_data__nop 0 | ||
| 3726 | #define R_IRQ_MASK0_CLR__ata_irq1__BITNR 9 | ||
| 3727 | #define R_IRQ_MASK0_CLR__ata_irq1__WIDTH 1 | ||
| 3728 | #define R_IRQ_MASK0_CLR__ata_irq1__clr 1 | ||
| 3729 | #define R_IRQ_MASK0_CLR__ata_irq1__nop 0 | ||
| 3730 | #define R_IRQ_MASK0_CLR__par0_ready__BITNR 8 | ||
| 3731 | #define R_IRQ_MASK0_CLR__par0_ready__WIDTH 1 | ||
| 3732 | #define R_IRQ_MASK0_CLR__par0_ready__clr 1 | ||
| 3733 | #define R_IRQ_MASK0_CLR__par0_ready__nop 0 | ||
| 3734 | #define R_IRQ_MASK0_CLR__ata_irq0__BITNR 8 | ||
| 3735 | #define R_IRQ_MASK0_CLR__ata_irq0__WIDTH 1 | ||
| 3736 | #define R_IRQ_MASK0_CLR__ata_irq0__clr 1 | ||
| 3737 | #define R_IRQ_MASK0_CLR__ata_irq0__nop 0 | ||
| 3738 | #define R_IRQ_MASK0_CLR__mio__BITNR 8 | ||
| 3739 | #define R_IRQ_MASK0_CLR__mio__WIDTH 1 | ||
| 3740 | #define R_IRQ_MASK0_CLR__mio__clr 1 | ||
| 3741 | #define R_IRQ_MASK0_CLR__mio__nop 0 | ||
| 3742 | #define R_IRQ_MASK0_CLR__scsi0__BITNR 8 | ||
| 3743 | #define R_IRQ_MASK0_CLR__scsi0__WIDTH 1 | ||
| 3744 | #define R_IRQ_MASK0_CLR__scsi0__clr 1 | ||
| 3745 | #define R_IRQ_MASK0_CLR__scsi0__nop 0 | ||
| 3746 | #define R_IRQ_MASK0_CLR__ata_dmaend__BITNR 7 | ||
| 3747 | #define R_IRQ_MASK0_CLR__ata_dmaend__WIDTH 1 | ||
| 3748 | #define R_IRQ_MASK0_CLR__ata_dmaend__clr 1 | ||
| 3749 | #define R_IRQ_MASK0_CLR__ata_dmaend__nop 0 | ||
| 3750 | #define R_IRQ_MASK0_CLR__irq_ext_vector_nr__BITNR 5 | ||
| 3751 | #define R_IRQ_MASK0_CLR__irq_ext_vector_nr__WIDTH 1 | ||
| 3752 | #define R_IRQ_MASK0_CLR__irq_ext_vector_nr__clr 1 | ||
| 3753 | #define R_IRQ_MASK0_CLR__irq_ext_vector_nr__nop 0 | ||
| 3754 | #define R_IRQ_MASK0_CLR__irq_int_vector_nr__BITNR 4 | ||
| 3755 | #define R_IRQ_MASK0_CLR__irq_int_vector_nr__WIDTH 1 | ||
| 3756 | #define R_IRQ_MASK0_CLR__irq_int_vector_nr__clr 1 | ||
| 3757 | #define R_IRQ_MASK0_CLR__irq_int_vector_nr__nop 0 | ||
| 3758 | #define R_IRQ_MASK0_CLR__ext_dma1__BITNR 3 | ||
| 3759 | #define R_IRQ_MASK0_CLR__ext_dma1__WIDTH 1 | ||
| 3760 | #define R_IRQ_MASK0_CLR__ext_dma1__clr 1 | ||
| 3761 | #define R_IRQ_MASK0_CLR__ext_dma1__nop 0 | ||
| 3762 | #define R_IRQ_MASK0_CLR__ext_dma0__BITNR 2 | ||
| 3763 | #define R_IRQ_MASK0_CLR__ext_dma0__WIDTH 1 | ||
| 3764 | #define R_IRQ_MASK0_CLR__ext_dma0__clr 1 | ||
| 3765 | #define R_IRQ_MASK0_CLR__ext_dma0__nop 0 | ||
| 3766 | #define R_IRQ_MASK0_CLR__timer1__BITNR 1 | ||
| 3767 | #define R_IRQ_MASK0_CLR__timer1__WIDTH 1 | ||
| 3768 | #define R_IRQ_MASK0_CLR__timer1__clr 1 | ||
| 3769 | #define R_IRQ_MASK0_CLR__timer1__nop 0 | ||
| 3770 | #define R_IRQ_MASK0_CLR__timer0__BITNR 0 | ||
| 3771 | #define R_IRQ_MASK0_CLR__timer0__WIDTH 1 | ||
| 3772 | #define R_IRQ_MASK0_CLR__timer0__clr 1 | ||
| 3773 | #define R_IRQ_MASK0_CLR__timer0__nop 0 | ||
| 3774 | |||
| 3775 | #define R_IRQ_READ0 (IO_TYPECAST_RO_UDWORD 0xb00000c4) | ||
| 3776 | #define R_IRQ_READ0__nmi_pin__BITNR 31 | ||
| 3777 | #define R_IRQ_READ0__nmi_pin__WIDTH 1 | ||
| 3778 | #define R_IRQ_READ0__nmi_pin__active 1 | ||
| 3779 | #define R_IRQ_READ0__nmi_pin__inactive 0 | ||
| 3780 | #define R_IRQ_READ0__watchdog_nmi__BITNR 30 | ||
| 3781 | #define R_IRQ_READ0__watchdog_nmi__WIDTH 1 | ||
| 3782 | #define R_IRQ_READ0__watchdog_nmi__active 1 | ||
| 3783 | #define R_IRQ_READ0__watchdog_nmi__inactive 0 | ||
| 3784 | #define R_IRQ_READ0__sqe_test_error__BITNR 29 | ||
| 3785 | #define R_IRQ_READ0__sqe_test_error__WIDTH 1 | ||
| 3786 | #define R_IRQ_READ0__sqe_test_error__active 1 | ||
| 3787 | #define R_IRQ_READ0__sqe_test_error__inactive 0 | ||
| 3788 | #define R_IRQ_READ0__carrier_loss__BITNR 28 | ||
| 3789 | #define R_IRQ_READ0__carrier_loss__WIDTH 1 | ||
| 3790 | #define R_IRQ_READ0__carrier_loss__active 1 | ||
| 3791 | #define R_IRQ_READ0__carrier_loss__inactive 0 | ||
| 3792 | #define R_IRQ_READ0__deferred__BITNR 27 | ||
| 3793 | #define R_IRQ_READ0__deferred__WIDTH 1 | ||
| 3794 | #define R_IRQ_READ0__deferred__active 1 | ||
| 3795 | #define R_IRQ_READ0__deferred__inactive 0 | ||
| 3796 | #define R_IRQ_READ0__late_col__BITNR 26 | ||
| 3797 | #define R_IRQ_READ0__late_col__WIDTH 1 | ||
| 3798 | #define R_IRQ_READ0__late_col__active 1 | ||
| 3799 | #define R_IRQ_READ0__late_col__inactive 0 | ||
| 3800 | #define R_IRQ_READ0__multiple_col__BITNR 25 | ||
| 3801 | #define R_IRQ_READ0__multiple_col__WIDTH 1 | ||
| 3802 | #define R_IRQ_READ0__multiple_col__active 1 | ||
| 3803 | #define R_IRQ_READ0__multiple_col__inactive 0 | ||
| 3804 | #define R_IRQ_READ0__single_col__BITNR 24 | ||
| 3805 | #define R_IRQ_READ0__single_col__WIDTH 1 | ||
| 3806 | #define R_IRQ_READ0__single_col__active 1 | ||
| 3807 | #define R_IRQ_READ0__single_col__inactive 0 | ||
| 3808 | #define R_IRQ_READ0__congestion__BITNR 23 | ||
| 3809 | #define R_IRQ_READ0__congestion__WIDTH 1 | ||
| 3810 | #define R_IRQ_READ0__congestion__active 1 | ||
| 3811 | #define R_IRQ_READ0__congestion__inactive 0 | ||
| 3812 | #define R_IRQ_READ0__oversize__BITNR 22 | ||
| 3813 | #define R_IRQ_READ0__oversize__WIDTH 1 | ||
| 3814 | #define R_IRQ_READ0__oversize__active 1 | ||
| 3815 | #define R_IRQ_READ0__oversize__inactive 0 | ||
| 3816 | #define R_IRQ_READ0__alignment_error__BITNR 21 | ||
| 3817 | #define R_IRQ_READ0__alignment_error__WIDTH 1 | ||
| 3818 | #define R_IRQ_READ0__alignment_error__active 1 | ||
| 3819 | #define R_IRQ_READ0__alignment_error__inactive 0 | ||
| 3820 | #define R_IRQ_READ0__crc_error__BITNR 20 | ||
| 3821 | #define R_IRQ_READ0__crc_error__WIDTH 1 | ||
| 3822 | #define R_IRQ_READ0__crc_error__active 1 | ||
| 3823 | #define R_IRQ_READ0__crc_error__inactive 0 | ||
| 3824 | #define R_IRQ_READ0__overrun__BITNR 19 | ||
| 3825 | #define R_IRQ_READ0__overrun__WIDTH 1 | ||
| 3826 | #define R_IRQ_READ0__overrun__active 1 | ||
| 3827 | #define R_IRQ_READ0__overrun__inactive 0 | ||
| 3828 | #define R_IRQ_READ0__underrun__BITNR 18 | ||
| 3829 | #define R_IRQ_READ0__underrun__WIDTH 1 | ||
| 3830 | #define R_IRQ_READ0__underrun__active 1 | ||
| 3831 | #define R_IRQ_READ0__underrun__inactive 0 | ||
| 3832 | #define R_IRQ_READ0__excessive_col__BITNR 17 | ||
| 3833 | #define R_IRQ_READ0__excessive_col__WIDTH 1 | ||
| 3834 | #define R_IRQ_READ0__excessive_col__active 1 | ||
| 3835 | #define R_IRQ_READ0__excessive_col__inactive 0 | ||
| 3836 | #define R_IRQ_READ0__mdio__BITNR 16 | ||
| 3837 | #define R_IRQ_READ0__mdio__WIDTH 1 | ||
| 3838 | #define R_IRQ_READ0__mdio__active 1 | ||
| 3839 | #define R_IRQ_READ0__mdio__inactive 0 | ||
| 3840 | #define R_IRQ_READ0__ata_drq3__BITNR 15 | ||
| 3841 | #define R_IRQ_READ0__ata_drq3__WIDTH 1 | ||
| 3842 | #define R_IRQ_READ0__ata_drq3__active 1 | ||
| 3843 | #define R_IRQ_READ0__ata_drq3__inactive 0 | ||
| 3844 | #define R_IRQ_READ0__ata_drq2__BITNR 14 | ||
| 3845 | #define R_IRQ_READ0__ata_drq2__WIDTH 1 | ||
| 3846 | #define R_IRQ_READ0__ata_drq2__active 1 | ||
| 3847 | #define R_IRQ_READ0__ata_drq2__inactive 0 | ||
| 3848 | #define R_IRQ_READ0__ata_drq1__BITNR 13 | ||
| 3849 | #define R_IRQ_READ0__ata_drq1__WIDTH 1 | ||
| 3850 | #define R_IRQ_READ0__ata_drq1__active 1 | ||
| 3851 | #define R_IRQ_READ0__ata_drq1__inactive 0 | ||
| 3852 | #define R_IRQ_READ0__ata_drq0__BITNR 12 | ||
| 3853 | #define R_IRQ_READ0__ata_drq0__WIDTH 1 | ||
| 3854 | #define R_IRQ_READ0__ata_drq0__active 1 | ||
| 3855 | #define R_IRQ_READ0__ata_drq0__inactive 0 | ||
| 3856 | #define R_IRQ_READ0__par0_ecp_cmd__BITNR 11 | ||
| 3857 | #define R_IRQ_READ0__par0_ecp_cmd__WIDTH 1 | ||
| 3858 | #define R_IRQ_READ0__par0_ecp_cmd__active 1 | ||
| 3859 | #define R_IRQ_READ0__par0_ecp_cmd__inactive 0 | ||
| 3860 | #define R_IRQ_READ0__ata_irq3__BITNR 11 | ||
| 3861 | #define R_IRQ_READ0__ata_irq3__WIDTH 1 | ||
| 3862 | #define R_IRQ_READ0__ata_irq3__active 1 | ||
| 3863 | #define R_IRQ_READ0__ata_irq3__inactive 0 | ||
| 3864 | #define R_IRQ_READ0__par0_peri__BITNR 10 | ||
| 3865 | #define R_IRQ_READ0__par0_peri__WIDTH 1 | ||
| 3866 | #define R_IRQ_READ0__par0_peri__active 1 | ||
| 3867 | #define R_IRQ_READ0__par0_peri__inactive 0 | ||
| 3868 | #define R_IRQ_READ0__ata_irq2__BITNR 10 | ||
| 3869 | #define R_IRQ_READ0__ata_irq2__WIDTH 1 | ||
| 3870 | #define R_IRQ_READ0__ata_irq2__active 1 | ||
| 3871 | #define R_IRQ_READ0__ata_irq2__inactive 0 | ||
| 3872 | #define R_IRQ_READ0__par0_data__BITNR 9 | ||
| 3873 | #define R_IRQ_READ0__par0_data__WIDTH 1 | ||
| 3874 | #define R_IRQ_READ0__par0_data__active 1 | ||
| 3875 | #define R_IRQ_READ0__par0_data__inactive 0 | ||
| 3876 | #define R_IRQ_READ0__ata_irq1__BITNR 9 | ||
| 3877 | #define R_IRQ_READ0__ata_irq1__WIDTH 1 | ||
| 3878 | #define R_IRQ_READ0__ata_irq1__active 1 | ||
| 3879 | #define R_IRQ_READ0__ata_irq1__inactive 0 | ||
| 3880 | #define R_IRQ_READ0__par0_ready__BITNR 8 | ||
| 3881 | #define R_IRQ_READ0__par0_ready__WIDTH 1 | ||
| 3882 | #define R_IRQ_READ0__par0_ready__active 1 | ||
| 3883 | #define R_IRQ_READ0__par0_ready__inactive 0 | ||
| 3884 | #define R_IRQ_READ0__ata_irq0__BITNR 8 | ||
| 3885 | #define R_IRQ_READ0__ata_irq0__WIDTH 1 | ||
| 3886 | #define R_IRQ_READ0__ata_irq0__active 1 | ||
| 3887 | #define R_IRQ_READ0__ata_irq0__inactive 0 | ||
| 3888 | #define R_IRQ_READ0__mio__BITNR 8 | ||
| 3889 | #define R_IRQ_READ0__mio__WIDTH 1 | ||
| 3890 | #define R_IRQ_READ0__mio__active 1 | ||
| 3891 | #define R_IRQ_READ0__mio__inactive 0 | ||
| 3892 | #define R_IRQ_READ0__scsi0__BITNR 8 | ||
| 3893 | #define R_IRQ_READ0__scsi0__WIDTH 1 | ||
| 3894 | #define R_IRQ_READ0__scsi0__active 1 | ||
| 3895 | #define R_IRQ_READ0__scsi0__inactive 0 | ||
| 3896 | #define R_IRQ_READ0__ata_dmaend__BITNR 7 | ||
| 3897 | #define R_IRQ_READ0__ata_dmaend__WIDTH 1 | ||
| 3898 | #define R_IRQ_READ0__ata_dmaend__active 1 | ||
| 3899 | #define R_IRQ_READ0__ata_dmaend__inactive 0 | ||
| 3900 | #define R_IRQ_READ0__irq_ext_vector_nr__BITNR 5 | ||
| 3901 | #define R_IRQ_READ0__irq_ext_vector_nr__WIDTH 1 | ||
| 3902 | #define R_IRQ_READ0__irq_ext_vector_nr__active 1 | ||
| 3903 | #define R_IRQ_READ0__irq_ext_vector_nr__inactive 0 | ||
| 3904 | #define R_IRQ_READ0__irq_int_vector_nr__BITNR 4 | ||
| 3905 | #define R_IRQ_READ0__irq_int_vector_nr__WIDTH 1 | ||
| 3906 | #define R_IRQ_READ0__irq_int_vector_nr__active 1 | ||
| 3907 | #define R_IRQ_READ0__irq_int_vector_nr__inactive 0 | ||
| 3908 | #define R_IRQ_READ0__ext_dma1__BITNR 3 | ||
| 3909 | #define R_IRQ_READ0__ext_dma1__WIDTH 1 | ||
| 3910 | #define R_IRQ_READ0__ext_dma1__active 1 | ||
| 3911 | #define R_IRQ_READ0__ext_dma1__inactive 0 | ||
| 3912 | #define R_IRQ_READ0__ext_dma0__BITNR 2 | ||
| 3913 | #define R_IRQ_READ0__ext_dma0__WIDTH 1 | ||
| 3914 | #define R_IRQ_READ0__ext_dma0__active 1 | ||
| 3915 | #define R_IRQ_READ0__ext_dma0__inactive 0 | ||
| 3916 | #define R_IRQ_READ0__timer1__BITNR 1 | ||
| 3917 | #define R_IRQ_READ0__timer1__WIDTH 1 | ||
| 3918 | #define R_IRQ_READ0__timer1__active 1 | ||
| 3919 | #define R_IRQ_READ0__timer1__inactive 0 | ||
| 3920 | #define R_IRQ_READ0__timer0__BITNR 0 | ||
| 3921 | #define R_IRQ_READ0__timer0__WIDTH 1 | ||
| 3922 | #define R_IRQ_READ0__timer0__active 1 | ||
| 3923 | #define R_IRQ_READ0__timer0__inactive 0 | ||
| 3924 | |||
| 3925 | #define R_IRQ_MASK0_SET (IO_TYPECAST_UDWORD 0xb00000c4) | ||
| 3926 | #define R_IRQ_MASK0_SET__nmi_pin__BITNR 31 | ||
| 3927 | #define R_IRQ_MASK0_SET__nmi_pin__WIDTH 1 | ||
| 3928 | #define R_IRQ_MASK0_SET__nmi_pin__set 1 | ||
| 3929 | #define R_IRQ_MASK0_SET__nmi_pin__nop 0 | ||
| 3930 | #define R_IRQ_MASK0_SET__watchdog_nmi__BITNR 30 | ||
| 3931 | #define R_IRQ_MASK0_SET__watchdog_nmi__WIDTH 1 | ||
| 3932 | #define R_IRQ_MASK0_SET__watchdog_nmi__set 1 | ||
| 3933 | #define R_IRQ_MASK0_SET__watchdog_nmi__nop 0 | ||
| 3934 | #define R_IRQ_MASK0_SET__sqe_test_error__BITNR 29 | ||
| 3935 | #define R_IRQ_MASK0_SET__sqe_test_error__WIDTH 1 | ||
| 3936 | #define R_IRQ_MASK0_SET__sqe_test_error__set 1 | ||
| 3937 | #define R_IRQ_MASK0_SET__sqe_test_error__nop 0 | ||
| 3938 | #define R_IRQ_MASK0_SET__carrier_loss__BITNR 28 | ||
| 3939 | #define R_IRQ_MASK0_SET__carrier_loss__WIDTH 1 | ||
| 3940 | #define R_IRQ_MASK0_SET__carrier_loss__set 1 | ||
| 3941 | #define R_IRQ_MASK0_SET__carrier_loss__nop 0 | ||
| 3942 | #define R_IRQ_MASK0_SET__deferred__BITNR 27 | ||
| 3943 | #define R_IRQ_MASK0_SET__deferred__WIDTH 1 | ||
| 3944 | #define R_IRQ_MASK0_SET__deferred__set 1 | ||
| 3945 | #define R_IRQ_MASK0_SET__deferred__nop 0 | ||
| 3946 | #define R_IRQ_MASK0_SET__late_col__BITNR 26 | ||
| 3947 | #define R_IRQ_MASK0_SET__late_col__WIDTH 1 | ||
| 3948 | #define R_IRQ_MASK0_SET__late_col__set 1 | ||
| 3949 | #define R_IRQ_MASK0_SET__late_col__nop 0 | ||
| 3950 | #define R_IRQ_MASK0_SET__multiple_col__BITNR 25 | ||
| 3951 | #define R_IRQ_MASK0_SET__multiple_col__WIDTH 1 | ||
| 3952 | #define R_IRQ_MASK0_SET__multiple_col__set 1 | ||
| 3953 | #define R_IRQ_MASK0_SET__multiple_col__nop 0 | ||
| 3954 | #define R_IRQ_MASK0_SET__single_col__BITNR 24 | ||
| 3955 | #define R_IRQ_MASK0_SET__single_col__WIDTH 1 | ||
| 3956 | #define R_IRQ_MASK0_SET__single_col__set 1 | ||
| 3957 | #define R_IRQ_MASK0_SET__single_col__nop 0 | ||
| 3958 | #define R_IRQ_MASK0_SET__congestion__BITNR 23 | ||
| 3959 | #define R_IRQ_MASK0_SET__congestion__WIDTH 1 | ||
| 3960 | #define R_IRQ_MASK0_SET__congestion__set 1 | ||
| 3961 | #define R_IRQ_MASK0_SET__congestion__nop 0 | ||
| 3962 | #define R_IRQ_MASK0_SET__oversize__BITNR 22 | ||
| 3963 | #define R_IRQ_MASK0_SET__oversize__WIDTH 1 | ||
| 3964 | #define R_IRQ_MASK0_SET__oversize__set 1 | ||
| 3965 | #define R_IRQ_MASK0_SET__oversize__nop 0 | ||
| 3966 | #define R_IRQ_MASK0_SET__alignment_error__BITNR 21 | ||
| 3967 | #define R_IRQ_MASK0_SET__alignment_error__WIDTH 1 | ||
| 3968 | #define R_IRQ_MASK0_SET__alignment_error__set 1 | ||
| 3969 | #define R_IRQ_MASK0_SET__alignment_error__nop 0 | ||
| 3970 | #define R_IRQ_MASK0_SET__crc_error__BITNR 20 | ||
| 3971 | #define R_IRQ_MASK0_SET__crc_error__WIDTH 1 | ||
| 3972 | #define R_IRQ_MASK0_SET__crc_error__set 1 | ||
| 3973 | #define R_IRQ_MASK0_SET__crc_error__nop 0 | ||
| 3974 | #define R_IRQ_MASK0_SET__overrun__BITNR 19 | ||
| 3975 | #define R_IRQ_MASK0_SET__overrun__WIDTH 1 | ||
| 3976 | #define R_IRQ_MASK0_SET__overrun__set 1 | ||
| 3977 | #define R_IRQ_MASK0_SET__overrun__nop 0 | ||
| 3978 | #define R_IRQ_MASK0_SET__underrun__BITNR 18 | ||
| 3979 | #define R_IRQ_MASK0_SET__underrun__WIDTH 1 | ||
| 3980 | #define R_IRQ_MASK0_SET__underrun__set 1 | ||
| 3981 | #define R_IRQ_MASK0_SET__underrun__nop 0 | ||
| 3982 | #define R_IRQ_MASK0_SET__excessive_col__BITNR 17 | ||
| 3983 | #define R_IRQ_MASK0_SET__excessive_col__WIDTH 1 | ||
| 3984 | #define R_IRQ_MASK0_SET__excessive_col__set 1 | ||
| 3985 | #define R_IRQ_MASK0_SET__excessive_col__nop 0 | ||
| 3986 | #define R_IRQ_MASK0_SET__mdio__BITNR 16 | ||
| 3987 | #define R_IRQ_MASK0_SET__mdio__WIDTH 1 | ||
| 3988 | #define R_IRQ_MASK0_SET__mdio__set 1 | ||
| 3989 | #define R_IRQ_MASK0_SET__mdio__nop 0 | ||
| 3990 | #define R_IRQ_MASK0_SET__ata_drq3__BITNR 15 | ||
| 3991 | #define R_IRQ_MASK0_SET__ata_drq3__WIDTH 1 | ||
| 3992 | #define R_IRQ_MASK0_SET__ata_drq3__set 1 | ||
| 3993 | #define R_IRQ_MASK0_SET__ata_drq3__nop 0 | ||
| 3994 | #define R_IRQ_MASK0_SET__ata_drq2__BITNR 14 | ||
| 3995 | #define R_IRQ_MASK0_SET__ata_drq2__WIDTH 1 | ||
| 3996 | #define R_IRQ_MASK0_SET__ata_drq2__set 1 | ||
| 3997 | #define R_IRQ_MASK0_SET__ata_drq2__nop 0 | ||
| 3998 | #define R_IRQ_MASK0_SET__ata_drq1__BITNR 13 | ||
| 3999 | #define R_IRQ_MASK0_SET__ata_drq1__WIDTH 1 | ||
| 4000 | #define R_IRQ_MASK0_SET__ata_drq1__set 1 | ||
| 4001 | #define R_IRQ_MASK0_SET__ata_drq1__nop 0 | ||
| 4002 | #define R_IRQ_MASK0_SET__ata_drq0__BITNR 12 | ||
| 4003 | #define R_IRQ_MASK0_SET__ata_drq0__WIDTH 1 | ||
| 4004 | #define R_IRQ_MASK0_SET__ata_drq0__set 1 | ||
| 4005 | #define R_IRQ_MASK0_SET__ata_drq0__nop 0 | ||
| 4006 | #define R_IRQ_MASK0_SET__par0_ecp_cmd__BITNR 11 | ||
| 4007 | #define R_IRQ_MASK0_SET__par0_ecp_cmd__WIDTH 1 | ||
| 4008 | #define R_IRQ_MASK0_SET__par0_ecp_cmd__set 1 | ||
| 4009 | #define R_IRQ_MASK0_SET__par0_ecp_cmd__nop 0 | ||
| 4010 | #define R_IRQ_MASK0_SET__ata_irq3__BITNR 11 | ||
| 4011 | #define R_IRQ_MASK0_SET__ata_irq3__WIDTH 1 | ||
| 4012 | #define R_IRQ_MASK0_SET__ata_irq3__set 1 | ||
| 4013 | #define R_IRQ_MASK0_SET__ata_irq3__nop 0 | ||
| 4014 | #define R_IRQ_MASK0_SET__par0_peri__BITNR 10 | ||
| 4015 | #define R_IRQ_MASK0_SET__par0_peri__WIDTH 1 | ||
| 4016 | #define R_IRQ_MASK0_SET__par0_peri__set 1 | ||
| 4017 | #define R_IRQ_MASK0_SET__par0_peri__nop 0 | ||
| 4018 | #define R_IRQ_MASK0_SET__ata_irq2__BITNR 10 | ||
| 4019 | #define R_IRQ_MASK0_SET__ata_irq2__WIDTH 1 | ||
| 4020 | #define R_IRQ_MASK0_SET__ata_irq2__set 1 | ||
| 4021 | #define R_IRQ_MASK0_SET__ata_irq2__nop 0 | ||
| 4022 | #define R_IRQ_MASK0_SET__par0_data__BITNR 9 | ||
| 4023 | #define R_IRQ_MASK0_SET__par0_data__WIDTH 1 | ||
| 4024 | #define R_IRQ_MASK0_SET__par0_data__set 1 | ||
| 4025 | #define R_IRQ_MASK0_SET__par0_data__nop 0 | ||
| 4026 | #define R_IRQ_MASK0_SET__ata_irq1__BITNR 9 | ||
| 4027 | #define R_IRQ_MASK0_SET__ata_irq1__WIDTH 1 | ||
| 4028 | #define R_IRQ_MASK0_SET__ata_irq1__set 1 | ||
| 4029 | #define R_IRQ_MASK0_SET__ata_irq1__nop 0 | ||
| 4030 | #define R_IRQ_MASK0_SET__par0_ready__BITNR 8 | ||
| 4031 | #define R_IRQ_MASK0_SET__par0_ready__WIDTH 1 | ||
| 4032 | #define R_IRQ_MASK0_SET__par0_ready__set 1 | ||
| 4033 | #define R_IRQ_MASK0_SET__par0_ready__nop 0 | ||
| 4034 | #define R_IRQ_MASK0_SET__ata_irq0__BITNR 8 | ||
| 4035 | #define R_IRQ_MASK0_SET__ata_irq0__WIDTH 1 | ||
| 4036 | #define R_IRQ_MASK0_SET__ata_irq0__set 1 | ||
| 4037 | #define R_IRQ_MASK0_SET__ata_irq0__nop 0 | ||
| 4038 | #define R_IRQ_MASK0_SET__mio__BITNR 8 | ||
| 4039 | #define R_IRQ_MASK0_SET__mio__WIDTH 1 | ||
| 4040 | #define R_IRQ_MASK0_SET__mio__set 1 | ||
| 4041 | #define R_IRQ_MASK0_SET__mio__nop 0 | ||
| 4042 | #define R_IRQ_MASK0_SET__scsi0__BITNR 8 | ||
| 4043 | #define R_IRQ_MASK0_SET__scsi0__WIDTH 1 | ||
| 4044 | #define R_IRQ_MASK0_SET__scsi0__set 1 | ||
| 4045 | #define R_IRQ_MASK0_SET__scsi0__nop 0 | ||
| 4046 | #define R_IRQ_MASK0_SET__ata_dmaend__BITNR 7 | ||
| 4047 | #define R_IRQ_MASK0_SET__ata_dmaend__WIDTH 1 | ||
| 4048 | #define R_IRQ_MASK0_SET__ata_dmaend__set 1 | ||
| 4049 | #define R_IRQ_MASK0_SET__ata_dmaend__nop 0 | ||
| 4050 | #define R_IRQ_MASK0_SET__irq_ext_vector_nr__BITNR 5 | ||
| 4051 | #define R_IRQ_MASK0_SET__irq_ext_vector_nr__WIDTH 1 | ||
| 4052 | #define R_IRQ_MASK0_SET__irq_ext_vector_nr__set 1 | ||
| 4053 | #define R_IRQ_MASK0_SET__irq_ext_vector_nr__nop 0 | ||
| 4054 | #define R_IRQ_MASK0_SET__irq_int_vector_nr__BITNR 4 | ||
| 4055 | #define R_IRQ_MASK0_SET__irq_int_vector_nr__WIDTH 1 | ||
| 4056 | #define R_IRQ_MASK0_SET__irq_int_vector_nr__set 1 | ||
| 4057 | #define R_IRQ_MASK0_SET__irq_int_vector_nr__nop 0 | ||
| 4058 | #define R_IRQ_MASK0_SET__ext_dma1__BITNR 3 | ||
| 4059 | #define R_IRQ_MASK0_SET__ext_dma1__WIDTH 1 | ||
| 4060 | #define R_IRQ_MASK0_SET__ext_dma1__set 1 | ||
| 4061 | #define R_IRQ_MASK0_SET__ext_dma1__nop 0 | ||
| 4062 | #define R_IRQ_MASK0_SET__ext_dma0__BITNR 2 | ||
| 4063 | #define R_IRQ_MASK0_SET__ext_dma0__WIDTH 1 | ||
| 4064 | #define R_IRQ_MASK0_SET__ext_dma0__set 1 | ||
| 4065 | #define R_IRQ_MASK0_SET__ext_dma0__nop 0 | ||
| 4066 | #define R_IRQ_MASK0_SET__timer1__BITNR 1 | ||
| 4067 | #define R_IRQ_MASK0_SET__timer1__WIDTH 1 | ||
| 4068 | #define R_IRQ_MASK0_SET__timer1__set 1 | ||
| 4069 | #define R_IRQ_MASK0_SET__timer1__nop 0 | ||
| 4070 | #define R_IRQ_MASK0_SET__timer0__BITNR 0 | ||
| 4071 | #define R_IRQ_MASK0_SET__timer0__WIDTH 1 | ||
| 4072 | #define R_IRQ_MASK0_SET__timer0__set 1 | ||
| 4073 | #define R_IRQ_MASK0_SET__timer0__nop 0 | ||
| 4074 | |||
| 4075 | #define R_IRQ_MASK1_RD (IO_TYPECAST_RO_UDWORD 0xb00000c8) | ||
| 4076 | #define R_IRQ_MASK1_RD__sw_int7__BITNR 31 | ||
| 4077 | #define R_IRQ_MASK1_RD__sw_int7__WIDTH 1 | ||
| 4078 | #define R_IRQ_MASK1_RD__sw_int7__active 1 | ||
| 4079 | #define R_IRQ_MASK1_RD__sw_int7__inactive 0 | ||
| 4080 | #define R_IRQ_MASK1_RD__sw_int6__BITNR 30 | ||
| 4081 | #define R_IRQ_MASK1_RD__sw_int6__WIDTH 1 | ||
| 4082 | #define R_IRQ_MASK1_RD__sw_int6__active 1 | ||
| 4083 | #define R_IRQ_MASK1_RD__sw_int6__inactive 0 | ||
| 4084 | #define R_IRQ_MASK1_RD__sw_int5__BITNR 29 | ||
| 4085 | #define R_IRQ_MASK1_RD__sw_int5__WIDTH 1 | ||
| 4086 | #define R_IRQ_MASK1_RD__sw_int5__active 1 | ||
| 4087 | #define R_IRQ_MASK1_RD__sw_int5__inactive 0 | ||
| 4088 | #define R_IRQ_MASK1_RD__sw_int4__BITNR 28 | ||
| 4089 | #define R_IRQ_MASK1_RD__sw_int4__WIDTH 1 | ||
| 4090 | #define R_IRQ_MASK1_RD__sw_int4__active 1 | ||
| 4091 | #define R_IRQ_MASK1_RD__sw_int4__inactive 0 | ||
| 4092 | #define R_IRQ_MASK1_RD__sw_int3__BITNR 27 | ||
| 4093 | #define R_IRQ_MASK1_RD__sw_int3__WIDTH 1 | ||
| 4094 | #define R_IRQ_MASK1_RD__sw_int3__active 1 | ||
| 4095 | #define R_IRQ_MASK1_RD__sw_int3__inactive 0 | ||
| 4096 | #define R_IRQ_MASK1_RD__sw_int2__BITNR 26 | ||
| 4097 | #define R_IRQ_MASK1_RD__sw_int2__WIDTH 1 | ||
| 4098 | #define R_IRQ_MASK1_RD__sw_int2__active 1 | ||
| 4099 | #define R_IRQ_MASK1_RD__sw_int2__inactive 0 | ||
| 4100 | #define R_IRQ_MASK1_RD__sw_int1__BITNR 25 | ||
| 4101 | #define R_IRQ_MASK1_RD__sw_int1__WIDTH 1 | ||
| 4102 | #define R_IRQ_MASK1_RD__sw_int1__active 1 | ||
| 4103 | #define R_IRQ_MASK1_RD__sw_int1__inactive 0 | ||
| 4104 | #define R_IRQ_MASK1_RD__sw_int0__BITNR 24 | ||
| 4105 | #define R_IRQ_MASK1_RD__sw_int0__WIDTH 1 | ||
| 4106 | #define R_IRQ_MASK1_RD__sw_int0__active 1 | ||
| 4107 | #define R_IRQ_MASK1_RD__sw_int0__inactive 0 | ||
| 4108 | #define R_IRQ_MASK1_RD__par1_ecp_cmd__BITNR 19 | ||
| 4109 | #define R_IRQ_MASK1_RD__par1_ecp_cmd__WIDTH 1 | ||
| 4110 | #define R_IRQ_MASK1_RD__par1_ecp_cmd__active 1 | ||
| 4111 | #define R_IRQ_MASK1_RD__par1_ecp_cmd__inactive 0 | ||
| 4112 | #define R_IRQ_MASK1_RD__par1_peri__BITNR 18 | ||
| 4113 | #define R_IRQ_MASK1_RD__par1_peri__WIDTH 1 | ||
| 4114 | #define R_IRQ_MASK1_RD__par1_peri__active 1 | ||
| 4115 | #define R_IRQ_MASK1_RD__par1_peri__inactive 0 | ||
| 4116 | #define R_IRQ_MASK1_RD__par1_data__BITNR 17 | ||
| 4117 | #define R_IRQ_MASK1_RD__par1_data__WIDTH 1 | ||
| 4118 | #define R_IRQ_MASK1_RD__par1_data__active 1 | ||
| 4119 | #define R_IRQ_MASK1_RD__par1_data__inactive 0 | ||
| 4120 | #define R_IRQ_MASK1_RD__par1_ready__BITNR 16 | ||
| 4121 | #define R_IRQ_MASK1_RD__par1_ready__WIDTH 1 | ||
| 4122 | #define R_IRQ_MASK1_RD__par1_ready__active 1 | ||
| 4123 | #define R_IRQ_MASK1_RD__par1_ready__inactive 0 | ||
| 4124 | #define R_IRQ_MASK1_RD__scsi1__BITNR 16 | ||
| 4125 | #define R_IRQ_MASK1_RD__scsi1__WIDTH 1 | ||
| 4126 | #define R_IRQ_MASK1_RD__scsi1__active 1 | ||
| 4127 | #define R_IRQ_MASK1_RD__scsi1__inactive 0 | ||
| 4128 | #define R_IRQ_MASK1_RD__ser3_ready__BITNR 15 | ||
| 4129 | #define R_IRQ_MASK1_RD__ser3_ready__WIDTH 1 | ||
| 4130 | #define R_IRQ_MASK1_RD__ser3_ready__active 1 | ||
| 4131 | #define R_IRQ_MASK1_RD__ser3_ready__inactive 0 | ||
| 4132 | #define R_IRQ_MASK1_RD__ser3_data__BITNR 14 | ||
| 4133 | #define R_IRQ_MASK1_RD__ser3_data__WIDTH 1 | ||
| 4134 | #define R_IRQ_MASK1_RD__ser3_data__active 1 | ||
| 4135 | #define R_IRQ_MASK1_RD__ser3_data__inactive 0 | ||
| 4136 | #define R_IRQ_MASK1_RD__ser2_ready__BITNR 13 | ||
| 4137 | #define R_IRQ_MASK1_RD__ser2_ready__WIDTH 1 | ||
| 4138 | #define R_IRQ_MASK1_RD__ser2_ready__active 1 | ||
| 4139 | #define R_IRQ_MASK1_RD__ser2_ready__inactive 0 | ||
| 4140 | #define R_IRQ_MASK1_RD__ser2_data__BITNR 12 | ||
| 4141 | #define R_IRQ_MASK1_RD__ser2_data__WIDTH 1 | ||
| 4142 | #define R_IRQ_MASK1_RD__ser2_data__active 1 | ||
| 4143 | #define R_IRQ_MASK1_RD__ser2_data__inactive 0 | ||
| 4144 | #define R_IRQ_MASK1_RD__ser1_ready__BITNR 11 | ||
| 4145 | #define R_IRQ_MASK1_RD__ser1_ready__WIDTH 1 | ||
| 4146 | #define R_IRQ_MASK1_RD__ser1_ready__active 1 | ||
| 4147 | #define R_IRQ_MASK1_RD__ser1_ready__inactive 0 | ||
| 4148 | #define R_IRQ_MASK1_RD__ser1_data__BITNR 10 | ||
| 4149 | #define R_IRQ_MASK1_RD__ser1_data__WIDTH 1 | ||
| 4150 | #define R_IRQ_MASK1_RD__ser1_data__active 1 | ||
| 4151 | #define R_IRQ_MASK1_RD__ser1_data__inactive 0 | ||
| 4152 | #define R_IRQ_MASK1_RD__ser0_ready__BITNR 9 | ||
| 4153 | #define R_IRQ_MASK1_RD__ser0_ready__WIDTH 1 | ||
| 4154 | #define R_IRQ_MASK1_RD__ser0_ready__active 1 | ||
| 4155 | #define R_IRQ_MASK1_RD__ser0_ready__inactive 0 | ||
| 4156 | #define R_IRQ_MASK1_RD__ser0_data__BITNR 8 | ||
| 4157 | #define R_IRQ_MASK1_RD__ser0_data__WIDTH 1 | ||
| 4158 | #define R_IRQ_MASK1_RD__ser0_data__active 1 | ||
| 4159 | #define R_IRQ_MASK1_RD__ser0_data__inactive 0 | ||
| 4160 | #define R_IRQ_MASK1_RD__pa7__BITNR 7 | ||
| 4161 | #define R_IRQ_MASK1_RD__pa7__WIDTH 1 | ||
| 4162 | #define R_IRQ_MASK1_RD__pa7__active 1 | ||
| 4163 | #define R_IRQ_MASK1_RD__pa7__inactive 0 | ||
| 4164 | #define R_IRQ_MASK1_RD__pa6__BITNR 6 | ||
| 4165 | #define R_IRQ_MASK1_RD__pa6__WIDTH 1 | ||
| 4166 | #define R_IRQ_MASK1_RD__pa6__active 1 | ||
| 4167 | #define R_IRQ_MASK1_RD__pa6__inactive 0 | ||
| 4168 | #define R_IRQ_MASK1_RD__pa5__BITNR 5 | ||
| 4169 | #define R_IRQ_MASK1_RD__pa5__WIDTH 1 | ||
| 4170 | #define R_IRQ_MASK1_RD__pa5__active 1 | ||
| 4171 | #define R_IRQ_MASK1_RD__pa5__inactive 0 | ||
| 4172 | #define R_IRQ_MASK1_RD__pa4__BITNR 4 | ||
| 4173 | #define R_IRQ_MASK1_RD__pa4__WIDTH 1 | ||
| 4174 | #define R_IRQ_MASK1_RD__pa4__active 1 | ||
| 4175 | #define R_IRQ_MASK1_RD__pa4__inactive 0 | ||
| 4176 | #define R_IRQ_MASK1_RD__pa3__BITNR 3 | ||
| 4177 | #define R_IRQ_MASK1_RD__pa3__WIDTH 1 | ||
| 4178 | #define R_IRQ_MASK1_RD__pa3__active 1 | ||
| 4179 | #define R_IRQ_MASK1_RD__pa3__inactive 0 | ||
| 4180 | #define R_IRQ_MASK1_RD__pa2__BITNR 2 | ||
| 4181 | #define R_IRQ_MASK1_RD__pa2__WIDTH 1 | ||
| 4182 | #define R_IRQ_MASK1_RD__pa2__active 1 | ||
| 4183 | #define R_IRQ_MASK1_RD__pa2__inactive 0 | ||
| 4184 | #define R_IRQ_MASK1_RD__pa1__BITNR 1 | ||
| 4185 | #define R_IRQ_MASK1_RD__pa1__WIDTH 1 | ||
| 4186 | #define R_IRQ_MASK1_RD__pa1__active 1 | ||
| 4187 | #define R_IRQ_MASK1_RD__pa1__inactive 0 | ||
| 4188 | #define R_IRQ_MASK1_RD__pa0__BITNR 0 | ||
| 4189 | #define R_IRQ_MASK1_RD__pa0__WIDTH 1 | ||
| 4190 | #define R_IRQ_MASK1_RD__pa0__active 1 | ||
| 4191 | #define R_IRQ_MASK1_RD__pa0__inactive 0 | ||
| 4192 | |||
| 4193 | #define R_IRQ_MASK1_CLR (IO_TYPECAST_UDWORD 0xb00000c8) | ||
| 4194 | #define R_IRQ_MASK1_CLR__sw_int7__BITNR 31 | ||
| 4195 | #define R_IRQ_MASK1_CLR__sw_int7__WIDTH 1 | ||
| 4196 | #define R_IRQ_MASK1_CLR__sw_int7__clr 1 | ||
| 4197 | #define R_IRQ_MASK1_CLR__sw_int7__nop 0 | ||
| 4198 | #define R_IRQ_MASK1_CLR__sw_int6__BITNR 30 | ||
| 4199 | #define R_IRQ_MASK1_CLR__sw_int6__WIDTH 1 | ||
| 4200 | #define R_IRQ_MASK1_CLR__sw_int6__clr 1 | ||
| 4201 | #define R_IRQ_MASK1_CLR__sw_int6__nop 0 | ||
| 4202 | #define R_IRQ_MASK1_CLR__sw_int5__BITNR 29 | ||
| 4203 | #define R_IRQ_MASK1_CLR__sw_int5__WIDTH 1 | ||
| 4204 | #define R_IRQ_MASK1_CLR__sw_int5__clr 1 | ||
| 4205 | #define R_IRQ_MASK1_CLR__sw_int5__nop 0 | ||
| 4206 | #define R_IRQ_MASK1_CLR__sw_int4__BITNR 28 | ||
| 4207 | #define R_IRQ_MASK1_CLR__sw_int4__WIDTH 1 | ||
| 4208 | #define R_IRQ_MASK1_CLR__sw_int4__clr 1 | ||
| 4209 | #define R_IRQ_MASK1_CLR__sw_int4__nop 0 | ||
| 4210 | #define R_IRQ_MASK1_CLR__sw_int3__BITNR 27 | ||
| 4211 | #define R_IRQ_MASK1_CLR__sw_int3__WIDTH 1 | ||
| 4212 | #define R_IRQ_MASK1_CLR__sw_int3__clr 1 | ||
| 4213 | #define R_IRQ_MASK1_CLR__sw_int3__nop 0 | ||
| 4214 | #define R_IRQ_MASK1_CLR__sw_int2__BITNR 26 | ||
| 4215 | #define R_IRQ_MASK1_CLR__sw_int2__WIDTH 1 | ||
| 4216 | #define R_IRQ_MASK1_CLR__sw_int2__clr 1 | ||
| 4217 | #define R_IRQ_MASK1_CLR__sw_int2__nop 0 | ||
| 4218 | #define R_IRQ_MASK1_CLR__sw_int1__BITNR 25 | ||
| 4219 | #define R_IRQ_MASK1_CLR__sw_int1__WIDTH 1 | ||
| 4220 | #define R_IRQ_MASK1_CLR__sw_int1__clr 1 | ||
| 4221 | #define R_IRQ_MASK1_CLR__sw_int1__nop 0 | ||
| 4222 | #define R_IRQ_MASK1_CLR__sw_int0__BITNR 24 | ||
| 4223 | #define R_IRQ_MASK1_CLR__sw_int0__WIDTH 1 | ||
| 4224 | #define R_IRQ_MASK1_CLR__sw_int0__clr 1 | ||
| 4225 | #define R_IRQ_MASK1_CLR__sw_int0__nop 0 | ||
| 4226 | #define R_IRQ_MASK1_CLR__par1_ecp_cmd__BITNR 19 | ||
| 4227 | #define R_IRQ_MASK1_CLR__par1_ecp_cmd__WIDTH 1 | ||
| 4228 | #define R_IRQ_MASK1_CLR__par1_ecp_cmd__clr 1 | ||
| 4229 | #define R_IRQ_MASK1_CLR__par1_ecp_cmd__nop 0 | ||
| 4230 | #define R_IRQ_MASK1_CLR__par1_peri__BITNR 18 | ||
| 4231 | #define R_IRQ_MASK1_CLR__par1_peri__WIDTH 1 | ||
| 4232 | #define R_IRQ_MASK1_CLR__par1_peri__clr 1 | ||
| 4233 | #define R_IRQ_MASK1_CLR__par1_peri__nop 0 | ||
| 4234 | #define R_IRQ_MASK1_CLR__par1_data__BITNR 17 | ||
| 4235 | #define R_IRQ_MASK1_CLR__par1_data__WIDTH 1 | ||
| 4236 | #define R_IRQ_MASK1_CLR__par1_data__clr 1 | ||
| 4237 | #define R_IRQ_MASK1_CLR__par1_data__nop 0 | ||
| 4238 | #define R_IRQ_MASK1_CLR__par1_ready__BITNR 16 | ||
| 4239 | #define R_IRQ_MASK1_CLR__par1_ready__WIDTH 1 | ||
| 4240 | #define R_IRQ_MASK1_CLR__par1_ready__clr 1 | ||
| 4241 | #define R_IRQ_MASK1_CLR__par1_ready__nop 0 | ||
| 4242 | #define R_IRQ_MASK1_CLR__scsi1__BITNR 16 | ||
| 4243 | #define R_IRQ_MASK1_CLR__scsi1__WIDTH 1 | ||
| 4244 | #define R_IRQ_MASK1_CLR__scsi1__clr 1 | ||
| 4245 | #define R_IRQ_MASK1_CLR__scsi1__nop 0 | ||
| 4246 | #define R_IRQ_MASK1_CLR__ser3_ready__BITNR 15 | ||
| 4247 | #define R_IRQ_MASK1_CLR__ser3_ready__WIDTH 1 | ||
| 4248 | #define R_IRQ_MASK1_CLR__ser3_ready__clr 1 | ||
| 4249 | #define R_IRQ_MASK1_CLR__ser3_ready__nop 0 | ||
| 4250 | #define R_IRQ_MASK1_CLR__ser3_data__BITNR 14 | ||
| 4251 | #define R_IRQ_MASK1_CLR__ser3_data__WIDTH 1 | ||
| 4252 | #define R_IRQ_MASK1_CLR__ser3_data__clr 1 | ||
| 4253 | #define R_IRQ_MASK1_CLR__ser3_data__nop 0 | ||
| 4254 | #define R_IRQ_MASK1_CLR__ser2_ready__BITNR 13 | ||
| 4255 | #define R_IRQ_MASK1_CLR__ser2_ready__WIDTH 1 | ||
| 4256 | #define R_IRQ_MASK1_CLR__ser2_ready__clr 1 | ||
| 4257 | #define R_IRQ_MASK1_CLR__ser2_ready__nop 0 | ||
| 4258 | #define R_IRQ_MASK1_CLR__ser2_data__BITNR 12 | ||
| 4259 | #define R_IRQ_MASK1_CLR__ser2_data__WIDTH 1 | ||
| 4260 | #define R_IRQ_MASK1_CLR__ser2_data__clr 1 | ||
| 4261 | #define R_IRQ_MASK1_CLR__ser2_data__nop 0 | ||
| 4262 | #define R_IRQ_MASK1_CLR__ser1_ready__BITNR 11 | ||
| 4263 | #define R_IRQ_MASK1_CLR__ser1_ready__WIDTH 1 | ||
| 4264 | #define R_IRQ_MASK1_CLR__ser1_ready__clr 1 | ||
| 4265 | #define R_IRQ_MASK1_CLR__ser1_ready__nop 0 | ||
| 4266 | #define R_IRQ_MASK1_CLR__ser1_data__BITNR 10 | ||
| 4267 | #define R_IRQ_MASK1_CLR__ser1_data__WIDTH 1 | ||
| 4268 | #define R_IRQ_MASK1_CLR__ser1_data__clr 1 | ||
| 4269 | #define R_IRQ_MASK1_CLR__ser1_data__nop 0 | ||
| 4270 | #define R_IRQ_MASK1_CLR__ser0_ready__BITNR 9 | ||
| 4271 | #define R_IRQ_MASK1_CLR__ser0_ready__WIDTH 1 | ||
| 4272 | #define R_IRQ_MASK1_CLR__ser0_ready__clr 1 | ||
| 4273 | #define R_IRQ_MASK1_CLR__ser0_ready__nop 0 | ||
| 4274 | #define R_IRQ_MASK1_CLR__ser0_data__BITNR 8 | ||
| 4275 | #define R_IRQ_MASK1_CLR__ser0_data__WIDTH 1 | ||
| 4276 | #define R_IRQ_MASK1_CLR__ser0_data__clr 1 | ||
| 4277 | #define R_IRQ_MASK1_CLR__ser0_data__nop 0 | ||
| 4278 | #define R_IRQ_MASK1_CLR__pa7__BITNR 7 | ||
| 4279 | #define R_IRQ_MASK1_CLR__pa7__WIDTH 1 | ||
| 4280 | #define R_IRQ_MASK1_CLR__pa7__clr 1 | ||
| 4281 | #define R_IRQ_MASK1_CLR__pa7__nop 0 | ||
| 4282 | #define R_IRQ_MASK1_CLR__pa6__BITNR 6 | ||
| 4283 | #define R_IRQ_MASK1_CLR__pa6__WIDTH 1 | ||
| 4284 | #define R_IRQ_MASK1_CLR__pa6__clr 1 | ||
| 4285 | #define R_IRQ_MASK1_CLR__pa6__nop 0 | ||
| 4286 | #define R_IRQ_MASK1_CLR__pa5__BITNR 5 | ||
| 4287 | #define R_IRQ_MASK1_CLR__pa5__WIDTH 1 | ||
| 4288 | #define R_IRQ_MASK1_CLR__pa5__clr 1 | ||
| 4289 | #define R_IRQ_MASK1_CLR__pa5__nop 0 | ||
| 4290 | #define R_IRQ_MASK1_CLR__pa4__BITNR 4 | ||
| 4291 | #define R_IRQ_MASK1_CLR__pa4__WIDTH 1 | ||
| 4292 | #define R_IRQ_MASK1_CLR__pa4__clr 1 | ||
| 4293 | #define R_IRQ_MASK1_CLR__pa4__nop 0 | ||
| 4294 | #define R_IRQ_MASK1_CLR__pa3__BITNR 3 | ||
| 4295 | #define R_IRQ_MASK1_CLR__pa3__WIDTH 1 | ||
| 4296 | #define R_IRQ_MASK1_CLR__pa3__clr 1 | ||
| 4297 | #define R_IRQ_MASK1_CLR__pa3__nop 0 | ||
| 4298 | #define R_IRQ_MASK1_CLR__pa2__BITNR 2 | ||
| 4299 | #define R_IRQ_MASK1_CLR__pa2__WIDTH 1 | ||
| 4300 | #define R_IRQ_MASK1_CLR__pa2__clr 1 | ||
| 4301 | #define R_IRQ_MASK1_CLR__pa2__nop 0 | ||
| 4302 | #define R_IRQ_MASK1_CLR__pa1__BITNR 1 | ||
| 4303 | #define R_IRQ_MASK1_CLR__pa1__WIDTH 1 | ||
| 4304 | #define R_IRQ_MASK1_CLR__pa1__clr 1 | ||
| 4305 | #define R_IRQ_MASK1_CLR__pa1__nop 0 | ||
| 4306 | #define R_IRQ_MASK1_CLR__pa0__BITNR 0 | ||
| 4307 | #define R_IRQ_MASK1_CLR__pa0__WIDTH 1 | ||
| 4308 | #define R_IRQ_MASK1_CLR__pa0__clr 1 | ||
| 4309 | #define R_IRQ_MASK1_CLR__pa0__nop 0 | ||
| 4310 | |||
| 4311 | #define R_IRQ_READ1 (IO_TYPECAST_RO_UDWORD 0xb00000cc) | ||
| 4312 | #define R_IRQ_READ1__sw_int7__BITNR 31 | ||
| 4313 | #define R_IRQ_READ1__sw_int7__WIDTH 1 | ||
| 4314 | #define R_IRQ_READ1__sw_int7__active 1 | ||
| 4315 | #define R_IRQ_READ1__sw_int7__inactive 0 | ||
| 4316 | #define R_IRQ_READ1__sw_int6__BITNR 30 | ||
| 4317 | #define R_IRQ_READ1__sw_int6__WIDTH 1 | ||
| 4318 | #define R_IRQ_READ1__sw_int6__active 1 | ||
| 4319 | #define R_IRQ_READ1__sw_int6__inactive 0 | ||
| 4320 | #define R_IRQ_READ1__sw_int5__BITNR 29 | ||
| 4321 | #define R_IRQ_READ1__sw_int5__WIDTH 1 | ||
| 4322 | #define R_IRQ_READ1__sw_int5__active 1 | ||
| 4323 | #define R_IRQ_READ1__sw_int5__inactive 0 | ||
| 4324 | #define R_IRQ_READ1__sw_int4__BITNR 28 | ||
| 4325 | #define R_IRQ_READ1__sw_int4__WIDTH 1 | ||
| 4326 | #define R_IRQ_READ1__sw_int4__active 1 | ||
| 4327 | #define R_IRQ_READ1__sw_int4__inactive 0 | ||
| 4328 | #define R_IRQ_READ1__sw_int3__BITNR 27 | ||
| 4329 | #define R_IRQ_READ1__sw_int3__WIDTH 1 | ||
| 4330 | #define R_IRQ_READ1__sw_int3__active 1 | ||
| 4331 | #define R_IRQ_READ1__sw_int3__inactive 0 | ||
| 4332 | #define R_IRQ_READ1__sw_int2__BITNR 26 | ||
| 4333 | #define R_IRQ_READ1__sw_int2__WIDTH 1 | ||
| 4334 | #define R_IRQ_READ1__sw_int2__active 1 | ||
| 4335 | #define R_IRQ_READ1__sw_int2__inactive 0 | ||
| 4336 | #define R_IRQ_READ1__sw_int1__BITNR 25 | ||
| 4337 | #define R_IRQ_READ1__sw_int1__WIDTH 1 | ||
| 4338 | #define R_IRQ_READ1__sw_int1__active 1 | ||
| 4339 | #define R_IRQ_READ1__sw_int1__inactive 0 | ||
| 4340 | #define R_IRQ_READ1__sw_int0__BITNR 24 | ||
| 4341 | #define R_IRQ_READ1__sw_int0__WIDTH 1 | ||
| 4342 | #define R_IRQ_READ1__sw_int0__active 1 | ||
| 4343 | #define R_IRQ_READ1__sw_int0__inactive 0 | ||
| 4344 | #define R_IRQ_READ1__par1_ecp_cmd__BITNR 19 | ||
| 4345 | #define R_IRQ_READ1__par1_ecp_cmd__WIDTH 1 | ||
| 4346 | #define R_IRQ_READ1__par1_ecp_cmd__active 1 | ||
| 4347 | #define R_IRQ_READ1__par1_ecp_cmd__inactive 0 | ||
| 4348 | #define R_IRQ_READ1__par1_peri__BITNR 18 | ||
| 4349 | #define R_IRQ_READ1__par1_peri__WIDTH 1 | ||
| 4350 | #define R_IRQ_READ1__par1_peri__active 1 | ||
| 4351 | #define R_IRQ_READ1__par1_peri__inactive 0 | ||
| 4352 | #define R_IRQ_READ1__par1_data__BITNR 17 | ||
| 4353 | #define R_IRQ_READ1__par1_data__WIDTH 1 | ||
| 4354 | #define R_IRQ_READ1__par1_data__active 1 | ||
| 4355 | #define R_IRQ_READ1__par1_data__inactive 0 | ||
| 4356 | #define R_IRQ_READ1__par1_ready__BITNR 16 | ||
| 4357 | #define R_IRQ_READ1__par1_ready__WIDTH 1 | ||
| 4358 | #define R_IRQ_READ1__par1_ready__active 1 | ||
| 4359 | #define R_IRQ_READ1__par1_ready__inactive 0 | ||
| 4360 | #define R_IRQ_READ1__scsi1__BITNR 16 | ||
| 4361 | #define R_IRQ_READ1__scsi1__WIDTH 1 | ||
| 4362 | #define R_IRQ_READ1__scsi1__active 1 | ||
| 4363 | #define R_IRQ_READ1__scsi1__inactive 0 | ||
| 4364 | #define R_IRQ_READ1__ser3_ready__BITNR 15 | ||
| 4365 | #define R_IRQ_READ1__ser3_ready__WIDTH 1 | ||
| 4366 | #define R_IRQ_READ1__ser3_ready__active 1 | ||
| 4367 | #define R_IRQ_READ1__ser3_ready__inactive 0 | ||
| 4368 | #define R_IRQ_READ1__ser3_data__BITNR 14 | ||
| 4369 | #define R_IRQ_READ1__ser3_data__WIDTH 1 | ||
| 4370 | #define R_IRQ_READ1__ser3_data__active 1 | ||
| 4371 | #define R_IRQ_READ1__ser3_data__inactive 0 | ||
| 4372 | #define R_IRQ_READ1__ser2_ready__BITNR 13 | ||
| 4373 | #define R_IRQ_READ1__ser2_ready__WIDTH 1 | ||
| 4374 | #define R_IRQ_READ1__ser2_ready__active 1 | ||
| 4375 | #define R_IRQ_READ1__ser2_ready__inactive 0 | ||
| 4376 | #define R_IRQ_READ1__ser2_data__BITNR 12 | ||
| 4377 | #define R_IRQ_READ1__ser2_data__WIDTH 1 | ||
| 4378 | #define R_IRQ_READ1__ser2_data__active 1 | ||
| 4379 | #define R_IRQ_READ1__ser2_data__inactive 0 | ||
| 4380 | #define R_IRQ_READ1__ser1_ready__BITNR 11 | ||
| 4381 | #define R_IRQ_READ1__ser1_ready__WIDTH 1 | ||
| 4382 | #define R_IRQ_READ1__ser1_ready__active 1 | ||
| 4383 | #define R_IRQ_READ1__ser1_ready__inactive 0 | ||
| 4384 | #define R_IRQ_READ1__ser1_data__BITNR 10 | ||
| 4385 | #define R_IRQ_READ1__ser1_data__WIDTH 1 | ||
| 4386 | #define R_IRQ_READ1__ser1_data__active 1 | ||
| 4387 | #define R_IRQ_READ1__ser1_data__inactive 0 | ||
| 4388 | #define R_IRQ_READ1__ser0_ready__BITNR 9 | ||
| 4389 | #define R_IRQ_READ1__ser0_ready__WIDTH 1 | ||
| 4390 | #define R_IRQ_READ1__ser0_ready__active 1 | ||
| 4391 | #define R_IRQ_READ1__ser0_ready__inactive 0 | ||
| 4392 | #define R_IRQ_READ1__ser0_data__BITNR 8 | ||
| 4393 | #define R_IRQ_READ1__ser0_data__WIDTH 1 | ||
| 4394 | #define R_IRQ_READ1__ser0_data__active 1 | ||
| 4395 | #define R_IRQ_READ1__ser0_data__inactive 0 | ||
| 4396 | #define R_IRQ_READ1__pa7__BITNR 7 | ||
| 4397 | #define R_IRQ_READ1__pa7__WIDTH 1 | ||
| 4398 | #define R_IRQ_READ1__pa7__active 1 | ||
| 4399 | #define R_IRQ_READ1__pa7__inactive 0 | ||
| 4400 | #define R_IRQ_READ1__pa6__BITNR 6 | ||
| 4401 | #define R_IRQ_READ1__pa6__WIDTH 1 | ||
| 4402 | #define R_IRQ_READ1__pa6__active 1 | ||
| 4403 | #define R_IRQ_READ1__pa6__inactive 0 | ||
| 4404 | #define R_IRQ_READ1__pa5__BITNR 5 | ||
| 4405 | #define R_IRQ_READ1__pa5__WIDTH 1 | ||
| 4406 | #define R_IRQ_READ1__pa5__active 1 | ||
| 4407 | #define R_IRQ_READ1__pa5__inactive 0 | ||
| 4408 | #define R_IRQ_READ1__pa4__BITNR 4 | ||
| 4409 | #define R_IRQ_READ1__pa4__WIDTH 1 | ||
| 4410 | #define R_IRQ_READ1__pa4__active 1 | ||
| 4411 | #define R_IRQ_READ1__pa4__inactive 0 | ||
| 4412 | #define R_IRQ_READ1__pa3__BITNR 3 | ||
| 4413 | #define R_IRQ_READ1__pa3__WIDTH 1 | ||
| 4414 | #define R_IRQ_READ1__pa3__active 1 | ||
| 4415 | #define R_IRQ_READ1__pa3__inactive 0 | ||
| 4416 | #define R_IRQ_READ1__pa2__BITNR 2 | ||
| 4417 | #define R_IRQ_READ1__pa2__WIDTH 1 | ||
| 4418 | #define R_IRQ_READ1__pa2__active 1 | ||
| 4419 | #define R_IRQ_READ1__pa2__inactive 0 | ||
| 4420 | #define R_IRQ_READ1__pa1__BITNR 1 | ||
| 4421 | #define R_IRQ_READ1__pa1__WIDTH 1 | ||
| 4422 | #define R_IRQ_READ1__pa1__active 1 | ||
| 4423 | #define R_IRQ_READ1__pa1__inactive 0 | ||
| 4424 | #define R_IRQ_READ1__pa0__BITNR 0 | ||
| 4425 | #define R_IRQ_READ1__pa0__WIDTH 1 | ||
| 4426 | #define R_IRQ_READ1__pa0__active 1 | ||
| 4427 | #define R_IRQ_READ1__pa0__inactive 0 | ||
| 4428 | |||
| 4429 | #define R_IRQ_MASK1_SET (IO_TYPECAST_UDWORD 0xb00000cc) | ||
| 4430 | #define R_IRQ_MASK1_SET__sw_int7__BITNR 31 | ||
| 4431 | #define R_IRQ_MASK1_SET__sw_int7__WIDTH 1 | ||
| 4432 | #define R_IRQ_MASK1_SET__sw_int7__set 1 | ||
| 4433 | #define R_IRQ_MASK1_SET__sw_int7__nop 0 | ||
| 4434 | #define R_IRQ_MASK1_SET__sw_int6__BITNR 30 | ||
| 4435 | #define R_IRQ_MASK1_SET__sw_int6__WIDTH 1 | ||
| 4436 | #define R_IRQ_MASK1_SET__sw_int6__set 1 | ||
| 4437 | #define R_IRQ_MASK1_SET__sw_int6__nop 0 | ||
| 4438 | #define R_IRQ_MASK1_SET__sw_int5__BITNR 29 | ||
| 4439 | #define R_IRQ_MASK1_SET__sw_int5__WIDTH 1 | ||
| 4440 | #define R_IRQ_MASK1_SET__sw_int5__set 1 | ||
| 4441 | #define R_IRQ_MASK1_SET__sw_int5__nop 0 | ||
| 4442 | #define R_IRQ_MASK1_SET__sw_int4__BITNR 28 | ||
| 4443 | #define R_IRQ_MASK1_SET__sw_int4__WIDTH 1 | ||
| 4444 | #define R_IRQ_MASK1_SET__sw_int4__set 1 | ||
| 4445 | #define R_IRQ_MASK1_SET__sw_int4__nop 0 | ||
| 4446 | #define R_IRQ_MASK1_SET__sw_int3__BITNR 27 | ||
| 4447 | #define R_IRQ_MASK1_SET__sw_int3__WIDTH 1 | ||
| 4448 | #define R_IRQ_MASK1_SET__sw_int3__set 1 | ||
| 4449 | #define R_IRQ_MASK1_SET__sw_int3__nop 0 | ||
| 4450 | #define R_IRQ_MASK1_SET__sw_int2__BITNR 26 | ||
| 4451 | #define R_IRQ_MASK1_SET__sw_int2__WIDTH 1 | ||
| 4452 | #define R_IRQ_MASK1_SET__sw_int2__set 1 | ||
| 4453 | #define R_IRQ_MASK1_SET__sw_int2__nop 0 | ||
| 4454 | #define R_IRQ_MASK1_SET__sw_int1__BITNR 25 | ||
| 4455 | #define R_IRQ_MASK1_SET__sw_int1__WIDTH 1 | ||
| 4456 | #define R_IRQ_MASK1_SET__sw_int1__set 1 | ||
| 4457 | #define R_IRQ_MASK1_SET__sw_int1__nop 0 | ||
| 4458 | #define R_IRQ_MASK1_SET__sw_int0__BITNR 24 | ||
| 4459 | #define R_IRQ_MASK1_SET__sw_int0__WIDTH 1 | ||
| 4460 | #define R_IRQ_MASK1_SET__sw_int0__set 1 | ||
| 4461 | #define R_IRQ_MASK1_SET__sw_int0__nop 0 | ||
| 4462 | #define R_IRQ_MASK1_SET__par1_ecp_cmd__BITNR 19 | ||
| 4463 | #define R_IRQ_MASK1_SET__par1_ecp_cmd__WIDTH 1 | ||
| 4464 | #define R_IRQ_MASK1_SET__par1_ecp_cmd__set 1 | ||
| 4465 | #define R_IRQ_MASK1_SET__par1_ecp_cmd__nop 0 | ||
| 4466 | #define R_IRQ_MASK1_SET__par1_peri__BITNR 18 | ||
| 4467 | #define R_IRQ_MASK1_SET__par1_peri__WIDTH 1 | ||
| 4468 | #define R_IRQ_MASK1_SET__par1_peri__set 1 | ||
| 4469 | #define R_IRQ_MASK1_SET__par1_peri__nop 0 | ||
| 4470 | #define R_IRQ_MASK1_SET__par1_data__BITNR 17 | ||
| 4471 | #define R_IRQ_MASK1_SET__par1_data__WIDTH 1 | ||
| 4472 | #define R_IRQ_MASK1_SET__par1_data__set 1 | ||
| 4473 | #define R_IRQ_MASK1_SET__par1_data__nop 0 | ||
| 4474 | #define R_IRQ_MASK1_SET__par1_ready__BITNR 16 | ||
| 4475 | #define R_IRQ_MASK1_SET__par1_ready__WIDTH 1 | ||
| 4476 | #define R_IRQ_MASK1_SET__par1_ready__set 1 | ||
| 4477 | #define R_IRQ_MASK1_SET__par1_ready__nop 0 | ||
| 4478 | #define R_IRQ_MASK1_SET__scsi1__BITNR 16 | ||
| 4479 | #define R_IRQ_MASK1_SET__scsi1__WIDTH 1 | ||
| 4480 | #define R_IRQ_MASK1_SET__scsi1__set 1 | ||
| 4481 | #define R_IRQ_MASK1_SET__scsi1__nop 0 | ||
| 4482 | #define R_IRQ_MASK1_SET__ser3_ready__BITNR 15 | ||
| 4483 | #define R_IRQ_MASK1_SET__ser3_ready__WIDTH 1 | ||
| 4484 | #define R_IRQ_MASK1_SET__ser3_ready__set 1 | ||
| 4485 | #define R_IRQ_MASK1_SET__ser3_ready__nop 0 | ||
| 4486 | #define R_IRQ_MASK1_SET__ser3_data__BITNR 14 | ||
| 4487 | #define R_IRQ_MASK1_SET__ser3_data__WIDTH 1 | ||
| 4488 | #define R_IRQ_MASK1_SET__ser3_data__set 1 | ||
| 4489 | #define R_IRQ_MASK1_SET__ser3_data__nop 0 | ||
| 4490 | #define R_IRQ_MASK1_SET__ser2_ready__BITNR 13 | ||
| 4491 | #define R_IRQ_MASK1_SET__ser2_ready__WIDTH 1 | ||
| 4492 | #define R_IRQ_MASK1_SET__ser2_ready__set 1 | ||
| 4493 | #define R_IRQ_MASK1_SET__ser2_ready__nop 0 | ||
| 4494 | #define R_IRQ_MASK1_SET__ser2_data__BITNR 12 | ||
| 4495 | #define R_IRQ_MASK1_SET__ser2_data__WIDTH 1 | ||
| 4496 | #define R_IRQ_MASK1_SET__ser2_data__set 1 | ||
| 4497 | #define R_IRQ_MASK1_SET__ser2_data__nop 0 | ||
| 4498 | #define R_IRQ_MASK1_SET__ser1_ready__BITNR 11 | ||
| 4499 | #define R_IRQ_MASK1_SET__ser1_ready__WIDTH 1 | ||
| 4500 | #define R_IRQ_MASK1_SET__ser1_ready__set 1 | ||
| 4501 | #define R_IRQ_MASK1_SET__ser1_ready__nop 0 | ||
| 4502 | #define R_IRQ_MASK1_SET__ser1_data__BITNR 10 | ||
| 4503 | #define R_IRQ_MASK1_SET__ser1_data__WIDTH 1 | ||
| 4504 | #define R_IRQ_MASK1_SET__ser1_data__set 1 | ||
| 4505 | #define R_IRQ_MASK1_SET__ser1_data__nop 0 | ||
| 4506 | #define R_IRQ_MASK1_SET__ser0_ready__BITNR 9 | ||
| 4507 | #define R_IRQ_MASK1_SET__ser0_ready__WIDTH 1 | ||
| 4508 | #define R_IRQ_MASK1_SET__ser0_ready__set 1 | ||
| 4509 | #define R_IRQ_MASK1_SET__ser0_ready__nop 0 | ||
| 4510 | #define R_IRQ_MASK1_SET__ser0_data__BITNR 8 | ||
| 4511 | #define R_IRQ_MASK1_SET__ser0_data__WIDTH 1 | ||
| 4512 | #define R_IRQ_MASK1_SET__ser0_data__set 1 | ||
| 4513 | #define R_IRQ_MASK1_SET__ser0_data__nop 0 | ||
| 4514 | #define R_IRQ_MASK1_SET__pa7__BITNR 7 | ||
| 4515 | #define R_IRQ_MASK1_SET__pa7__WIDTH 1 | ||
| 4516 | #define R_IRQ_MASK1_SET__pa7__set 1 | ||
| 4517 | #define R_IRQ_MASK1_SET__pa7__nop 0 | ||
| 4518 | #define R_IRQ_MASK1_SET__pa6__BITNR 6 | ||
| 4519 | #define R_IRQ_MASK1_SET__pa6__WIDTH 1 | ||
| 4520 | #define R_IRQ_MASK1_SET__pa6__set 1 | ||
| 4521 | #define R_IRQ_MASK1_SET__pa6__nop 0 | ||
| 4522 | #define R_IRQ_MASK1_SET__pa5__BITNR 5 | ||
| 4523 | #define R_IRQ_MASK1_SET__pa5__WIDTH 1 | ||
| 4524 | #define R_IRQ_MASK1_SET__pa5__set 1 | ||
| 4525 | #define R_IRQ_MASK1_SET__pa5__nop 0 | ||
| 4526 | #define R_IRQ_MASK1_SET__pa4__BITNR 4 | ||
| 4527 | #define R_IRQ_MASK1_SET__pa4__WIDTH 1 | ||
| 4528 | #define R_IRQ_MASK1_SET__pa4__set 1 | ||
| 4529 | #define R_IRQ_MASK1_SET__pa4__nop 0 | ||
| 4530 | #define R_IRQ_MASK1_SET__pa3__BITNR 3 | ||
| 4531 | #define R_IRQ_MASK1_SET__pa3__WIDTH 1 | ||
| 4532 | #define R_IRQ_MASK1_SET__pa3__set 1 | ||
| 4533 | #define R_IRQ_MASK1_SET__pa3__nop 0 | ||
| 4534 | #define R_IRQ_MASK1_SET__pa2__BITNR 2 | ||
| 4535 | #define R_IRQ_MASK1_SET__pa2__WIDTH 1 | ||
| 4536 | #define R_IRQ_MASK1_SET__pa2__set 1 | ||
| 4537 | #define R_IRQ_MASK1_SET__pa2__nop 0 | ||
| 4538 | #define R_IRQ_MASK1_SET__pa1__BITNR 1 | ||
| 4539 | #define R_IRQ_MASK1_SET__pa1__WIDTH 1 | ||
| 4540 | #define R_IRQ_MASK1_SET__pa1__set 1 | ||
| 4541 | #define R_IRQ_MASK1_SET__pa1__nop 0 | ||
| 4542 | #define R_IRQ_MASK1_SET__pa0__BITNR 0 | ||
| 4543 | #define R_IRQ_MASK1_SET__pa0__WIDTH 1 | ||
| 4544 | #define R_IRQ_MASK1_SET__pa0__set 1 | ||
| 4545 | #define R_IRQ_MASK1_SET__pa0__nop 0 | ||
| 4546 | |||
| 4547 | #define R_IRQ_MASK2_RD (IO_TYPECAST_RO_UDWORD 0xb00000d0) | ||
| 4548 | #define R_IRQ_MASK2_RD__dma8_sub3_descr__BITNR 23 | ||
| 4549 | #define R_IRQ_MASK2_RD__dma8_sub3_descr__WIDTH 1 | ||
| 4550 | #define R_IRQ_MASK2_RD__dma8_sub3_descr__active 1 | ||
| 4551 | #define R_IRQ_MASK2_RD__dma8_sub3_descr__inactive 0 | ||
| 4552 | #define R_IRQ_MASK2_RD__dma8_sub2_descr__BITNR 22 | ||
| 4553 | #define R_IRQ_MASK2_RD__dma8_sub2_descr__WIDTH 1 | ||
| 4554 | #define R_IRQ_MASK2_RD__dma8_sub2_descr__active 1 | ||
| 4555 | #define R_IRQ_MASK2_RD__dma8_sub2_descr__inactive 0 | ||
| 4556 | #define R_IRQ_MASK2_RD__dma8_sub1_descr__BITNR 21 | ||
| 4557 | #define R_IRQ_MASK2_RD__dma8_sub1_descr__WIDTH 1 | ||
| 4558 | #define R_IRQ_MASK2_RD__dma8_sub1_descr__active 1 | ||
| 4559 | #define R_IRQ_MASK2_RD__dma8_sub1_descr__inactive 0 | ||
| 4560 | #define R_IRQ_MASK2_RD__dma8_sub0_descr__BITNR 20 | ||
| 4561 | #define R_IRQ_MASK2_RD__dma8_sub0_descr__WIDTH 1 | ||
| 4562 | #define R_IRQ_MASK2_RD__dma8_sub0_descr__active 1 | ||
| 4563 | #define R_IRQ_MASK2_RD__dma8_sub0_descr__inactive 0 | ||
| 4564 | #define R_IRQ_MASK2_RD__dma9_eop__BITNR 19 | ||
| 4565 | #define R_IRQ_MASK2_RD__dma9_eop__WIDTH 1 | ||
| 4566 | #define R_IRQ_MASK2_RD__dma9_eop__active 1 | ||
| 4567 | #define R_IRQ_MASK2_RD__dma9_eop__inactive 0 | ||
| 4568 | #define R_IRQ_MASK2_RD__dma9_descr__BITNR 18 | ||
| 4569 | #define R_IRQ_MASK2_RD__dma9_descr__WIDTH 1 | ||
| 4570 | #define R_IRQ_MASK2_RD__dma9_descr__active 1 | ||
| 4571 | #define R_IRQ_MASK2_RD__dma9_descr__inactive 0 | ||
| 4572 | #define R_IRQ_MASK2_RD__dma8_eop__BITNR 17 | ||
| 4573 | #define R_IRQ_MASK2_RD__dma8_eop__WIDTH 1 | ||
| 4574 | #define R_IRQ_MASK2_RD__dma8_eop__active 1 | ||
| 4575 | #define R_IRQ_MASK2_RD__dma8_eop__inactive 0 | ||
| 4576 | #define R_IRQ_MASK2_RD__dma8_descr__BITNR 16 | ||
| 4577 | #define R_IRQ_MASK2_RD__dma8_descr__WIDTH 1 | ||
| 4578 | #define R_IRQ_MASK2_RD__dma8_descr__active 1 | ||
| 4579 | #define R_IRQ_MASK2_RD__dma8_descr__inactive 0 | ||
| 4580 | #define R_IRQ_MASK2_RD__dma7_eop__BITNR 15 | ||
| 4581 | #define R_IRQ_MASK2_RD__dma7_eop__WIDTH 1 | ||
| 4582 | #define R_IRQ_MASK2_RD__dma7_eop__active 1 | ||
| 4583 | #define R_IRQ_MASK2_RD__dma7_eop__inactive 0 | ||
| 4584 | #define R_IRQ_MASK2_RD__dma7_descr__BITNR 14 | ||
| 4585 | #define R_IRQ_MASK2_RD__dma7_descr__WIDTH 1 | ||
| 4586 | #define R_IRQ_MASK2_RD__dma7_descr__active 1 | ||
| 4587 | #define R_IRQ_MASK2_RD__dma7_descr__inactive 0 | ||
| 4588 | #define R_IRQ_MASK2_RD__dma6_eop__BITNR 13 | ||
| 4589 | #define R_IRQ_MASK2_RD__dma6_eop__WIDTH 1 | ||
| 4590 | #define R_IRQ_MASK2_RD__dma6_eop__active 1 | ||
| 4591 | #define R_IRQ_MASK2_RD__dma6_eop__inactive 0 | ||
| 4592 | #define R_IRQ_MASK2_RD__dma6_descr__BITNR 12 | ||
| 4593 | #define R_IRQ_MASK2_RD__dma6_descr__WIDTH 1 | ||
| 4594 | #define R_IRQ_MASK2_RD__dma6_descr__active 1 | ||
| 4595 | #define R_IRQ_MASK2_RD__dma6_descr__inactive 0 | ||
| 4596 | #define R_IRQ_MASK2_RD__dma5_eop__BITNR 11 | ||
| 4597 | #define R_IRQ_MASK2_RD__dma5_eop__WIDTH 1 | ||
| 4598 | #define R_IRQ_MASK2_RD__dma5_eop__active 1 | ||
| 4599 | #define R_IRQ_MASK2_RD__dma5_eop__inactive 0 | ||
| 4600 | #define R_IRQ_MASK2_RD__dma5_descr__BITNR 10 | ||
| 4601 | #define R_IRQ_MASK2_RD__dma5_descr__WIDTH 1 | ||
| 4602 | #define R_IRQ_MASK2_RD__dma5_descr__active 1 | ||
| 4603 | #define R_IRQ_MASK2_RD__dma5_descr__inactive 0 | ||
| 4604 | #define R_IRQ_MASK2_RD__dma4_eop__BITNR 9 | ||
| 4605 | #define R_IRQ_MASK2_RD__dma4_eop__WIDTH 1 | ||
| 4606 | #define R_IRQ_MASK2_RD__dma4_eop__active 1 | ||
| 4607 | #define R_IRQ_MASK2_RD__dma4_eop__inactive 0 | ||
| 4608 | #define R_IRQ_MASK2_RD__dma4_descr__BITNR 8 | ||
| 4609 | #define R_IRQ_MASK2_RD__dma4_descr__WIDTH 1 | ||
| 4610 | #define R_IRQ_MASK2_RD__dma4_descr__active 1 | ||
| 4611 | #define R_IRQ_MASK2_RD__dma4_descr__inactive 0 | ||
| 4612 | #define R_IRQ_MASK2_RD__dma3_eop__BITNR 7 | ||
| 4613 | #define R_IRQ_MASK2_RD__dma3_eop__WIDTH 1 | ||
| 4614 | #define R_IRQ_MASK2_RD__dma3_eop__active 1 | ||
| 4615 | #define R_IRQ_MASK2_RD__dma3_eop__inactive 0 | ||
| 4616 | #define R_IRQ_MASK2_RD__dma3_descr__BITNR 6 | ||
| 4617 | #define R_IRQ_MASK2_RD__dma3_descr__WIDTH 1 | ||
| 4618 | #define R_IRQ_MASK2_RD__dma3_descr__active 1 | ||
| 4619 | #define R_IRQ_MASK2_RD__dma3_descr__inactive 0 | ||
| 4620 | #define R_IRQ_MASK2_RD__dma2_eop__BITNR 5 | ||
| 4621 | #define R_IRQ_MASK2_RD__dma2_eop__WIDTH 1 | ||
| 4622 | #define R_IRQ_MASK2_RD__dma2_eop__active 1 | ||
| 4623 | #define R_IRQ_MASK2_RD__dma2_eop__inactive 0 | ||
| 4624 | #define R_IRQ_MASK2_RD__dma2_descr__BITNR 4 | ||
| 4625 | #define R_IRQ_MASK2_RD__dma2_descr__WIDTH 1 | ||
| 4626 | #define R_IRQ_MASK2_RD__dma2_descr__active 1 | ||
| 4627 | #define R_IRQ_MASK2_RD__dma2_descr__inactive 0 | ||
| 4628 | #define R_IRQ_MASK2_RD__dma1_eop__BITNR 3 | ||
| 4629 | #define R_IRQ_MASK2_RD__dma1_eop__WIDTH 1 | ||
| 4630 | #define R_IRQ_MASK2_RD__dma1_eop__active 1 | ||
| 4631 | #define R_IRQ_MASK2_RD__dma1_eop__inactive 0 | ||
| 4632 | #define R_IRQ_MASK2_RD__dma1_descr__BITNR 2 | ||
| 4633 | #define R_IRQ_MASK2_RD__dma1_descr__WIDTH 1 | ||
| 4634 | #define R_IRQ_MASK2_RD__dma1_descr__active 1 | ||
| 4635 | #define R_IRQ_MASK2_RD__dma1_descr__inactive 0 | ||
| 4636 | #define R_IRQ_MASK2_RD__dma0_eop__BITNR 1 | ||
| 4637 | #define R_IRQ_MASK2_RD__dma0_eop__WIDTH 1 | ||
| 4638 | #define R_IRQ_MASK2_RD__dma0_eop__active 1 | ||
| 4639 | #define R_IRQ_MASK2_RD__dma0_eop__inactive 0 | ||
| 4640 | #define R_IRQ_MASK2_RD__dma0_descr__BITNR 0 | ||
| 4641 | #define R_IRQ_MASK2_RD__dma0_descr__WIDTH 1 | ||
| 4642 | #define R_IRQ_MASK2_RD__dma0_descr__active 1 | ||
| 4643 | #define R_IRQ_MASK2_RD__dma0_descr__inactive 0 | ||
| 4644 | |||
| 4645 | #define R_IRQ_MASK2_CLR (IO_TYPECAST_UDWORD 0xb00000d0) | ||
| 4646 | #define R_IRQ_MASK2_CLR__dma8_sub3_descr__BITNR 23 | ||
| 4647 | #define R_IRQ_MASK2_CLR__dma8_sub3_descr__WIDTH 1 | ||
| 4648 | #define R_IRQ_MASK2_CLR__dma8_sub3_descr__clr 1 | ||
| 4649 | #define R_IRQ_MASK2_CLR__dma8_sub3_descr__nop 0 | ||
| 4650 | #define R_IRQ_MASK2_CLR__dma8_sub2_descr__BITNR 22 | ||
| 4651 | #define R_IRQ_MASK2_CLR__dma8_sub2_descr__WIDTH 1 | ||
| 4652 | #define R_IRQ_MASK2_CLR__dma8_sub2_descr__clr 1 | ||
| 4653 | #define R_IRQ_MASK2_CLR__dma8_sub2_descr__nop 0 | ||
| 4654 | #define R_IRQ_MASK2_CLR__dma8_sub1_descr__BITNR 21 | ||
| 4655 | #define R_IRQ_MASK2_CLR__dma8_sub1_descr__WIDTH 1 | ||
| 4656 | #define R_IRQ_MASK2_CLR__dma8_sub1_descr__clr 1 | ||
| 4657 | #define R_IRQ_MASK2_CLR__dma8_sub1_descr__nop 0 | ||
| 4658 | #define R_IRQ_MASK2_CLR__dma8_sub0_descr__BITNR 20 | ||
| 4659 | #define R_IRQ_MASK2_CLR__dma8_sub0_descr__WIDTH 1 | ||
| 4660 | #define R_IRQ_MASK2_CLR__dma8_sub0_descr__clr 1 | ||
| 4661 | #define R_IRQ_MASK2_CLR__dma8_sub0_descr__nop 0 | ||
| 4662 | #define R_IRQ_MASK2_CLR__dma9_eop__BITNR 19 | ||
| 4663 | #define R_IRQ_MASK2_CLR__dma9_eop__WIDTH 1 | ||
| 4664 | #define R_IRQ_MASK2_CLR__dma9_eop__clr 1 | ||
| 4665 | #define R_IRQ_MASK2_CLR__dma9_eop__nop 0 | ||
| 4666 | #define R_IRQ_MASK2_CLR__dma9_descr__BITNR 18 | ||
| 4667 | #define R_IRQ_MASK2_CLR__dma9_descr__WIDTH 1 | ||
| 4668 | #define R_IRQ_MASK2_CLR__dma9_descr__clr 1 | ||
| 4669 | #define R_IRQ_MASK2_CLR__dma9_descr__nop 0 | ||
| 4670 | #define R_IRQ_MASK2_CLR__dma8_eop__BITNR 17 | ||
| 4671 | #define R_IRQ_MASK2_CLR__dma8_eop__WIDTH 1 | ||
| 4672 | #define R_IRQ_MASK2_CLR__dma8_eop__clr 1 | ||
| 4673 | #define R_IRQ_MASK2_CLR__dma8_eop__nop 0 | ||
| 4674 | #define R_IRQ_MASK2_CLR__dma8_descr__BITNR 16 | ||
| 4675 | #define R_IRQ_MASK2_CLR__dma8_descr__WIDTH 1 | ||
| 4676 | #define R_IRQ_MASK2_CLR__dma8_descr__clr 1 | ||
| 4677 | #define R_IRQ_MASK2_CLR__dma8_descr__nop 0 | ||
| 4678 | #define R_IRQ_MASK2_CLR__dma7_eop__BITNR 15 | ||
| 4679 | #define R_IRQ_MASK2_CLR__dma7_eop__WIDTH 1 | ||
| 4680 | #define R_IRQ_MASK2_CLR__dma7_eop__clr 1 | ||
| 4681 | #define R_IRQ_MASK2_CLR__dma7_eop__nop 0 | ||
| 4682 | #define R_IRQ_MASK2_CLR__dma7_descr__BITNR 14 | ||
| 4683 | #define R_IRQ_MASK2_CLR__dma7_descr__WIDTH 1 | ||
| 4684 | #define R_IRQ_MASK2_CLR__dma7_descr__clr 1 | ||
| 4685 | #define R_IRQ_MASK2_CLR__dma7_descr__nop 0 | ||
| 4686 | #define R_IRQ_MASK2_CLR__dma6_eop__BITNR 13 | ||
| 4687 | #define R_IRQ_MASK2_CLR__dma6_eop__WIDTH 1 | ||
| 4688 | #define R_IRQ_MASK2_CLR__dma6_eop__clr 1 | ||
| 4689 | #define R_IRQ_MASK2_CLR__dma6_eop__nop 0 | ||
| 4690 | #define R_IRQ_MASK2_CLR__dma6_descr__BITNR 12 | ||
| 4691 | #define R_IRQ_MASK2_CLR__dma6_descr__WIDTH 1 | ||
| 4692 | #define R_IRQ_MASK2_CLR__dma6_descr__clr 1 | ||
| 4693 | #define R_IRQ_MASK2_CLR__dma6_descr__nop 0 | ||
| 4694 | #define R_IRQ_MASK2_CLR__dma5_eop__BITNR 11 | ||
| 4695 | #define R_IRQ_MASK2_CLR__dma5_eop__WIDTH 1 | ||
| 4696 | #define R_IRQ_MASK2_CLR__dma5_eop__clr 1 | ||
| 4697 | #define R_IRQ_MASK2_CLR__dma5_eop__nop 0 | ||
| 4698 | #define R_IRQ_MASK2_CLR__dma5_descr__BITNR 10 | ||
| 4699 | #define R_IRQ_MASK2_CLR__dma5_descr__WIDTH 1 | ||
| 4700 | #define R_IRQ_MASK2_CLR__dma5_descr__clr 1 | ||
| 4701 | #define R_IRQ_MASK2_CLR__dma5_descr__nop 0 | ||
| 4702 | #define R_IRQ_MASK2_CLR__dma4_eop__BITNR 9 | ||
| 4703 | #define R_IRQ_MASK2_CLR__dma4_eop__WIDTH 1 | ||
| 4704 | #define R_IRQ_MASK2_CLR__dma4_eop__clr 1 | ||
| 4705 | #define R_IRQ_MASK2_CLR__dma4_eop__nop 0 | ||
| 4706 | #define R_IRQ_MASK2_CLR__dma4_descr__BITNR 8 | ||
| 4707 | #define R_IRQ_MASK2_CLR__dma4_descr__WIDTH 1 | ||
| 4708 | #define R_IRQ_MASK2_CLR__dma4_descr__clr 1 | ||
| 4709 | #define R_IRQ_MASK2_CLR__dma4_descr__nop 0 | ||
| 4710 | #define R_IRQ_MASK2_CLR__dma3_eop__BITNR 7 | ||
| 4711 | #define R_IRQ_MASK2_CLR__dma3_eop__WIDTH 1 | ||
| 4712 | #define R_IRQ_MASK2_CLR__dma3_eop__clr 1 | ||
| 4713 | #define R_IRQ_MASK2_CLR__dma3_eop__nop 0 | ||
| 4714 | #define R_IRQ_MASK2_CLR__dma3_descr__BITNR 6 | ||
| 4715 | #define R_IRQ_MASK2_CLR__dma3_descr__WIDTH 1 | ||
| 4716 | #define R_IRQ_MASK2_CLR__dma3_descr__clr 1 | ||
| 4717 | #define R_IRQ_MASK2_CLR__dma3_descr__nop 0 | ||
| 4718 | #define R_IRQ_MASK2_CLR__dma2_eop__BITNR 5 | ||
| 4719 | #define R_IRQ_MASK2_CLR__dma2_eop__WIDTH 1 | ||
| 4720 | #define R_IRQ_MASK2_CLR__dma2_eop__clr 1 | ||
| 4721 | #define R_IRQ_MASK2_CLR__dma2_eop__nop 0 | ||
| 4722 | #define R_IRQ_MASK2_CLR__dma2_descr__BITNR 4 | ||
| 4723 | #define R_IRQ_MASK2_CLR__dma2_descr__WIDTH 1 | ||
| 4724 | #define R_IRQ_MASK2_CLR__dma2_descr__clr 1 | ||
| 4725 | #define R_IRQ_MASK2_CLR__dma2_descr__nop 0 | ||
| 4726 | #define R_IRQ_MASK2_CLR__dma1_eop__BITNR 3 | ||
| 4727 | #define R_IRQ_MASK2_CLR__dma1_eop__WIDTH 1 | ||
| 4728 | #define R_IRQ_MASK2_CLR__dma1_eop__clr 1 | ||
| 4729 | #define R_IRQ_MASK2_CLR__dma1_eop__nop 0 | ||
| 4730 | #define R_IRQ_MASK2_CLR__dma1_descr__BITNR 2 | ||
| 4731 | #define R_IRQ_MASK2_CLR__dma1_descr__WIDTH 1 | ||
| 4732 | #define R_IRQ_MASK2_CLR__dma1_descr__clr 1 | ||
| 4733 | #define R_IRQ_MASK2_CLR__dma1_descr__nop 0 | ||
| 4734 | #define R_IRQ_MASK2_CLR__dma0_eop__BITNR 1 | ||
| 4735 | #define R_IRQ_MASK2_CLR__dma0_eop__WIDTH 1 | ||
| 4736 | #define R_IRQ_MASK2_CLR__dma0_eop__clr 1 | ||
| 4737 | #define R_IRQ_MASK2_CLR__dma0_eop__nop 0 | ||
| 4738 | #define R_IRQ_MASK2_CLR__dma0_descr__BITNR 0 | ||
| 4739 | #define R_IRQ_MASK2_CLR__dma0_descr__WIDTH 1 | ||
| 4740 | #define R_IRQ_MASK2_CLR__dma0_descr__clr 1 | ||
| 4741 | #define R_IRQ_MASK2_CLR__dma0_descr__nop 0 | ||
| 4742 | |||
| 4743 | #define R_IRQ_READ2 (IO_TYPECAST_RO_UDWORD 0xb00000d4) | ||
| 4744 | #define R_IRQ_READ2__dma8_sub3_descr__BITNR 23 | ||
| 4745 | #define R_IRQ_READ2__dma8_sub3_descr__WIDTH 1 | ||
| 4746 | #define R_IRQ_READ2__dma8_sub3_descr__active 1 | ||
| 4747 | #define R_IRQ_READ2__dma8_sub3_descr__inactive 0 | ||
| 4748 | #define R_IRQ_READ2__dma8_sub2_descr__BITNR 22 | ||
| 4749 | #define R_IRQ_READ2__dma8_sub2_descr__WIDTH 1 | ||
| 4750 | #define R_IRQ_READ2__dma8_sub2_descr__active 1 | ||
| 4751 | #define R_IRQ_READ2__dma8_sub2_descr__inactive 0 | ||
| 4752 | #define R_IRQ_READ2__dma8_sub1_descr__BITNR 21 | ||
| 4753 | #define R_IRQ_READ2__dma8_sub1_descr__WIDTH 1 | ||
| 4754 | #define R_IRQ_READ2__dma8_sub1_descr__active 1 | ||
| 4755 | #define R_IRQ_READ2__dma8_sub1_descr__inactive 0 | ||
| 4756 | #define R_IRQ_READ2__dma8_sub0_descr__BITNR 20 | ||
| 4757 | #define R_IRQ_READ2__dma8_sub0_descr__WIDTH 1 | ||
| 4758 | #define R_IRQ_READ2__dma8_sub0_descr__active 1 | ||
| 4759 | #define R_IRQ_READ2__dma8_sub0_descr__inactive 0 | ||
| 4760 | #define R_IRQ_READ2__dma9_eop__BITNR 19 | ||
| 4761 | #define R_IRQ_READ2__dma9_eop__WIDTH 1 | ||
| 4762 | #define R_IRQ_READ2__dma9_eop__active 1 | ||
| 4763 | #define R_IRQ_READ2__dma9_eop__inactive 0 | ||
| 4764 | #define R_IRQ_READ2__dma9_descr__BITNR 18 | ||
| 4765 | #define R_IRQ_READ2__dma9_descr__WIDTH 1 | ||
| 4766 | #define R_IRQ_READ2__dma9_descr__active 1 | ||
| 4767 | #define R_IRQ_READ2__dma9_descr__inactive 0 | ||
| 4768 | #define R_IRQ_READ2__dma8_eop__BITNR 17 | ||
| 4769 | #define R_IRQ_READ2__dma8_eop__WIDTH 1 | ||
| 4770 | #define R_IRQ_READ2__dma8_eop__active 1 | ||
| 4771 | #define R_IRQ_READ2__dma8_eop__inactive 0 | ||
| 4772 | #define R_IRQ_READ2__dma8_descr__BITNR 16 | ||
| 4773 | #define R_IRQ_READ2__dma8_descr__WIDTH 1 | ||
| 4774 | #define R_IRQ_READ2__dma8_descr__active 1 | ||
| 4775 | #define R_IRQ_READ2__dma8_descr__inactive 0 | ||
| 4776 | #define R_IRQ_READ2__dma7_eop__BITNR 15 | ||
| 4777 | #define R_IRQ_READ2__dma7_eop__WIDTH 1 | ||
| 4778 | #define R_IRQ_READ2__dma7_eop__active 1 | ||
| 4779 | #define R_IRQ_READ2__dma7_eop__inactive 0 | ||
| 4780 | #define R_IRQ_READ2__dma7_descr__BITNR 14 | ||
| 4781 | #define R_IRQ_READ2__dma7_descr__WIDTH 1 | ||
| 4782 | #define R_IRQ_READ2__dma7_descr__active 1 | ||
| 4783 | #define R_IRQ_READ2__dma7_descr__inactive 0 | ||
| 4784 | #define R_IRQ_READ2__dma6_eop__BITNR 13 | ||
| 4785 | #define R_IRQ_READ2__dma6_eop__WIDTH 1 | ||
| 4786 | #define R_IRQ_READ2__dma6_eop__active 1 | ||
| 4787 | #define R_IRQ_READ2__dma6_eop__inactive 0 | ||
| 4788 | #define R_IRQ_READ2__dma6_descr__BITNR 12 | ||
| 4789 | #define R_IRQ_READ2__dma6_descr__WIDTH 1 | ||
| 4790 | #define R_IRQ_READ2__dma6_descr__active 1 | ||
| 4791 | #define R_IRQ_READ2__dma6_descr__inactive 0 | ||
| 4792 | #define R_IRQ_READ2__dma5_eop__BITNR 11 | ||
| 4793 | #define R_IRQ_READ2__dma5_eop__WIDTH 1 | ||
| 4794 | #define R_IRQ_READ2__dma5_eop__active 1 | ||
| 4795 | #define R_IRQ_READ2__dma5_eop__inactive 0 | ||
| 4796 | #define R_IRQ_READ2__dma5_descr__BITNR 10 | ||
| 4797 | #define R_IRQ_READ2__dma5_descr__WIDTH 1 | ||
| 4798 | #define R_IRQ_READ2__dma5_descr__active 1 | ||
| 4799 | #define R_IRQ_READ2__dma5_descr__inactive 0 | ||
| 4800 | #define R_IRQ_READ2__dma4_eop__BITNR 9 | ||
| 4801 | #define R_IRQ_READ2__dma4_eop__WIDTH 1 | ||
| 4802 | #define R_IRQ_READ2__dma4_eop__active 1 | ||
| 4803 | #define R_IRQ_READ2__dma4_eop__inactive 0 | ||
| 4804 | #define R_IRQ_READ2__dma4_descr__BITNR 8 | ||
| 4805 | #define R_IRQ_READ2__dma4_descr__WIDTH 1 | ||
| 4806 | #define R_IRQ_READ2__dma4_descr__active 1 | ||
| 4807 | #define R_IRQ_READ2__dma4_descr__inactive 0 | ||
| 4808 | #define R_IRQ_READ2__dma3_eop__BITNR 7 | ||
| 4809 | #define R_IRQ_READ2__dma3_eop__WIDTH 1 | ||
| 4810 | #define R_IRQ_READ2__dma3_eop__active 1 | ||
| 4811 | #define R_IRQ_READ2__dma3_eop__inactive 0 | ||
| 4812 | #define R_IRQ_READ2__dma3_descr__BITNR 6 | ||
| 4813 | #define R_IRQ_READ2__dma3_descr__WIDTH 1 | ||
| 4814 | #define R_IRQ_READ2__dma3_descr__active 1 | ||
| 4815 | #define R_IRQ_READ2__dma3_descr__inactive 0 | ||
| 4816 | #define R_IRQ_READ2__dma2_eop__BITNR 5 | ||
| 4817 | #define R_IRQ_READ2__dma2_eop__WIDTH 1 | ||
| 4818 | #define R_IRQ_READ2__dma2_eop__active 1 | ||
| 4819 | #define R_IRQ_READ2__dma2_eop__inactive 0 | ||
| 4820 | #define R_IRQ_READ2__dma2_descr__BITNR 4 | ||
| 4821 | #define R_IRQ_READ2__dma2_descr__WIDTH 1 | ||
| 4822 | #define R_IRQ_READ2__dma2_descr__active 1 | ||
| 4823 | #define R_IRQ_READ2__dma2_descr__inactive 0 | ||
| 4824 | #define R_IRQ_READ2__dma1_eop__BITNR 3 | ||
| 4825 | #define R_IRQ_READ2__dma1_eop__WIDTH 1 | ||
| 4826 | #define R_IRQ_READ2__dma1_eop__active 1 | ||
| 4827 | #define R_IRQ_READ2__dma1_eop__inactive 0 | ||
| 4828 | #define R_IRQ_READ2__dma1_descr__BITNR 2 | ||
| 4829 | #define R_IRQ_READ2__dma1_descr__WIDTH 1 | ||
| 4830 | #define R_IRQ_READ2__dma1_descr__active 1 | ||
| 4831 | #define R_IRQ_READ2__dma1_descr__inactive 0 | ||
| 4832 | #define R_IRQ_READ2__dma0_eop__BITNR 1 | ||
| 4833 | #define R_IRQ_READ2__dma0_eop__WIDTH 1 | ||
| 4834 | #define R_IRQ_READ2__dma0_eop__active 1 | ||
| 4835 | #define R_IRQ_READ2__dma0_eop__inactive 0 | ||
| 4836 | #define R_IRQ_READ2__dma0_descr__BITNR 0 | ||
| 4837 | #define R_IRQ_READ2__dma0_descr__WIDTH 1 | ||
| 4838 | #define R_IRQ_READ2__dma0_descr__active 1 | ||
| 4839 | #define R_IRQ_READ2__dma0_descr__inactive 0 | ||
| 4840 | |||
| 4841 | #define R_IRQ_MASK2_SET (IO_TYPECAST_UDWORD 0xb00000d4) | ||
| 4842 | #define R_IRQ_MASK2_SET__dma8_sub3_descr__BITNR 23 | ||
| 4843 | #define R_IRQ_MASK2_SET__dma8_sub3_descr__WIDTH 1 | ||
| 4844 | #define R_IRQ_MASK2_SET__dma8_sub3_descr__set 1 | ||
| 4845 | #define R_IRQ_MASK2_SET__dma8_sub3_descr__nop 0 | ||
| 4846 | #define R_IRQ_MASK2_SET__dma8_sub2_descr__BITNR 22 | ||
| 4847 | #define R_IRQ_MASK2_SET__dma8_sub2_descr__WIDTH 1 | ||
| 4848 | #define R_IRQ_MASK2_SET__dma8_sub2_descr__set 1 | ||
| 4849 | #define R_IRQ_MASK2_SET__dma8_sub2_descr__nop 0 | ||
| 4850 | #define R_IRQ_MASK2_SET__dma8_sub1_descr__BITNR 21 | ||
| 4851 | #define R_IRQ_MASK2_SET__dma8_sub1_descr__WIDTH 1 | ||
| 4852 | #define R_IRQ_MASK2_SET__dma8_sub1_descr__set 1 | ||
| 4853 | #define R_IRQ_MASK2_SET__dma8_sub1_descr__nop 0 | ||
| 4854 | #define R_IRQ_MASK2_SET__dma8_sub0_descr__BITNR 20 | ||
| 4855 | #define R_IRQ_MASK2_SET__dma8_sub0_descr__WIDTH 1 | ||
| 4856 | #define R_IRQ_MASK2_SET__dma8_sub0_descr__set 1 | ||
| 4857 | #define R_IRQ_MASK2_SET__dma8_sub0_descr__nop 0 | ||
| 4858 | #define R_IRQ_MASK2_SET__dma9_eop__BITNR 19 | ||
| 4859 | #define R_IRQ_MASK2_SET__dma9_eop__WIDTH 1 | ||
| 4860 | #define R_IRQ_MASK2_SET__dma9_eop__set 1 | ||
| 4861 | #define R_IRQ_MASK2_SET__dma9_eop__nop 0 | ||
| 4862 | #define R_IRQ_MASK2_SET__dma9_descr__BITNR 18 | ||
| 4863 | #define R_IRQ_MASK2_SET__dma9_descr__WIDTH 1 | ||
| 4864 | #define R_IRQ_MASK2_SET__dma9_descr__set 1 | ||
| 4865 | #define R_IRQ_MASK2_SET__dma9_descr__nop 0 | ||
| 4866 | #define R_IRQ_MASK2_SET__dma8_eop__BITNR 17 | ||
| 4867 | #define R_IRQ_MASK2_SET__dma8_eop__WIDTH 1 | ||
| 4868 | #define R_IRQ_MASK2_SET__dma8_eop__set 1 | ||
| 4869 | #define R_IRQ_MASK2_SET__dma8_eop__nop 0 | ||
| 4870 | #define R_IRQ_MASK2_SET__dma8_descr__BITNR 16 | ||
| 4871 | #define R_IRQ_MASK2_SET__dma8_descr__WIDTH 1 | ||
| 4872 | #define R_IRQ_MASK2_SET__dma8_descr__set 1 | ||
| 4873 | #define R_IRQ_MASK2_SET__dma8_descr__nop 0 | ||
| 4874 | #define R_IRQ_MASK2_SET__dma7_eop__BITNR 15 | ||
| 4875 | #define R_IRQ_MASK2_SET__dma7_eop__WIDTH 1 | ||
| 4876 | #define R_IRQ_MASK2_SET__dma7_eop__set 1 | ||
| 4877 | #define R_IRQ_MASK2_SET__dma7_eop__nop 0 | ||
| 4878 | #define R_IRQ_MASK2_SET__dma7_descr__BITNR 14 | ||
| 4879 | #define R_IRQ_MASK2_SET__dma7_descr__WIDTH 1 | ||
| 4880 | #define R_IRQ_MASK2_SET__dma7_descr__set 1 | ||
| 4881 | #define R_IRQ_MASK2_SET__dma7_descr__nop 0 | ||
| 4882 | #define R_IRQ_MASK2_SET__dma6_eop__BITNR 13 | ||
| 4883 | #define R_IRQ_MASK2_SET__dma6_eop__WIDTH 1 | ||
| 4884 | #define R_IRQ_MASK2_SET__dma6_eop__set 1 | ||
| 4885 | #define R_IRQ_MASK2_SET__dma6_eop__nop 0 | ||
| 4886 | #define R_IRQ_MASK2_SET__dma6_descr__BITNR 12 | ||
| 4887 | #define R_IRQ_MASK2_SET__dma6_descr__WIDTH 1 | ||
| 4888 | #define R_IRQ_MASK2_SET__dma6_descr__set 1 | ||
| 4889 | #define R_IRQ_MASK2_SET__dma6_descr__nop 0 | ||
| 4890 | #define R_IRQ_MASK2_SET__dma5_eop__BITNR 11 | ||
| 4891 | #define R_IRQ_MASK2_SET__dma5_eop__WIDTH 1 | ||
| 4892 | #define R_IRQ_MASK2_SET__dma5_eop__set 1 | ||
| 4893 | #define R_IRQ_MASK2_SET__dma5_eop__nop 0 | ||
| 4894 | #define R_IRQ_MASK2_SET__dma5_descr__BITNR 10 | ||
| 4895 | #define R_IRQ_MASK2_SET__dma5_descr__WIDTH 1 | ||
| 4896 | #define R_IRQ_MASK2_SET__dma5_descr__set 1 | ||
| 4897 | #define R_IRQ_MASK2_SET__dma5_descr__nop 0 | ||
| 4898 | #define R_IRQ_MASK2_SET__dma4_eop__BITNR 9 | ||
| 4899 | #define R_IRQ_MASK2_SET__dma4_eop__WIDTH 1 | ||
| 4900 | #define R_IRQ_MASK2_SET__dma4_eop__set 1 | ||
| 4901 | #define R_IRQ_MASK2_SET__dma4_eop__nop 0 | ||
| 4902 | #define R_IRQ_MASK2_SET__dma4_descr__BITNR 8 | ||
| 4903 | #define R_IRQ_MASK2_SET__dma4_descr__WIDTH 1 | ||
| 4904 | #define R_IRQ_MASK2_SET__dma4_descr__set 1 | ||
| 4905 | #define R_IRQ_MASK2_SET__dma4_descr__nop 0 | ||
| 4906 | #define R_IRQ_MASK2_SET__dma3_eop__BITNR 7 | ||
| 4907 | #define R_IRQ_MASK2_SET__dma3_eop__WIDTH 1 | ||
| 4908 | #define R_IRQ_MASK2_SET__dma3_eop__set 1 | ||
| 4909 | #define R_IRQ_MASK2_SET__dma3_eop__nop 0 | ||
| 4910 | #define R_IRQ_MASK2_SET__dma3_descr__BITNR 6 | ||
| 4911 | #define R_IRQ_MASK2_SET__dma3_descr__WIDTH 1 | ||
| 4912 | #define R_IRQ_MASK2_SET__dma3_descr__set 1 | ||
| 4913 | #define R_IRQ_MASK2_SET__dma3_descr__nop 0 | ||
| 4914 | #define R_IRQ_MASK2_SET__dma2_eop__BITNR 5 | ||
| 4915 | #define R_IRQ_MASK2_SET__dma2_eop__WIDTH 1 | ||
| 4916 | #define R_IRQ_MASK2_SET__dma2_eop__set 1 | ||
| 4917 | #define R_IRQ_MASK2_SET__dma2_eop__nop 0 | ||
| 4918 | #define R_IRQ_MASK2_SET__dma2_descr__BITNR 4 | ||
| 4919 | #define R_IRQ_MASK2_SET__dma2_descr__WIDTH 1 | ||
| 4920 | #define R_IRQ_MASK2_SET__dma2_descr__set 1 | ||
| 4921 | #define R_IRQ_MASK2_SET__dma2_descr__nop 0 | ||
| 4922 | #define R_IRQ_MASK2_SET__dma1_eop__BITNR 3 | ||
| 4923 | #define R_IRQ_MASK2_SET__dma1_eop__WIDTH 1 | ||
| 4924 | #define R_IRQ_MASK2_SET__dma1_eop__set 1 | ||
| 4925 | #define R_IRQ_MASK2_SET__dma1_eop__nop 0 | ||
| 4926 | #define R_IRQ_MASK2_SET__dma1_descr__BITNR 2 | ||
| 4927 | #define R_IRQ_MASK2_SET__dma1_descr__WIDTH 1 | ||
| 4928 | #define R_IRQ_MASK2_SET__dma1_descr__set 1 | ||
| 4929 | #define R_IRQ_MASK2_SET__dma1_descr__nop 0 | ||
| 4930 | #define R_IRQ_MASK2_SET__dma0_eop__BITNR 1 | ||
| 4931 | #define R_IRQ_MASK2_SET__dma0_eop__WIDTH 1 | ||
| 4932 | #define R_IRQ_MASK2_SET__dma0_eop__set 1 | ||
| 4933 | #define R_IRQ_MASK2_SET__dma0_eop__nop 0 | ||
| 4934 | #define R_IRQ_MASK2_SET__dma0_descr__BITNR 0 | ||
| 4935 | #define R_IRQ_MASK2_SET__dma0_descr__WIDTH 1 | ||
| 4936 | #define R_IRQ_MASK2_SET__dma0_descr__set 1 | ||
| 4937 | #define R_IRQ_MASK2_SET__dma0_descr__nop 0 | ||
| 4938 | |||
| 4939 | #define R_VECT_MASK_RD (IO_TYPECAST_RO_UDWORD 0xb00000d8) | ||
| 4940 | #define R_VECT_MASK_RD__usb__BITNR 31 | ||
| 4941 | #define R_VECT_MASK_RD__usb__WIDTH 1 | ||
| 4942 | #define R_VECT_MASK_RD__usb__active 1 | ||
| 4943 | #define R_VECT_MASK_RD__usb__inactive 0 | ||
| 4944 | #define R_VECT_MASK_RD__dma9__BITNR 25 | ||
| 4945 | #define R_VECT_MASK_RD__dma9__WIDTH 1 | ||
| 4946 | #define R_VECT_MASK_RD__dma9__active 1 | ||
| 4947 | #define R_VECT_MASK_RD__dma9__inactive 0 | ||
| 4948 | #define R_VECT_MASK_RD__dma8__BITNR 24 | ||
| 4949 | #define R_VECT_MASK_RD__dma8__WIDTH 1 | ||
| 4950 | #define R_VECT_MASK_RD__dma8__active 1 | ||
| 4951 | #define R_VECT_MASK_RD__dma8__inactive 0 | ||
| 4952 | #define R_VECT_MASK_RD__dma7__BITNR 23 | ||
| 4953 | #define R_VECT_MASK_RD__dma7__WIDTH 1 | ||
| 4954 | #define R_VECT_MASK_RD__dma7__active 1 | ||
| 4955 | #define R_VECT_MASK_RD__dma7__inactive 0 | ||
| 4956 | #define R_VECT_MASK_RD__dma6__BITNR 22 | ||
| 4957 | #define R_VECT_MASK_RD__dma6__WIDTH 1 | ||
| 4958 | #define R_VECT_MASK_RD__dma6__active 1 | ||
| 4959 | #define R_VECT_MASK_RD__dma6__inactive 0 | ||
| 4960 | #define R_VECT_MASK_RD__dma5__BITNR 21 | ||
| 4961 | #define R_VECT_MASK_RD__dma5__WIDTH 1 | ||
| 4962 | #define R_VECT_MASK_RD__dma5__active 1 | ||
| 4963 | #define R_VECT_MASK_RD__dma5__inactive 0 | ||
| 4964 | #define R_VECT_MASK_RD__dma4__BITNR 20 | ||
| 4965 | #define R_VECT_MASK_RD__dma4__WIDTH 1 | ||
| 4966 | #define R_VECT_MASK_RD__dma4__active 1 | ||
| 4967 | #define R_VECT_MASK_RD__dma4__inactive 0 | ||
| 4968 | #define R_VECT_MASK_RD__dma3__BITNR 19 | ||
| 4969 | #define R_VECT_MASK_RD__dma3__WIDTH 1 | ||
| 4970 | #define R_VECT_MASK_RD__dma3__active 1 | ||
| 4971 | #define R_VECT_MASK_RD__dma3__inactive 0 | ||
| 4972 | #define R_VECT_MASK_RD__dma2__BITNR 18 | ||
| 4973 | #define R_VECT_MASK_RD__dma2__WIDTH 1 | ||
| 4974 | #define R_VECT_MASK_RD__dma2__active 1 | ||
| 4975 | #define R_VECT_MASK_RD__dma2__inactive 0 | ||
| 4976 | #define R_VECT_MASK_RD__dma1__BITNR 17 | ||
| 4977 | #define R_VECT_MASK_RD__dma1__WIDTH 1 | ||
| 4978 | #define R_VECT_MASK_RD__dma1__active 1 | ||
| 4979 | #define R_VECT_MASK_RD__dma1__inactive 0 | ||
| 4980 | #define R_VECT_MASK_RD__dma0__BITNR 16 | ||
| 4981 | #define R_VECT_MASK_RD__dma0__WIDTH 1 | ||
| 4982 | #define R_VECT_MASK_RD__dma0__active 1 | ||
| 4983 | #define R_VECT_MASK_RD__dma0__inactive 0 | ||
| 4984 | #define R_VECT_MASK_RD__ext_dma1__BITNR 13 | ||
| 4985 | #define R_VECT_MASK_RD__ext_dma1__WIDTH 1 | ||
| 4986 | #define R_VECT_MASK_RD__ext_dma1__active 1 | ||
| 4987 | #define R_VECT_MASK_RD__ext_dma1__inactive 0 | ||
| 4988 | #define R_VECT_MASK_RD__ext_dma0__BITNR 12 | ||
| 4989 | #define R_VECT_MASK_RD__ext_dma0__WIDTH 1 | ||
| 4990 | #define R_VECT_MASK_RD__ext_dma0__active 1 | ||
| 4991 | #define R_VECT_MASK_RD__ext_dma0__inactive 0 | ||
| 4992 | #define R_VECT_MASK_RD__pa__BITNR 11 | ||
| 4993 | #define R_VECT_MASK_RD__pa__WIDTH 1 | ||
| 4994 | #define R_VECT_MASK_RD__pa__active 1 | ||
| 4995 | #define R_VECT_MASK_RD__pa__inactive 0 | ||
| 4996 | #define R_VECT_MASK_RD__irq_intnr__BITNR 10 | ||
| 4997 | #define R_VECT_MASK_RD__irq_intnr__WIDTH 1 | ||
| 4998 | #define R_VECT_MASK_RD__irq_intnr__active 1 | ||
| 4999 | #define R_VECT_MASK_RD__irq_intnr__inactive 0 | ||
| 5000 | #define R_VECT_MASK_RD__sw__BITNR 9 | ||
| 5001 | #define R_VECT_MASK_RD__sw__WIDTH 1 | ||
| 5002 | #define R_VECT_MASK_RD__sw__active 1 | ||
| 5003 | #define R_VECT_MASK_RD__sw__inactive 0 | ||
| 5004 | #define R_VECT_MASK_RD__serial__BITNR 8 | ||
| 5005 | #define R_VECT_MASK_RD__serial__WIDTH 1 | ||
| 5006 | #define R_VECT_MASK_RD__serial__active 1 | ||
| 5007 | #define R_VECT_MASK_RD__serial__inactive 0 | ||
| 5008 | #define R_VECT_MASK_RD__snmp__BITNR 7 | ||
| 5009 | #define R_VECT_MASK_RD__snmp__WIDTH 1 | ||
| 5010 | #define R_VECT_MASK_RD__snmp__active 1 | ||
| 5011 | #define R_VECT_MASK_RD__snmp__inactive 0 | ||
| 5012 | #define R_VECT_MASK_RD__network__BITNR 6 | ||
| 5013 | #define R_VECT_MASK_RD__network__WIDTH 1 | ||
| 5014 | #define R_VECT_MASK_RD__network__active 1 | ||
| 5015 | #define R_VECT_MASK_RD__network__inactive 0 | ||
| 5016 | #define R_VECT_MASK_RD__scsi1__BITNR 5 | ||
| 5017 | #define R_VECT_MASK_RD__scsi1__WIDTH 1 | ||
| 5018 | #define R_VECT_MASK_RD__scsi1__active 1 | ||
| 5019 | #define R_VECT_MASK_RD__scsi1__inactive 0 | ||
| 5020 | #define R_VECT_MASK_RD__par1__BITNR 5 | ||
| 5021 | #define R_VECT_MASK_RD__par1__WIDTH 1 | ||
| 5022 | #define R_VECT_MASK_RD__par1__active 1 | ||
| 5023 | #define R_VECT_MASK_RD__par1__inactive 0 | ||
| 5024 | #define R_VECT_MASK_RD__scsi0__BITNR 4 | ||
| 5025 | #define R_VECT_MASK_RD__scsi0__WIDTH 1 | ||
| 5026 | #define R_VECT_MASK_RD__scsi0__active 1 | ||
| 5027 | #define R_VECT_MASK_RD__scsi0__inactive 0 | ||
| 5028 | #define R_VECT_MASK_RD__par0__BITNR 4 | ||
| 5029 | #define R_VECT_MASK_RD__par0__WIDTH 1 | ||
| 5030 | #define R_VECT_MASK_RD__par0__active 1 | ||
| 5031 | #define R_VECT_MASK_RD__par0__inactive 0 | ||
| 5032 | #define R_VECT_MASK_RD__ata__BITNR 4 | ||
| 5033 | #define R_VECT_MASK_RD__ata__WIDTH 1 | ||
| 5034 | #define R_VECT_MASK_RD__ata__active 1 | ||
| 5035 | #define R_VECT_MASK_RD__ata__inactive 0 | ||
| 5036 | #define R_VECT_MASK_RD__mio__BITNR 4 | ||
| 5037 | #define R_VECT_MASK_RD__mio__WIDTH 1 | ||
| 5038 | #define R_VECT_MASK_RD__mio__active 1 | ||
| 5039 | #define R_VECT_MASK_RD__mio__inactive 0 | ||
| 5040 | #define R_VECT_MASK_RD__timer1__BITNR 3 | ||
| 5041 | #define R_VECT_MASK_RD__timer1__WIDTH 1 | ||
| 5042 | #define R_VECT_MASK_RD__timer1__active 1 | ||
| 5043 | #define R_VECT_MASK_RD__timer1__inactive 0 | ||
| 5044 | #define R_VECT_MASK_RD__timer0__BITNR 2 | ||
| 5045 | #define R_VECT_MASK_RD__timer0__WIDTH 1 | ||
| 5046 | #define R_VECT_MASK_RD__timer0__active 1 | ||
| 5047 | #define R_VECT_MASK_RD__timer0__inactive 0 | ||
| 5048 | #define R_VECT_MASK_RD__nmi__BITNR 1 | ||
| 5049 | #define R_VECT_MASK_RD__nmi__WIDTH 1 | ||
| 5050 | #define R_VECT_MASK_RD__nmi__active 1 | ||
| 5051 | #define R_VECT_MASK_RD__nmi__inactive 0 | ||
| 5052 | #define R_VECT_MASK_RD__some__BITNR 0 | ||
| 5053 | #define R_VECT_MASK_RD__some__WIDTH 1 | ||
| 5054 | #define R_VECT_MASK_RD__some__active 1 | ||
| 5055 | #define R_VECT_MASK_RD__some__inactive 0 | ||
| 5056 | |||
| 5057 | #define R_VECT_MASK_CLR (IO_TYPECAST_UDWORD 0xb00000d8) | ||
| 5058 | #define R_VECT_MASK_CLR__usb__BITNR 31 | ||
| 5059 | #define R_VECT_MASK_CLR__usb__WIDTH 1 | ||
| 5060 | #define R_VECT_MASK_CLR__usb__clr 1 | ||
| 5061 | #define R_VECT_MASK_CLR__usb__nop 0 | ||
| 5062 | #define R_VECT_MASK_CLR__dma9__BITNR 25 | ||
| 5063 | #define R_VECT_MASK_CLR__dma9__WIDTH 1 | ||
| 5064 | #define R_VECT_MASK_CLR__dma9__clr 1 | ||
| 5065 | #define R_VECT_MASK_CLR__dma9__nop 0 | ||
| 5066 | #define R_VECT_MASK_CLR__dma8__BITNR 24 | ||
| 5067 | #define R_VECT_MASK_CLR__dma8__WIDTH 1 | ||
| 5068 | #define R_VECT_MASK_CLR__dma8__clr 1 | ||
| 5069 | #define R_VECT_MASK_CLR__dma8__nop 0 | ||
| 5070 | #define R_VECT_MASK_CLR__dma7__BITNR 23 | ||
| 5071 | #define R_VECT_MASK_CLR__dma7__WIDTH 1 | ||
| 5072 | #define R_VECT_MASK_CLR__dma7__clr 1 | ||
| 5073 | #define R_VECT_MASK_CLR__dma7__nop 0 | ||
| 5074 | #define R_VECT_MASK_CLR__dma6__BITNR 22 | ||
| 5075 | #define R_VECT_MASK_CLR__dma6__WIDTH 1 | ||
| 5076 | #define R_VECT_MASK_CLR__dma6__clr 1 | ||
| 5077 | #define R_VECT_MASK_CLR__dma6__nop 0 | ||
| 5078 | #define R_VECT_MASK_CLR__dma5__BITNR 21 | ||
| 5079 | #define R_VECT_MASK_CLR__dma5__WIDTH 1 | ||
| 5080 | #define R_VECT_MASK_CLR__dma5__clr 1 | ||
| 5081 | #define R_VECT_MASK_CLR__dma5__nop 0 | ||
| 5082 | #define R_VECT_MASK_CLR__dma4__BITNR 20 | ||
| 5083 | #define R_VECT_MASK_CLR__dma4__WIDTH 1 | ||
| 5084 | #define R_VECT_MASK_CLR__dma4__clr 1 | ||
| 5085 | #define R_VECT_MASK_CLR__dma4__nop 0 | ||
| 5086 | #define R_VECT_MASK_CLR__dma3__BITNR 19 | ||
| 5087 | #define R_VECT_MASK_CLR__dma3__WIDTH 1 | ||
| 5088 | #define R_VECT_MASK_CLR__dma3__clr 1 | ||
| 5089 | #define R_VECT_MASK_CLR__dma3__nop 0 | ||
| 5090 | #define R_VECT_MASK_CLR__dma2__BITNR 18 | ||
| 5091 | #define R_VECT_MASK_CLR__dma2__WIDTH 1 | ||
| 5092 | #define R_VECT_MASK_CLR__dma2__clr 1 | ||
| 5093 | #define R_VECT_MASK_CLR__dma2__nop 0 | ||
| 5094 | #define R_VECT_MASK_CLR__dma1__BITNR 17 | ||
| 5095 | #define R_VECT_MASK_CLR__dma1__WIDTH 1 | ||
| 5096 | #define R_VECT_MASK_CLR__dma1__clr 1 | ||
| 5097 | #define R_VECT_MASK_CLR__dma1__nop 0 | ||
| 5098 | #define R_VECT_MASK_CLR__dma0__BITNR 16 | ||
| 5099 | #define R_VECT_MASK_CLR__dma0__WIDTH 1 | ||
| 5100 | #define R_VECT_MASK_CLR__dma0__clr 1 | ||
| 5101 | #define R_VECT_MASK_CLR__dma0__nop 0 | ||
| 5102 | #define R_VECT_MASK_CLR__ext_dma1__BITNR 13 | ||
| 5103 | #define R_VECT_MASK_CLR__ext_dma1__WIDTH 1 | ||
| 5104 | #define R_VECT_MASK_CLR__ext_dma1__clr 1 | ||
| 5105 | #define R_VECT_MASK_CLR__ext_dma1__nop 0 | ||
| 5106 | #define R_VECT_MASK_CLR__ext_dma0__BITNR 12 | ||
| 5107 | #define R_VECT_MASK_CLR__ext_dma0__WIDTH 1 | ||
| 5108 | #define R_VECT_MASK_CLR__ext_dma0__clr 1 | ||
| 5109 | #define R_VECT_MASK_CLR__ext_dma0__nop 0 | ||
| 5110 | #define R_VECT_MASK_CLR__pa__BITNR 11 | ||
| 5111 | #define R_VECT_MASK_CLR__pa__WIDTH 1 | ||
| 5112 | #define R_VECT_MASK_CLR__pa__clr 1 | ||
| 5113 | #define R_VECT_MASK_CLR__pa__nop 0 | ||
| 5114 | #define R_VECT_MASK_CLR__irq_intnr__BITNR 10 | ||
| 5115 | #define R_VECT_MASK_CLR__irq_intnr__WIDTH 1 | ||
| 5116 | #define R_VECT_MASK_CLR__irq_intnr__clr 1 | ||
| 5117 | #define R_VECT_MASK_CLR__irq_intnr__nop 0 | ||
| 5118 | #define R_VECT_MASK_CLR__sw__BITNR 9 | ||
| 5119 | #define R_VECT_MASK_CLR__sw__WIDTH 1 | ||
| 5120 | #define R_VECT_MASK_CLR__sw__clr 1 | ||
| 5121 | #define R_VECT_MASK_CLR__sw__nop 0 | ||
| 5122 | #define R_VECT_MASK_CLR__serial__BITNR 8 | ||
| 5123 | #define R_VECT_MASK_CLR__serial__WIDTH 1 | ||
| 5124 | #define R_VECT_MASK_CLR__serial__clr 1 | ||
| 5125 | #define R_VECT_MASK_CLR__serial__nop 0 | ||
| 5126 | #define R_VECT_MASK_CLR__snmp__BITNR 7 | ||
| 5127 | #define R_VECT_MASK_CLR__snmp__WIDTH 1 | ||
| 5128 | #define R_VECT_MASK_CLR__snmp__clr 1 | ||
| 5129 | #define R_VECT_MASK_CLR__snmp__nop 0 | ||
| 5130 | #define R_VECT_MASK_CLR__network__BITNR 6 | ||
| 5131 | #define R_VECT_MASK_CLR__network__WIDTH 1 | ||
| 5132 | #define R_VECT_MASK_CLR__network__clr 1 | ||
| 5133 | #define R_VECT_MASK_CLR__network__nop 0 | ||
| 5134 | #define R_VECT_MASK_CLR__scsi1__BITNR 5 | ||
| 5135 | #define R_VECT_MASK_CLR__scsi1__WIDTH 1 | ||
| 5136 | #define R_VECT_MASK_CLR__scsi1__clr 1 | ||
| 5137 | #define R_VECT_MASK_CLR__scsi1__nop 0 | ||
| 5138 | #define R_VECT_MASK_CLR__par1__BITNR 5 | ||
| 5139 | #define R_VECT_MASK_CLR__par1__WIDTH 1 | ||
| 5140 | #define R_VECT_MASK_CLR__par1__clr 1 | ||
| 5141 | #define R_VECT_MASK_CLR__par1__nop 0 | ||
| 5142 | #define R_VECT_MASK_CLR__scsi0__BITNR 4 | ||
| 5143 | #define R_VECT_MASK_CLR__scsi0__WIDTH 1 | ||
| 5144 | #define R_VECT_MASK_CLR__scsi0__clr 1 | ||
| 5145 | #define R_VECT_MASK_CLR__scsi0__nop 0 | ||
| 5146 | #define R_VECT_MASK_CLR__par0__BITNR 4 | ||
| 5147 | #define R_VECT_MASK_CLR__par0__WIDTH 1 | ||
| 5148 | #define R_VECT_MASK_CLR__par0__clr 1 | ||
| 5149 | #define R_VECT_MASK_CLR__par0__nop 0 | ||
| 5150 | #define R_VECT_MASK_CLR__ata__BITNR 4 | ||
| 5151 | #define R_VECT_MASK_CLR__ata__WIDTH 1 | ||
| 5152 | #define R_VECT_MASK_CLR__ata__clr 1 | ||
| 5153 | #define R_VECT_MASK_CLR__ata__nop 0 | ||
| 5154 | #define R_VECT_MASK_CLR__mio__BITNR 4 | ||
| 5155 | #define R_VECT_MASK_CLR__mio__WIDTH 1 | ||
| 5156 | #define R_VECT_MASK_CLR__mio__clr 1 | ||
| 5157 | #define R_VECT_MASK_CLR__mio__nop 0 | ||
| 5158 | #define R_VECT_MASK_CLR__timer1__BITNR 3 | ||
| 5159 | #define R_VECT_MASK_CLR__timer1__WIDTH 1 | ||
| 5160 | #define R_VECT_MASK_CLR__timer1__clr 1 | ||
| 5161 | #define R_VECT_MASK_CLR__timer1__nop 0 | ||
| 5162 | #define R_VECT_MASK_CLR__timer0__BITNR 2 | ||
| 5163 | #define R_VECT_MASK_CLR__timer0__WIDTH 1 | ||
| 5164 | #define R_VECT_MASK_CLR__timer0__clr 1 | ||
| 5165 | #define R_VECT_MASK_CLR__timer0__nop 0 | ||
| 5166 | #define R_VECT_MASK_CLR__nmi__BITNR 1 | ||
| 5167 | #define R_VECT_MASK_CLR__nmi__WIDTH 1 | ||
| 5168 | #define R_VECT_MASK_CLR__nmi__clr 1 | ||
| 5169 | #define R_VECT_MASK_CLR__nmi__nop 0 | ||
| 5170 | #define R_VECT_MASK_CLR__some__BITNR 0 | ||
| 5171 | #define R_VECT_MASK_CLR__some__WIDTH 1 | ||
| 5172 | #define R_VECT_MASK_CLR__some__clr 1 | ||
| 5173 | #define R_VECT_MASK_CLR__some__nop 0 | ||
| 5174 | |||
| 5175 | #define R_VECT_READ (IO_TYPECAST_RO_UDWORD 0xb00000dc) | ||
| 5176 | #define R_VECT_READ__usb__BITNR 31 | ||
| 5177 | #define R_VECT_READ__usb__WIDTH 1 | ||
| 5178 | #define R_VECT_READ__usb__active 1 | ||
| 5179 | #define R_VECT_READ__usb__inactive 0 | ||
| 5180 | #define R_VECT_READ__dma9__BITNR 25 | ||
| 5181 | #define R_VECT_READ__dma9__WIDTH 1 | ||
| 5182 | #define R_VECT_READ__dma9__active 1 | ||
| 5183 | #define R_VECT_READ__dma9__inactive 0 | ||
| 5184 | #define R_VECT_READ__dma8__BITNR 24 | ||
| 5185 | #define R_VECT_READ__dma8__WIDTH 1 | ||
| 5186 | #define R_VECT_READ__dma8__active 1 | ||
| 5187 | #define R_VECT_READ__dma8__inactive 0 | ||
| 5188 | #define R_VECT_READ__dma7__BITNR 23 | ||
| 5189 | #define R_VECT_READ__dma7__WIDTH 1 | ||
| 5190 | #define R_VECT_READ__dma7__active 1 | ||
| 5191 | #define R_VECT_READ__dma7__inactive 0 | ||
| 5192 | #define R_VECT_READ__dma6__BITNR 22 | ||
| 5193 | #define R_VECT_READ__dma6__WIDTH 1 | ||
| 5194 | #define R_VECT_READ__dma6__active 1 | ||
| 5195 | #define R_VECT_READ__dma6__inactive 0 | ||
| 5196 | #define R_VECT_READ__dma5__BITNR 21 | ||
| 5197 | #define R_VECT_READ__dma5__WIDTH 1 | ||
| 5198 | #define R_VECT_READ__dma5__active 1 | ||
| 5199 | #define R_VECT_READ__dma5__inactive 0 | ||
| 5200 | #define R_VECT_READ__dma4__BITNR 20 | ||
| 5201 | #define R_VECT_READ__dma4__WIDTH 1 | ||
| 5202 | #define R_VECT_READ__dma4__active 1 | ||
| 5203 | #define R_VECT_READ__dma4__inactive 0 | ||
| 5204 | #define R_VECT_READ__dma3__BITNR 19 | ||
| 5205 | #define R_VECT_READ__dma3__WIDTH 1 | ||
| 5206 | #define R_VECT_READ__dma3__active 1 | ||
| 5207 | #define R_VECT_READ__dma3__inactive 0 | ||
| 5208 | #define R_VECT_READ__dma2__BITNR 18 | ||
| 5209 | #define R_VECT_READ__dma2__WIDTH 1 | ||
| 5210 | #define R_VECT_READ__dma2__active 1 | ||
| 5211 | #define R_VECT_READ__dma2__inactive 0 | ||
| 5212 | #define R_VECT_READ__dma1__BITNR 17 | ||
| 5213 | #define R_VECT_READ__dma1__WIDTH 1 | ||
| 5214 | #define R_VECT_READ__dma1__active 1 | ||
| 5215 | #define R_VECT_READ__dma1__inactive 0 | ||
| 5216 | #define R_VECT_READ__dma0__BITNR 16 | ||
| 5217 | #define R_VECT_READ__dma0__WIDTH 1 | ||
| 5218 | #define R_VECT_READ__dma0__active 1 | ||
| 5219 | #define R_VECT_READ__dma0__inactive 0 | ||
| 5220 | #define R_VECT_READ__ext_dma1__BITNR 13 | ||
| 5221 | #define R_VECT_READ__ext_dma1__WIDTH 1 | ||
| 5222 | #define R_VECT_READ__ext_dma1__active 1 | ||
| 5223 | #define R_VECT_READ__ext_dma1__inactive 0 | ||
| 5224 | #define R_VECT_READ__ext_dma0__BITNR 12 | ||
| 5225 | #define R_VECT_READ__ext_dma0__WIDTH 1 | ||
| 5226 | #define R_VECT_READ__ext_dma0__active 1 | ||
| 5227 | #define R_VECT_READ__ext_dma0__inactive 0 | ||
| 5228 | #define R_VECT_READ__pa__BITNR 11 | ||
| 5229 | #define R_VECT_READ__pa__WIDTH 1 | ||
| 5230 | #define R_VECT_READ__pa__active 1 | ||
| 5231 | #define R_VECT_READ__pa__inactive 0 | ||
| 5232 | #define R_VECT_READ__irq_intnr__BITNR 10 | ||
| 5233 | #define R_VECT_READ__irq_intnr__WIDTH 1 | ||
| 5234 | #define R_VECT_READ__irq_intnr__active 1 | ||
| 5235 | #define R_VECT_READ__irq_intnr__inactive 0 | ||
| 5236 | #define R_VECT_READ__sw__BITNR 9 | ||
| 5237 | #define R_VECT_READ__sw__WIDTH 1 | ||
| 5238 | #define R_VECT_READ__sw__active 1 | ||
| 5239 | #define R_VECT_READ__sw__inactive 0 | ||
| 5240 | #define R_VECT_READ__serial__BITNR 8 | ||
| 5241 | #define R_VECT_READ__serial__WIDTH 1 | ||
| 5242 | #define R_VECT_READ__serial__active 1 | ||
| 5243 | #define R_VECT_READ__serial__inactive 0 | ||
| 5244 | #define R_VECT_READ__snmp__BITNR 7 | ||
| 5245 | #define R_VECT_READ__snmp__WIDTH 1 | ||
| 5246 | #define R_VECT_READ__snmp__active 1 | ||
| 5247 | #define R_VECT_READ__snmp__inactive 0 | ||
| 5248 | #define R_VECT_READ__network__BITNR 6 | ||
| 5249 | #define R_VECT_READ__network__WIDTH 1 | ||
| 5250 | #define R_VECT_READ__network__active 1 | ||
| 5251 | #define R_VECT_READ__network__inactive 0 | ||
| 5252 | #define R_VECT_READ__scsi1__BITNR 5 | ||
| 5253 | #define R_VECT_READ__scsi1__WIDTH 1 | ||
| 5254 | #define R_VECT_READ__scsi1__active 1 | ||
| 5255 | #define R_VECT_READ__scsi1__inactive 0 | ||
| 5256 | #define R_VECT_READ__par1__BITNR 5 | ||
| 5257 | #define R_VECT_READ__par1__WIDTH 1 | ||
| 5258 | #define R_VECT_READ__par1__active 1 | ||
| 5259 | #define R_VECT_READ__par1__inactive 0 | ||
| 5260 | #define R_VECT_READ__scsi0__BITNR 4 | ||
| 5261 | #define R_VECT_READ__scsi0__WIDTH 1 | ||
| 5262 | #define R_VECT_READ__scsi0__active 1 | ||
| 5263 | #define R_VECT_READ__scsi0__inactive 0 | ||
| 5264 | #define R_VECT_READ__par0__BITNR 4 | ||
| 5265 | #define R_VECT_READ__par0__WIDTH 1 | ||
| 5266 | #define R_VECT_READ__par0__active 1 | ||
| 5267 | #define R_VECT_READ__par0__inactive 0 | ||
| 5268 | #define R_VECT_READ__ata__BITNR 4 | ||
| 5269 | #define R_VECT_READ__ata__WIDTH 1 | ||
| 5270 | #define R_VECT_READ__ata__active 1 | ||
| 5271 | #define R_VECT_READ__ata__inactive 0 | ||
| 5272 | #define R_VECT_READ__mio__BITNR 4 | ||
| 5273 | #define R_VECT_READ__mio__WIDTH 1 | ||
| 5274 | #define R_VECT_READ__mio__active 1 | ||
| 5275 | #define R_VECT_READ__mio__inactive 0 | ||
| 5276 | #define R_VECT_READ__timer1__BITNR 3 | ||
| 5277 | #define R_VECT_READ__timer1__WIDTH 1 | ||
| 5278 | #define R_VECT_READ__timer1__active 1 | ||
| 5279 | #define R_VECT_READ__timer1__inactive 0 | ||
| 5280 | #define R_VECT_READ__timer0__BITNR 2 | ||
| 5281 | #define R_VECT_READ__timer0__WIDTH 1 | ||
| 5282 | #define R_VECT_READ__timer0__active 1 | ||
| 5283 | #define R_VECT_READ__timer0__inactive 0 | ||
| 5284 | #define R_VECT_READ__nmi__BITNR 1 | ||
| 5285 | #define R_VECT_READ__nmi__WIDTH 1 | ||
| 5286 | #define R_VECT_READ__nmi__active 1 | ||
| 5287 | #define R_VECT_READ__nmi__inactive 0 | ||
| 5288 | #define R_VECT_READ__some__BITNR 0 | ||
| 5289 | #define R_VECT_READ__some__WIDTH 1 | ||
| 5290 | #define R_VECT_READ__some__active 1 | ||
| 5291 | #define R_VECT_READ__some__inactive 0 | ||
| 5292 | |||
| 5293 | #define R_VECT_MASK_SET (IO_TYPECAST_UDWORD 0xb00000dc) | ||
| 5294 | #define R_VECT_MASK_SET__usb__BITNR 31 | ||
| 5295 | #define R_VECT_MASK_SET__usb__WIDTH 1 | ||
| 5296 | #define R_VECT_MASK_SET__usb__set 1 | ||
| 5297 | #define R_VECT_MASK_SET__usb__nop 0 | ||
| 5298 | #define R_VECT_MASK_SET__dma9__BITNR 25 | ||
| 5299 | #define R_VECT_MASK_SET__dma9__WIDTH 1 | ||
| 5300 | #define R_VECT_MASK_SET__dma9__set 1 | ||
| 5301 | #define R_VECT_MASK_SET__dma9__nop 0 | ||
| 5302 | #define R_VECT_MASK_SET__dma8__BITNR 24 | ||
| 5303 | #define R_VECT_MASK_SET__dma8__WIDTH 1 | ||
| 5304 | #define R_VECT_MASK_SET__dma8__set 1 | ||
| 5305 | #define R_VECT_MASK_SET__dma8__nop 0 | ||
| 5306 | #define R_VECT_MASK_SET__dma7__BITNR 23 | ||
| 5307 | #define R_VECT_MASK_SET__dma7__WIDTH 1 | ||
| 5308 | #define R_VECT_MASK_SET__dma7__set 1 | ||
| 5309 | #define R_VECT_MASK_SET__dma7__nop 0 | ||
| 5310 | #define R_VECT_MASK_SET__dma6__BITNR 22 | ||
| 5311 | #define R_VECT_MASK_SET__dma6__WIDTH 1 | ||
| 5312 | #define R_VECT_MASK_SET__dma6__set 1 | ||
| 5313 | #define R_VECT_MASK_SET__dma6__nop 0 | ||
| 5314 | #define R_VECT_MASK_SET__dma5__BITNR 21 | ||
| 5315 | #define R_VECT_MASK_SET__dma5__WIDTH 1 | ||
| 5316 | #define R_VECT_MASK_SET__dma5__set 1 | ||
| 5317 | #define R_VECT_MASK_SET__dma5__nop 0 | ||
| 5318 | #define R_VECT_MASK_SET__dma4__BITNR 20 | ||
| 5319 | #define R_VECT_MASK_SET__dma4__WIDTH 1 | ||
| 5320 | #define R_VECT_MASK_SET__dma4__set 1 | ||
| 5321 | #define R_VECT_MASK_SET__dma4__nop 0 | ||
| 5322 | #define R_VECT_MASK_SET__dma3__BITNR 19 | ||
| 5323 | #define R_VECT_MASK_SET__dma3__WIDTH 1 | ||
| 5324 | #define R_VECT_MASK_SET__dma3__set 1 | ||
| 5325 | #define R_VECT_MASK_SET__dma3__nop 0 | ||
| 5326 | #define R_VECT_MASK_SET__dma2__BITNR 18 | ||
| 5327 | #define R_VECT_MASK_SET__dma2__WIDTH 1 | ||
| 5328 | #define R_VECT_MASK_SET__dma2__set 1 | ||
| 5329 | #define R_VECT_MASK_SET__dma2__nop 0 | ||
| 5330 | #define R_VECT_MASK_SET__dma1__BITNR 17 | ||
| 5331 | #define R_VECT_MASK_SET__dma1__WIDTH 1 | ||
| 5332 | #define R_VECT_MASK_SET__dma1__set 1 | ||
| 5333 | #define R_VECT_MASK_SET__dma1__nop 0 | ||
| 5334 | #define R_VECT_MASK_SET__dma0__BITNR 16 | ||
| 5335 | #define R_VECT_MASK_SET__dma0__WIDTH 1 | ||
| 5336 | #define R_VECT_MASK_SET__dma0__set 1 | ||
| 5337 | #define R_VECT_MASK_SET__dma0__nop 0 | ||
| 5338 | #define R_VECT_MASK_SET__ext_dma1__BITNR 13 | ||
| 5339 | #define R_VECT_MASK_SET__ext_dma1__WIDTH 1 | ||
| 5340 | #define R_VECT_MASK_SET__ext_dma1__set 1 | ||
| 5341 | #define R_VECT_MASK_SET__ext_dma1__nop 0 | ||
| 5342 | #define R_VECT_MASK_SET__ext_dma0__BITNR 12 | ||
| 5343 | #define R_VECT_MASK_SET__ext_dma0__WIDTH 1 | ||
| 5344 | #define R_VECT_MASK_SET__ext_dma0__set 1 | ||
| 5345 | #define R_VECT_MASK_SET__ext_dma0__nop 0 | ||
| 5346 | #define R_VECT_MASK_SET__pa__BITNR 11 | ||
| 5347 | #define R_VECT_MASK_SET__pa__WIDTH 1 | ||
| 5348 | #define R_VECT_MASK_SET__pa__set 1 | ||
| 5349 | #define R_VECT_MASK_SET__pa__nop 0 | ||
| 5350 | #define R_VECT_MASK_SET__irq_intnr__BITNR 10 | ||
| 5351 | #define R_VECT_MASK_SET__irq_intnr__WIDTH 1 | ||
| 5352 | #define R_VECT_MASK_SET__irq_intnr__set 1 | ||
| 5353 | #define R_VECT_MASK_SET__irq_intnr__nop 0 | ||
| 5354 | #define R_VECT_MASK_SET__sw__BITNR 9 | ||
| 5355 | #define R_VECT_MASK_SET__sw__WIDTH 1 | ||
| 5356 | #define R_VECT_MASK_SET__sw__set 1 | ||
| 5357 | #define R_VECT_MASK_SET__sw__nop 0 | ||
| 5358 | #define R_VECT_MASK_SET__serial__BITNR 8 | ||
| 5359 | #define R_VECT_MASK_SET__serial__WIDTH 1 | ||
| 5360 | #define R_VECT_MASK_SET__serial__set 1 | ||
| 5361 | #define R_VECT_MASK_SET__serial__nop 0 | ||
| 5362 | #define R_VECT_MASK_SET__snmp__BITNR 7 | ||
| 5363 | #define R_VECT_MASK_SET__snmp__WIDTH 1 | ||
| 5364 | #define R_VECT_MASK_SET__snmp__set 1 | ||
| 5365 | #define R_VECT_MASK_SET__snmp__nop 0 | ||
| 5366 | #define R_VECT_MASK_SET__network__BITNR 6 | ||
| 5367 | #define R_VECT_MASK_SET__network__WIDTH 1 | ||
| 5368 | #define R_VECT_MASK_SET__network__set 1 | ||
| 5369 | #define R_VECT_MASK_SET__network__nop 0 | ||
| 5370 | #define R_VECT_MASK_SET__scsi1__BITNR 5 | ||
| 5371 | #define R_VECT_MASK_SET__scsi1__WIDTH 1 | ||
| 5372 | #define R_VECT_MASK_SET__scsi1__set 1 | ||
| 5373 | #define R_VECT_MASK_SET__scsi1__nop 0 | ||
| 5374 | #define R_VECT_MASK_SET__par1__BITNR 5 | ||
| 5375 | #define R_VECT_MASK_SET__par1__WIDTH 1 | ||
| 5376 | #define R_VECT_MASK_SET__par1__set 1 | ||
| 5377 | #define R_VECT_MASK_SET__par1__nop 0 | ||
| 5378 | #define R_VECT_MASK_SET__scsi0__BITNR 4 | ||
| 5379 | #define R_VECT_MASK_SET__scsi0__WIDTH 1 | ||
| 5380 | #define R_VECT_MASK_SET__scsi0__set 1 | ||
| 5381 | #define R_VECT_MASK_SET__scsi0__nop 0 | ||
| 5382 | #define R_VECT_MASK_SET__par0__BITNR 4 | ||
| 5383 | #define R_VECT_MASK_SET__par0__WIDTH 1 | ||
| 5384 | #define R_VECT_MASK_SET__par0__set 1 | ||
| 5385 | #define R_VECT_MASK_SET__par0__nop 0 | ||
| 5386 | #define R_VECT_MASK_SET__ata__BITNR 4 | ||
| 5387 | #define R_VECT_MASK_SET__ata__WIDTH 1 | ||
| 5388 | #define R_VECT_MASK_SET__ata__set 1 | ||
| 5389 | #define R_VECT_MASK_SET__ata__nop 0 | ||
| 5390 | #define R_VECT_MASK_SET__mio__BITNR 4 | ||
| 5391 | #define R_VECT_MASK_SET__mio__WIDTH 1 | ||
| 5392 | #define R_VECT_MASK_SET__mio__set 1 | ||
| 5393 | #define R_VECT_MASK_SET__mio__nop 0 | ||
| 5394 | #define R_VECT_MASK_SET__timer1__BITNR 3 | ||
| 5395 | #define R_VECT_MASK_SET__timer1__WIDTH 1 | ||
| 5396 | #define R_VECT_MASK_SET__timer1__set 1 | ||
| 5397 | #define R_VECT_MASK_SET__timer1__nop 0 | ||
| 5398 | #define R_VECT_MASK_SET__timer0__BITNR 2 | ||
| 5399 | #define R_VECT_MASK_SET__timer0__WIDTH 1 | ||
| 5400 | #define R_VECT_MASK_SET__timer0__set 1 | ||
| 5401 | #define R_VECT_MASK_SET__timer0__nop 0 | ||
| 5402 | #define R_VECT_MASK_SET__nmi__BITNR 1 | ||
| 5403 | #define R_VECT_MASK_SET__nmi__WIDTH 1 | ||
| 5404 | #define R_VECT_MASK_SET__nmi__set 1 | ||
| 5405 | #define R_VECT_MASK_SET__nmi__nop 0 | ||
| 5406 | #define R_VECT_MASK_SET__some__BITNR 0 | ||
| 5407 | #define R_VECT_MASK_SET__some__WIDTH 1 | ||
| 5408 | #define R_VECT_MASK_SET__some__set 1 | ||
| 5409 | #define R_VECT_MASK_SET__some__nop 0 | ||
| 5410 | |||
| 5411 | /* | ||
| 5412 | !* DMA registers | ||
| 5413 | !*/ | ||
| 5414 | |||
| 5415 | #define R_SET_EOP (IO_TYPECAST_UDWORD 0xb000003c) | ||
| 5416 | #define R_SET_EOP__ch9_eop__BITNR 3 | ||
| 5417 | #define R_SET_EOP__ch9_eop__WIDTH 1 | ||
| 5418 | #define R_SET_EOP__ch9_eop__set 1 | ||
| 5419 | #define R_SET_EOP__ch9_eop__nop 0 | ||
| 5420 | #define R_SET_EOP__ch7_eop__BITNR 2 | ||
| 5421 | #define R_SET_EOP__ch7_eop__WIDTH 1 | ||
| 5422 | #define R_SET_EOP__ch7_eop__set 1 | ||
| 5423 | #define R_SET_EOP__ch7_eop__nop 0 | ||
| 5424 | #define R_SET_EOP__ch5_eop__BITNR 1 | ||
| 5425 | #define R_SET_EOP__ch5_eop__WIDTH 1 | ||
| 5426 | #define R_SET_EOP__ch5_eop__set 1 | ||
| 5427 | #define R_SET_EOP__ch5_eop__nop 0 | ||
| 5428 | #define R_SET_EOP__ch3_eop__BITNR 0 | ||
| 5429 | #define R_SET_EOP__ch3_eop__WIDTH 1 | ||
| 5430 | #define R_SET_EOP__ch3_eop__set 1 | ||
| 5431 | #define R_SET_EOP__ch3_eop__nop 0 | ||
| 5432 | |||
| 5433 | #define R_DMA_CH0_HWSW (IO_TYPECAST_UDWORD 0xb0000100) | ||
| 5434 | #define R_DMA_CH0_HWSW__hw__BITNR 16 | ||
| 5435 | #define R_DMA_CH0_HWSW__hw__WIDTH 16 | ||
| 5436 | #define R_DMA_CH0_HWSW__sw__BITNR 0 | ||
| 5437 | #define R_DMA_CH0_HWSW__sw__WIDTH 16 | ||
| 5438 | |||
| 5439 | #define R_DMA_CH0_DESCR (IO_TYPECAST_UDWORD 0xb000010c) | ||
| 5440 | #define R_DMA_CH0_DESCR__descr__BITNR 0 | ||
| 5441 | #define R_DMA_CH0_DESCR__descr__WIDTH 32 | ||
| 5442 | |||
| 5443 | #define R_DMA_CH0_NEXT (IO_TYPECAST_UDWORD 0xb0000104) | ||
| 5444 | #define R_DMA_CH0_NEXT__next__BITNR 0 | ||
| 5445 | #define R_DMA_CH0_NEXT__next__WIDTH 32 | ||
| 5446 | |||
| 5447 | #define R_DMA_CH0_BUF (IO_TYPECAST_UDWORD 0xb0000108) | ||
| 5448 | #define R_DMA_CH0_BUF__buf__BITNR 0 | ||
| 5449 | #define R_DMA_CH0_BUF__buf__WIDTH 32 | ||
| 5450 | |||
| 5451 | #define R_DMA_CH0_FIRST (IO_TYPECAST_UDWORD 0xb00001a0) | ||
| 5452 | #define R_DMA_CH0_FIRST__first__BITNR 0 | ||
| 5453 | #define R_DMA_CH0_FIRST__first__WIDTH 32 | ||
| 5454 | |||
| 5455 | #define R_DMA_CH0_CMD (IO_TYPECAST_BYTE 0xb00001d0) | ||
| 5456 | #define R_DMA_CH0_CMD__cmd__BITNR 0 | ||
| 5457 | #define R_DMA_CH0_CMD__cmd__WIDTH 3 | ||
| 5458 | #define R_DMA_CH0_CMD__cmd__hold 0 | ||
| 5459 | #define R_DMA_CH0_CMD__cmd__start 1 | ||
| 5460 | #define R_DMA_CH0_CMD__cmd__restart 3 | ||
| 5461 | #define R_DMA_CH0_CMD__cmd__continue 3 | ||
| 5462 | #define R_DMA_CH0_CMD__cmd__reset 4 | ||
| 5463 | |||
| 5464 | #define R_DMA_CH0_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d1) | ||
| 5465 | #define R_DMA_CH0_CLR_INTR__clr_eop__BITNR 1 | ||
| 5466 | #define R_DMA_CH0_CLR_INTR__clr_eop__WIDTH 1 | ||
| 5467 | #define R_DMA_CH0_CLR_INTR__clr_eop__do 1 | ||
| 5468 | #define R_DMA_CH0_CLR_INTR__clr_eop__dont 0 | ||
| 5469 | #define R_DMA_CH0_CLR_INTR__clr_descr__BITNR 0 | ||
| 5470 | #define R_DMA_CH0_CLR_INTR__clr_descr__WIDTH 1 | ||
| 5471 | #define R_DMA_CH0_CLR_INTR__clr_descr__do 1 | ||
| 5472 | #define R_DMA_CH0_CLR_INTR__clr_descr__dont 0 | ||
| 5473 | |||
| 5474 | #define R_DMA_CH0_STATUS (IO_TYPECAST_RO_BYTE 0xb00001d2) | ||
| 5475 | #define R_DMA_CH0_STATUS__avail__BITNR 0 | ||
| 5476 | #define R_DMA_CH0_STATUS__avail__WIDTH 7 | ||
| 5477 | |||
| 5478 | #define R_DMA_CH1_HWSW (IO_TYPECAST_UDWORD 0xb0000110) | ||
| 5479 | #define R_DMA_CH1_HWSW__hw__BITNR 16 | ||
| 5480 | #define R_DMA_CH1_HWSW__hw__WIDTH 16 | ||
| 5481 | #define R_DMA_CH1_HWSW__sw__BITNR 0 | ||
| 5482 | #define R_DMA_CH1_HWSW__sw__WIDTH 16 | ||
| 5483 | |||
| 5484 | #define R_DMA_CH1_DESCR (IO_TYPECAST_UDWORD 0xb000011c) | ||
| 5485 | #define R_DMA_CH1_DESCR__descr__BITNR 0 | ||
| 5486 | #define R_DMA_CH1_DESCR__descr__WIDTH 32 | ||
| 5487 | |||
| 5488 | #define R_DMA_CH1_NEXT (IO_TYPECAST_UDWORD 0xb0000114) | ||
| 5489 | #define R_DMA_CH1_NEXT__next__BITNR 0 | ||
| 5490 | #define R_DMA_CH1_NEXT__next__WIDTH 32 | ||
| 5491 | |||
| 5492 | #define R_DMA_CH1_BUF (IO_TYPECAST_UDWORD 0xb0000118) | ||
| 5493 | #define R_DMA_CH1_BUF__buf__BITNR 0 | ||
| 5494 | #define R_DMA_CH1_BUF__buf__WIDTH 32 | ||
| 5495 | |||
| 5496 | #define R_DMA_CH1_FIRST (IO_TYPECAST_UDWORD 0xb00001a4) | ||
| 5497 | #define R_DMA_CH1_FIRST__first__BITNR 0 | ||
| 5498 | #define R_DMA_CH1_FIRST__first__WIDTH 32 | ||
| 5499 | |||
| 5500 | #define R_DMA_CH1_CMD (IO_TYPECAST_BYTE 0xb00001d4) | ||
| 5501 | #define R_DMA_CH1_CMD__cmd__BITNR 0 | ||
| 5502 | #define R_DMA_CH1_CMD__cmd__WIDTH 3 | ||
| 5503 | #define R_DMA_CH1_CMD__cmd__hold 0 | ||
| 5504 | #define R_DMA_CH1_CMD__cmd__start 1 | ||
| 5505 | #define R_DMA_CH1_CMD__cmd__restart 3 | ||
| 5506 | #define R_DMA_CH1_CMD__cmd__continue 3 | ||
| 5507 | #define R_DMA_CH1_CMD__cmd__reset 4 | ||
| 5508 | |||
| 5509 | #define R_DMA_CH1_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d5) | ||
| 5510 | #define R_DMA_CH1_CLR_INTR__clr_eop__BITNR 1 | ||
| 5511 | #define R_DMA_CH1_CLR_INTR__clr_eop__WIDTH 1 | ||
| 5512 | #define R_DMA_CH1_CLR_INTR__clr_eop__do 1 | ||
| 5513 | #define R_DMA_CH1_CLR_INTR__clr_eop__dont 0 | ||
| 5514 | #define R_DMA_CH1_CLR_INTR__clr_descr__BITNR 0 | ||
| 5515 | #define R_DMA_CH1_CLR_INTR__clr_descr__WIDTH 1 | ||
| 5516 | #define R_DMA_CH1_CLR_INTR__clr_descr__do 1 | ||
| 5517 | #define R_DMA_CH1_CLR_INTR__clr_descr__dont 0 | ||
| 5518 | |||
| 5519 | #define R_DMA_CH1_STATUS (IO_TYPECAST_RO_BYTE 0xb00001d6) | ||
| 5520 | #define R_DMA_CH1_STATUS__avail__BITNR 0 | ||
| 5521 | #define R_DMA_CH1_STATUS__avail__WIDTH 7 | ||
| 5522 | |||
| 5523 | #define R_DMA_CH2_HWSW (IO_TYPECAST_UDWORD 0xb0000120) | ||
| 5524 | #define R_DMA_CH2_HWSW__hw__BITNR 16 | ||
| 5525 | #define R_DMA_CH2_HWSW__hw__WIDTH 16 | ||
| 5526 | #define R_DMA_CH2_HWSW__sw__BITNR 0 | ||
| 5527 | #define R_DMA_CH2_HWSW__sw__WIDTH 16 | ||
| 5528 | |||
| 5529 | #define R_DMA_CH2_DESCR (IO_TYPECAST_UDWORD 0xb000012c) | ||
| 5530 | #define R_DMA_CH2_DESCR__descr__BITNR 0 | ||
| 5531 | #define R_DMA_CH2_DESCR__descr__WIDTH 32 | ||
| 5532 | |||
| 5533 | #define R_DMA_CH2_NEXT (IO_TYPECAST_UDWORD 0xb0000124) | ||
| 5534 | #define R_DMA_CH2_NEXT__next__BITNR 0 | ||
| 5535 | #define R_DMA_CH2_NEXT__next__WIDTH 32 | ||
| 5536 | |||
| 5537 | #define R_DMA_CH2_BUF (IO_TYPECAST_UDWORD 0xb0000128) | ||
| 5538 | #define R_DMA_CH2_BUF__buf__BITNR 0 | ||
| 5539 | #define R_DMA_CH2_BUF__buf__WIDTH 32 | ||
| 5540 | |||
| 5541 | #define R_DMA_CH2_FIRST (IO_TYPECAST_UDWORD 0xb00001a8) | ||
| 5542 | #define R_DMA_CH2_FIRST__first__BITNR 0 | ||
| 5543 | #define R_DMA_CH2_FIRST__first__WIDTH 32 | ||
| 5544 | |||
| 5545 | #define R_DMA_CH2_CMD (IO_TYPECAST_BYTE 0xb00001d8) | ||
| 5546 | #define R_DMA_CH2_CMD__cmd__BITNR 0 | ||
| 5547 | #define R_DMA_CH2_CMD__cmd__WIDTH 3 | ||
| 5548 | #define R_DMA_CH2_CMD__cmd__hold 0 | ||
| 5549 | #define R_DMA_CH2_CMD__cmd__start 1 | ||
| 5550 | #define R_DMA_CH2_CMD__cmd__restart 3 | ||
| 5551 | #define R_DMA_CH2_CMD__cmd__continue 3 | ||
| 5552 | #define R_DMA_CH2_CMD__cmd__reset 4 | ||
| 5553 | |||
| 5554 | #define R_DMA_CH2_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d9) | ||
| 5555 | #define R_DMA_CH2_CLR_INTR__clr_eop__BITNR 1 | ||
| 5556 | #define R_DMA_CH2_CLR_INTR__clr_eop__WIDTH 1 | ||
| 5557 | #define R_DMA_CH2_CLR_INTR__clr_eop__do 1 | ||
| 5558 | #define R_DMA_CH2_CLR_INTR__clr_eop__dont 0 | ||
| 5559 | #define R_DMA_CH2_CLR_INTR__clr_descr__BITNR 0 | ||
| 5560 | #define R_DMA_CH2_CLR_INTR__clr_descr__WIDTH 1 | ||
| 5561 | #define R_DMA_CH2_CLR_INTR__clr_descr__do 1 | ||
| 5562 | #define R_DMA_CH2_CLR_INTR__clr_descr__dont 0 | ||
| 5563 | |||
| 5564 | #define R_DMA_CH2_STATUS (IO_TYPECAST_RO_BYTE 0xb00001da) | ||
| 5565 | #define R_DMA_CH2_STATUS__avail__BITNR 0 | ||
| 5566 | #define R_DMA_CH2_STATUS__avail__WIDTH 7 | ||
| 5567 | |||
| 5568 | #define R_DMA_CH3_HWSW (IO_TYPECAST_UDWORD 0xb0000130) | ||
| 5569 | #define R_DMA_CH3_HWSW__hw__BITNR 16 | ||
| 5570 | #define R_DMA_CH3_HWSW__hw__WIDTH 16 | ||
| 5571 | #define R_DMA_CH3_HWSW__sw__BITNR 0 | ||
| 5572 | #define R_DMA_CH3_HWSW__sw__WIDTH 16 | ||
| 5573 | |||
| 5574 | #define R_DMA_CH3_DESCR (IO_TYPECAST_UDWORD 0xb000013c) | ||
| 5575 | #define R_DMA_CH3_DESCR__descr__BITNR 0 | ||
| 5576 | #define R_DMA_CH3_DESCR__descr__WIDTH 32 | ||
| 5577 | |||
| 5578 | #define R_DMA_CH3_NEXT (IO_TYPECAST_UDWORD 0xb0000134) | ||
| 5579 | #define R_DMA_CH3_NEXT__next__BITNR 0 | ||
| 5580 | #define R_DMA_CH3_NEXT__next__WIDTH 32 | ||
| 5581 | |||
| 5582 | #define R_DMA_CH3_BUF (IO_TYPECAST_UDWORD 0xb0000138) | ||
| 5583 | #define R_DMA_CH3_BUF__buf__BITNR 0 | ||
| 5584 | #define R_DMA_CH3_BUF__buf__WIDTH 32 | ||
| 5585 | |||
| 5586 | #define R_DMA_CH3_FIRST (IO_TYPECAST_UDWORD 0xb00001ac) | ||
| 5587 | #define R_DMA_CH3_FIRST__first__BITNR 0 | ||
| 5588 | #define R_DMA_CH3_FIRST__first__WIDTH 32 | ||
| 5589 | |||
| 5590 | #define R_DMA_CH3_CMD (IO_TYPECAST_BYTE 0xb00001dc) | ||
| 5591 | #define R_DMA_CH3_CMD__cmd__BITNR 0 | ||
| 5592 | #define R_DMA_CH3_CMD__cmd__WIDTH 3 | ||
| 5593 | #define R_DMA_CH3_CMD__cmd__hold 0 | ||
| 5594 | #define R_DMA_CH3_CMD__cmd__start 1 | ||
| 5595 | #define R_DMA_CH3_CMD__cmd__restart 3 | ||
| 5596 | #define R_DMA_CH3_CMD__cmd__continue 3 | ||
| 5597 | #define R_DMA_CH3_CMD__cmd__reset 4 | ||
| 5598 | |||
| 5599 | #define R_DMA_CH3_CLR_INTR (IO_TYPECAST_BYTE 0xb00001dd) | ||
| 5600 | #define R_DMA_CH3_CLR_INTR__clr_eop__BITNR 1 | ||
| 5601 | #define R_DMA_CH3_CLR_INTR__clr_eop__WIDTH 1 | ||
| 5602 | #define R_DMA_CH3_CLR_INTR__clr_eop__do 1 | ||
| 5603 | #define R_DMA_CH3_CLR_INTR__clr_eop__dont 0 | ||
| 5604 | #define R_DMA_CH3_CLR_INTR__clr_descr__BITNR 0 | ||
| 5605 | #define R_DMA_CH3_CLR_INTR__clr_descr__WIDTH 1 | ||
| 5606 | #define R_DMA_CH3_CLR_INTR__clr_descr__do 1 | ||
| 5607 | #define R_DMA_CH3_CLR_INTR__clr_descr__dont 0 | ||
| 5608 | |||
| 5609 | #define R_DMA_CH3_STATUS (IO_TYPECAST_RO_BYTE 0xb00001de) | ||
| 5610 | #define R_DMA_CH3_STATUS__avail__BITNR 0 | ||
| 5611 | #define R_DMA_CH3_STATUS__avail__WIDTH 7 | ||
| 5612 | |||
| 5613 | #define R_DMA_CH4_HWSW (IO_TYPECAST_UDWORD 0xb0000140) | ||
| 5614 | #define R_DMA_CH4_HWSW__hw__BITNR 16 | ||
| 5615 | #define R_DMA_CH4_HWSW__hw__WIDTH 16 | ||
| 5616 | #define R_DMA_CH4_HWSW__sw__BITNR 0 | ||
| 5617 | #define R_DMA_CH4_HWSW__sw__WIDTH 16 | ||
| 5618 | |||
| 5619 | #define R_DMA_CH4_DESCR (IO_TYPECAST_UDWORD 0xb000014c) | ||
| 5620 | #define R_DMA_CH4_DESCR__descr__BITNR 0 | ||
| 5621 | #define R_DMA_CH4_DESCR__descr__WIDTH 32 | ||
| 5622 | |||
| 5623 | #define R_DMA_CH4_NEXT (IO_TYPECAST_UDWORD 0xb0000144) | ||
| 5624 | #define R_DMA_CH4_NEXT__next__BITNR 0 | ||
| 5625 | #define R_DMA_CH4_NEXT__next__WIDTH 32 | ||
| 5626 | |||
| 5627 | #define R_DMA_CH4_BUF (IO_TYPECAST_UDWORD 0xb0000148) | ||
| 5628 | #define R_DMA_CH4_BUF__buf__BITNR 0 | ||
| 5629 | #define R_DMA_CH4_BUF__buf__WIDTH 32 | ||
| 5630 | |||
| 5631 | #define R_DMA_CH4_FIRST (IO_TYPECAST_UDWORD 0xb00001b0) | ||
| 5632 | #define R_DMA_CH4_FIRST__first__BITNR 0 | ||
| 5633 | #define R_DMA_CH4_FIRST__first__WIDTH 32 | ||
| 5634 | |||
| 5635 | #define R_DMA_CH4_CMD (IO_TYPECAST_BYTE 0xb00001e0) | ||
| 5636 | #define R_DMA_CH4_CMD__cmd__BITNR 0 | ||
| 5637 | #define R_DMA_CH4_CMD__cmd__WIDTH 3 | ||
| 5638 | #define R_DMA_CH4_CMD__cmd__hold 0 | ||
| 5639 | #define R_DMA_CH4_CMD__cmd__start 1 | ||
| 5640 | #define R_DMA_CH4_CMD__cmd__restart 3 | ||
| 5641 | #define R_DMA_CH4_CMD__cmd__continue 3 | ||
| 5642 | #define R_DMA_CH4_CMD__cmd__reset 4 | ||
| 5643 | |||
| 5644 | #define R_DMA_CH4_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e1) | ||
| 5645 | #define R_DMA_CH4_CLR_INTR__clr_eop__BITNR 1 | ||
| 5646 | #define R_DMA_CH4_CLR_INTR__clr_eop__WIDTH 1 | ||
| 5647 | #define R_DMA_CH4_CLR_INTR__clr_eop__do 1 | ||
| 5648 | #define R_DMA_CH4_CLR_INTR__clr_eop__dont 0 | ||
| 5649 | #define R_DMA_CH4_CLR_INTR__clr_descr__BITNR 0 | ||
| 5650 | #define R_DMA_CH4_CLR_INTR__clr_descr__WIDTH 1 | ||
| 5651 | #define R_DMA_CH4_CLR_INTR__clr_descr__do 1 | ||
| 5652 | #define R_DMA_CH4_CLR_INTR__clr_descr__dont 0 | ||
| 5653 | |||
| 5654 | #define R_DMA_CH4_STATUS (IO_TYPECAST_RO_BYTE 0xb00001e2) | ||
| 5655 | #define R_DMA_CH4_STATUS__avail__BITNR 0 | ||
| 5656 | #define R_DMA_CH4_STATUS__avail__WIDTH 7 | ||
| 5657 | |||
| 5658 | #define R_DMA_CH5_HWSW (IO_TYPECAST_UDWORD 0xb0000150) | ||
| 5659 | #define R_DMA_CH5_HWSW__hw__BITNR 16 | ||
| 5660 | #define R_DMA_CH5_HWSW__hw__WIDTH 16 | ||
| 5661 | #define R_DMA_CH5_HWSW__sw__BITNR 0 | ||
| 5662 | #define R_DMA_CH5_HWSW__sw__WIDTH 16 | ||
| 5663 | |||
| 5664 | #define R_DMA_CH5_DESCR (IO_TYPECAST_UDWORD 0xb000015c) | ||
| 5665 | #define R_DMA_CH5_DESCR__descr__BITNR 0 | ||
| 5666 | #define R_DMA_CH5_DESCR__descr__WIDTH 32 | ||
| 5667 | |||
| 5668 | #define R_DMA_CH5_NEXT (IO_TYPECAST_UDWORD 0xb0000154) | ||
| 5669 | #define R_DMA_CH5_NEXT__next__BITNR 0 | ||
| 5670 | #define R_DMA_CH5_NEXT__next__WIDTH 32 | ||
| 5671 | |||
| 5672 | #define R_DMA_CH5_BUF (IO_TYPECAST_UDWORD 0xb0000158) | ||
| 5673 | #define R_DMA_CH5_BUF__buf__BITNR 0 | ||
| 5674 | #define R_DMA_CH5_BUF__buf__WIDTH 32 | ||
| 5675 | |||
| 5676 | #define R_DMA_CH5_FIRST (IO_TYPECAST_UDWORD 0xb00001b4) | ||
| 5677 | #define R_DMA_CH5_FIRST__first__BITNR 0 | ||
| 5678 | #define R_DMA_CH5_FIRST__first__WIDTH 32 | ||
| 5679 | |||
| 5680 | #define R_DMA_CH5_CMD (IO_TYPECAST_BYTE 0xb00001e4) | ||
| 5681 | #define R_DMA_CH5_CMD__cmd__BITNR 0 | ||
| 5682 | #define R_DMA_CH5_CMD__cmd__WIDTH 3 | ||
| 5683 | #define R_DMA_CH5_CMD__cmd__hold 0 | ||
| 5684 | #define R_DMA_CH5_CMD__cmd__start 1 | ||
| 5685 | #define R_DMA_CH5_CMD__cmd__restart 3 | ||
| 5686 | #define R_DMA_CH5_CMD__cmd__continue 3 | ||
| 5687 | #define R_DMA_CH5_CMD__cmd__reset 4 | ||
| 5688 | |||
| 5689 | #define R_DMA_CH5_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e5) | ||
| 5690 | #define R_DMA_CH5_CLR_INTR__clr_eop__BITNR 1 | ||
| 5691 | #define R_DMA_CH5_CLR_INTR__clr_eop__WIDTH 1 | ||
| 5692 | #define R_DMA_CH5_CLR_INTR__clr_eop__do 1 | ||
| 5693 | #define R_DMA_CH5_CLR_INTR__clr_eop__dont 0 | ||
| 5694 | #define R_DMA_CH5_CLR_INTR__clr_descr__BITNR 0 | ||
| 5695 | #define R_DMA_CH5_CLR_INTR__clr_descr__WIDTH 1 | ||
| 5696 | #define R_DMA_CH5_CLR_INTR__clr_descr__do 1 | ||
| 5697 | #define R_DMA_CH5_CLR_INTR__clr_descr__dont 0 | ||
| 5698 | |||
| 5699 | #define R_DMA_CH5_STATUS (IO_TYPECAST_RO_BYTE 0xb00001e6) | ||
| 5700 | #define R_DMA_CH5_STATUS__avail__BITNR 0 | ||
| 5701 | #define R_DMA_CH5_STATUS__avail__WIDTH 7 | ||
| 5702 | |||
| 5703 | #define R_DMA_CH6_HWSW (IO_TYPECAST_UDWORD 0xb0000160) | ||
| 5704 | #define R_DMA_CH6_HWSW__hw__BITNR 16 | ||
| 5705 | #define R_DMA_CH6_HWSW__hw__WIDTH 16 | ||
| 5706 | #define R_DMA_CH6_HWSW__sw__BITNR 0 | ||
| 5707 | #define R_DMA_CH6_HWSW__sw__WIDTH 16 | ||
| 5708 | |||
| 5709 | #define R_DMA_CH6_DESCR (IO_TYPECAST_UDWORD 0xb000016c) | ||
| 5710 | #define R_DMA_CH6_DESCR__descr__BITNR 0 | ||
| 5711 | #define R_DMA_CH6_DESCR__descr__WIDTH 32 | ||
| 5712 | |||
| 5713 | #define R_DMA_CH6_NEXT (IO_TYPECAST_UDWORD 0xb0000164) | ||
| 5714 | #define R_DMA_CH6_NEXT__next__BITNR 0 | ||
| 5715 | #define R_DMA_CH6_NEXT__next__WIDTH 32 | ||
| 5716 | |||
| 5717 | #define R_DMA_CH6_BUF (IO_TYPECAST_UDWORD 0xb0000168) | ||
| 5718 | #define R_DMA_CH6_BUF__buf__BITNR 0 | ||
| 5719 | #define R_DMA_CH6_BUF__buf__WIDTH 32 | ||
| 5720 | |||
| 5721 | #define R_DMA_CH6_FIRST (IO_TYPECAST_UDWORD 0xb00001b8) | ||
| 5722 | #define R_DMA_CH6_FIRST__first__BITNR 0 | ||
| 5723 | #define R_DMA_CH6_FIRST__first__WIDTH 32 | ||
| 5724 | |||
| 5725 | #define R_DMA_CH6_CMD (IO_TYPECAST_BYTE 0xb00001e8) | ||
| 5726 | #define R_DMA_CH6_CMD__cmd__BITNR 0 | ||
| 5727 | #define R_DMA_CH6_CMD__cmd__WIDTH 3 | ||
| 5728 | #define R_DMA_CH6_CMD__cmd__hold 0 | ||
| 5729 | #define R_DMA_CH6_CMD__cmd__start 1 | ||
| 5730 | #define R_DMA_CH6_CMD__cmd__restart 3 | ||
| 5731 | #define R_DMA_CH6_CMD__cmd__continue 3 | ||
| 5732 | #define R_DMA_CH6_CMD__cmd__reset 4 | ||
| 5733 | |||
| 5734 | #define R_DMA_CH6_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e9) | ||
| 5735 | #define R_DMA_CH6_CLR_INTR__clr_eop__BITNR 1 | ||
| 5736 | #define R_DMA_CH6_CLR_INTR__clr_eop__WIDTH 1 | ||
| 5737 | #define R_DMA_CH6_CLR_INTR__clr_eop__do 1 | ||
| 5738 | #define R_DMA_CH6_CLR_INTR__clr_eop__dont 0 | ||
| 5739 | #define R_DMA_CH6_CLR_INTR__clr_descr__BITNR 0 | ||
| 5740 | #define R_DMA_CH6_CLR_INTR__clr_descr__WIDTH 1 | ||
| 5741 | #define R_DMA_CH6_CLR_INTR__clr_descr__do 1 | ||
| 5742 | #define R_DMA_CH6_CLR_INTR__clr_descr__dont 0 | ||
| 5743 | |||
| 5744 | #define R_DMA_CH6_STATUS (IO_TYPECAST_RO_BYTE 0xb00001ea) | ||
| 5745 | #define R_DMA_CH6_STATUS__avail__BITNR 0 | ||
| 5746 | #define R_DMA_CH6_STATUS__avail__WIDTH 7 | ||
| 5747 | |||
| 5748 | #define R_DMA_CH7_HWSW (IO_TYPECAST_UDWORD 0xb0000170) | ||
| 5749 | #define R_DMA_CH7_HWSW__hw__BITNR 16 | ||
| 5750 | #define R_DMA_CH7_HWSW__hw__WIDTH 16 | ||
| 5751 | #define R_DMA_CH7_HWSW__sw__BITNR 0 | ||
| 5752 | #define R_DMA_CH7_HWSW__sw__WIDTH 16 | ||
| 5753 | |||
| 5754 | #define R_DMA_CH7_DESCR (IO_TYPECAST_UDWORD 0xb000017c) | ||
| 5755 | #define R_DMA_CH7_DESCR__descr__BITNR 0 | ||
| 5756 | #define R_DMA_CH7_DESCR__descr__WIDTH 32 | ||
| 5757 | |||
| 5758 | #define R_DMA_CH7_NEXT (IO_TYPECAST_UDWORD 0xb0000174) | ||
| 5759 | #define R_DMA_CH7_NEXT__next__BITNR 0 | ||
| 5760 | #define R_DMA_CH7_NEXT__next__WIDTH 32 | ||
| 5761 | |||
| 5762 | #define R_DMA_CH7_BUF (IO_TYPECAST_UDWORD 0xb0000178) | ||
| 5763 | #define R_DMA_CH7_BUF__buf__BITNR 0 | ||
| 5764 | #define R_DMA_CH7_BUF__buf__WIDTH 32 | ||
| 5765 | |||
| 5766 | #define R_DMA_CH7_FIRST (IO_TYPECAST_UDWORD 0xb00001bc) | ||
| 5767 | #define R_DMA_CH7_FIRST__first__BITNR 0 | ||
| 5768 | #define R_DMA_CH7_FIRST__first__WIDTH 32 | ||
| 5769 | |||
| 5770 | #define R_DMA_CH7_CMD (IO_TYPECAST_BYTE 0xb00001ec) | ||
| 5771 | #define R_DMA_CH7_CMD__cmd__BITNR 0 | ||
| 5772 | #define R_DMA_CH7_CMD__cmd__WIDTH 3 | ||
| 5773 | #define R_DMA_CH7_CMD__cmd__hold 0 | ||
| 5774 | #define R_DMA_CH7_CMD__cmd__start 1 | ||
| 5775 | #define R_DMA_CH7_CMD__cmd__restart 3 | ||
| 5776 | #define R_DMA_CH7_CMD__cmd__continue 3 | ||
| 5777 | #define R_DMA_CH7_CMD__cmd__reset 4 | ||
| 5778 | |||
| 5779 | #define R_DMA_CH7_CLR_INTR (IO_TYPECAST_BYTE 0xb00001ed) | ||
| 5780 | #define R_DMA_CH7_CLR_INTR__clr_eop__BITNR 1 | ||
| 5781 | #define R_DMA_CH7_CLR_INTR__clr_eop__WIDTH 1 | ||
| 5782 | #define R_DMA_CH7_CLR_INTR__clr_eop__do 1 | ||
| 5783 | #define R_DMA_CH7_CLR_INTR__clr_eop__dont 0 | ||
| 5784 | #define R_DMA_CH7_CLR_INTR__clr_descr__BITNR 0 | ||
| 5785 | #define R_DMA_CH7_CLR_INTR__clr_descr__WIDTH 1 | ||
| 5786 | #define R_DMA_CH7_CLR_INTR__clr_descr__do 1 | ||
| 5787 | #define R_DMA_CH7_CLR_INTR__clr_descr__dont 0 | ||
| 5788 | |||
| 5789 | #define R_DMA_CH7_STATUS (IO_TYPECAST_RO_BYTE 0xb00001ee) | ||
| 5790 | #define R_DMA_CH7_STATUS__avail__BITNR 0 | ||
| 5791 | #define R_DMA_CH7_STATUS__avail__WIDTH 7 | ||
| 5792 | |||
| 5793 | #define R_DMA_CH8_HWSW (IO_TYPECAST_UDWORD 0xb0000180) | ||
| 5794 | #define R_DMA_CH8_HWSW__hw__BITNR 16 | ||
| 5795 | #define R_DMA_CH8_HWSW__hw__WIDTH 16 | ||
| 5796 | #define R_DMA_CH8_HWSW__sw__BITNR 0 | ||
| 5797 | #define R_DMA_CH8_HWSW__sw__WIDTH 16 | ||
| 5798 | |||
| 5799 | #define R_DMA_CH8_DESCR (IO_TYPECAST_UDWORD 0xb000018c) | ||
| 5800 | #define R_DMA_CH8_DESCR__descr__BITNR 0 | ||
| 5801 | #define R_DMA_CH8_DESCR__descr__WIDTH 32 | ||
| 5802 | |||
| 5803 | #define R_DMA_CH8_NEXT (IO_TYPECAST_UDWORD 0xb0000184) | ||
| 5804 | #define R_DMA_CH8_NEXT__next__BITNR 0 | ||
| 5805 | #define R_DMA_CH8_NEXT__next__WIDTH 32 | ||
| 5806 | |||
| 5807 | #define R_DMA_CH8_BUF (IO_TYPECAST_UDWORD 0xb0000188) | ||
| 5808 | #define R_DMA_CH8_BUF__buf__BITNR 0 | ||
| 5809 | #define R_DMA_CH8_BUF__buf__WIDTH 32 | ||
| 5810 | |||
| 5811 | #define R_DMA_CH8_FIRST (IO_TYPECAST_UDWORD 0xb00001c0) | ||
| 5812 | #define R_DMA_CH8_FIRST__first__BITNR 0 | ||
| 5813 | #define R_DMA_CH8_FIRST__first__WIDTH 32 | ||
| 5814 | |||
| 5815 | #define R_DMA_CH8_CMD (IO_TYPECAST_BYTE 0xb00001f0) | ||
| 5816 | #define R_DMA_CH8_CMD__cmd__BITNR 0 | ||
| 5817 | #define R_DMA_CH8_CMD__cmd__WIDTH 3 | ||
| 5818 | #define R_DMA_CH8_CMD__cmd__hold 0 | ||
| 5819 | #define R_DMA_CH8_CMD__cmd__start 1 | ||
| 5820 | #define R_DMA_CH8_CMD__cmd__restart 3 | ||
| 5821 | #define R_DMA_CH8_CMD__cmd__continue 3 | ||
| 5822 | #define R_DMA_CH8_CMD__cmd__reset 4 | ||
| 5823 | |||
| 5824 | #define R_DMA_CH8_CLR_INTR (IO_TYPECAST_BYTE 0xb00001f1) | ||
| 5825 | #define R_DMA_CH8_CLR_INTR__clr_eop__BITNR 1 | ||
| 5826 | #define R_DMA_CH8_CLR_INTR__clr_eop__WIDTH 1 | ||
| 5827 | #define R_DMA_CH8_CLR_INTR__clr_eop__do 1 | ||
| 5828 | #define R_DMA_CH8_CLR_INTR__clr_eop__dont 0 | ||
| 5829 | #define R_DMA_CH8_CLR_INTR__clr_descr__BITNR 0 | ||
| 5830 | #define R_DMA_CH8_CLR_INTR__clr_descr__WIDTH 1 | ||
| 5831 | #define R_DMA_CH8_CLR_INTR__clr_descr__do 1 | ||
| 5832 | #define R_DMA_CH8_CLR_INTR__clr_descr__dont 0 | ||
| 5833 | |||
| 5834 | #define R_DMA_CH8_STATUS (IO_TYPECAST_RO_BYTE 0xb00001f2) | ||
| 5835 | #define R_DMA_CH8_STATUS__avail__BITNR 0 | ||
| 5836 | #define R_DMA_CH8_STATUS__avail__WIDTH 7 | ||
| 5837 | |||
| 5838 | #define R_DMA_CH8_SUB (IO_TYPECAST_UDWORD 0xb000018c) | ||
| 5839 | #define R_DMA_CH8_SUB__sub__BITNR 0 | ||
| 5840 | #define R_DMA_CH8_SUB__sub__WIDTH 32 | ||
| 5841 | |||
| 5842 | #define R_DMA_CH8_NEP (IO_TYPECAST_UDWORD 0xb00001c0) | ||
| 5843 | #define R_DMA_CH8_NEP__nep__BITNR 0 | ||
| 5844 | #define R_DMA_CH8_NEP__nep__WIDTH 32 | ||
| 5845 | |||
| 5846 | #define R_DMA_CH8_SUB0_EP (IO_TYPECAST_UDWORD 0xb00001c8) | ||
| 5847 | #define R_DMA_CH8_SUB0_EP__ep__BITNR 0 | ||
| 5848 | #define R_DMA_CH8_SUB0_EP__ep__WIDTH 32 | ||
| 5849 | |||
| 5850 | #define R_DMA_CH8_SUB0_CMD (IO_TYPECAST_BYTE 0xb00001d3) | ||
| 5851 | #define R_DMA_CH8_SUB0_CMD__cmd__BITNR 0 | ||
| 5852 | #define R_DMA_CH8_SUB0_CMD__cmd__WIDTH 1 | ||
| 5853 | #define R_DMA_CH8_SUB0_CMD__cmd__stop 0 | ||
| 5854 | #define R_DMA_CH8_SUB0_CMD__cmd__start 1 | ||
| 5855 | |||
| 5856 | #define R_DMA_CH8_SUB0_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e3) | ||
| 5857 | #define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__BITNR 0 | ||
| 5858 | #define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__WIDTH 1 | ||
| 5859 | #define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__dont 0 | ||
| 5860 | #define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__do 1 | ||
| 5861 | |||
| 5862 | #define R_DMA_CH8_SUB1_EP (IO_TYPECAST_UDWORD 0xb00001cc) | ||
| 5863 | #define R_DMA_CH8_SUB1_EP__ep__BITNR 0 | ||
| 5864 | #define R_DMA_CH8_SUB1_EP__ep__WIDTH 32 | ||
| 5865 | |||
| 5866 | #define R_DMA_CH8_SUB1_CMD (IO_TYPECAST_BYTE 0xb00001d7) | ||
| 5867 | #define R_DMA_CH8_SUB1_CMD__cmd__BITNR 0 | ||
| 5868 | #define R_DMA_CH8_SUB1_CMD__cmd__WIDTH 1 | ||
| 5869 | #define R_DMA_CH8_SUB1_CMD__cmd__stop 0 | ||
| 5870 | #define R_DMA_CH8_SUB1_CMD__cmd__start 1 | ||
| 5871 | |||
| 5872 | #define R_DMA_CH8_SUB1_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e7) | ||
| 5873 | #define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__BITNR 0 | ||
| 5874 | #define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__WIDTH 1 | ||
| 5875 | #define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__dont 0 | ||
| 5876 | #define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__do 1 | ||
| 5877 | |||
| 5878 | #define R_DMA_CH8_SUB2_EP (IO_TYPECAST_UDWORD 0xb00001f8) | ||
| 5879 | #define R_DMA_CH8_SUB2_EP__ep__BITNR 0 | ||
| 5880 | #define R_DMA_CH8_SUB2_EP__ep__WIDTH 32 | ||
| 5881 | |||
| 5882 | #define R_DMA_CH8_SUB2_CMD (IO_TYPECAST_BYTE 0xb00001db) | ||
| 5883 | #define R_DMA_CH8_SUB2_CMD__cmd__BITNR 0 | ||
| 5884 | #define R_DMA_CH8_SUB2_CMD__cmd__WIDTH 1 | ||
| 5885 | #define R_DMA_CH8_SUB2_CMD__cmd__stop 0 | ||
| 5886 | #define R_DMA_CH8_SUB2_CMD__cmd__start 1 | ||
| 5887 | |||
| 5888 | #define R_DMA_CH8_SUB2_CLR_INTR (IO_TYPECAST_BYTE 0xb00001eb) | ||
| 5889 | #define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__BITNR 0 | ||
| 5890 | #define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__WIDTH 1 | ||
| 5891 | #define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__dont 0 | ||
| 5892 | #define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__do 1 | ||
| 5893 | |||
| 5894 | #define R_DMA_CH8_SUB3_EP (IO_TYPECAST_UDWORD 0xb00001fc) | ||
| 5895 | #define R_DMA_CH8_SUB3_EP__ep__BITNR 0 | ||
| 5896 | #define R_DMA_CH8_SUB3_EP__ep__WIDTH 32 | ||
| 5897 | |||
| 5898 | #define R_DMA_CH8_SUB3_CMD (IO_TYPECAST_BYTE 0xb00001df) | ||
| 5899 | #define R_DMA_CH8_SUB3_CMD__cmd__BITNR 0 | ||
| 5900 | #define R_DMA_CH8_SUB3_CMD__cmd__WIDTH 1 | ||
| 5901 | #define R_DMA_CH8_SUB3_CMD__cmd__stop 0 | ||
| 5902 | #define R_DMA_CH8_SUB3_CMD__cmd__start 1 | ||
| 5903 | |||
| 5904 | #define R_DMA_CH8_SUB3_CLR_INTR (IO_TYPECAST_BYTE 0xb00001ef) | ||
| 5905 | #define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__BITNR 0 | ||
| 5906 | #define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__WIDTH 1 | ||
| 5907 | #define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__dont 0 | ||
| 5908 | #define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__do 1 | ||
| 5909 | |||
| 5910 | #define R_DMA_CH9_HWSW (IO_TYPECAST_UDWORD 0xb0000190) | ||
| 5911 | #define R_DMA_CH9_HWSW__hw__BITNR 16 | ||
| 5912 | #define R_DMA_CH9_HWSW__hw__WIDTH 16 | ||
| 5913 | #define R_DMA_CH9_HWSW__sw__BITNR 0 | ||
| 5914 | #define R_DMA_CH9_HWSW__sw__WIDTH 16 | ||
| 5915 | |||
| 5916 | #define R_DMA_CH9_DESCR (IO_TYPECAST_UDWORD 0xb000019c) | ||
| 5917 | #define R_DMA_CH9_DESCR__descr__BITNR 0 | ||
| 5918 | #define R_DMA_CH9_DESCR__descr__WIDTH 32 | ||
| 5919 | |||
| 5920 | #define R_DMA_CH9_NEXT (IO_TYPECAST_UDWORD 0xb0000194) | ||
| 5921 | #define R_DMA_CH9_NEXT__next__BITNR 0 | ||
| 5922 | #define R_DMA_CH9_NEXT__next__WIDTH 32 | ||
| 5923 | |||
| 5924 | #define R_DMA_CH9_BUF (IO_TYPECAST_UDWORD 0xb0000198) | ||
| 5925 | #define R_DMA_CH9_BUF__buf__BITNR 0 | ||
| 5926 | #define R_DMA_CH9_BUF__buf__WIDTH 32 | ||
| 5927 | |||
| 5928 | #define R_DMA_CH9_FIRST (IO_TYPECAST_UDWORD 0xb00001c4) | ||
| 5929 | #define R_DMA_CH9_FIRST__first__BITNR 0 | ||
| 5930 | #define R_DMA_CH9_FIRST__first__WIDTH 32 | ||
| 5931 | |||
| 5932 | #define R_DMA_CH9_CMD (IO_TYPECAST_BYTE 0xb00001f4) | ||
| 5933 | #define R_DMA_CH9_CMD__cmd__BITNR 0 | ||
| 5934 | #define R_DMA_CH9_CMD__cmd__WIDTH 3 | ||
| 5935 | #define R_DMA_CH9_CMD__cmd__hold 0 | ||
| 5936 | #define R_DMA_CH9_CMD__cmd__start 1 | ||
| 5937 | #define R_DMA_CH9_CMD__cmd__restart 3 | ||
| 5938 | #define R_DMA_CH9_CMD__cmd__continue 3 | ||
| 5939 | #define R_DMA_CH9_CMD__cmd__reset 4 | ||
| 5940 | |||
| 5941 | #define R_DMA_CH9_CLR_INTR (IO_TYPECAST_BYTE 0xb00001f5) | ||
| 5942 | #define R_DMA_CH9_CLR_INTR__clr_eop__BITNR 1 | ||
| 5943 | #define R_DMA_CH9_CLR_INTR__clr_eop__WIDTH 1 | ||
| 5944 | #define R_DMA_CH9_CLR_INTR__clr_eop__do 1 | ||
| 5945 | #define R_DMA_CH9_CLR_INTR__clr_eop__dont 0 | ||
| 5946 | #define R_DMA_CH9_CLR_INTR__clr_descr__BITNR 0 | ||
| 5947 | #define R_DMA_CH9_CLR_INTR__clr_descr__WIDTH 1 | ||
| 5948 | #define R_DMA_CH9_CLR_INTR__clr_descr__do 1 | ||
| 5949 | #define R_DMA_CH9_CLR_INTR__clr_descr__dont 0 | ||
| 5950 | |||
| 5951 | #define R_DMA_CH9_STATUS (IO_TYPECAST_RO_BYTE 0xb00001f6) | ||
| 5952 | #define R_DMA_CH9_STATUS__avail__BITNR 0 | ||
| 5953 | #define R_DMA_CH9_STATUS__avail__WIDTH 7 | ||
| 5954 | |||
| 5955 | /* | ||
| 5956 | !* Test mode registers | ||
| 5957 | !*/ | ||
| 5958 | |||
| 5959 | #define R_TEST_MODE (IO_TYPECAST_UDWORD 0xb00000fc) | ||
| 5960 | #define R_TEST_MODE__single_step__BITNR 19 | ||
| 5961 | #define R_TEST_MODE__single_step__WIDTH 1 | ||
| 5962 | #define R_TEST_MODE__single_step__on 1 | ||
| 5963 | #define R_TEST_MODE__single_step__off 0 | ||
| 5964 | #define R_TEST_MODE__step_wr__BITNR 18 | ||
| 5965 | #define R_TEST_MODE__step_wr__WIDTH 1 | ||
| 5966 | #define R_TEST_MODE__step_wr__on 1 | ||
| 5967 | #define R_TEST_MODE__step_wr__off 0 | ||
| 5968 | #define R_TEST_MODE__step_rd__BITNR 17 | ||
| 5969 | #define R_TEST_MODE__step_rd__WIDTH 1 | ||
| 5970 | #define R_TEST_MODE__step_rd__on 1 | ||
| 5971 | #define R_TEST_MODE__step_rd__off 0 | ||
| 5972 | #define R_TEST_MODE__step_fetch__BITNR 16 | ||
| 5973 | #define R_TEST_MODE__step_fetch__WIDTH 1 | ||
| 5974 | #define R_TEST_MODE__step_fetch__on 1 | ||
| 5975 | #define R_TEST_MODE__step_fetch__off 0 | ||
| 5976 | #define R_TEST_MODE__mmu_test__BITNR 12 | ||
| 5977 | #define R_TEST_MODE__mmu_test__WIDTH 1 | ||
| 5978 | #define R_TEST_MODE__mmu_test__on 1 | ||
| 5979 | #define R_TEST_MODE__mmu_test__off 0 | ||
| 5980 | #define R_TEST_MODE__usb_test__BITNR 11 | ||
| 5981 | #define R_TEST_MODE__usb_test__WIDTH 1 | ||
| 5982 | #define R_TEST_MODE__usb_test__on 1 | ||
| 5983 | #define R_TEST_MODE__usb_test__off 0 | ||
| 5984 | #define R_TEST_MODE__scsi_timer_test__BITNR 10 | ||
| 5985 | #define R_TEST_MODE__scsi_timer_test__WIDTH 1 | ||
| 5986 | #define R_TEST_MODE__scsi_timer_test__on 1 | ||
| 5987 | #define R_TEST_MODE__scsi_timer_test__off 0 | ||
| 5988 | #define R_TEST_MODE__backoff__BITNR 9 | ||
| 5989 | #define R_TEST_MODE__backoff__WIDTH 1 | ||
| 5990 | #define R_TEST_MODE__backoff__on 1 | ||
| 5991 | #define R_TEST_MODE__backoff__off 0 | ||
| 5992 | #define R_TEST_MODE__snmp_test__BITNR 8 | ||
| 5993 | #define R_TEST_MODE__snmp_test__WIDTH 1 | ||
| 5994 | #define R_TEST_MODE__snmp_test__on 1 | ||
| 5995 | #define R_TEST_MODE__snmp_test__off 0 | ||
| 5996 | #define R_TEST_MODE__snmp_inc__BITNR 7 | ||
| 5997 | #define R_TEST_MODE__snmp_inc__WIDTH 1 | ||
| 5998 | #define R_TEST_MODE__snmp_inc__do 1 | ||
| 5999 | #define R_TEST_MODE__snmp_inc__dont 0 | ||
| 6000 | #define R_TEST_MODE__ser_loop__BITNR 6 | ||
| 6001 | #define R_TEST_MODE__ser_loop__WIDTH 1 | ||
| 6002 | #define R_TEST_MODE__ser_loop__on 1 | ||
| 6003 | #define R_TEST_MODE__ser_loop__off 0 | ||
| 6004 | #define R_TEST_MODE__baudrate__BITNR 5 | ||
| 6005 | #define R_TEST_MODE__baudrate__WIDTH 1 | ||
| 6006 | #define R_TEST_MODE__baudrate__on 1 | ||
| 6007 | #define R_TEST_MODE__baudrate__off 0 | ||
| 6008 | #define R_TEST_MODE__timer__BITNR 3 | ||
| 6009 | #define R_TEST_MODE__timer__WIDTH 2 | ||
| 6010 | #define R_TEST_MODE__timer__off 0 | ||
| 6011 | #define R_TEST_MODE__timer__even 1 | ||
| 6012 | #define R_TEST_MODE__timer__odd 2 | ||
| 6013 | #define R_TEST_MODE__timer__all 3 | ||
| 6014 | #define R_TEST_MODE__cache_test__BITNR 2 | ||
| 6015 | #define R_TEST_MODE__cache_test__WIDTH 1 | ||
| 6016 | #define R_TEST_MODE__cache_test__normal 0 | ||
| 6017 | #define R_TEST_MODE__cache_test__test 1 | ||
| 6018 | #define R_TEST_MODE__tag_test__BITNR 1 | ||
| 6019 | #define R_TEST_MODE__tag_test__WIDTH 1 | ||
| 6020 | #define R_TEST_MODE__tag_test__normal 0 | ||
| 6021 | #define R_TEST_MODE__tag_test__test 1 | ||
| 6022 | #define R_TEST_MODE__cache_enable__BITNR 0 | ||
| 6023 | #define R_TEST_MODE__cache_enable__WIDTH 1 | ||
| 6024 | #define R_TEST_MODE__cache_enable__enable 1 | ||
| 6025 | #define R_TEST_MODE__cache_enable__disable 0 | ||
| 6026 | |||
| 6027 | #define R_SINGLE_STEP (IO_TYPECAST_BYTE 0xb00000fe) | ||
| 6028 | #define R_SINGLE_STEP__single_step__BITNR 3 | ||
| 6029 | #define R_SINGLE_STEP__single_step__WIDTH 1 | ||
| 6030 | #define R_SINGLE_STEP__single_step__on 1 | ||
| 6031 | #define R_SINGLE_STEP__single_step__off 0 | ||
| 6032 | #define R_SINGLE_STEP__step_wr__BITNR 2 | ||
| 6033 | #define R_SINGLE_STEP__step_wr__WIDTH 1 | ||
| 6034 | #define R_SINGLE_STEP__step_wr__on 1 | ||
| 6035 | #define R_SINGLE_STEP__step_wr__off 0 | ||
| 6036 | #define R_SINGLE_STEP__step_rd__BITNR 1 | ||
| 6037 | #define R_SINGLE_STEP__step_rd__WIDTH 1 | ||
| 6038 | #define R_SINGLE_STEP__step_rd__on 1 | ||
| 6039 | #define R_SINGLE_STEP__step_rd__off 0 | ||
| 6040 | #define R_SINGLE_STEP__step_fetch__BITNR 0 | ||
| 6041 | #define R_SINGLE_STEP__step_fetch__WIDTH 1 | ||
| 6042 | #define R_SINGLE_STEP__step_fetch__on 1 | ||
| 6043 | #define R_SINGLE_STEP__step_fetch__off 0 | ||
| 6044 | |||
| 6045 | /* | ||
| 6046 | !* USB interface control registers | ||
| 6047 | !*/ | ||
| 6048 | |||
| 6049 | #define R_USB_REVISION (IO_TYPECAST_RO_BYTE 0xb0000200) | ||
| 6050 | #define R_USB_REVISION__major__BITNR 4 | ||
| 6051 | #define R_USB_REVISION__major__WIDTH 4 | ||
| 6052 | #define R_USB_REVISION__minor__BITNR 0 | ||
| 6053 | #define R_USB_REVISION__minor__WIDTH 4 | ||
| 6054 | |||
| 6055 | #define R_USB_COMMAND (IO_TYPECAST_BYTE 0xb0000201) | ||
| 6056 | #define R_USB_COMMAND__port_sel__BITNR 6 | ||
| 6057 | #define R_USB_COMMAND__port_sel__WIDTH 2 | ||
| 6058 | #define R_USB_COMMAND__port_sel__nop 0 | ||
| 6059 | #define R_USB_COMMAND__port_sel__port1 1 | ||
| 6060 | #define R_USB_COMMAND__port_sel__port2 2 | ||
| 6061 | #define R_USB_COMMAND__port_sel__both 3 | ||
| 6062 | #define R_USB_COMMAND__port_cmd__BITNR 4 | ||
| 6063 | #define R_USB_COMMAND__port_cmd__WIDTH 2 | ||
| 6064 | #define R_USB_COMMAND__port_cmd__reset 0 | ||
| 6065 | #define R_USB_COMMAND__port_cmd__disable 1 | ||
| 6066 | #define R_USB_COMMAND__port_cmd__suspend 2 | ||
| 6067 | #define R_USB_COMMAND__port_cmd__resume 3 | ||
| 6068 | #define R_USB_COMMAND__busy__BITNR 3 | ||
| 6069 | #define R_USB_COMMAND__busy__WIDTH 1 | ||
| 6070 | #define R_USB_COMMAND__busy__no 0 | ||
| 6071 | #define R_USB_COMMAND__busy__yes 1 | ||
| 6072 | #define R_USB_COMMAND__ctrl_cmd__BITNR 0 | ||
| 6073 | #define R_USB_COMMAND__ctrl_cmd__WIDTH 3 | ||
| 6074 | #define R_USB_COMMAND__ctrl_cmd__nop 0 | ||
| 6075 | #define R_USB_COMMAND__ctrl_cmd__reset 1 | ||
| 6076 | #define R_USB_COMMAND__ctrl_cmd__deconfig 2 | ||
| 6077 | #define R_USB_COMMAND__ctrl_cmd__host_config 3 | ||
| 6078 | #define R_USB_COMMAND__ctrl_cmd__dev_config 4 | ||
| 6079 | #define R_USB_COMMAND__ctrl_cmd__host_nop 5 | ||
| 6080 | #define R_USB_COMMAND__ctrl_cmd__host_run 6 | ||
| 6081 | #define R_USB_COMMAND__ctrl_cmd__host_stop 7 | ||
| 6082 | |||
| 6083 | #define R_USB_COMMAND_DEV (IO_TYPECAST_BYTE 0xb0000201) | ||
| 6084 | #define R_USB_COMMAND_DEV__port_sel__BITNR 6 | ||
| 6085 | #define R_USB_COMMAND_DEV__port_sel__WIDTH 2 | ||
| 6086 | #define R_USB_COMMAND_DEV__port_sel__nop 0 | ||
| 6087 | #define R_USB_COMMAND_DEV__port_sel__dummy1 1 | ||
| 6088 | #define R_USB_COMMAND_DEV__port_sel__dummy2 2 | ||
| 6089 | #define R_USB_COMMAND_DEV__port_sel__any 3 | ||
| 6090 | #define R_USB_COMMAND_DEV__port_cmd__BITNR 4 | ||
| 6091 | #define R_USB_COMMAND_DEV__port_cmd__WIDTH 2 | ||
| 6092 | #define R_USB_COMMAND_DEV__port_cmd__active 0 | ||
| 6093 | #define R_USB_COMMAND_DEV__port_cmd__passive 1 | ||
| 6094 | #define R_USB_COMMAND_DEV__port_cmd__nop 2 | ||
| 6095 | #define R_USB_COMMAND_DEV__port_cmd__wakeup 3 | ||
| 6096 | #define R_USB_COMMAND_DEV__busy__BITNR 3 | ||
| 6097 | #define R_USB_COMMAND_DEV__busy__WIDTH 1 | ||
| 6098 | #define R_USB_COMMAND_DEV__busy__no 0 | ||
| 6099 | #define R_USB_COMMAND_DEV__busy__yes 1 | ||
| 6100 | #define R_USB_COMMAND_DEV__ctrl_cmd__BITNR 0 | ||
| 6101 | #define R_USB_COMMAND_DEV__ctrl_cmd__WIDTH 3 | ||
| 6102 | #define R_USB_COMMAND_DEV__ctrl_cmd__nop 0 | ||
| 6103 | #define R_USB_COMMAND_DEV__ctrl_cmd__reset 1 | ||
| 6104 | #define R_USB_COMMAND_DEV__ctrl_cmd__deconfig 2 | ||
| 6105 | #define R_USB_COMMAND_DEV__ctrl_cmd__host_config 3 | ||
| 6106 | #define R_USB_COMMAND_DEV__ctrl_cmd__dev_config 4 | ||
| 6107 | #define R_USB_COMMAND_DEV__ctrl_cmd__dev_active 5 | ||
| 6108 | #define R_USB_COMMAND_DEV__ctrl_cmd__dev_passive 6 | ||
| 6109 | #define R_USB_COMMAND_DEV__ctrl_cmd__dev_nop 7 | ||
| 6110 | |||
| 6111 | #define R_USB_STATUS (IO_TYPECAST_RO_BYTE 0xb0000202) | ||
| 6112 | #define R_USB_STATUS__ourun__BITNR 5 | ||
| 6113 | #define R_USB_STATUS__ourun__WIDTH 1 | ||
| 6114 | #define R_USB_STATUS__ourun__no 0 | ||
| 6115 | #define R_USB_STATUS__ourun__yes 1 | ||
| 6116 | #define R_USB_STATUS__perror__BITNR 4 | ||
| 6117 | #define R_USB_STATUS__perror__WIDTH 1 | ||
| 6118 | #define R_USB_STATUS__perror__no 0 | ||
| 6119 | #define R_USB_STATUS__perror__yes 1 | ||
| 6120 | #define R_USB_STATUS__device_mode__BITNR 3 | ||
| 6121 | #define R_USB_STATUS__device_mode__WIDTH 1 | ||
| 6122 | #define R_USB_STATUS__device_mode__no 0 | ||
| 6123 | #define R_USB_STATUS__device_mode__yes 1 | ||
| 6124 | #define R_USB_STATUS__host_mode__BITNR 2 | ||
| 6125 | #define R_USB_STATUS__host_mode__WIDTH 1 | ||
| 6126 | #define R_USB_STATUS__host_mode__no 0 | ||
| 6127 | #define R_USB_STATUS__host_mode__yes 1 | ||
| 6128 | #define R_USB_STATUS__started__BITNR 1 | ||
| 6129 | #define R_USB_STATUS__started__WIDTH 1 | ||
| 6130 | #define R_USB_STATUS__started__no 0 | ||
| 6131 | #define R_USB_STATUS__started__yes 1 | ||
| 6132 | #define R_USB_STATUS__running__BITNR 0 | ||
| 6133 | #define R_USB_STATUS__running__WIDTH 1 | ||
| 6134 | #define R_USB_STATUS__running__no 0 | ||
| 6135 | #define R_USB_STATUS__running__yes 1 | ||
| 6136 | |||
| 6137 | #define R_USB_IRQ_MASK_SET (IO_TYPECAST_UWORD 0xb0000204) | ||
| 6138 | #define R_USB_IRQ_MASK_SET__iso_eof__BITNR 13 | ||
| 6139 | #define R_USB_IRQ_MASK_SET__iso_eof__WIDTH 1 | ||
| 6140 | #define R_USB_IRQ_MASK_SET__iso_eof__nop 0 | ||
| 6141 | #define R_USB_IRQ_MASK_SET__iso_eof__set 1 | ||
| 6142 | #define R_USB_IRQ_MASK_SET__intr_eof__BITNR 12 | ||
| 6143 | #define R_USB_IRQ_MASK_SET__intr_eof__WIDTH 1 | ||
| 6144 | #define R_USB_IRQ_MASK_SET__intr_eof__nop 0 | ||
| 6145 | #define R_USB_IRQ_MASK_SET__intr_eof__set 1 | ||
| 6146 | #define R_USB_IRQ_MASK_SET__iso_eot__BITNR 11 | ||
| 6147 | #define R_USB_IRQ_MASK_SET__iso_eot__WIDTH 1 | ||
| 6148 | #define R_USB_IRQ_MASK_SET__iso_eot__nop 0 | ||
| 6149 | #define R_USB_IRQ_MASK_SET__iso_eot__set 1 | ||
| 6150 | #define R_USB_IRQ_MASK_SET__intr_eot__BITNR 10 | ||
| 6151 | #define R_USB_IRQ_MASK_SET__intr_eot__WIDTH 1 | ||
| 6152 | #define R_USB_IRQ_MASK_SET__intr_eot__nop 0 | ||
| 6153 | #define R_USB_IRQ_MASK_SET__intr_eot__set 1 | ||
| 6154 | #define R_USB_IRQ_MASK_SET__ctl_eot__BITNR 9 | ||
| 6155 | #define R_USB_IRQ_MASK_SET__ctl_eot__WIDTH 1 | ||
| 6156 | #define R_USB_IRQ_MASK_SET__ctl_eot__nop 0 | ||
| 6157 | #define R_USB_IRQ_MASK_SET__ctl_eot__set 1 | ||
| 6158 | #define R_USB_IRQ_MASK_SET__bulk_eot__BITNR 8 | ||
| 6159 | #define R_USB_IRQ_MASK_SET__bulk_eot__WIDTH 1 | ||
| 6160 | #define R_USB_IRQ_MASK_SET__bulk_eot__nop 0 | ||
| 6161 | #define R_USB_IRQ_MASK_SET__bulk_eot__set 1 | ||
| 6162 | #define R_USB_IRQ_MASK_SET__epid_attn__BITNR 3 | ||
| 6163 | #define R_USB_IRQ_MASK_SET__epid_attn__WIDTH 1 | ||
| 6164 | #define R_USB_IRQ_MASK_SET__epid_attn__nop 0 | ||
| 6165 | #define R_USB_IRQ_MASK_SET__epid_attn__set 1 | ||
| 6166 | #define R_USB_IRQ_MASK_SET__sof__BITNR 2 | ||
| 6167 | #define R_USB_IRQ_MASK_SET__sof__WIDTH 1 | ||
| 6168 | #define R_USB_IRQ_MASK_SET__sof__nop 0 | ||
| 6169 | #define R_USB_IRQ_MASK_SET__sof__set 1 | ||
| 6170 | #define R_USB_IRQ_MASK_SET__port_status__BITNR 1 | ||
| 6171 | #define R_USB_IRQ_MASK_SET__port_status__WIDTH 1 | ||
| 6172 | #define R_USB_IRQ_MASK_SET__port_status__nop 0 | ||
| 6173 | #define R_USB_IRQ_MASK_SET__port_status__set 1 | ||
| 6174 | #define R_USB_IRQ_MASK_SET__ctl_status__BITNR 0 | ||
| 6175 | #define R_USB_IRQ_MASK_SET__ctl_status__WIDTH 1 | ||
| 6176 | #define R_USB_IRQ_MASK_SET__ctl_status__nop 0 | ||
| 6177 | #define R_USB_IRQ_MASK_SET__ctl_status__set 1 | ||
| 6178 | |||
| 6179 | #define R_USB_IRQ_MASK_READ (IO_TYPECAST_RO_UWORD 0xb0000204) | ||
| 6180 | #define R_USB_IRQ_MASK_READ__iso_eof__BITNR 13 | ||
| 6181 | #define R_USB_IRQ_MASK_READ__iso_eof__WIDTH 1 | ||
| 6182 | #define R_USB_IRQ_MASK_READ__iso_eof__no_pend 0 | ||
| 6183 | #define R_USB_IRQ_MASK_READ__iso_eof__pend 1 | ||
| 6184 | #define R_USB_IRQ_MASK_READ__intr_eof__BITNR 12 | ||
| 6185 | #define R_USB_IRQ_MASK_READ__intr_eof__WIDTH 1 | ||
| 6186 | #define R_USB_IRQ_MASK_READ__intr_eof__no_pend 0 | ||
| 6187 | #define R_USB_IRQ_MASK_READ__intr_eof__pend 1 | ||
| 6188 | #define R_USB_IRQ_MASK_READ__iso_eot__BITNR 11 | ||
| 6189 | #define R_USB_IRQ_MASK_READ__iso_eot__WIDTH 1 | ||
| 6190 | #define R_USB_IRQ_MASK_READ__iso_eot__no_pend 0 | ||
| 6191 | #define R_USB_IRQ_MASK_READ__iso_eot__pend 1 | ||
| 6192 | #define R_USB_IRQ_MASK_READ__intr_eot__BITNR 10 | ||
| 6193 | #define R_USB_IRQ_MASK_READ__intr_eot__WIDTH 1 | ||
| 6194 | #define R_USB_IRQ_MASK_READ__intr_eot__no_pend 0 | ||
| 6195 | #define R_USB_IRQ_MASK_READ__intr_eot__pend 1 | ||
| 6196 | #define R_USB_IRQ_MASK_READ__ctl_eot__BITNR 9 | ||
| 6197 | #define R_USB_IRQ_MASK_READ__ctl_eot__WIDTH 1 | ||
| 6198 | #define R_USB_IRQ_MASK_READ__ctl_eot__no_pend 0 | ||
| 6199 | #define R_USB_IRQ_MASK_READ__ctl_eot__pend 1 | ||
| 6200 | #define R_USB_IRQ_MASK_READ__bulk_eot__BITNR 8 | ||
| 6201 | #define R_USB_IRQ_MASK_READ__bulk_eot__WIDTH 1 | ||
| 6202 | #define R_USB_IRQ_MASK_READ__bulk_eot__no_pend 0 | ||
| 6203 | #define R_USB_IRQ_MASK_READ__bulk_eot__pend 1 | ||
| 6204 | #define R_USB_IRQ_MASK_READ__epid_attn__BITNR 3 | ||
| 6205 | #define R_USB_IRQ_MASK_READ__epid_attn__WIDTH 1 | ||
| 6206 | #define R_USB_IRQ_MASK_READ__epid_attn__no_pend 0 | ||
| 6207 | #define R_USB_IRQ_MASK_READ__epid_attn__pend 1 | ||
| 6208 | #define R_USB_IRQ_MASK_READ__sof__BITNR 2 | ||
| 6209 | #define R_USB_IRQ_MASK_READ__sof__WIDTH 1 | ||
| 6210 | #define R_USB_IRQ_MASK_READ__sof__no_pend 0 | ||
| 6211 | #define R_USB_IRQ_MASK_READ__sof__pend 1 | ||
| 6212 | #define R_USB_IRQ_MASK_READ__port_status__BITNR 1 | ||
| 6213 | #define R_USB_IRQ_MASK_READ__port_status__WIDTH 1 | ||
| 6214 | #define R_USB_IRQ_MASK_READ__port_status__no_pend 0 | ||
| 6215 | #define R_USB_IRQ_MASK_READ__port_status__pend 1 | ||
| 6216 | #define R_USB_IRQ_MASK_READ__ctl_status__BITNR 0 | ||
| 6217 | #define R_USB_IRQ_MASK_READ__ctl_status__WIDTH 1 | ||
| 6218 | #define R_USB_IRQ_MASK_READ__ctl_status__no_pend 0 | ||
| 6219 | #define R_USB_IRQ_MASK_READ__ctl_status__pend 1 | ||
| 6220 | |||
| 6221 | #define R_USB_IRQ_MASK_CLR (IO_TYPECAST_UWORD 0xb0000206) | ||
| 6222 | #define R_USB_IRQ_MASK_CLR__iso_eof__BITNR 13 | ||
| 6223 | #define R_USB_IRQ_MASK_CLR__iso_eof__WIDTH 1 | ||
| 6224 | #define R_USB_IRQ_MASK_CLR__iso_eof__nop 0 | ||
| 6225 | #define R_USB_IRQ_MASK_CLR__iso_eof__clr 1 | ||
| 6226 | #define R_USB_IRQ_MASK_CLR__intr_eof__BITNR 12 | ||
| 6227 | #define R_USB_IRQ_MASK_CLR__intr_eof__WIDTH 1 | ||
| 6228 | #define R_USB_IRQ_MASK_CLR__intr_eof__nop 0 | ||
| 6229 | #define R_USB_IRQ_MASK_CLR__intr_eof__clr 1 | ||
| 6230 | #define R_USB_IRQ_MASK_CLR__iso_eot__BITNR 11 | ||
| 6231 | #define R_USB_IRQ_MASK_CLR__iso_eot__WIDTH 1 | ||
| 6232 | #define R_USB_IRQ_MASK_CLR__iso_eot__nop 0 | ||
| 6233 | #define R_USB_IRQ_MASK_CLR__iso_eot__clr 1 | ||
| 6234 | #define R_USB_IRQ_MASK_CLR__intr_eot__BITNR 10 | ||
| 6235 | #define R_USB_IRQ_MASK_CLR__intr_eot__WIDTH 1 | ||
| 6236 | #define R_USB_IRQ_MASK_CLR__intr_eot__nop 0 | ||
| 6237 | #define R_USB_IRQ_MASK_CLR__intr_eot__clr 1 | ||
| 6238 | #define R_USB_IRQ_MASK_CLR__ctl_eot__BITNR 9 | ||
| 6239 | #define R_USB_IRQ_MASK_CLR__ctl_eot__WIDTH 1 | ||
| 6240 | #define R_USB_IRQ_MASK_CLR__ctl_eot__nop 0 | ||
| 6241 | #define R_USB_IRQ_MASK_CLR__ctl_eot__clr 1 | ||
| 6242 | #define R_USB_IRQ_MASK_CLR__bulk_eot__BITNR 8 | ||
| 6243 | #define R_USB_IRQ_MASK_CLR__bulk_eot__WIDTH 1 | ||
| 6244 | #define R_USB_IRQ_MASK_CLR__bulk_eot__nop 0 | ||
| 6245 | #define R_USB_IRQ_MASK_CLR__bulk_eot__clr 1 | ||
| 6246 | #define R_USB_IRQ_MASK_CLR__epid_attn__BITNR 3 | ||
| 6247 | #define R_USB_IRQ_MASK_CLR__epid_attn__WIDTH 1 | ||
| 6248 | #define R_USB_IRQ_MASK_CLR__epid_attn__nop 0 | ||
| 6249 | #define R_USB_IRQ_MASK_CLR__epid_attn__clr 1 | ||
| 6250 | #define R_USB_IRQ_MASK_CLR__sof__BITNR 2 | ||
| 6251 | #define R_USB_IRQ_MASK_CLR__sof__WIDTH 1 | ||
| 6252 | #define R_USB_IRQ_MASK_CLR__sof__nop 0 | ||
| 6253 | #define R_USB_IRQ_MASK_CLR__sof__clr 1 | ||
| 6254 | #define R_USB_IRQ_MASK_CLR__port_status__BITNR 1 | ||
| 6255 | #define R_USB_IRQ_MASK_CLR__port_status__WIDTH 1 | ||
| 6256 | #define R_USB_IRQ_MASK_CLR__port_status__nop 0 | ||
| 6257 | #define R_USB_IRQ_MASK_CLR__port_status__clr 1 | ||
| 6258 | #define R_USB_IRQ_MASK_CLR__ctl_status__BITNR 0 | ||
| 6259 | #define R_USB_IRQ_MASK_CLR__ctl_status__WIDTH 1 | ||
| 6260 | #define R_USB_IRQ_MASK_CLR__ctl_status__nop 0 | ||
| 6261 | #define R_USB_IRQ_MASK_CLR__ctl_status__clr 1 | ||
| 6262 | |||
| 6263 | #define R_USB_IRQ_READ (IO_TYPECAST_RO_UWORD 0xb0000206) | ||
| 6264 | #define R_USB_IRQ_READ__iso_eof__BITNR 13 | ||
| 6265 | #define R_USB_IRQ_READ__iso_eof__WIDTH 1 | ||
| 6266 | #define R_USB_IRQ_READ__iso_eof__no_pend 0 | ||
| 6267 | #define R_USB_IRQ_READ__iso_eof__pend 1 | ||
| 6268 | #define R_USB_IRQ_READ__intr_eof__BITNR 12 | ||
| 6269 | #define R_USB_IRQ_READ__intr_eof__WIDTH 1 | ||
| 6270 | #define R_USB_IRQ_READ__intr_eof__no_pend 0 | ||
| 6271 | #define R_USB_IRQ_READ__intr_eof__pend 1 | ||
| 6272 | #define R_USB_IRQ_READ__iso_eot__BITNR 11 | ||
| 6273 | #define R_USB_IRQ_READ__iso_eot__WIDTH 1 | ||
| 6274 | #define R_USB_IRQ_READ__iso_eot__no_pend 0 | ||
| 6275 | #define R_USB_IRQ_READ__iso_eot__pend 1 | ||
| 6276 | #define R_USB_IRQ_READ__intr_eot__BITNR 10 | ||
| 6277 | #define R_USB_IRQ_READ__intr_eot__WIDTH 1 | ||
| 6278 | #define R_USB_IRQ_READ__intr_eot__no_pend 0 | ||
| 6279 | #define R_USB_IRQ_READ__intr_eot__pend 1 | ||
| 6280 | #define R_USB_IRQ_READ__ctl_eot__BITNR 9 | ||
| 6281 | #define R_USB_IRQ_READ__ctl_eot__WIDTH 1 | ||
| 6282 | #define R_USB_IRQ_READ__ctl_eot__no_pend 0 | ||
| 6283 | #define R_USB_IRQ_READ__ctl_eot__pend 1 | ||
| 6284 | #define R_USB_IRQ_READ__bulk_eot__BITNR 8 | ||
| 6285 | #define R_USB_IRQ_READ__bulk_eot__WIDTH 1 | ||
| 6286 | #define R_USB_IRQ_READ__bulk_eot__no_pend 0 | ||
| 6287 | #define R_USB_IRQ_READ__bulk_eot__pend 1 | ||
| 6288 | #define R_USB_IRQ_READ__epid_attn__BITNR 3 | ||
| 6289 | #define R_USB_IRQ_READ__epid_attn__WIDTH 1 | ||
| 6290 | #define R_USB_IRQ_READ__epid_attn__no_pend 0 | ||
| 6291 | #define R_USB_IRQ_READ__epid_attn__pend 1 | ||
| 6292 | #define R_USB_IRQ_READ__sof__BITNR 2 | ||
| 6293 | #define R_USB_IRQ_READ__sof__WIDTH 1 | ||
| 6294 | #define R_USB_IRQ_READ__sof__no_pend 0 | ||
| 6295 | #define R_USB_IRQ_READ__sof__pend 1 | ||
| 6296 | #define R_USB_IRQ_READ__port_status__BITNR 1 | ||
| 6297 | #define R_USB_IRQ_READ__port_status__WIDTH 1 | ||
| 6298 | #define R_USB_IRQ_READ__port_status__no_pend 0 | ||
| 6299 | #define R_USB_IRQ_READ__port_status__pend 1 | ||
| 6300 | #define R_USB_IRQ_READ__ctl_status__BITNR 0 | ||
| 6301 | #define R_USB_IRQ_READ__ctl_status__WIDTH 1 | ||
| 6302 | #define R_USB_IRQ_READ__ctl_status__no_pend 0 | ||
| 6303 | #define R_USB_IRQ_READ__ctl_status__pend 1 | ||
| 6304 | |||
| 6305 | #define R_USB_IRQ_MASK_SET_DEV (IO_TYPECAST_UWORD 0xb0000204) | ||
| 6306 | #define R_USB_IRQ_MASK_SET_DEV__out_eot__BITNR 12 | ||
| 6307 | #define R_USB_IRQ_MASK_SET_DEV__out_eot__WIDTH 1 | ||
| 6308 | #define R_USB_IRQ_MASK_SET_DEV__out_eot__nop 0 | ||
| 6309 | #define R_USB_IRQ_MASK_SET_DEV__out_eot__set 1 | ||
| 6310 | #define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__BITNR 11 | ||
| 6311 | #define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__WIDTH 1 | ||
| 6312 | #define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__nop 0 | ||
| 6313 | #define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__set 1 | ||
| 6314 | #define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__BITNR 10 | ||
| 6315 | #define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__WIDTH 1 | ||
| 6316 | #define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__nop 0 | ||
| 6317 | #define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__set 1 | ||
| 6318 | #define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__BITNR 9 | ||
| 6319 | #define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__WIDTH 1 | ||
| 6320 | #define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__nop 0 | ||
| 6321 | #define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__set 1 | ||
| 6322 | #define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__BITNR 8 | ||
| 6323 | #define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__WIDTH 1 | ||
| 6324 | #define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__nop 0 | ||
| 6325 | #define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__set 1 | ||
| 6326 | #define R_USB_IRQ_MASK_SET_DEV__epid_attn__BITNR 3 | ||
| 6327 | #define R_USB_IRQ_MASK_SET_DEV__epid_attn__WIDTH 1 | ||
| 6328 | #define R_USB_IRQ_MASK_SET_DEV__epid_attn__nop 0 | ||
| 6329 | #define R_USB_IRQ_MASK_SET_DEV__epid_attn__set 1 | ||
| 6330 | #define R_USB_IRQ_MASK_SET_DEV__sof__BITNR 2 | ||
| 6331 | #define R_USB_IRQ_MASK_SET_DEV__sof__WIDTH 1 | ||
| 6332 | #define R_USB_IRQ_MASK_SET_DEV__sof__nop 0 | ||
| 6333 | #define R_USB_IRQ_MASK_SET_DEV__sof__set 1 | ||
| 6334 | #define R_USB_IRQ_MASK_SET_DEV__port_status__BITNR 1 | ||
| 6335 | #define R_USB_IRQ_MASK_SET_DEV__port_status__WIDTH 1 | ||
| 6336 | #define R_USB_IRQ_MASK_SET_DEV__port_status__nop 0 | ||
| 6337 | #define R_USB_IRQ_MASK_SET_DEV__port_status__set 1 | ||
| 6338 | #define R_USB_IRQ_MASK_SET_DEV__ctl_status__BITNR 0 | ||
| 6339 | #define R_USB_IRQ_MASK_SET_DEV__ctl_status__WIDTH 1 | ||
| 6340 | #define R_USB_IRQ_MASK_SET_DEV__ctl_status__nop 0 | ||
| 6341 | #define R_USB_IRQ_MASK_SET_DEV__ctl_status__set 1 | ||
| 6342 | |||
| 6343 | #define R_USB_IRQ_MASK_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000204) | ||
| 6344 | #define R_USB_IRQ_MASK_READ_DEV__out_eot__BITNR 12 | ||
| 6345 | #define R_USB_IRQ_MASK_READ_DEV__out_eot__WIDTH 1 | ||
| 6346 | #define R_USB_IRQ_MASK_READ_DEV__out_eot__no_pend 0 | ||
| 6347 | #define R_USB_IRQ_MASK_READ_DEV__out_eot__pend 1 | ||
| 6348 | #define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__BITNR 11 | ||
| 6349 | #define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__WIDTH 1 | ||
| 6350 | #define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__no_pend 0 | ||
| 6351 | #define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__pend 1 | ||
| 6352 | #define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__BITNR 10 | ||
| 6353 | #define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__WIDTH 1 | ||
| 6354 | #define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__no_pend 0 | ||
| 6355 | #define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__pend 1 | ||
| 6356 | #define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__BITNR 9 | ||
| 6357 | #define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__WIDTH 1 | ||
| 6358 | #define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__no_pend 0 | ||
| 6359 | #define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__pend 1 | ||
| 6360 | #define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__BITNR 8 | ||
| 6361 | #define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__WIDTH 1 | ||
| 6362 | #define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__no_pend 0 | ||
| 6363 | #define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__pend 1 | ||
| 6364 | #define R_USB_IRQ_MASK_READ_DEV__epid_attn__BITNR 3 | ||
| 6365 | #define R_USB_IRQ_MASK_READ_DEV__epid_attn__WIDTH 1 | ||
| 6366 | #define R_USB_IRQ_MASK_READ_DEV__epid_attn__no_pend 0 | ||
| 6367 | #define R_USB_IRQ_MASK_READ_DEV__epid_attn__pend 1 | ||
| 6368 | #define R_USB_IRQ_MASK_READ_DEV__sof__BITNR 2 | ||
| 6369 | #define R_USB_IRQ_MASK_READ_DEV__sof__WIDTH 1 | ||
| 6370 | #define R_USB_IRQ_MASK_READ_DEV__sof__no_pend 0 | ||
| 6371 | #define R_USB_IRQ_MASK_READ_DEV__sof__pend 1 | ||
| 6372 | #define R_USB_IRQ_MASK_READ_DEV__port_status__BITNR 1 | ||
| 6373 | #define R_USB_IRQ_MASK_READ_DEV__port_status__WIDTH 1 | ||
| 6374 | #define R_USB_IRQ_MASK_READ_DEV__port_status__no_pend 0 | ||
| 6375 | #define R_USB_IRQ_MASK_READ_DEV__port_status__pend 1 | ||
| 6376 | #define R_USB_IRQ_MASK_READ_DEV__ctl_status__BITNR 0 | ||
| 6377 | #define R_USB_IRQ_MASK_READ_DEV__ctl_status__WIDTH 1 | ||
| 6378 | #define R_USB_IRQ_MASK_READ_DEV__ctl_status__no_pend 0 | ||
| 6379 | #define R_USB_IRQ_MASK_READ_DEV__ctl_status__pend 1 | ||
| 6380 | |||
| 6381 | #define R_USB_IRQ_MASK_CLR_DEV (IO_TYPECAST_UWORD 0xb0000206) | ||
| 6382 | #define R_USB_IRQ_MASK_CLR_DEV__out_eot__BITNR 12 | ||
| 6383 | #define R_USB_IRQ_MASK_CLR_DEV__out_eot__WIDTH 1 | ||
| 6384 | #define R_USB_IRQ_MASK_CLR_DEV__out_eot__nop 0 | ||
| 6385 | #define R_USB_IRQ_MASK_CLR_DEV__out_eot__clr 1 | ||
| 6386 | #define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__BITNR 11 | ||
| 6387 | #define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__WIDTH 1 | ||
| 6388 | #define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__nop 0 | ||
| 6389 | #define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__clr 1 | ||
| 6390 | #define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__BITNR 10 | ||
| 6391 | #define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__WIDTH 1 | ||
| 6392 | #define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__nop 0 | ||
| 6393 | #define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__clr 1 | ||
| 6394 | #define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__BITNR 9 | ||
| 6395 | #define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__WIDTH 1 | ||
| 6396 | #define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__nop 0 | ||
| 6397 | #define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__clr 1 | ||
| 6398 | #define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__BITNR 8 | ||
| 6399 | #define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__WIDTH 1 | ||
| 6400 | #define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__nop 0 | ||
| 6401 | #define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__clr 1 | ||
| 6402 | #define R_USB_IRQ_MASK_CLR_DEV__epid_attn__BITNR 3 | ||
| 6403 | #define R_USB_IRQ_MASK_CLR_DEV__epid_attn__WIDTH 1 | ||
| 6404 | #define R_USB_IRQ_MASK_CLR_DEV__epid_attn__nop 0 | ||
| 6405 | #define R_USB_IRQ_MASK_CLR_DEV__epid_attn__clr 1 | ||
| 6406 | #define R_USB_IRQ_MASK_CLR_DEV__sof__BITNR 2 | ||
| 6407 | #define R_USB_IRQ_MASK_CLR_DEV__sof__WIDTH 1 | ||
| 6408 | #define R_USB_IRQ_MASK_CLR_DEV__sof__nop 0 | ||
| 6409 | #define R_USB_IRQ_MASK_CLR_DEV__sof__clr 1 | ||
| 6410 | #define R_USB_IRQ_MASK_CLR_DEV__port_status__BITNR 1 | ||
| 6411 | #define R_USB_IRQ_MASK_CLR_DEV__port_status__WIDTH 1 | ||
| 6412 | #define R_USB_IRQ_MASK_CLR_DEV__port_status__nop 0 | ||
| 6413 | #define R_USB_IRQ_MASK_CLR_DEV__port_status__clr 1 | ||
| 6414 | #define R_USB_IRQ_MASK_CLR_DEV__ctl_status__BITNR 0 | ||
| 6415 | #define R_USB_IRQ_MASK_CLR_DEV__ctl_status__WIDTH 1 | ||
| 6416 | #define R_USB_IRQ_MASK_CLR_DEV__ctl_status__nop 0 | ||
| 6417 | #define R_USB_IRQ_MASK_CLR_DEV__ctl_status__clr 1 | ||
| 6418 | |||
| 6419 | #define R_USB_IRQ_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000206) | ||
| 6420 | #define R_USB_IRQ_READ_DEV__out_eot__BITNR 12 | ||
| 6421 | #define R_USB_IRQ_READ_DEV__out_eot__WIDTH 1 | ||
| 6422 | #define R_USB_IRQ_READ_DEV__out_eot__no_pend 0 | ||
| 6423 | #define R_USB_IRQ_READ_DEV__out_eot__pend 1 | ||
| 6424 | #define R_USB_IRQ_READ_DEV__ep3_in_eot__BITNR 11 | ||
| 6425 | #define R_USB_IRQ_READ_DEV__ep3_in_eot__WIDTH 1 | ||
| 6426 | #define R_USB_IRQ_READ_DEV__ep3_in_eot__no_pend 0 | ||
| 6427 | #define R_USB_IRQ_READ_DEV__ep3_in_eot__pend 1 | ||
| 6428 | #define R_USB_IRQ_READ_DEV__ep2_in_eot__BITNR 10 | ||
| 6429 | #define R_USB_IRQ_READ_DEV__ep2_in_eot__WIDTH 1 | ||
| 6430 | #define R_USB_IRQ_READ_DEV__ep2_in_eot__no_pend 0 | ||
| 6431 | #define R_USB_IRQ_READ_DEV__ep2_in_eot__pend 1 | ||
| 6432 | #define R_USB_IRQ_READ_DEV__ep1_in_eot__BITNR 9 | ||
| 6433 | #define R_USB_IRQ_READ_DEV__ep1_in_eot__WIDTH 1 | ||
| 6434 | #define R_USB_IRQ_READ_DEV__ep1_in_eot__no_pend 0 | ||
| 6435 | #define R_USB_IRQ_READ_DEV__ep1_in_eot__pend 1 | ||
| 6436 | #define R_USB_IRQ_READ_DEV__ep0_in_eot__BITNR 8 | ||
| 6437 | #define R_USB_IRQ_READ_DEV__ep0_in_eot__WIDTH 1 | ||
| 6438 | #define R_USB_IRQ_READ_DEV__ep0_in_eot__no_pend 0 | ||
| 6439 | #define R_USB_IRQ_READ_DEV__ep0_in_eot__pend 1 | ||
| 6440 | #define R_USB_IRQ_READ_DEV__epid_attn__BITNR 3 | ||
| 6441 | #define R_USB_IRQ_READ_DEV__epid_attn__WIDTH 1 | ||
| 6442 | #define R_USB_IRQ_READ_DEV__epid_attn__no_pend 0 | ||
| 6443 | #define R_USB_IRQ_READ_DEV__epid_attn__pend 1 | ||
| 6444 | #define R_USB_IRQ_READ_DEV__sof__BITNR 2 | ||
| 6445 | #define R_USB_IRQ_READ_DEV__sof__WIDTH 1 | ||
| 6446 | #define R_USB_IRQ_READ_DEV__sof__no_pend 0 | ||
| 6447 | #define R_USB_IRQ_READ_DEV__sof__pend 1 | ||
| 6448 | #define R_USB_IRQ_READ_DEV__port_status__BITNR 1 | ||
| 6449 | #define R_USB_IRQ_READ_DEV__port_status__WIDTH 1 | ||
| 6450 | #define R_USB_IRQ_READ_DEV__port_status__no_pend 0 | ||
| 6451 | #define R_USB_IRQ_READ_DEV__port_status__pend 1 | ||
| 6452 | #define R_USB_IRQ_READ_DEV__ctl_status__BITNR 0 | ||
| 6453 | #define R_USB_IRQ_READ_DEV__ctl_status__WIDTH 1 | ||
| 6454 | #define R_USB_IRQ_READ_DEV__ctl_status__no_pend 0 | ||
| 6455 | #define R_USB_IRQ_READ_DEV__ctl_status__pend 1 | ||
| 6456 | |||
| 6457 | #define R_USB_FM_NUMBER (IO_TYPECAST_UDWORD 0xb000020c) | ||
| 6458 | #define R_USB_FM_NUMBER__value__BITNR 0 | ||
| 6459 | #define R_USB_FM_NUMBER__value__WIDTH 32 | ||
| 6460 | |||
| 6461 | #define R_USB_FM_INTERVAL (IO_TYPECAST_UWORD 0xb0000210) | ||
| 6462 | #define R_USB_FM_INTERVAL__fixed__BITNR 6 | ||
| 6463 | #define R_USB_FM_INTERVAL__fixed__WIDTH 8 | ||
| 6464 | #define R_USB_FM_INTERVAL__adj__BITNR 0 | ||
| 6465 | #define R_USB_FM_INTERVAL__adj__WIDTH 6 | ||
| 6466 | |||
| 6467 | #define R_USB_FM_REMAINING (IO_TYPECAST_RO_UWORD 0xb0000212) | ||
| 6468 | #define R_USB_FM_REMAINING__value__BITNR 0 | ||
| 6469 | #define R_USB_FM_REMAINING__value__WIDTH 14 | ||
| 6470 | |||
| 6471 | #define R_USB_FM_PSTART (IO_TYPECAST_UWORD 0xb0000214) | ||
| 6472 | #define R_USB_FM_PSTART__value__BITNR 0 | ||
| 6473 | #define R_USB_FM_PSTART__value__WIDTH 14 | ||
| 6474 | |||
| 6475 | #define R_USB_RH_STATUS (IO_TYPECAST_RO_BYTE 0xb0000203) | ||
| 6476 | #define R_USB_RH_STATUS__babble2__BITNR 7 | ||
| 6477 | #define R_USB_RH_STATUS__babble2__WIDTH 1 | ||
| 6478 | #define R_USB_RH_STATUS__babble2__no 0 | ||
| 6479 | #define R_USB_RH_STATUS__babble2__yes 1 | ||
| 6480 | #define R_USB_RH_STATUS__babble1__BITNR 6 | ||
| 6481 | #define R_USB_RH_STATUS__babble1__WIDTH 1 | ||
| 6482 | #define R_USB_RH_STATUS__babble1__no 0 | ||
| 6483 | #define R_USB_RH_STATUS__babble1__yes 1 | ||
| 6484 | #define R_USB_RH_STATUS__bus1__BITNR 4 | ||
| 6485 | #define R_USB_RH_STATUS__bus1__WIDTH 2 | ||
| 6486 | #define R_USB_RH_STATUS__bus1__SE0 0 | ||
| 6487 | #define R_USB_RH_STATUS__bus1__Diff0 1 | ||
| 6488 | #define R_USB_RH_STATUS__bus1__Diff1 2 | ||
| 6489 | #define R_USB_RH_STATUS__bus1__SE1 3 | ||
| 6490 | #define R_USB_RH_STATUS__bus2__BITNR 2 | ||
| 6491 | #define R_USB_RH_STATUS__bus2__WIDTH 2 | ||
| 6492 | #define R_USB_RH_STATUS__bus2__SE0 0 | ||
| 6493 | #define R_USB_RH_STATUS__bus2__Diff0 1 | ||
| 6494 | #define R_USB_RH_STATUS__bus2__Diff1 2 | ||
| 6495 | #define R_USB_RH_STATUS__bus2__SE1 3 | ||
| 6496 | #define R_USB_RH_STATUS__nports__BITNR 0 | ||
| 6497 | #define R_USB_RH_STATUS__nports__WIDTH 2 | ||
| 6498 | |||
| 6499 | #define R_USB_RH_PORT_STATUS_1 (IO_TYPECAST_RO_UWORD 0xb0000218) | ||
| 6500 | #define R_USB_RH_PORT_STATUS_1__speed__BITNR 9 | ||
| 6501 | #define R_USB_RH_PORT_STATUS_1__speed__WIDTH 1 | ||
| 6502 | #define R_USB_RH_PORT_STATUS_1__speed__full 0 | ||
| 6503 | #define R_USB_RH_PORT_STATUS_1__speed__low 1 | ||
| 6504 | #define R_USB_RH_PORT_STATUS_1__power__BITNR 8 | ||
| 6505 | #define R_USB_RH_PORT_STATUS_1__power__WIDTH 1 | ||
| 6506 | #define R_USB_RH_PORT_STATUS_1__reset__BITNR 4 | ||
| 6507 | #define R_USB_RH_PORT_STATUS_1__reset__WIDTH 1 | ||
| 6508 | #define R_USB_RH_PORT_STATUS_1__reset__no 0 | ||
| 6509 | #define R_USB_RH_PORT_STATUS_1__reset__yes 1 | ||
| 6510 | #define R_USB_RH_PORT_STATUS_1__overcurrent__BITNR 3 | ||
| 6511 | #define R_USB_RH_PORT_STATUS_1__overcurrent__WIDTH 1 | ||
| 6512 | #define R_USB_RH_PORT_STATUS_1__overcurrent__no 0 | ||
| 6513 | #define R_USB_RH_PORT_STATUS_1__overcurrent__yes 1 | ||
| 6514 | #define R_USB_RH_PORT_STATUS_1__suspended__BITNR 2 | ||
| 6515 | #define R_USB_RH_PORT_STATUS_1__suspended__WIDTH 1 | ||
| 6516 | #define R_USB_RH_PORT_STATUS_1__suspended__no 0 | ||
| 6517 | #define R_USB_RH_PORT_STATUS_1__suspended__yes 1 | ||
| 6518 | #define R_USB_RH_PORT_STATUS_1__enabled__BITNR 1 | ||
| 6519 | #define R_USB_RH_PORT_STATUS_1__enabled__WIDTH 1 | ||
| 6520 | #define R_USB_RH_PORT_STATUS_1__enabled__no 0 | ||
| 6521 | #define R_USB_RH_PORT_STATUS_1__enabled__yes 1 | ||
| 6522 | #define R_USB_RH_PORT_STATUS_1__connected__BITNR 0 | ||
| 6523 | #define R_USB_RH_PORT_STATUS_1__connected__WIDTH 1 | ||
| 6524 | #define R_USB_RH_PORT_STATUS_1__connected__no 0 | ||
| 6525 | #define R_USB_RH_PORT_STATUS_1__connected__yes 1 | ||
| 6526 | |||
| 6527 | #define R_USB_RH_PORT_STATUS_2 (IO_TYPECAST_RO_UWORD 0xb000021a) | ||
| 6528 | #define R_USB_RH_PORT_STATUS_2__speed__BITNR 9 | ||
| 6529 | #define R_USB_RH_PORT_STATUS_2__speed__WIDTH 1 | ||
| 6530 | #define R_USB_RH_PORT_STATUS_2__speed__full 0 | ||
| 6531 | #define R_USB_RH_PORT_STATUS_2__speed__low 1 | ||
| 6532 | #define R_USB_RH_PORT_STATUS_2__power__BITNR 8 | ||
| 6533 | #define R_USB_RH_PORT_STATUS_2__power__WIDTH 1 | ||
| 6534 | #define R_USB_RH_PORT_STATUS_2__reset__BITNR 4 | ||
| 6535 | #define R_USB_RH_PORT_STATUS_2__reset__WIDTH 1 | ||
| 6536 | #define R_USB_RH_PORT_STATUS_2__reset__no 0 | ||
| 6537 | #define R_USB_RH_PORT_STATUS_2__reset__yes 1 | ||
| 6538 | #define R_USB_RH_PORT_STATUS_2__overcurrent__BITNR 3 | ||
| 6539 | #define R_USB_RH_PORT_STATUS_2__overcurrent__WIDTH 1 | ||
| 6540 | #define R_USB_RH_PORT_STATUS_2__overcurrent__no 0 | ||
| 6541 | #define R_USB_RH_PORT_STATUS_2__overcurrent__yes 1 | ||
| 6542 | #define R_USB_RH_PORT_STATUS_2__suspended__BITNR 2 | ||
| 6543 | #define R_USB_RH_PORT_STATUS_2__suspended__WIDTH 1 | ||
| 6544 | #define R_USB_RH_PORT_STATUS_2__suspended__no 0 | ||
| 6545 | #define R_USB_RH_PORT_STATUS_2__suspended__yes 1 | ||
| 6546 | #define R_USB_RH_PORT_STATUS_2__enabled__BITNR 1 | ||
| 6547 | #define R_USB_RH_PORT_STATUS_2__enabled__WIDTH 1 | ||
| 6548 | #define R_USB_RH_PORT_STATUS_2__enabled__no 0 | ||
| 6549 | #define R_USB_RH_PORT_STATUS_2__enabled__yes 1 | ||
| 6550 | #define R_USB_RH_PORT_STATUS_2__connected__BITNR 0 | ||
| 6551 | #define R_USB_RH_PORT_STATUS_2__connected__WIDTH 1 | ||
| 6552 | #define R_USB_RH_PORT_STATUS_2__connected__no 0 | ||
| 6553 | #define R_USB_RH_PORT_STATUS_2__connected__yes 1 | ||
| 6554 | |||
| 6555 | #define R_USB_EPT_INDEX (IO_TYPECAST_BYTE 0xb0000208) | ||
| 6556 | #define R_USB_EPT_INDEX__value__BITNR 0 | ||
| 6557 | #define R_USB_EPT_INDEX__value__WIDTH 5 | ||
| 6558 | |||
| 6559 | #define R_USB_EPT_DATA (IO_TYPECAST_UDWORD 0xb000021c) | ||
| 6560 | #define R_USB_EPT_DATA__valid__BITNR 31 | ||
| 6561 | #define R_USB_EPT_DATA__valid__WIDTH 1 | ||
| 6562 | #define R_USB_EPT_DATA__valid__no 0 | ||
| 6563 | #define R_USB_EPT_DATA__valid__yes 1 | ||
| 6564 | #define R_USB_EPT_DATA__hold__BITNR 30 | ||
| 6565 | #define R_USB_EPT_DATA__hold__WIDTH 1 | ||
| 6566 | #define R_USB_EPT_DATA__hold__no 0 | ||
| 6567 | #define R_USB_EPT_DATA__hold__yes 1 | ||
| 6568 | #define R_USB_EPT_DATA__error_count_in__BITNR 28 | ||
| 6569 | #define R_USB_EPT_DATA__error_count_in__WIDTH 2 | ||
| 6570 | #define R_USB_EPT_DATA__t_in__BITNR 27 | ||
| 6571 | #define R_USB_EPT_DATA__t_in__WIDTH 1 | ||
| 6572 | #define R_USB_EPT_DATA__low_speed__BITNR 26 | ||
| 6573 | #define R_USB_EPT_DATA__low_speed__WIDTH 1 | ||
| 6574 | #define R_USB_EPT_DATA__low_speed__no 0 | ||
| 6575 | #define R_USB_EPT_DATA__low_speed__yes 1 | ||
| 6576 | #define R_USB_EPT_DATA__port__BITNR 24 | ||
| 6577 | #define R_USB_EPT_DATA__port__WIDTH 2 | ||
| 6578 | #define R_USB_EPT_DATA__port__any 0 | ||
| 6579 | #define R_USB_EPT_DATA__port__p1 1 | ||
| 6580 | #define R_USB_EPT_DATA__port__p2 2 | ||
| 6581 | #define R_USB_EPT_DATA__port__undef 3 | ||
| 6582 | #define R_USB_EPT_DATA__error_code__BITNR 22 | ||
| 6583 | #define R_USB_EPT_DATA__error_code__WIDTH 2 | ||
| 6584 | #define R_USB_EPT_DATA__error_code__no_error 0 | ||
| 6585 | #define R_USB_EPT_DATA__error_code__stall 1 | ||
| 6586 | #define R_USB_EPT_DATA__error_code__bus_error 2 | ||
| 6587 | #define R_USB_EPT_DATA__error_code__buffer_error 3 | ||
| 6588 | #define R_USB_EPT_DATA__t_out__BITNR 21 | ||
| 6589 | #define R_USB_EPT_DATA__t_out__WIDTH 1 | ||
| 6590 | #define R_USB_EPT_DATA__error_count_out__BITNR 19 | ||
| 6591 | #define R_USB_EPT_DATA__error_count_out__WIDTH 2 | ||
| 6592 | #define R_USB_EPT_DATA__max_len__BITNR 11 | ||
| 6593 | #define R_USB_EPT_DATA__max_len__WIDTH 7 | ||
| 6594 | #define R_USB_EPT_DATA__ep__BITNR 7 | ||
| 6595 | #define R_USB_EPT_DATA__ep__WIDTH 4 | ||
| 6596 | #define R_USB_EPT_DATA__dev__BITNR 0 | ||
| 6597 | #define R_USB_EPT_DATA__dev__WIDTH 7 | ||
| 6598 | |||
| 6599 | #define R_USB_EPT_DATA_ISO (IO_TYPECAST_UDWORD 0xb000021c) | ||
| 6600 | #define R_USB_EPT_DATA_ISO__valid__BITNR 31 | ||
| 6601 | #define R_USB_EPT_DATA_ISO__valid__WIDTH 1 | ||
| 6602 | #define R_USB_EPT_DATA_ISO__valid__no 0 | ||
| 6603 | #define R_USB_EPT_DATA_ISO__valid__yes 1 | ||
| 6604 | #define R_USB_EPT_DATA_ISO__port__BITNR 24 | ||
| 6605 | #define R_USB_EPT_DATA_ISO__port__WIDTH 2 | ||
| 6606 | #define R_USB_EPT_DATA_ISO__port__any 0 | ||
| 6607 | #define R_USB_EPT_DATA_ISO__port__p1 1 | ||
| 6608 | #define R_USB_EPT_DATA_ISO__port__p2 2 | ||
| 6609 | #define R_USB_EPT_DATA_ISO__port__undef 3 | ||
| 6610 | #define R_USB_EPT_DATA_ISO__error_code__BITNR 22 | ||
| 6611 | #define R_USB_EPT_DATA_ISO__error_code__WIDTH 2 | ||
| 6612 | #define R_USB_EPT_DATA_ISO__error_code__no_error 0 | ||
| 6613 | #define R_USB_EPT_DATA_ISO__error_code__stall 1 | ||
| 6614 | #define R_USB_EPT_DATA_ISO__error_code__bus_error 2 | ||
| 6615 | #define R_USB_EPT_DATA_ISO__error_code__TBD3 3 | ||
| 6616 | #define R_USB_EPT_DATA_ISO__max_len__BITNR 11 | ||
| 6617 | #define R_USB_EPT_DATA_ISO__max_len__WIDTH 10 | ||
| 6618 | #define R_USB_EPT_DATA_ISO__ep__BITNR 7 | ||
| 6619 | #define R_USB_EPT_DATA_ISO__ep__WIDTH 4 | ||
| 6620 | #define R_USB_EPT_DATA_ISO__dev__BITNR 0 | ||
| 6621 | #define R_USB_EPT_DATA_ISO__dev__WIDTH 7 | ||
| 6622 | |||
| 6623 | #define R_USB_EPT_DATA_DEV (IO_TYPECAST_UDWORD 0xb000021c) | ||
| 6624 | #define R_USB_EPT_DATA_DEV__valid__BITNR 31 | ||
| 6625 | #define R_USB_EPT_DATA_DEV__valid__WIDTH 1 | ||
| 6626 | #define R_USB_EPT_DATA_DEV__valid__no 0 | ||
| 6627 | #define R_USB_EPT_DATA_DEV__valid__yes 1 | ||
| 6628 | #define R_USB_EPT_DATA_DEV__hold__BITNR 30 | ||
| 6629 | #define R_USB_EPT_DATA_DEV__hold__WIDTH 1 | ||
| 6630 | #define R_USB_EPT_DATA_DEV__hold__no 0 | ||
| 6631 | #define R_USB_EPT_DATA_DEV__hold__yes 1 | ||
| 6632 | #define R_USB_EPT_DATA_DEV__stall__BITNR 29 | ||
| 6633 | #define R_USB_EPT_DATA_DEV__stall__WIDTH 1 | ||
| 6634 | #define R_USB_EPT_DATA_DEV__stall__no 0 | ||
| 6635 | #define R_USB_EPT_DATA_DEV__stall__yes 1 | ||
| 6636 | #define R_USB_EPT_DATA_DEV__iso_resp__BITNR 28 | ||
| 6637 | #define R_USB_EPT_DATA_DEV__iso_resp__WIDTH 1 | ||
| 6638 | #define R_USB_EPT_DATA_DEV__iso_resp__quiet 0 | ||
| 6639 | #define R_USB_EPT_DATA_DEV__iso_resp__yes 1 | ||
| 6640 | #define R_USB_EPT_DATA_DEV__ctrl__BITNR 27 | ||
| 6641 | #define R_USB_EPT_DATA_DEV__ctrl__WIDTH 1 | ||
| 6642 | #define R_USB_EPT_DATA_DEV__ctrl__no 0 | ||
| 6643 | #define R_USB_EPT_DATA_DEV__ctrl__yes 1 | ||
| 6644 | #define R_USB_EPT_DATA_DEV__iso__BITNR 26 | ||
| 6645 | #define R_USB_EPT_DATA_DEV__iso__WIDTH 1 | ||
| 6646 | #define R_USB_EPT_DATA_DEV__iso__no 0 | ||
| 6647 | #define R_USB_EPT_DATA_DEV__iso__yes 1 | ||
| 6648 | #define R_USB_EPT_DATA_DEV__port__BITNR 24 | ||
| 6649 | #define R_USB_EPT_DATA_DEV__port__WIDTH 2 | ||
| 6650 | #define R_USB_EPT_DATA_DEV__control_phase__BITNR 22 | ||
| 6651 | #define R_USB_EPT_DATA_DEV__control_phase__WIDTH 1 | ||
| 6652 | #define R_USB_EPT_DATA_DEV__t__BITNR 21 | ||
| 6653 | #define R_USB_EPT_DATA_DEV__t__WIDTH 1 | ||
| 6654 | #define R_USB_EPT_DATA_DEV__max_len__BITNR 11 | ||
| 6655 | #define R_USB_EPT_DATA_DEV__max_len__WIDTH 10 | ||
| 6656 | #define R_USB_EPT_DATA_DEV__ep__BITNR 7 | ||
| 6657 | #define R_USB_EPT_DATA_DEV__ep__WIDTH 4 | ||
| 6658 | #define R_USB_EPT_DATA_DEV__dev__BITNR 0 | ||
| 6659 | #define R_USB_EPT_DATA_DEV__dev__WIDTH 7 | ||
| 6660 | |||
| 6661 | #define R_USB_SNMP_TERROR (IO_TYPECAST_UDWORD 0xb0000220) | ||
| 6662 | #define R_USB_SNMP_TERROR__value__BITNR 0 | ||
| 6663 | #define R_USB_SNMP_TERROR__value__WIDTH 32 | ||
| 6664 | |||
| 6665 | #define R_USB_EPID_ATTN (IO_TYPECAST_RO_UDWORD 0xb0000224) | ||
| 6666 | #define R_USB_EPID_ATTN__value__BITNR 0 | ||
| 6667 | #define R_USB_EPID_ATTN__value__WIDTH 32 | ||
| 6668 | |||
| 6669 | #define R_USB_PORT1_DISABLE (IO_TYPECAST_BYTE 0xb000006a) | ||
| 6670 | #define R_USB_PORT1_DISABLE__disable__BITNR 0 | ||
| 6671 | #define R_USB_PORT1_DISABLE__disable__WIDTH 1 | ||
| 6672 | #define R_USB_PORT1_DISABLE__disable__yes 0 | ||
| 6673 | #define R_USB_PORT1_DISABLE__disable__no 1 | ||
| 6674 | |||
| 6675 | #define R_USB_PORT2_DISABLE (IO_TYPECAST_BYTE 0xb0000052) | ||
| 6676 | #define R_USB_PORT2_DISABLE__disable__BITNR 0 | ||
| 6677 | #define R_USB_PORT2_DISABLE__disable__WIDTH 1 | ||
| 6678 | #define R_USB_PORT2_DISABLE__disable__yes 0 | ||
| 6679 | #define R_USB_PORT2_DISABLE__disable__no 1 | ||
| 6680 | |||
| 6681 | /* | ||
| 6682 | !* MMU registers | ||
| 6683 | !*/ | ||
| 6684 | |||
| 6685 | #define R_MMU_CONFIG (IO_TYPECAST_UDWORD 0xb0000240) | ||
| 6686 | #define R_MMU_CONFIG__mmu_enable__BITNR 31 | ||
| 6687 | #define R_MMU_CONFIG__mmu_enable__WIDTH 1 | ||
| 6688 | #define R_MMU_CONFIG__mmu_enable__enable 1 | ||
| 6689 | #define R_MMU_CONFIG__mmu_enable__disable 0 | ||
| 6690 | #define R_MMU_CONFIG__inv_excp__BITNR 18 | ||
| 6691 | #define R_MMU_CONFIG__inv_excp__WIDTH 1 | ||
| 6692 | #define R_MMU_CONFIG__inv_excp__enable 1 | ||
| 6693 | #define R_MMU_CONFIG__inv_excp__disable 0 | ||
| 6694 | #define R_MMU_CONFIG__acc_excp__BITNR 17 | ||
| 6695 | #define R_MMU_CONFIG__acc_excp__WIDTH 1 | ||
| 6696 | #define R_MMU_CONFIG__acc_excp__enable 1 | ||
| 6697 | #define R_MMU_CONFIG__acc_excp__disable 0 | ||
| 6698 | #define R_MMU_CONFIG__we_excp__BITNR 16 | ||
| 6699 | #define R_MMU_CONFIG__we_excp__WIDTH 1 | ||
| 6700 | #define R_MMU_CONFIG__we_excp__enable 1 | ||
| 6701 | #define R_MMU_CONFIG__we_excp__disable 0 | ||
| 6702 | #define R_MMU_CONFIG__seg_f__BITNR 15 | ||
| 6703 | #define R_MMU_CONFIG__seg_f__WIDTH 1 | ||
| 6704 | #define R_MMU_CONFIG__seg_f__seg 1 | ||
| 6705 | #define R_MMU_CONFIG__seg_f__page 0 | ||
| 6706 | #define R_MMU_CONFIG__seg_e__BITNR 14 | ||
| 6707 | #define R_MMU_CONFIG__seg_e__WIDTH 1 | ||
| 6708 | #define R_MMU_CONFIG__seg_e__seg 1 | ||
| 6709 | #define R_MMU_CONFIG__seg_e__page 0 | ||
| 6710 | #define R_MMU_CONFIG__seg_d__BITNR 13 | ||
| 6711 | #define R_MMU_CONFIG__seg_d__WIDTH 1 | ||
| 6712 | #define R_MMU_CONFIG__seg_d__seg 1 | ||
| 6713 | #define R_MMU_CONFIG__seg_d__page 0 | ||
| 6714 | #define R_MMU_CONFIG__seg_c__BITNR 12 | ||
| 6715 | #define R_MMU_CONFIG__seg_c__WIDTH 1 | ||
| 6716 | #define R_MMU_CONFIG__seg_c__seg 1 | ||
| 6717 | #define R_MMU_CONFIG__seg_c__page 0 | ||
| 6718 | #define R_MMU_CONFIG__seg_b__BITNR 11 | ||
| 6719 | #define R_MMU_CONFIG__seg_b__WIDTH 1 | ||
| 6720 | #define R_MMU_CONFIG__seg_b__seg 1 | ||
| 6721 | #define R_MMU_CONFIG__seg_b__page 0 | ||
| 6722 | #define R_MMU_CONFIG__seg_a__BITNR 10 | ||
| 6723 | #define R_MMU_CONFIG__seg_a__WIDTH 1 | ||
| 6724 | #define R_MMU_CONFIG__seg_a__seg 1 | ||
| 6725 | #define R_MMU_CONFIG__seg_a__page 0 | ||
| 6726 | #define R_MMU_CONFIG__seg_9__BITNR 9 | ||
| 6727 | #define R_MMU_CONFIG__seg_9__WIDTH 1 | ||
| 6728 | #define R_MMU_CONFIG__seg_9__seg 1 | ||
| 6729 | #define R_MMU_CONFIG__seg_9__page 0 | ||
| 6730 | #define R_MMU_CONFIG__seg_8__BITNR 8 | ||
| 6731 | #define R_MMU_CONFIG__seg_8__WIDTH 1 | ||
| 6732 | #define R_MMU_CONFIG__seg_8__seg 1 | ||
| 6733 | #define R_MMU_CONFIG__seg_8__page 0 | ||
| 6734 | #define R_MMU_CONFIG__seg_7__BITNR 7 | ||
| 6735 | #define R_MMU_CONFIG__seg_7__WIDTH 1 | ||
| 6736 | #define R_MMU_CONFIG__seg_7__seg 1 | ||
| 6737 | #define R_MMU_CONFIG__seg_7__page 0 | ||
| 6738 | #define R_MMU_CONFIG__seg_6__BITNR 6 | ||
| 6739 | #define R_MMU_CONFIG__seg_6__WIDTH 1 | ||
| 6740 | #define R_MMU_CONFIG__seg_6__seg 1 | ||
| 6741 | #define R_MMU_CONFIG__seg_6__page 0 | ||
| 6742 | #define R_MMU_CONFIG__seg_5__BITNR 5 | ||
| 6743 | #define R_MMU_CONFIG__seg_5__WIDTH 1 | ||
| 6744 | #define R_MMU_CONFIG__seg_5__seg 1 | ||
| 6745 | #define R_MMU_CONFIG__seg_5__page 0 | ||
| 6746 | #define R_MMU_CONFIG__seg_4__BITNR 4 | ||
| 6747 | #define R_MMU_CONFIG__seg_4__WIDTH 1 | ||
| 6748 | #define R_MMU_CONFIG__seg_4__seg 1 | ||
| 6749 | #define R_MMU_CONFIG__seg_4__page 0 | ||
| 6750 | #define R_MMU_CONFIG__seg_3__BITNR 3 | ||
| 6751 | #define R_MMU_CONFIG__seg_3__WIDTH 1 | ||
| 6752 | #define R_MMU_CONFIG__seg_3__seg 1 | ||
| 6753 | #define R_MMU_CONFIG__seg_3__page 0 | ||
| 6754 | #define R_MMU_CONFIG__seg_2__BITNR 2 | ||
| 6755 | #define R_MMU_CONFIG__seg_2__WIDTH 1 | ||
| 6756 | #define R_MMU_CONFIG__seg_2__seg 1 | ||
| 6757 | #define R_MMU_CONFIG__seg_2__page 0 | ||
| 6758 | #define R_MMU_CONFIG__seg_1__BITNR 1 | ||
| 6759 | #define R_MMU_CONFIG__seg_1__WIDTH 1 | ||
| 6760 | #define R_MMU_CONFIG__seg_1__seg 1 | ||
| 6761 | #define R_MMU_CONFIG__seg_1__page 0 | ||
| 6762 | #define R_MMU_CONFIG__seg_0__BITNR 0 | ||
| 6763 | #define R_MMU_CONFIG__seg_0__WIDTH 1 | ||
| 6764 | #define R_MMU_CONFIG__seg_0__seg 1 | ||
| 6765 | #define R_MMU_CONFIG__seg_0__page 0 | ||
| 6766 | |||
| 6767 | #define R_MMU_KSEG (IO_TYPECAST_UWORD 0xb0000240) | ||
| 6768 | #define R_MMU_KSEG__seg_f__BITNR 15 | ||
| 6769 | #define R_MMU_KSEG__seg_f__WIDTH 1 | ||
| 6770 | #define R_MMU_KSEG__seg_f__seg 1 | ||
| 6771 | #define R_MMU_KSEG__seg_f__page 0 | ||
| 6772 | #define R_MMU_KSEG__seg_e__BITNR 14 | ||
| 6773 | #define R_MMU_KSEG__seg_e__WIDTH 1 | ||
| 6774 | #define R_MMU_KSEG__seg_e__seg 1 | ||
| 6775 | #define R_MMU_KSEG__seg_e__page 0 | ||
| 6776 | #define R_MMU_KSEG__seg_d__BITNR 13 | ||
| 6777 | #define R_MMU_KSEG__seg_d__WIDTH 1 | ||
| 6778 | #define R_MMU_KSEG__seg_d__seg 1 | ||
| 6779 | #define R_MMU_KSEG__seg_d__page 0 | ||
| 6780 | #define R_MMU_KSEG__seg_c__BITNR 12 | ||
| 6781 | #define R_MMU_KSEG__seg_c__WIDTH 1 | ||
| 6782 | #define R_MMU_KSEG__seg_c__seg 1 | ||
| 6783 | #define R_MMU_KSEG__seg_c__page 0 | ||
| 6784 | #define R_MMU_KSEG__seg_b__BITNR 11 | ||
| 6785 | #define R_MMU_KSEG__seg_b__WIDTH 1 | ||
| 6786 | #define R_MMU_KSEG__seg_b__seg 1 | ||
| 6787 | #define R_MMU_KSEG__seg_b__page 0 | ||
| 6788 | #define R_MMU_KSEG__seg_a__BITNR 10 | ||
| 6789 | #define R_MMU_KSEG__seg_a__WIDTH 1 | ||
| 6790 | #define R_MMU_KSEG__seg_a__seg 1 | ||
| 6791 | #define R_MMU_KSEG__seg_a__page 0 | ||
| 6792 | #define R_MMU_KSEG__seg_9__BITNR 9 | ||
| 6793 | #define R_MMU_KSEG__seg_9__WIDTH 1 | ||
| 6794 | #define R_MMU_KSEG__seg_9__seg 1 | ||
| 6795 | #define R_MMU_KSEG__seg_9__page 0 | ||
| 6796 | #define R_MMU_KSEG__seg_8__BITNR 8 | ||
| 6797 | #define R_MMU_KSEG__seg_8__WIDTH 1 | ||
| 6798 | #define R_MMU_KSEG__seg_8__seg 1 | ||
| 6799 | #define R_MMU_KSEG__seg_8__page 0 | ||
| 6800 | #define R_MMU_KSEG__seg_7__BITNR 7 | ||
| 6801 | #define R_MMU_KSEG__seg_7__WIDTH 1 | ||
| 6802 | #define R_MMU_KSEG__seg_7__seg 1 | ||
| 6803 | #define R_MMU_KSEG__seg_7__page 0 | ||
| 6804 | #define R_MMU_KSEG__seg_6__BITNR 6 | ||
| 6805 | #define R_MMU_KSEG__seg_6__WIDTH 1 | ||
| 6806 | #define R_MMU_KSEG__seg_6__seg 1 | ||
| 6807 | #define R_MMU_KSEG__seg_6__page 0 | ||
| 6808 | #define R_MMU_KSEG__seg_5__BITNR 5 | ||
| 6809 | #define R_MMU_KSEG__seg_5__WIDTH 1 | ||
| 6810 | #define R_MMU_KSEG__seg_5__seg 1 | ||
| 6811 | #define R_MMU_KSEG__seg_5__page 0 | ||
| 6812 | #define R_MMU_KSEG__seg_4__BITNR 4 | ||
| 6813 | #define R_MMU_KSEG__seg_4__WIDTH 1 | ||
| 6814 | #define R_MMU_KSEG__seg_4__seg 1 | ||
| 6815 | #define R_MMU_KSEG__seg_4__page 0 | ||
| 6816 | #define R_MMU_KSEG__seg_3__BITNR 3 | ||
| 6817 | #define R_MMU_KSEG__seg_3__WIDTH 1 | ||
| 6818 | #define R_MMU_KSEG__seg_3__seg 1 | ||
| 6819 | #define R_MMU_KSEG__seg_3__page 0 | ||
| 6820 | #define R_MMU_KSEG__seg_2__BITNR 2 | ||
| 6821 | #define R_MMU_KSEG__seg_2__WIDTH 1 | ||
| 6822 | #define R_MMU_KSEG__seg_2__seg 1 | ||
| 6823 | #define R_MMU_KSEG__seg_2__page 0 | ||
| 6824 | #define R_MMU_KSEG__seg_1__BITNR 1 | ||
| 6825 | #define R_MMU_KSEG__seg_1__WIDTH 1 | ||
| 6826 | #define R_MMU_KSEG__seg_1__seg 1 | ||
| 6827 | #define R_MMU_KSEG__seg_1__page 0 | ||
| 6828 | #define R_MMU_KSEG__seg_0__BITNR 0 | ||
| 6829 | #define R_MMU_KSEG__seg_0__WIDTH 1 | ||
| 6830 | #define R_MMU_KSEG__seg_0__seg 1 | ||
| 6831 | #define R_MMU_KSEG__seg_0__page 0 | ||
| 6832 | |||
| 6833 | #define R_MMU_CTRL (IO_TYPECAST_BYTE 0xb0000242) | ||
| 6834 | #define R_MMU_CTRL__inv_excp__BITNR 2 | ||
| 6835 | #define R_MMU_CTRL__inv_excp__WIDTH 1 | ||
| 6836 | #define R_MMU_CTRL__inv_excp__enable 1 | ||
| 6837 | #define R_MMU_CTRL__inv_excp__disable 0 | ||
| 6838 | #define R_MMU_CTRL__acc_excp__BITNR 1 | ||
| 6839 | #define R_MMU_CTRL__acc_excp__WIDTH 1 | ||
| 6840 | #define R_MMU_CTRL__acc_excp__enable 1 | ||
| 6841 | #define R_MMU_CTRL__acc_excp__disable 0 | ||
| 6842 | #define R_MMU_CTRL__we_excp__BITNR 0 | ||
| 6843 | #define R_MMU_CTRL__we_excp__WIDTH 1 | ||
| 6844 | #define R_MMU_CTRL__we_excp__enable 1 | ||
| 6845 | #define R_MMU_CTRL__we_excp__disable 0 | ||
| 6846 | |||
| 6847 | #define R_MMU_ENABLE (IO_TYPECAST_BYTE 0xb0000243) | ||
| 6848 | #define R_MMU_ENABLE__mmu_enable__BITNR 7 | ||
| 6849 | #define R_MMU_ENABLE__mmu_enable__WIDTH 1 | ||
| 6850 | #define R_MMU_ENABLE__mmu_enable__enable 1 | ||
| 6851 | #define R_MMU_ENABLE__mmu_enable__disable 0 | ||
| 6852 | |||
| 6853 | #define R_MMU_KBASE_LO (IO_TYPECAST_UDWORD 0xb0000244) | ||
| 6854 | #define R_MMU_KBASE_LO__base_7__BITNR 28 | ||
| 6855 | #define R_MMU_KBASE_LO__base_7__WIDTH 4 | ||
| 6856 | #define R_MMU_KBASE_LO__base_6__BITNR 24 | ||
| 6857 | #define R_MMU_KBASE_LO__base_6__WIDTH 4 | ||
| 6858 | #define R_MMU_KBASE_LO__base_5__BITNR 20 | ||
| 6859 | #define R_MMU_KBASE_LO__base_5__WIDTH 4 | ||
| 6860 | #define R_MMU_KBASE_LO__base_4__BITNR 16 | ||
| 6861 | #define R_MMU_KBASE_LO__base_4__WIDTH 4 | ||
| 6862 | #define R_MMU_KBASE_LO__base_3__BITNR 12 | ||
| 6863 | #define R_MMU_KBASE_LO__base_3__WIDTH 4 | ||
| 6864 | #define R_MMU_KBASE_LO__base_2__BITNR 8 | ||
| 6865 | #define R_MMU_KBASE_LO__base_2__WIDTH 4 | ||
| 6866 | #define R_MMU_KBASE_LO__base_1__BITNR 4 | ||
| 6867 | #define R_MMU_KBASE_LO__base_1__WIDTH 4 | ||
| 6868 | #define R_MMU_KBASE_LO__base_0__BITNR 0 | ||
| 6869 | #define R_MMU_KBASE_LO__base_0__WIDTH 4 | ||
| 6870 | |||
| 6871 | #define R_MMU_KBASE_HI (IO_TYPECAST_UDWORD 0xb0000248) | ||
| 6872 | #define R_MMU_KBASE_HI__base_f__BITNR 28 | ||
| 6873 | #define R_MMU_KBASE_HI__base_f__WIDTH 4 | ||
| 6874 | #define R_MMU_KBASE_HI__base_e__BITNR 24 | ||
| 6875 | #define R_MMU_KBASE_HI__base_e__WIDTH 4 | ||
| 6876 | #define R_MMU_KBASE_HI__base_d__BITNR 20 | ||
| 6877 | #define R_MMU_KBASE_HI__base_d__WIDTH 4 | ||
| 6878 | #define R_MMU_KBASE_HI__base_c__BITNR 16 | ||
| 6879 | #define R_MMU_KBASE_HI__base_c__WIDTH 4 | ||
| 6880 | #define R_MMU_KBASE_HI__base_b__BITNR 12 | ||
| 6881 | #define R_MMU_KBASE_HI__base_b__WIDTH 4 | ||
| 6882 | #define R_MMU_KBASE_HI__base_a__BITNR 8 | ||
| 6883 | #define R_MMU_KBASE_HI__base_a__WIDTH 4 | ||
| 6884 | #define R_MMU_KBASE_HI__base_9__BITNR 4 | ||
| 6885 | #define R_MMU_KBASE_HI__base_9__WIDTH 4 | ||
| 6886 | #define R_MMU_KBASE_HI__base_8__BITNR 0 | ||
| 6887 | #define R_MMU_KBASE_HI__base_8__WIDTH 4 | ||
| 6888 | |||
| 6889 | #define R_MMU_CONTEXT (IO_TYPECAST_BYTE 0xb000024c) | ||
| 6890 | #define R_MMU_CONTEXT__page_id__BITNR 0 | ||
| 6891 | #define R_MMU_CONTEXT__page_id__WIDTH 6 | ||
| 6892 | |||
| 6893 | #define R_MMU_CAUSE (IO_TYPECAST_RO_UDWORD 0xb0000250) | ||
| 6894 | #define R_MMU_CAUSE__vpn__BITNR 13 | ||
| 6895 | #define R_MMU_CAUSE__vpn__WIDTH 19 | ||
| 6896 | #define R_MMU_CAUSE__miss_excp__BITNR 12 | ||
| 6897 | #define R_MMU_CAUSE__miss_excp__WIDTH 1 | ||
| 6898 | #define R_MMU_CAUSE__miss_excp__yes 1 | ||
| 6899 | #define R_MMU_CAUSE__miss_excp__no 0 | ||
| 6900 | #define R_MMU_CAUSE__inv_excp__BITNR 11 | ||
| 6901 | #define R_MMU_CAUSE__inv_excp__WIDTH 1 | ||
| 6902 | #define R_MMU_CAUSE__inv_excp__yes 1 | ||
| 6903 | #define R_MMU_CAUSE__inv_excp__no 0 | ||
| 6904 | #define R_MMU_CAUSE__acc_excp__BITNR 10 | ||
| 6905 | #define R_MMU_CAUSE__acc_excp__WIDTH 1 | ||
| 6906 | #define R_MMU_CAUSE__acc_excp__yes 1 | ||
| 6907 | #define R_MMU_CAUSE__acc_excp__no 0 | ||
| 6908 | #define R_MMU_CAUSE__we_excp__BITNR 9 | ||
| 6909 | #define R_MMU_CAUSE__we_excp__WIDTH 1 | ||
| 6910 | #define R_MMU_CAUSE__we_excp__yes 1 | ||
| 6911 | #define R_MMU_CAUSE__we_excp__no 0 | ||
| 6912 | #define R_MMU_CAUSE__wr_rd__BITNR 8 | ||
| 6913 | #define R_MMU_CAUSE__wr_rd__WIDTH 1 | ||
| 6914 | #define R_MMU_CAUSE__wr_rd__write 1 | ||
| 6915 | #define R_MMU_CAUSE__wr_rd__read 0 | ||
| 6916 | #define R_MMU_CAUSE__page_id__BITNR 0 | ||
| 6917 | #define R_MMU_CAUSE__page_id__WIDTH 6 | ||
| 6918 | |||
| 6919 | #define R_TLB_SELECT (IO_TYPECAST_BYTE 0xb0000254) | ||
| 6920 | #define R_TLB_SELECT__index__BITNR 0 | ||
| 6921 | #define R_TLB_SELECT__index__WIDTH 6 | ||
| 6922 | |||
| 6923 | #define R_TLB_LO (IO_TYPECAST_UDWORD 0xb0000258) | ||
| 6924 | #define R_TLB_LO__pfn__BITNR 13 | ||
| 6925 | #define R_TLB_LO__pfn__WIDTH 19 | ||
| 6926 | #define R_TLB_LO__global__BITNR 3 | ||
| 6927 | #define R_TLB_LO__global__WIDTH 1 | ||
| 6928 | #define R_TLB_LO__global__yes 1 | ||
| 6929 | #define R_TLB_LO__global__no 0 | ||
| 6930 | #define R_TLB_LO__valid__BITNR 2 | ||
| 6931 | #define R_TLB_LO__valid__WIDTH 1 | ||
| 6932 | #define R_TLB_LO__valid__yes 1 | ||
| 6933 | #define R_TLB_LO__valid__no 0 | ||
| 6934 | #define R_TLB_LO__kernel__BITNR 1 | ||
| 6935 | #define R_TLB_LO__kernel__WIDTH 1 | ||
| 6936 | #define R_TLB_LO__kernel__yes 1 | ||
| 6937 | #define R_TLB_LO__kernel__no 0 | ||
| 6938 | #define R_TLB_LO__we__BITNR 0 | ||
| 6939 | #define R_TLB_LO__we__WIDTH 1 | ||
| 6940 | #define R_TLB_LO__we__yes 1 | ||
| 6941 | #define R_TLB_LO__we__no 0 | ||
| 6942 | |||
| 6943 | #define R_TLB_HI (IO_TYPECAST_UDWORD 0xb000025c) | ||
| 6944 | #define R_TLB_HI__vpn__BITNR 13 | ||
| 6945 | #define R_TLB_HI__vpn__WIDTH 19 | ||
| 6946 | #define R_TLB_HI__page_id__BITNR 0 | ||
| 6947 | #define R_TLB_HI__page_id__WIDTH 6 | ||
| 6948 | |||
| 6949 | /* | ||
| 6950 | !* Syncrounous serial port registers | ||
| 6951 | !*/ | ||
| 6952 | |||
| 6953 | #define R_SYNC_SERIAL1_REC_DATA (IO_TYPECAST_RO_UDWORD 0xb000006c) | ||
| 6954 | #define R_SYNC_SERIAL1_REC_DATA__data_in__BITNR 0 | ||
| 6955 | #define R_SYNC_SERIAL1_REC_DATA__data_in__WIDTH 32 | ||
| 6956 | |||
| 6957 | #define R_SYNC_SERIAL1_REC_WORD (IO_TYPECAST_RO_UWORD 0xb000006c) | ||
| 6958 | #define R_SYNC_SERIAL1_REC_WORD__data_in__BITNR 0 | ||
| 6959 | #define R_SYNC_SERIAL1_REC_WORD__data_in__WIDTH 16 | ||
| 6960 | |||
| 6961 | #define R_SYNC_SERIAL1_REC_BYTE (IO_TYPECAST_RO_BYTE 0xb000006c) | ||
| 6962 | #define R_SYNC_SERIAL1_REC_BYTE__data_in__BITNR 0 | ||
| 6963 | #define R_SYNC_SERIAL1_REC_BYTE__data_in__WIDTH 8 | ||
| 6964 | |||
| 6965 | #define R_SYNC_SERIAL1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000068) | ||
| 6966 | #define R_SYNC_SERIAL1_STATUS__rec_status__BITNR 15 | ||
| 6967 | #define R_SYNC_SERIAL1_STATUS__rec_status__WIDTH 1 | ||
| 6968 | #define R_SYNC_SERIAL1_STATUS__rec_status__running 0 | ||
| 6969 | #define R_SYNC_SERIAL1_STATUS__rec_status__idle 1 | ||
| 6970 | #define R_SYNC_SERIAL1_STATUS__tr_empty__BITNR 14 | ||
| 6971 | #define R_SYNC_SERIAL1_STATUS__tr_empty__WIDTH 1 | ||
| 6972 | #define R_SYNC_SERIAL1_STATUS__tr_empty__empty 1 | ||
| 6973 | #define R_SYNC_SERIAL1_STATUS__tr_empty__not_empty 0 | ||
| 6974 | #define R_SYNC_SERIAL1_STATUS__tr_ready__BITNR 13 | ||
| 6975 | #define R_SYNC_SERIAL1_STATUS__tr_ready__WIDTH 1 | ||
| 6976 | #define R_SYNC_SERIAL1_STATUS__tr_ready__full 0 | ||
| 6977 | #define R_SYNC_SERIAL1_STATUS__tr_ready__ready 1 | ||
| 6978 | #define R_SYNC_SERIAL1_STATUS__pin_1__BITNR 12 | ||
| 6979 | #define R_SYNC_SERIAL1_STATUS__pin_1__WIDTH 1 | ||
| 6980 | #define R_SYNC_SERIAL1_STATUS__pin_1__low 0 | ||
| 6981 | #define R_SYNC_SERIAL1_STATUS__pin_1__high 1 | ||
| 6982 | #define R_SYNC_SERIAL1_STATUS__pin_0__BITNR 11 | ||
| 6983 | #define R_SYNC_SERIAL1_STATUS__pin_0__WIDTH 1 | ||
| 6984 | #define R_SYNC_SERIAL1_STATUS__pin_0__low 0 | ||
| 6985 | #define R_SYNC_SERIAL1_STATUS__pin_0__high 1 | ||
| 6986 | #define R_SYNC_SERIAL1_STATUS__underflow__BITNR 10 | ||
| 6987 | #define R_SYNC_SERIAL1_STATUS__underflow__WIDTH 1 | ||
| 6988 | #define R_SYNC_SERIAL1_STATUS__underflow__no 0 | ||
| 6989 | #define R_SYNC_SERIAL1_STATUS__underflow__yes 1 | ||
| 6990 | #define R_SYNC_SERIAL1_STATUS__overrun__BITNR 9 | ||
| 6991 | #define R_SYNC_SERIAL1_STATUS__overrun__WIDTH 1 | ||
| 6992 | #define R_SYNC_SERIAL1_STATUS__overrun__no 0 | ||
| 6993 | #define R_SYNC_SERIAL1_STATUS__overrun__yes 1 | ||
| 6994 | #define R_SYNC_SERIAL1_STATUS__data_avail__BITNR 8 | ||
| 6995 | #define R_SYNC_SERIAL1_STATUS__data_avail__WIDTH 1 | ||
| 6996 | #define R_SYNC_SERIAL1_STATUS__data_avail__no 0 | ||
| 6997 | #define R_SYNC_SERIAL1_STATUS__data_avail__yes 1 | ||
| 6998 | #define R_SYNC_SERIAL1_STATUS__data__BITNR 0 | ||
| 6999 | #define R_SYNC_SERIAL1_STATUS__data__WIDTH 8 | ||
| 7000 | |||
| 7001 | #define R_SYNC_SERIAL1_TR_DATA (IO_TYPECAST_UDWORD 0xb000006c) | ||
| 7002 | #define R_SYNC_SERIAL1_TR_DATA__data_out__BITNR 0 | ||
| 7003 | #define R_SYNC_SERIAL1_TR_DATA__data_out__WIDTH 32 | ||
| 7004 | |||
| 7005 | #define R_SYNC_SERIAL1_TR_WORD (IO_TYPECAST_UWORD 0xb000006c) | ||
| 7006 | #define R_SYNC_SERIAL1_TR_WORD__data_out__BITNR 0 | ||
| 7007 | #define R_SYNC_SERIAL1_TR_WORD__data_out__WIDTH 16 | ||
| 7008 | |||
| 7009 | #define R_SYNC_SERIAL1_TR_BYTE (IO_TYPECAST_BYTE 0xb000006c) | ||
| 7010 | #define R_SYNC_SERIAL1_TR_BYTE__data_out__BITNR 0 | ||
| 7011 | #define R_SYNC_SERIAL1_TR_BYTE__data_out__WIDTH 8 | ||
| 7012 | |||
| 7013 | #define R_SYNC_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068) | ||
| 7014 | #define R_SYNC_SERIAL1_CTRL__tr_baud__BITNR 28 | ||
| 7015 | #define R_SYNC_SERIAL1_CTRL__tr_baud__WIDTH 4 | ||
| 7016 | #define R_SYNC_SERIAL1_CTRL__tr_baud__c150Hz 0 | ||
| 7017 | #define R_SYNC_SERIAL1_CTRL__tr_baud__c300Hz 1 | ||
| 7018 | #define R_SYNC_SERIAL1_CTRL__tr_baud__c600Hz 2 | ||
| 7019 | #define R_SYNC_SERIAL1_CTRL__tr_baud__c1200Hz 3 | ||
| 7020 | #define R_SYNC_SERIAL1_CTRL__tr_baud__c2400Hz 4 | ||
| 7021 | #define R_SYNC_SERIAL1_CTRL__tr_baud__c4800Hz 5 | ||
| 7022 | #define R_SYNC_SERIAL1_CTRL__tr_baud__c9600Hz 6 | ||
| 7023 | #define R_SYNC_SERIAL1_CTRL__tr_baud__c19k2Hz 7 | ||
| 7024 | #define R_SYNC_SERIAL1_CTRL__tr_baud__c28k8Hz 8 | ||
| 7025 | #define R_SYNC_SERIAL1_CTRL__tr_baud__c57k6Hz 9 | ||
| 7026 | #define R_SYNC_SERIAL1_CTRL__tr_baud__c115k2Hz 10 | ||
| 7027 | #define R_SYNC_SERIAL1_CTRL__tr_baud__c230k4Hz 11 | ||
| 7028 | #define R_SYNC_SERIAL1_CTRL__tr_baud__c460k8Hz 12 | ||
| 7029 | #define R_SYNC_SERIAL1_CTRL__tr_baud__c921k6Hz 13 | ||
| 7030 | #define R_SYNC_SERIAL1_CTRL__tr_baud__c3125kHz 14 | ||
| 7031 | #define R_SYNC_SERIAL1_CTRL__tr_baud__reserved 15 | ||
| 7032 | #define R_SYNC_SERIAL1_CTRL__dma_enable__BITNR 27 | ||
| 7033 | #define R_SYNC_SERIAL1_CTRL__dma_enable__WIDTH 1 | ||
| 7034 | #define R_SYNC_SERIAL1_CTRL__dma_enable__on 1 | ||
| 7035 | #define R_SYNC_SERIAL1_CTRL__dma_enable__off 0 | ||
| 7036 | #define R_SYNC_SERIAL1_CTRL__mode__BITNR 24 | ||
| 7037 | #define R_SYNC_SERIAL1_CTRL__mode__WIDTH 3 | ||
| 7038 | #define R_SYNC_SERIAL1_CTRL__mode__master_output 0 | ||
| 7039 | #define R_SYNC_SERIAL1_CTRL__mode__slave_output 1 | ||
| 7040 | #define R_SYNC_SERIAL1_CTRL__mode__master_input 2 | ||
| 7041 | #define R_SYNC_SERIAL1_CTRL__mode__slave_input 3 | ||
| 7042 | #define R_SYNC_SERIAL1_CTRL__mode__master_bidir 4 | ||
| 7043 | #define R_SYNC_SERIAL1_CTRL__mode__slave_bidir 5 | ||
| 7044 | #define R_SYNC_SERIAL1_CTRL__error__BITNR 23 | ||
| 7045 | #define R_SYNC_SERIAL1_CTRL__error__WIDTH 1 | ||
| 7046 | #define R_SYNC_SERIAL1_CTRL__error__normal 0 | ||
| 7047 | #define R_SYNC_SERIAL1_CTRL__error__ignore 1 | ||
| 7048 | #define R_SYNC_SERIAL1_CTRL__rec_enable__BITNR 22 | ||
| 7049 | #define R_SYNC_SERIAL1_CTRL__rec_enable__WIDTH 1 | ||
| 7050 | #define R_SYNC_SERIAL1_CTRL__rec_enable__disable 0 | ||
| 7051 | #define R_SYNC_SERIAL1_CTRL__rec_enable__enable 1 | ||
| 7052 | #define R_SYNC_SERIAL1_CTRL__f_synctype__BITNR 21 | ||
| 7053 | #define R_SYNC_SERIAL1_CTRL__f_synctype__WIDTH 1 | ||
| 7054 | #define R_SYNC_SERIAL1_CTRL__f_synctype__normal 0 | ||
| 7055 | #define R_SYNC_SERIAL1_CTRL__f_synctype__early 1 | ||
| 7056 | #define R_SYNC_SERIAL1_CTRL__f_syncsize__BITNR 19 | ||
| 7057 | #define R_SYNC_SERIAL1_CTRL__f_syncsize__WIDTH 2 | ||
| 7058 | #define R_SYNC_SERIAL1_CTRL__f_syncsize__bit 0 | ||
| 7059 | #define R_SYNC_SERIAL1_CTRL__f_syncsize__word 1 | ||
| 7060 | #define R_SYNC_SERIAL1_CTRL__f_syncsize__extended 2 | ||
| 7061 | #define R_SYNC_SERIAL1_CTRL__f_syncsize__reserved 3 | ||
| 7062 | #define R_SYNC_SERIAL1_CTRL__f_sync__BITNR 18 | ||
| 7063 | #define R_SYNC_SERIAL1_CTRL__f_sync__WIDTH 1 | ||
| 7064 | #define R_SYNC_SERIAL1_CTRL__f_sync__on 0 | ||
| 7065 | #define R_SYNC_SERIAL1_CTRL__f_sync__off 1 | ||
| 7066 | #define R_SYNC_SERIAL1_CTRL__clk_mode__BITNR 17 | ||
| 7067 | #define R_SYNC_SERIAL1_CTRL__clk_mode__WIDTH 1 | ||
| 7068 | #define R_SYNC_SERIAL1_CTRL__clk_mode__normal 0 | ||
| 7069 | #define R_SYNC_SERIAL1_CTRL__clk_mode__gated 1 | ||
| 7070 | #define R_SYNC_SERIAL1_CTRL__clk_halt__BITNR 16 | ||
| 7071 | #define R_SYNC_SERIAL1_CTRL__clk_halt__WIDTH 1 | ||
| 7072 | #define R_SYNC_SERIAL1_CTRL__clk_halt__running 0 | ||
| 7073 | #define R_SYNC_SERIAL1_CTRL__clk_halt__stopped 1 | ||
| 7074 | #define R_SYNC_SERIAL1_CTRL__bitorder__BITNR 15 | ||
| 7075 | #define R_SYNC_SERIAL1_CTRL__bitorder__WIDTH 1 | ||
| 7076 | #define R_SYNC_SERIAL1_CTRL__bitorder__lsb 0 | ||
| 7077 | #define R_SYNC_SERIAL1_CTRL__bitorder__msb 1 | ||
| 7078 | #define R_SYNC_SERIAL1_CTRL__tr_enable__BITNR 14 | ||
| 7079 | #define R_SYNC_SERIAL1_CTRL__tr_enable__WIDTH 1 | ||
| 7080 | #define R_SYNC_SERIAL1_CTRL__tr_enable__disable 0 | ||
| 7081 | #define R_SYNC_SERIAL1_CTRL__tr_enable__enable 1 | ||
| 7082 | #define R_SYNC_SERIAL1_CTRL__wordsize__BITNR 11 | ||
| 7083 | #define R_SYNC_SERIAL1_CTRL__wordsize__WIDTH 3 | ||
| 7084 | #define R_SYNC_SERIAL1_CTRL__wordsize__size8bit 0 | ||
| 7085 | #define R_SYNC_SERIAL1_CTRL__wordsize__size12bit 1 | ||
| 7086 | #define R_SYNC_SERIAL1_CTRL__wordsize__size16bit 2 | ||
| 7087 | #define R_SYNC_SERIAL1_CTRL__wordsize__size24bit 3 | ||
| 7088 | #define R_SYNC_SERIAL1_CTRL__wordsize__size32bit 4 | ||
| 7089 | #define R_SYNC_SERIAL1_CTRL__buf_empty__BITNR 10 | ||
| 7090 | #define R_SYNC_SERIAL1_CTRL__buf_empty__WIDTH 1 | ||
| 7091 | #define R_SYNC_SERIAL1_CTRL__buf_empty__lmt_8 0 | ||
| 7092 | #define R_SYNC_SERIAL1_CTRL__buf_empty__lmt_0 1 | ||
| 7093 | #define R_SYNC_SERIAL1_CTRL__buf_full__BITNR 9 | ||
| 7094 | #define R_SYNC_SERIAL1_CTRL__buf_full__WIDTH 1 | ||
| 7095 | #define R_SYNC_SERIAL1_CTRL__buf_full__lmt_32 0 | ||
| 7096 | #define R_SYNC_SERIAL1_CTRL__buf_full__lmt_8 1 | ||
| 7097 | #define R_SYNC_SERIAL1_CTRL__flow_ctrl__BITNR 8 | ||
| 7098 | #define R_SYNC_SERIAL1_CTRL__flow_ctrl__WIDTH 1 | ||
| 7099 | #define R_SYNC_SERIAL1_CTRL__flow_ctrl__disabled 0 | ||
| 7100 | #define R_SYNC_SERIAL1_CTRL__flow_ctrl__enabled 1 | ||
| 7101 | #define R_SYNC_SERIAL1_CTRL__clk_polarity__BITNR 6 | ||
| 7102 | #define R_SYNC_SERIAL1_CTRL__clk_polarity__WIDTH 1 | ||
| 7103 | #define R_SYNC_SERIAL1_CTRL__clk_polarity__pos 0 | ||
| 7104 | #define R_SYNC_SERIAL1_CTRL__clk_polarity__neg 1 | ||
| 7105 | #define R_SYNC_SERIAL1_CTRL__frame_polarity__BITNR 5 | ||
| 7106 | #define R_SYNC_SERIAL1_CTRL__frame_polarity__WIDTH 1 | ||
| 7107 | #define R_SYNC_SERIAL1_CTRL__frame_polarity__normal 0 | ||
| 7108 | #define R_SYNC_SERIAL1_CTRL__frame_polarity__inverted 1 | ||
| 7109 | #define R_SYNC_SERIAL1_CTRL__status_polarity__BITNR 4 | ||
| 7110 | #define R_SYNC_SERIAL1_CTRL__status_polarity__WIDTH 1 | ||
| 7111 | #define R_SYNC_SERIAL1_CTRL__status_polarity__normal 0 | ||
| 7112 | #define R_SYNC_SERIAL1_CTRL__status_polarity__inverted 1 | ||
| 7113 | #define R_SYNC_SERIAL1_CTRL__clk_driver__BITNR 3 | ||
| 7114 | #define R_SYNC_SERIAL1_CTRL__clk_driver__WIDTH 1 | ||
| 7115 | #define R_SYNC_SERIAL1_CTRL__clk_driver__normal 0 | ||
| 7116 | #define R_SYNC_SERIAL1_CTRL__clk_driver__inverted 1 | ||
| 7117 | #define R_SYNC_SERIAL1_CTRL__frame_driver__BITNR 2 | ||
| 7118 | #define R_SYNC_SERIAL1_CTRL__frame_driver__WIDTH 1 | ||
| 7119 | #define R_SYNC_SERIAL1_CTRL__frame_driver__normal 0 | ||
| 7120 | #define R_SYNC_SERIAL1_CTRL__frame_driver__inverted 1 | ||
| 7121 | #define R_SYNC_SERIAL1_CTRL__status_driver__BITNR 1 | ||
| 7122 | #define R_SYNC_SERIAL1_CTRL__status_driver__WIDTH 1 | ||
| 7123 | #define R_SYNC_SERIAL1_CTRL__status_driver__normal 0 | ||
| 7124 | #define R_SYNC_SERIAL1_CTRL__status_driver__inverted 1 | ||
| 7125 | #define R_SYNC_SERIAL1_CTRL__def_out0__BITNR 0 | ||
| 7126 | #define R_SYNC_SERIAL1_CTRL__def_out0__WIDTH 1 | ||
| 7127 | #define R_SYNC_SERIAL1_CTRL__def_out0__high 1 | ||
| 7128 | #define R_SYNC_SERIAL1_CTRL__def_out0__low 0 | ||
| 7129 | |||
| 7130 | #define R_SYNC_SERIAL3_REC_DATA (IO_TYPECAST_RO_UDWORD 0xb000007c) | ||
| 7131 | #define R_SYNC_SERIAL3_REC_DATA__data_in__BITNR 0 | ||
| 7132 | #define R_SYNC_SERIAL3_REC_DATA__data_in__WIDTH 32 | ||
| 7133 | |||
| 7134 | #define R_SYNC_SERIAL3_REC_WORD (IO_TYPECAST_RO_UWORD 0xb000007c) | ||
| 7135 | #define R_SYNC_SERIAL3_REC_WORD__data_in__BITNR 0 | ||
| 7136 | #define R_SYNC_SERIAL3_REC_WORD__data_in__WIDTH 16 | ||
| 7137 | |||
| 7138 | #define R_SYNC_SERIAL3_REC_BYTE (IO_TYPECAST_RO_BYTE 0xb000007c) | ||
| 7139 | #define R_SYNC_SERIAL3_REC_BYTE__data_in__BITNR 0 | ||
| 7140 | #define R_SYNC_SERIAL3_REC_BYTE__data_in__WIDTH 8 | ||
| 7141 | |||
| 7142 | #define R_SYNC_SERIAL3_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000078) | ||
| 7143 | #define R_SYNC_SERIAL3_STATUS__rec_status__BITNR 15 | ||
| 7144 | #define R_SYNC_SERIAL3_STATUS__rec_status__WIDTH 1 | ||
| 7145 | #define R_SYNC_SERIAL3_STATUS__rec_status__running 0 | ||
| 7146 | #define R_SYNC_SERIAL3_STATUS__rec_status__idle 1 | ||
| 7147 | #define R_SYNC_SERIAL3_STATUS__tr_empty__BITNR 14 | ||
| 7148 | #define R_SYNC_SERIAL3_STATUS__tr_empty__WIDTH 1 | ||
| 7149 | #define R_SYNC_SERIAL3_STATUS__tr_empty__empty 1 | ||
| 7150 | #define R_SYNC_SERIAL3_STATUS__tr_empty__not_empty 0 | ||
| 7151 | #define R_SYNC_SERIAL3_STATUS__tr_ready__BITNR 13 | ||
| 7152 | #define R_SYNC_SERIAL3_STATUS__tr_ready__WIDTH 1 | ||
| 7153 | #define R_SYNC_SERIAL3_STATUS__tr_ready__full 0 | ||
| 7154 | #define R_SYNC_SERIAL3_STATUS__tr_ready__ready 1 | ||
| 7155 | #define R_SYNC_SERIAL3_STATUS__pin_1__BITNR 12 | ||
| 7156 | #define R_SYNC_SERIAL3_STATUS__pin_1__WIDTH 1 | ||
| 7157 | #define R_SYNC_SERIAL3_STATUS__pin_1__low 0 | ||
| 7158 | #define R_SYNC_SERIAL3_STATUS__pin_1__high 1 | ||
| 7159 | #define R_SYNC_SERIAL3_STATUS__pin_0__BITNR 11 | ||
| 7160 | #define R_SYNC_SERIAL3_STATUS__pin_0__WIDTH 1 | ||
| 7161 | #define R_SYNC_SERIAL3_STATUS__pin_0__low 0 | ||
| 7162 | #define R_SYNC_SERIAL3_STATUS__pin_0__high 1 | ||
| 7163 | #define R_SYNC_SERIAL3_STATUS__underflow__BITNR 10 | ||
| 7164 | #define R_SYNC_SERIAL3_STATUS__underflow__WIDTH 1 | ||
| 7165 | #define R_SYNC_SERIAL3_STATUS__underflow__no 0 | ||
| 7166 | #define R_SYNC_SERIAL3_STATUS__underflow__yes 1 | ||
| 7167 | #define R_SYNC_SERIAL3_STATUS__overrun__BITNR 9 | ||
| 7168 | #define R_SYNC_SERIAL3_STATUS__overrun__WIDTH 1 | ||
| 7169 | #define R_SYNC_SERIAL3_STATUS__overrun__no 0 | ||
| 7170 | #define R_SYNC_SERIAL3_STATUS__overrun__yes 1 | ||
| 7171 | #define R_SYNC_SERIAL3_STATUS__data_avail__BITNR 8 | ||
| 7172 | #define R_SYNC_SERIAL3_STATUS__data_avail__WIDTH 1 | ||
| 7173 | #define R_SYNC_SERIAL3_STATUS__data_avail__no 0 | ||
| 7174 | #define R_SYNC_SERIAL3_STATUS__data_avail__yes 1 | ||
| 7175 | #define R_SYNC_SERIAL3_STATUS__data__BITNR 0 | ||
| 7176 | #define R_SYNC_SERIAL3_STATUS__data__WIDTH 8 | ||
| 7177 | |||
| 7178 | #define R_SYNC_SERIAL3_TR_DATA (IO_TYPECAST_UDWORD 0xb000007c) | ||
| 7179 | #define R_SYNC_SERIAL3_TR_DATA__data_out__BITNR 0 | ||
| 7180 | #define R_SYNC_SERIAL3_TR_DATA__data_out__WIDTH 32 | ||
| 7181 | |||
| 7182 | #define R_SYNC_SERIAL3_TR_WORD (IO_TYPECAST_UWORD 0xb000007c) | ||
| 7183 | #define R_SYNC_SERIAL3_TR_WORD__data_out__BITNR 0 | ||
| 7184 | #define R_SYNC_SERIAL3_TR_WORD__data_out__WIDTH 16 | ||
| 7185 | |||
| 7186 | #define R_SYNC_SERIAL3_TR_BYTE (IO_TYPECAST_BYTE 0xb000007c) | ||
| 7187 | #define R_SYNC_SERIAL3_TR_BYTE__data_out__BITNR 0 | ||
| 7188 | #define R_SYNC_SERIAL3_TR_BYTE__data_out__WIDTH 8 | ||
| 7189 | |||
| 7190 | #define R_SYNC_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078) | ||
| 7191 | #define R_SYNC_SERIAL3_CTRL__tr_baud__BITNR 28 | ||
| 7192 | #define R_SYNC_SERIAL3_CTRL__tr_baud__WIDTH 4 | ||
| 7193 | #define R_SYNC_SERIAL3_CTRL__tr_baud__c150Hz 0 | ||
| 7194 | #define R_SYNC_SERIAL3_CTRL__tr_baud__c300Hz 1 | ||
| 7195 | #define R_SYNC_SERIAL3_CTRL__tr_baud__c600Hz 2 | ||
| 7196 | #define R_SYNC_SERIAL3_CTRL__tr_baud__c1200Hz 3 | ||
| 7197 | #define R_SYNC_SERIAL3_CTRL__tr_baud__c2400Hz 4 | ||
| 7198 | #define R_SYNC_SERIAL3_CTRL__tr_baud__c4800Hz 5 | ||
| 7199 | #define R_SYNC_SERIAL3_CTRL__tr_baud__c9600Hz 6 | ||
| 7200 | #define R_SYNC_SERIAL3_CTRL__tr_baud__c19k2Hz 7 | ||
| 7201 | #define R_SYNC_SERIAL3_CTRL__tr_baud__c28k8Hz 8 | ||
| 7202 | #define R_SYNC_SERIAL3_CTRL__tr_baud__c57k6Hz 9 | ||
| 7203 | #define R_SYNC_SERIAL3_CTRL__tr_baud__c115k2Hz 10 | ||
| 7204 | #define R_SYNC_SERIAL3_CTRL__tr_baud__c230k4Hz 11 | ||
| 7205 | #define R_SYNC_SERIAL3_CTRL__tr_baud__c460k8Hz 12 | ||
| 7206 | #define R_SYNC_SERIAL3_CTRL__tr_baud__c921k6Hz 13 | ||
| 7207 | #define R_SYNC_SERIAL3_CTRL__tr_baud__c3125kHz 14 | ||
| 7208 | #define R_SYNC_SERIAL3_CTRL__tr_baud__reserved 15 | ||
| 7209 | #define R_SYNC_SERIAL3_CTRL__dma_enable__BITNR 27 | ||
| 7210 | #define R_SYNC_SERIAL3_CTRL__dma_enable__WIDTH 1 | ||
| 7211 | #define R_SYNC_SERIAL3_CTRL__dma_enable__on 1 | ||
| 7212 | #define R_SYNC_SERIAL3_CTRL__dma_enable__off 0 | ||
| 7213 | #define R_SYNC_SERIAL3_CTRL__mode__BITNR 24 | ||
| 7214 | #define R_SYNC_SERIAL3_CTRL__mode__WIDTH 3 | ||
| 7215 | #define R_SYNC_SERIAL3_CTRL__mode__master_output 0 | ||
| 7216 | #define R_SYNC_SERIAL3_CTRL__mode__slave_output 1 | ||
| 7217 | #define R_SYNC_SERIAL3_CTRL__mode__master_input 2 | ||
| 7218 | #define R_SYNC_SERIAL3_CTRL__mode__slave_input 3 | ||
| 7219 | #define R_SYNC_SERIAL3_CTRL__mode__master_bidir 4 | ||
| 7220 | #define R_SYNC_SERIAL3_CTRL__mode__slave_bidir 5 | ||
| 7221 | #define R_SYNC_SERIAL3_CTRL__error__BITNR 23 | ||
| 7222 | #define R_SYNC_SERIAL3_CTRL__error__WIDTH 1 | ||
| 7223 | #define R_SYNC_SERIAL3_CTRL__error__normal 0 | ||
| 7224 | #define R_SYNC_SERIAL3_CTRL__error__ignore 1 | ||
| 7225 | #define R_SYNC_SERIAL3_CTRL__rec_enable__BITNR 22 | ||
| 7226 | #define R_SYNC_SERIAL3_CTRL__rec_enable__WIDTH 1 | ||
| 7227 | #define R_SYNC_SERIAL3_CTRL__rec_enable__disable 0 | ||
| 7228 | #define R_SYNC_SERIAL3_CTRL__rec_enable__enable 1 | ||
| 7229 | #define R_SYNC_SERIAL3_CTRL__f_synctype__BITNR 21 | ||
| 7230 | #define R_SYNC_SERIAL3_CTRL__f_synctype__WIDTH 1 | ||
| 7231 | #define R_SYNC_SERIAL3_CTRL__f_synctype__normal 0 | ||
| 7232 | #define R_SYNC_SERIAL3_CTRL__f_synctype__early 1 | ||
| 7233 | #define R_SYNC_SERIAL3_CTRL__f_syncsize__BITNR 19 | ||
| 7234 | #define R_SYNC_SERIAL3_CTRL__f_syncsize__WIDTH 2 | ||
| 7235 | #define R_SYNC_SERIAL3_CTRL__f_syncsize__bit 0 | ||
| 7236 | #define R_SYNC_SERIAL3_CTRL__f_syncsize__word 1 | ||
| 7237 | #define R_SYNC_SERIAL3_CTRL__f_syncsize__extended 2 | ||
| 7238 | #define R_SYNC_SERIAL3_CTRL__f_syncsize__reserved 3 | ||
| 7239 | #define R_SYNC_SERIAL3_CTRL__f_sync__BITNR 18 | ||
| 7240 | #define R_SYNC_SERIAL3_CTRL__f_sync__WIDTH 1 | ||
| 7241 | #define R_SYNC_SERIAL3_CTRL__f_sync__on 0 | ||
| 7242 | #define R_SYNC_SERIAL3_CTRL__f_sync__off 1 | ||
| 7243 | #define R_SYNC_SERIAL3_CTRL__clk_mode__BITNR 17 | ||
| 7244 | #define R_SYNC_SERIAL3_CTRL__clk_mode__WIDTH 1 | ||
| 7245 | #define R_SYNC_SERIAL3_CTRL__clk_mode__normal 0 | ||
| 7246 | #define R_SYNC_SERIAL3_CTRL__clk_mode__gated 1 | ||
| 7247 | #define R_SYNC_SERIAL3_CTRL__clk_halt__BITNR 16 | ||
| 7248 | #define R_SYNC_SERIAL3_CTRL__clk_halt__WIDTH 1 | ||
| 7249 | #define R_SYNC_SERIAL3_CTRL__clk_halt__running 0 | ||
| 7250 | #define R_SYNC_SERIAL3_CTRL__clk_halt__stopped 1 | ||
| 7251 | #define R_SYNC_SERIAL3_CTRL__bitorder__BITNR 15 | ||
| 7252 | #define R_SYNC_SERIAL3_CTRL__bitorder__WIDTH 1 | ||
| 7253 | #define R_SYNC_SERIAL3_CTRL__bitorder__lsb 0 | ||
| 7254 | #define R_SYNC_SERIAL3_CTRL__bitorder__msb 1 | ||
| 7255 | #define R_SYNC_SERIAL3_CTRL__tr_enable__BITNR 14 | ||
| 7256 | #define R_SYNC_SERIAL3_CTRL__tr_enable__WIDTH 1 | ||
| 7257 | #define R_SYNC_SERIAL3_CTRL__tr_enable__disable 0 | ||
| 7258 | #define R_SYNC_SERIAL3_CTRL__tr_enable__enable 1 | ||
| 7259 | #define R_SYNC_SERIAL3_CTRL__wordsize__BITNR 11 | ||
| 7260 | #define R_SYNC_SERIAL3_CTRL__wordsize__WIDTH 3 | ||
| 7261 | #define R_SYNC_SERIAL3_CTRL__wordsize__size8bit 0 | ||
| 7262 | #define R_SYNC_SERIAL3_CTRL__wordsize__size12bit 1 | ||
| 7263 | #define R_SYNC_SERIAL3_CTRL__wordsize__size16bit 2 | ||
| 7264 | #define R_SYNC_SERIAL3_CTRL__wordsize__size24bit 3 | ||
| 7265 | #define R_SYNC_SERIAL3_CTRL__wordsize__size32bit 4 | ||
| 7266 | #define R_SYNC_SERIAL3_CTRL__buf_empty__BITNR 10 | ||
| 7267 | #define R_SYNC_SERIAL3_CTRL__buf_empty__WIDTH 1 | ||
| 7268 | #define R_SYNC_SERIAL3_CTRL__buf_empty__lmt_8 0 | ||
| 7269 | #define R_SYNC_SERIAL3_CTRL__buf_empty__lmt_0 1 | ||
| 7270 | #define R_SYNC_SERIAL3_CTRL__buf_full__BITNR 9 | ||
| 7271 | #define R_SYNC_SERIAL3_CTRL__buf_full__WIDTH 1 | ||
| 7272 | #define R_SYNC_SERIAL3_CTRL__buf_full__lmt_32 0 | ||
| 7273 | #define R_SYNC_SERIAL3_CTRL__buf_full__lmt_8 1 | ||
| 7274 | #define R_SYNC_SERIAL3_CTRL__flow_ctrl__BITNR 8 | ||
| 7275 | #define R_SYNC_SERIAL3_CTRL__flow_ctrl__WIDTH 1 | ||
| 7276 | #define R_SYNC_SERIAL3_CTRL__flow_ctrl__disabled 0 | ||
| 7277 | #define R_SYNC_SERIAL3_CTRL__flow_ctrl__enabled 1 | ||
| 7278 | #define R_SYNC_SERIAL3_CTRL__clk_polarity__BITNR 6 | ||
| 7279 | #define R_SYNC_SERIAL3_CTRL__clk_polarity__WIDTH 1 | ||
| 7280 | #define R_SYNC_SERIAL3_CTRL__clk_polarity__pos 0 | ||
| 7281 | #define R_SYNC_SERIAL3_CTRL__clk_polarity__neg 1 | ||
| 7282 | #define R_SYNC_SERIAL3_CTRL__frame_polarity__BITNR 5 | ||
| 7283 | #define R_SYNC_SERIAL3_CTRL__frame_polarity__WIDTH 1 | ||
| 7284 | #define R_SYNC_SERIAL3_CTRL__frame_polarity__normal 0 | ||
| 7285 | #define R_SYNC_SERIAL3_CTRL__frame_polarity__inverted 1 | ||
| 7286 | #define R_SYNC_SERIAL3_CTRL__status_polarity__BITNR 4 | ||
| 7287 | #define R_SYNC_SERIAL3_CTRL__status_polarity__WIDTH 1 | ||
| 7288 | #define R_SYNC_SERIAL3_CTRL__status_polarity__normal 0 | ||
| 7289 | #define R_SYNC_SERIAL3_CTRL__status_polarity__inverted 1 | ||
| 7290 | #define R_SYNC_SERIAL3_CTRL__clk_driver__BITNR 3 | ||
| 7291 | #define R_SYNC_SERIAL3_CTRL__clk_driver__WIDTH 1 | ||
| 7292 | #define R_SYNC_SERIAL3_CTRL__clk_driver__normal 0 | ||
| 7293 | #define R_SYNC_SERIAL3_CTRL__clk_driver__inverted 1 | ||
| 7294 | #define R_SYNC_SERIAL3_CTRL__frame_driver__BITNR 2 | ||
| 7295 | #define R_SYNC_SERIAL3_CTRL__frame_driver__WIDTH 1 | ||
| 7296 | #define R_SYNC_SERIAL3_CTRL__frame_driver__normal 0 | ||
| 7297 | #define R_SYNC_SERIAL3_CTRL__frame_driver__inverted 1 | ||
| 7298 | #define R_SYNC_SERIAL3_CTRL__status_driver__BITNR 1 | ||
| 7299 | #define R_SYNC_SERIAL3_CTRL__status_driver__WIDTH 1 | ||
| 7300 | #define R_SYNC_SERIAL3_CTRL__status_driver__normal 0 | ||
| 7301 | #define R_SYNC_SERIAL3_CTRL__status_driver__inverted 1 | ||
| 7302 | #define R_SYNC_SERIAL3_CTRL__def_out0__BITNR 0 | ||
| 7303 | #define R_SYNC_SERIAL3_CTRL__def_out0__WIDTH 1 | ||
| 7304 | #define R_SYNC_SERIAL3_CTRL__def_out0__high 1 | ||
| 7305 | #define R_SYNC_SERIAL3_CTRL__def_out0__low 0 | ||
| 7306 | |||
diff --git a/include/asm-cris/arch-v10/sv_addr_ag.h b/include/asm-cris/arch-v10/sv_addr_ag.h new file mode 100644 index 000000000000..e4a6b68b8982 --- /dev/null +++ b/include/asm-cris/arch-v10/sv_addr_ag.h | |||
| @@ -0,0 +1,139 @@ | |||
| 1 | /*!************************************************************************** | ||
| 2 | *! | ||
| 3 | *! MACROS: | ||
| 4 | *! IO_MASK(reg,field) | ||
| 5 | *! IO_STATE(reg,field,state) | ||
| 6 | *! IO_EXTRACT(reg,field,val) | ||
| 7 | *! IO_STATE_VALUE(reg,field,state) | ||
| 8 | *! IO_BITNR(reg,field) | ||
| 9 | *! IO_WIDTH(reg,field) | ||
| 10 | *! IO_FIELD(reg,field,val) | ||
| 11 | *! IO_RD(reg) | ||
| 12 | *! All moderegister addresses and fields of these. | ||
| 13 | *! | ||
| 14 | *!**************************************************************************/ | ||
| 15 | |||
| 16 | #ifndef __sv_addr_ag_h__ | ||
| 17 | #define __sv_addr_ag_h__ | ||
| 18 | |||
| 19 | |||
| 20 | #define __test_sv_addr__ 0 | ||
| 21 | |||
| 22 | /*------------------------------------------------------------ | ||
| 23 | !* General macros to manipulate moderegisters. | ||
| 24 | !*-----------------------------------------------------------*/ | ||
| 25 | |||
| 26 | /* IO_MASK returns a mask for a specified bitfield in a register. | ||
| 27 | Note that this macro doesn't work when field width is 32 bits. */ | ||
| 28 | #define IO_MASK(reg, field) IO_MASK_ (reg##_, field##_) | ||
| 29 | #define IO_MASK_(reg_, field_) \ | ||
| 30 | ( ( ( 1 << reg_##_##field_##_WIDTH ) - 1 ) << reg_##_##field_##_BITNR ) | ||
| 31 | |||
| 32 | /* IO_STATE returns a constant corresponding to a one of the symbolic | ||
| 33 | states that the bitfield can have. (Shifted to correct position) */ | ||
| 34 | #define IO_STATE(reg, field, state) IO_STATE_ (reg##_, field##_, _##state) | ||
| 35 | #define IO_STATE_(reg_, field_, _state) \ | ||
| 36 | ( reg_##_##field_##_state << reg_##_##field_##_BITNR ) | ||
| 37 | |||
| 38 | /* IO_EXTRACT returns the masked and shifted value corresponding to the | ||
| 39 | bitfield can have. */ | ||
| 40 | #define IO_EXTRACT(reg, field, val) IO_EXTRACT_ (reg##_, field##_, val) | ||
| 41 | #define IO_EXTRACT_(reg_, field_, val) ( (( ( ( 1 << reg_##_##field_##_WIDTH ) \ | ||
| 42 | - 1 ) << reg_##_##field_##_BITNR ) & (val)) >> reg_##_##field_##_BITNR ) | ||
| 43 | |||
| 44 | /* IO_STATE_VALUE returns a constant corresponding to a one of the symbolic | ||
| 45 | states that the bitfield can have. (Not shifted) */ | ||
| 46 | #define IO_STATE_VALUE(reg, field, state) \ | ||
| 47 | IO_STATE_VALUE_ (reg##_, field##_, _##state) | ||
| 48 | #define IO_STATE_VALUE_(reg_, field_, _state) ( reg_##_##field_##_state ) | ||
| 49 | |||
| 50 | /* IO_FIELD shifts the val parameter to be aligned with the bitfield | ||
| 51 | specified. */ | ||
| 52 | #define IO_FIELD(reg, field, val) IO_FIELD_ (reg##_, field##_, val) | ||
| 53 | #define IO_FIELD_(reg_, field_, val) ((val) << reg_##_##field_##_BITNR) | ||
| 54 | |||
| 55 | /* IO_BITNR returns the starting bitnumber of a bitfield. Bit 0 is | ||
| 56 | LSB and the returned bitnumber is LSB of the field. */ | ||
| 57 | #define IO_BITNR(reg, field) IO_BITNR_ (reg##_, field##_) | ||
| 58 | #define IO_BITNR_(reg_, field_) (reg_##_##field_##_BITNR) | ||
| 59 | |||
| 60 | /* IO_WIDTH returns the width, in bits, of a bitfield. */ | ||
| 61 | #define IO_WIDTH(reg, field) IO_WIDTH_ (reg##_, field##_) | ||
| 62 | #define IO_WIDTH_(reg_, field_) (reg_##_##field_##_WIDTH) | ||
| 63 | |||
| 64 | /*--- Obsolete. Kept for backw compatibility. ---*/ | ||
| 65 | /* Reads (or writes) a byte/uword/udword from the specified mode | ||
| 66 | register. */ | ||
| 67 | #define IO_RD(reg) (*(volatile u32*)(reg)) | ||
| 68 | #define IO_RD_B(reg) (*(volatile u8*)(reg)) | ||
| 69 | #define IO_RD_W(reg) (*(volatile u16*)(reg)) | ||
| 70 | #define IO_RD_D(reg) (*(volatile u32*)(reg)) | ||
| 71 | |||
| 72 | /*------------------------------------------------------------ | ||
| 73 | !* Start addresses of the different memory areas. | ||
| 74 | !*-----------------------------------------------------------*/ | ||
| 75 | |||
| 76 | #define MEM_CSE0_START (0x00000000) | ||
| 77 | #define MEM_CSE0_SIZE (0x04000000) | ||
| 78 | #define MEM_CSE1_START (0x04000000) | ||
| 79 | #define MEM_CSE1_SIZE (0x04000000) | ||
| 80 | #define MEM_CSR0_START (0x08000000) | ||
| 81 | #define MEM_CSR1_START (0x0c000000) | ||
| 82 | #define MEM_CSP0_START (0x10000000) | ||
| 83 | #define MEM_CSP1_START (0x14000000) | ||
| 84 | #define MEM_CSP2_START (0x18000000) | ||
| 85 | #define MEM_CSP3_START (0x1c000000) | ||
| 86 | #define MEM_CSP4_START (0x20000000) | ||
| 87 | #define MEM_CSP5_START (0x24000000) | ||
| 88 | #define MEM_CSP6_START (0x28000000) | ||
| 89 | #define MEM_CSP7_START (0x2c000000) | ||
| 90 | #define MEM_DRAM_START (0x40000000) | ||
| 91 | |||
| 92 | #define MEM_NON_CACHEABLE (0x80000000) | ||
| 93 | |||
| 94 | /*------------------------------------------------------------ | ||
| 95 | !* Type casts used in mode register macros, making pointer | ||
| 96 | !* dereferencing possible. Empty in assembler. | ||
| 97 | !*-----------------------------------------------------------*/ | ||
| 98 | |||
| 99 | #ifndef __ASSEMBLER__ | ||
| 100 | # define IO_TYPECAST_UDWORD (volatile u32*) | ||
| 101 | # define IO_TYPECAST_RO_UDWORD (const volatile u32*) | ||
| 102 | # define IO_TYPECAST_UWORD (volatile u16*) | ||
| 103 | # define IO_TYPECAST_RO_UWORD (const volatile u16*) | ||
| 104 | # define IO_TYPECAST_BYTE (volatile u8*) | ||
| 105 | # define IO_TYPECAST_RO_BYTE (const volatile u8*) | ||
| 106 | #else | ||
| 107 | # define IO_TYPECAST_UDWORD | ||
| 108 | # define IO_TYPECAST_RO_UDWORD | ||
| 109 | # define IO_TYPECAST_UWORD | ||
| 110 | # define IO_TYPECAST_RO_UWORD | ||
| 111 | # define IO_TYPECAST_BYTE | ||
| 112 | # define IO_TYPECAST_RO_BYTE | ||
| 113 | #endif | ||
| 114 | |||
| 115 | /*------------------------------------------------------------*/ | ||
| 116 | |||
| 117 | #include "sv_addr.agh" | ||
| 118 | |||
| 119 | #if __test_sv_addr__ | ||
| 120 | /* IO_MASK( R_BUS_CONFIG , CE ) */ | ||
| 121 | IO_MASK( R_WAITSTATES , SRAM_WS ) | ||
| 122 | IO_MASK( R_TEST , W32 ) | ||
| 123 | |||
| 124 | IO_STATE( R_BUS_CONFIG, CE, DISABLE ) | ||
| 125 | IO_STATE( R_BUS_CONFIG, CE, ENABLE ) | ||
| 126 | |||
| 127 | IO_STATE( R_DRAM_TIMING, REF, IVAL2 ) | ||
| 128 | |||
| 129 | IO_MASK( R_DRAM_TIMING, REF ) | ||
| 130 | |||
| 131 | IO_MASK( R_EXT_DMA_0_STAT, TFR_COUNT ) >> IO_BITNR( R_EXT_DMA_0_STAT, TFR_COUNT ) | ||
| 132 | |||
| 133 | IO_RD(R_EXT_DMA_0_STAT) & IO_MASK( R_EXT_DMA_0_STAT, S ) | ||
| 134 | == IO_STATE( R_EXT_DMA_0_STAT, S, STARTED ) | ||
| 135 | #endif | ||
| 136 | |||
| 137 | |||
| 138 | #endif /* ifndef __sv_addr_ag_h__ */ | ||
| 139 | |||
diff --git a/include/asm-cris/arch-v10/svinto.h b/include/asm-cris/arch-v10/svinto.h new file mode 100644 index 000000000000..0881a1af7cee --- /dev/null +++ b/include/asm-cris/arch-v10/svinto.h | |||
| @@ -0,0 +1,64 @@ | |||
| 1 | #ifndef _ASM_CRIS_SVINTO_H | ||
| 2 | #define _ASM_CRIS_SVINTO_H | ||
| 3 | |||
| 4 | #include "sv_addr_ag.h" | ||
| 5 | |||
| 6 | extern unsigned int genconfig_shadow; /* defined and set in head.S */ | ||
| 7 | |||
| 8 | /* dma stuff */ | ||
| 9 | |||
| 10 | enum { /* Available in: */ | ||
| 11 | d_eol = (1 << 0), /* flags */ | ||
| 12 | d_eop = (1 << 1), /* flags & status */ | ||
| 13 | d_wait = (1 << 2), /* flags */ | ||
| 14 | d_int = (1 << 3), /* flags */ | ||
| 15 | d_txerr = (1 << 4), /* flags */ | ||
| 16 | d_stop = (1 << 4), /* status */ | ||
| 17 | d_ecp = (1 << 4), /* flags & status */ | ||
| 18 | d_pri = (1 << 5), /* flags & status */ | ||
| 19 | d_alignerr = (1 << 6), /* status */ | ||
| 20 | d_crcerr = (1 << 7) /* status */ | ||
| 21 | }; | ||
| 22 | |||
| 23 | /* Do remember that DMA does not go through the MMU and needs | ||
| 24 | * a real physical address, not an address virtually mapped or | ||
| 25 | * paged. Therefore the buf/next ptrs below are unsigned long instead | ||
| 26 | * of void * to give a warning if you try to put a pointer directly | ||
| 27 | * to them instead of going through virt_to_phys/phys_to_virt. | ||
| 28 | */ | ||
| 29 | |||
| 30 | typedef struct etrax_dma_descr { | ||
| 31 | unsigned short sw_len; /* 0-1 */ | ||
| 32 | unsigned short ctrl; /* 2-3 */ | ||
| 33 | unsigned long next; /* 4-7 */ | ||
| 34 | unsigned long buf; /* 8-11 */ | ||
| 35 | unsigned short hw_len; /* 12-13 */ | ||
| 36 | unsigned char status; /* 14 */ | ||
| 37 | unsigned char fifo_len; /* 15 */ | ||
| 38 | } etrax_dma_descr; | ||
| 39 | |||
| 40 | |||
| 41 | /* Use this for constant numbers only */ | ||
| 42 | #define RESET_DMA_NUM( n ) \ | ||
| 43 | *R_DMA_CH##n##_CMD = IO_STATE( R_DMA_CH0_CMD, cmd, reset ) | ||
| 44 | |||
| 45 | /* Use this for constant numbers or symbols, | ||
| 46 | * having two macros makes it possible to use constant expressions. | ||
| 47 | */ | ||
| 48 | #define RESET_DMA( n ) RESET_DMA_NUM( n ) | ||
| 49 | |||
| 50 | |||
| 51 | /* Use this for constant numbers only */ | ||
| 52 | #define WAIT_DMA_NUM( n ) \ | ||
| 53 | while( (*R_DMA_CH##n##_CMD & IO_MASK( R_DMA_CH0_CMD, cmd )) != \ | ||
| 54 | IO_STATE( R_DMA_CH0_CMD, cmd, hold ) ) | ||
| 55 | |||
| 56 | /* Use this for constant numbers or symbols | ||
| 57 | * having two macros makes it possible to use constant expressions. | ||
| 58 | */ | ||
| 59 | #define WAIT_DMA( n ) WAIT_DMA_NUM( n ) | ||
| 60 | |||
| 61 | extern void prepare_rx_descriptor(struct etrax_dma_descr *desc); | ||
| 62 | extern void flush_etrax_cache(void); | ||
| 63 | |||
| 64 | #endif | ||
diff --git a/include/asm-cris/arch-v10/system.h b/include/asm-cris/arch-v10/system.h new file mode 100644 index 000000000000..781ca30229a8 --- /dev/null +++ b/include/asm-cris/arch-v10/system.h | |||
| @@ -0,0 +1,62 @@ | |||
| 1 | #ifndef __ASM_CRIS_ARCH_SYSTEM_H | ||
| 2 | #define __ASM_CRIS_ARCH_SYSTEM_H | ||
| 3 | |||
| 4 | #include <linux/config.h> | ||
| 5 | |||
| 6 | /* read the CPU version register */ | ||
| 7 | |||
| 8 | extern inline unsigned long rdvr(void) { | ||
| 9 | unsigned char vr; | ||
| 10 | __asm__ volatile ("move $vr,%0" : "=rm" (vr)); | ||
| 11 | return vr; | ||
| 12 | } | ||
| 13 | |||
| 14 | /* read/write the user-mode stackpointer */ | ||
| 15 | |||
| 16 | extern inline unsigned long rdusp(void) { | ||
| 17 | unsigned long usp; | ||
| 18 | __asm__ __volatile__("move $usp,%0" : "=rm" (usp)); | ||
| 19 | return usp; | ||
| 20 | } | ||
| 21 | |||
| 22 | #define wrusp(usp) \ | ||
| 23 | __asm__ __volatile__("move %0,$usp" : /* no outputs */ : "rm" (usp)) | ||
| 24 | |||
| 25 | /* read the current stackpointer */ | ||
| 26 | |||
| 27 | extern inline unsigned long rdsp(void) { | ||
| 28 | unsigned long sp; | ||
| 29 | __asm__ __volatile__("move.d $sp,%0" : "=rm" (sp)); | ||
| 30 | return sp; | ||
| 31 | } | ||
| 32 | |||
| 33 | extern inline unsigned long _get_base(char * addr) | ||
| 34 | { | ||
| 35 | return 0; | ||
| 36 | } | ||
| 37 | |||
| 38 | #define nop() __asm__ __volatile__ ("nop"); | ||
| 39 | |||
| 40 | #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) | ||
| 41 | #define tas(ptr) (xchg((ptr),1)) | ||
| 42 | |||
| 43 | struct __xchg_dummy { unsigned long a[100]; }; | ||
| 44 | #define __xg(x) ((struct __xchg_dummy *)(x)) | ||
| 45 | |||
| 46 | /* interrupt control.. */ | ||
| 47 | #define local_save_flags(x) __asm__ __volatile__ ("move $ccr,%0" : "=rm" (x) : : "memory"); | ||
| 48 | #define local_irq_restore(x) __asm__ __volatile__ ("move %0,$ccr" : : "rm" (x) : "memory"); | ||
| 49 | #define local_irq_disable() __asm__ __volatile__ ( "di" : : :"memory"); | ||
| 50 | #define local_irq_enable() __asm__ __volatile__ ( "ei" : : :"memory"); | ||
| 51 | |||
| 52 | #define irqs_disabled() \ | ||
| 53 | ({ \ | ||
| 54 | unsigned long flags; \ | ||
| 55 | local_save_flags(flags); \ | ||
| 56 | !(flags & (1<<5)); \ | ||
| 57 | }) | ||
| 58 | |||
| 59 | /* For spinlocks etc */ | ||
| 60 | #define local_irq_save(x) __asm__ __volatile__ ("move $ccr,%0\n\tdi" : "=rm" (x) : : "memory"); | ||
| 61 | |||
| 62 | #endif | ||
diff --git a/include/asm-cris/arch-v10/thread_info.h b/include/asm-cris/arch-v10/thread_info.h new file mode 100644 index 000000000000..357f5df0c907 --- /dev/null +++ b/include/asm-cris/arch-v10/thread_info.h | |||
| @@ -0,0 +1,12 @@ | |||
| 1 | #ifndef _ASM_ARCH_THREAD_INFO_H | ||
| 2 | #define _ASM_ARCH_THREAD_INFO_H | ||
| 3 | |||
| 4 | /* how to get the thread information struct from C */ | ||
| 5 | extern inline struct thread_info *current_thread_info(void) | ||
| 6 | { | ||
| 7 | struct thread_info *ti; | ||
| 8 | __asm__("and.d $sp,%0; ":"=r" (ti) : "0" (~8191UL)); | ||
| 9 | return ti; | ||
| 10 | } | ||
| 11 | |||
| 12 | #endif | ||
diff --git a/include/asm-cris/arch-v10/timex.h b/include/asm-cris/arch-v10/timex.h new file mode 100644 index 000000000000..ecfc553c06a5 --- /dev/null +++ b/include/asm-cris/arch-v10/timex.h | |||
| @@ -0,0 +1,30 @@ | |||
| 1 | /* | ||
| 2 | * Use prescale timer at 25000 Hz instead of the baudrate timer at | ||
| 3 | * 19200 to get rid of the 64ppm to fast timer (and we get better | ||
| 4 | * resolution within a jiffie as well. | ||
| 5 | */ | ||
| 6 | #ifndef _ASM_CRIS_ARCH_TIMEX_H | ||
| 7 | #define _ASM_CRIS_ARCH_TIMEX_H | ||
| 8 | |||
| 9 | /* The prescaler clock runs at 25MHz, we divide it by 1000 in the prescaler */ | ||
| 10 | /* If you change anything here you must check time.c as well... */ | ||
| 11 | #define PRESCALE_FREQ 25000000 | ||
| 12 | #define PRESCALE_VALUE 1000 | ||
| 13 | #define CLOCK_TICK_RATE 25000 /* Underlying frequency of the HZ timer */ | ||
| 14 | /* The timer0 values gives 40us resolution (1/25000) but interrupts at HZ*/ | ||
| 15 | #define TIMER0_FREQ (CLOCK_TICK_RATE) | ||
| 16 | #define TIMER0_CLKSEL flexible | ||
| 17 | #define TIMER0_DIV (TIMER0_FREQ/(HZ)) | ||
| 18 | |||
| 19 | |||
| 20 | #define GET_JIFFIES_USEC() \ | ||
| 21 | ( (TIMER0_DIV - *R_TIMER0_DATA) * (1000000/HZ)/TIMER0_DIV ) | ||
| 22 | |||
| 23 | unsigned long get_ns_in_jiffie(void); | ||
| 24 | |||
| 25 | extern inline unsigned long get_us_in_jiffie_highres(void) | ||
| 26 | { | ||
| 27 | return get_ns_in_jiffie()/1000; | ||
| 28 | } | ||
| 29 | |||
| 30 | #endif | ||
diff --git a/include/asm-cris/arch-v10/tlb.h b/include/asm-cris/arch-v10/tlb.h new file mode 100644 index 000000000000..31525bbe75c3 --- /dev/null +++ b/include/asm-cris/arch-v10/tlb.h | |||
| @@ -0,0 +1,13 @@ | |||
| 1 | #ifndef _CRIS_ARCH_TLB_H | ||
| 2 | #define _CRIS_ARCH_TLB_H | ||
| 3 | |||
| 4 | /* The TLB can host up to 64 different mm contexts at the same time. | ||
| 5 | * The last page_id is never running - it is used as an invalid page_id | ||
| 6 | * so we can make TLB entries that will never match. | ||
| 7 | */ | ||
| 8 | #define NUM_TLB_ENTRIES 64 | ||
| 9 | #define NUM_PAGEID 64 | ||
| 10 | #define INVALID_PAGEID 63 | ||
| 11 | #define NO_CONTEXT -1 | ||
| 12 | |||
| 13 | #endif | ||
diff --git a/include/asm-cris/arch-v10/uaccess.h b/include/asm-cris/arch-v10/uaccess.h new file mode 100644 index 000000000000..787d2e60c83c --- /dev/null +++ b/include/asm-cris/arch-v10/uaccess.h | |||
| @@ -0,0 +1,660 @@ | |||
| 1 | /* | ||
| 2 | * Authors: Bjorn Wesen (bjornw@axis.com) | ||
| 3 | * Hans-Peter Nilsson (hp@axis.com) | ||
| 4 | * | ||
| 5 | */ | ||
| 6 | #ifndef _CRIS_ARCH_UACCESS_H | ||
| 7 | #define _CRIS_ARCH_UACCESS_H | ||
| 8 | |||
| 9 | /* | ||
| 10 | * We don't tell gcc that we are accessing memory, but this is OK | ||
| 11 | * because we do not write to any memory gcc knows about, so there | ||
| 12 | * are no aliasing issues. | ||
| 13 | * | ||
| 14 | * Note that PC at a fault is the address *after* the faulting | ||
| 15 | * instruction. | ||
| 16 | */ | ||
| 17 | #define __put_user_asm(x, addr, err, op) \ | ||
| 18 | __asm__ __volatile__( \ | ||
| 19 | " "op" %1,[%2]\n" \ | ||
| 20 | "2:\n" \ | ||
| 21 | " .section .fixup,\"ax\"\n" \ | ||
| 22 | "3: move.d %3,%0\n" \ | ||
| 23 | " jump 2b\n" \ | ||
| 24 | " .previous\n" \ | ||
| 25 | " .section __ex_table,\"a\"\n" \ | ||
| 26 | " .dword 2b,3b\n" \ | ||
| 27 | " .previous\n" \ | ||
| 28 | : "=r" (err) \ | ||
| 29 | : "r" (x), "r" (addr), "g" (-EFAULT), "0" (err)) | ||
| 30 | |||
| 31 | #define __put_user_asm_64(x, addr, err) \ | ||
| 32 | __asm__ __volatile__( \ | ||
| 33 | " move.d %M1,[%2]\n" \ | ||
| 34 | "2: move.d %H1,[%2+4]\n" \ | ||
| 35 | "4:\n" \ | ||
| 36 | " .section .fixup,\"ax\"\n" \ | ||
| 37 | "3: move.d %3,%0\n" \ | ||
| 38 | " jump 4b\n" \ | ||
| 39 | " .previous\n" \ | ||
| 40 | " .section __ex_table,\"a\"\n" \ | ||
| 41 | " .dword 2b,3b\n" \ | ||
| 42 | " .dword 4b,3b\n" \ | ||
| 43 | " .previous\n" \ | ||
| 44 | : "=r" (err) \ | ||
| 45 | : "r" (x), "r" (addr), "g" (-EFAULT), "0" (err)) | ||
| 46 | |||
| 47 | /* See comment before __put_user_asm. */ | ||
| 48 | |||
| 49 | #define __get_user_asm(x, addr, err, op) \ | ||
| 50 | __asm__ __volatile__( \ | ||
| 51 | " "op" [%2],%1\n" \ | ||
| 52 | "2:\n" \ | ||
| 53 | " .section .fixup,\"ax\"\n" \ | ||
| 54 | "3: move.d %3,%0\n" \ | ||
| 55 | " moveq 0,%1\n" \ | ||
| 56 | " jump 2b\n" \ | ||
| 57 | " .previous\n" \ | ||
| 58 | " .section __ex_table,\"a\"\n" \ | ||
| 59 | " .dword 2b,3b\n" \ | ||
| 60 | " .previous\n" \ | ||
| 61 | : "=r" (err), "=r" (x) \ | ||
| 62 | : "r" (addr), "g" (-EFAULT), "0" (err)) | ||
| 63 | |||
| 64 | #define __get_user_asm_64(x, addr, err) \ | ||
| 65 | __asm__ __volatile__( \ | ||
| 66 | " move.d [%2],%M1\n" \ | ||
| 67 | "2: move.d [%2+4],%H1\n" \ | ||
| 68 | "4:\n" \ | ||
| 69 | " .section .fixup,\"ax\"\n" \ | ||
| 70 | "3: move.d %3,%0\n" \ | ||
| 71 | " moveq 0,%1\n" \ | ||
| 72 | " jump 4b\n" \ | ||
| 73 | " .previous\n" \ | ||
| 74 | " .section __ex_table,\"a\"\n" \ | ||
| 75 | " .dword 2b,3b\n" \ | ||
| 76 | " .dword 4b,3b\n" \ | ||
| 77 | " .previous\n" \ | ||
| 78 | : "=r" (err), "=r" (x) \ | ||
| 79 | : "r" (addr), "g" (-EFAULT), "0" (err)) | ||
| 80 | |||
| 81 | /* | ||
| 82 | * Copy a null terminated string from userspace. | ||
| 83 | * | ||
| 84 | * Must return: | ||
| 85 | * -EFAULT for an exception | ||
| 86 | * count if we hit the buffer limit | ||
| 87 | * bytes copied if we hit a null byte | ||
| 88 | * (without the null byte) | ||
| 89 | */ | ||
| 90 | extern inline long | ||
| 91 | __do_strncpy_from_user(char *dst, const char *src, long count) | ||
| 92 | { | ||
| 93 | long res; | ||
| 94 | |||
| 95 | if (count == 0) | ||
| 96 | return 0; | ||
| 97 | |||
| 98 | /* | ||
| 99 | * Currently, in 2.4.0-test9, most ports use a simple byte-copy loop. | ||
| 100 | * So do we. | ||
| 101 | * | ||
| 102 | * This code is deduced from: | ||
| 103 | * | ||
| 104 | * char tmp2; | ||
| 105 | * long tmp1, tmp3 | ||
| 106 | * tmp1 = count; | ||
| 107 | * while ((*dst++ = (tmp2 = *src++)) != 0 | ||
| 108 | * && --tmp1) | ||
| 109 | * ; | ||
| 110 | * | ||
| 111 | * res = count - tmp1; | ||
| 112 | * | ||
| 113 | * with tweaks. | ||
| 114 | */ | ||
| 115 | |||
| 116 | __asm__ __volatile__ ( | ||
| 117 | " move.d %3,%0\n" | ||
| 118 | " move.b [%2+],$r9\n" | ||
| 119 | "1: beq 2f\n" | ||
| 120 | " move.b $r9,[%1+]\n" | ||
| 121 | |||
| 122 | " subq 1,%0\n" | ||
| 123 | " bne 1b\n" | ||
| 124 | " move.b [%2+],$r9\n" | ||
| 125 | |||
| 126 | "2: sub.d %3,%0\n" | ||
| 127 | " neg.d %0,%0\n" | ||
| 128 | "3:\n" | ||
| 129 | " .section .fixup,\"ax\"\n" | ||
| 130 | "4: move.d %7,%0\n" | ||
| 131 | " jump 3b\n" | ||
| 132 | |||
| 133 | /* There's one address for a fault at the first move, and | ||
| 134 | two possible PC values for a fault at the second move, | ||
| 135 | being a delay-slot filler. However, the branch-target | ||
| 136 | for the second move is the same as the first address. | ||
| 137 | Just so you don't get confused... */ | ||
| 138 | " .previous\n" | ||
| 139 | " .section __ex_table,\"a\"\n" | ||
| 140 | " .dword 1b,4b\n" | ||
| 141 | " .dword 2b,4b\n" | ||
| 142 | " .previous" | ||
| 143 | : "=r" (res), "=r" (dst), "=r" (src), "=r" (count) | ||
| 144 | : "3" (count), "1" (dst), "2" (src), "g" (-EFAULT) | ||
| 145 | : "r9"); | ||
| 146 | |||
| 147 | return res; | ||
| 148 | } | ||
| 149 | |||
| 150 | /* A few copy asms to build up the more complex ones from. | ||
| 151 | |||
| 152 | Note again, a post-increment is performed regardless of whether a bus | ||
| 153 | fault occurred in that instruction, and PC for a faulted insn is the | ||
| 154 | address *after* the insn. */ | ||
| 155 | |||
| 156 | #define __asm_copy_user_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 157 | __asm__ __volatile__ ( \ | ||
| 158 | COPY \ | ||
| 159 | "1:\n" \ | ||
| 160 | " .section .fixup,\"ax\"\n" \ | ||
| 161 | FIXUP \ | ||
| 162 | " jump 1b\n" \ | ||
| 163 | " .previous\n" \ | ||
| 164 | " .section __ex_table,\"a\"\n" \ | ||
| 165 | TENTRY \ | ||
| 166 | " .previous\n" \ | ||
| 167 | : "=r" (to), "=r" (from), "=r" (ret) \ | ||
| 168 | : "0" (to), "1" (from), "2" (ret) \ | ||
| 169 | : "r9", "memory") | ||
| 170 | |||
| 171 | #define __asm_copy_from_user_1(to, from, ret) \ | ||
| 172 | __asm_copy_user_cont(to, from, ret, \ | ||
| 173 | " move.b [%1+],$r9\n" \ | ||
| 174 | "2: move.b $r9,[%0+]\n", \ | ||
| 175 | "3: addq 1,%2\n" \ | ||
| 176 | " clear.b [%0+]\n", \ | ||
| 177 | " .dword 2b,3b\n") | ||
| 178 | |||
| 179 | #define __asm_copy_from_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 180 | __asm_copy_user_cont(to, from, ret, \ | ||
| 181 | " move.w [%1+],$r9\n" \ | ||
| 182 | "2: move.w $r9,[%0+]\n" COPY, \ | ||
| 183 | "3: addq 2,%2\n" \ | ||
| 184 | " clear.w [%0+]\n" FIXUP, \ | ||
| 185 | " .dword 2b,3b\n" TENTRY) | ||
| 186 | |||
| 187 | #define __asm_copy_from_user_2(to, from, ret) \ | ||
| 188 | __asm_copy_from_user_2x_cont(to, from, ret, "", "", "") | ||
| 189 | |||
| 190 | #define __asm_copy_from_user_3(to, from, ret) \ | ||
| 191 | __asm_copy_from_user_2x_cont(to, from, ret, \ | ||
| 192 | " move.b [%1+],$r9\n" \ | ||
| 193 | "4: move.b $r9,[%0+]\n", \ | ||
| 194 | "5: addq 1,%2\n" \ | ||
| 195 | " clear.b [%0+]\n", \ | ||
| 196 | " .dword 4b,5b\n") | ||
| 197 | |||
| 198 | #define __asm_copy_from_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 199 | __asm_copy_user_cont(to, from, ret, \ | ||
| 200 | " move.d [%1+],$r9\n" \ | ||
| 201 | "2: move.d $r9,[%0+]\n" COPY, \ | ||
| 202 | "3: addq 4,%2\n" \ | ||
| 203 | " clear.d [%0+]\n" FIXUP, \ | ||
| 204 | " .dword 2b,3b\n" TENTRY) | ||
| 205 | |||
| 206 | #define __asm_copy_from_user_4(to, from, ret) \ | ||
| 207 | __asm_copy_from_user_4x_cont(to, from, ret, "", "", "") | ||
| 208 | |||
| 209 | #define __asm_copy_from_user_5(to, from, ret) \ | ||
| 210 | __asm_copy_from_user_4x_cont(to, from, ret, \ | ||
| 211 | " move.b [%1+],$r9\n" \ | ||
| 212 | "4: move.b $r9,[%0+]\n", \ | ||
| 213 | "5: addq 1,%2\n" \ | ||
| 214 | " clear.b [%0+]\n", \ | ||
| 215 | " .dword 4b,5b\n") | ||
| 216 | |||
| 217 | #define __asm_copy_from_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 218 | __asm_copy_from_user_4x_cont(to, from, ret, \ | ||
| 219 | " move.w [%1+],$r9\n" \ | ||
| 220 | "4: move.w $r9,[%0+]\n" COPY, \ | ||
| 221 | "5: addq 2,%2\n" \ | ||
| 222 | " clear.w [%0+]\n" FIXUP, \ | ||
| 223 | " .dword 4b,5b\n" TENTRY) | ||
| 224 | |||
| 225 | #define __asm_copy_from_user_6(to, from, ret) \ | ||
| 226 | __asm_copy_from_user_6x_cont(to, from, ret, "", "", "") | ||
| 227 | |||
| 228 | #define __asm_copy_from_user_7(to, from, ret) \ | ||
| 229 | __asm_copy_from_user_6x_cont(to, from, ret, \ | ||
| 230 | " move.b [%1+],$r9\n" \ | ||
| 231 | "6: move.b $r9,[%0+]\n", \ | ||
| 232 | "7: addq 1,%2\n" \ | ||
| 233 | " clear.b [%0+]\n", \ | ||
| 234 | " .dword 6b,7b\n") | ||
| 235 | |||
| 236 | #define __asm_copy_from_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 237 | __asm_copy_from_user_4x_cont(to, from, ret, \ | ||
| 238 | " move.d [%1+],$r9\n" \ | ||
| 239 | "4: move.d $r9,[%0+]\n" COPY, \ | ||
| 240 | "5: addq 4,%2\n" \ | ||
| 241 | " clear.d [%0+]\n" FIXUP, \ | ||
| 242 | " .dword 4b,5b\n" TENTRY) | ||
| 243 | |||
| 244 | #define __asm_copy_from_user_8(to, from, ret) \ | ||
| 245 | __asm_copy_from_user_8x_cont(to, from, ret, "", "", "") | ||
| 246 | |||
| 247 | #define __asm_copy_from_user_9(to, from, ret) \ | ||
| 248 | __asm_copy_from_user_8x_cont(to, from, ret, \ | ||
| 249 | " move.b [%1+],$r9\n" \ | ||
| 250 | "6: move.b $r9,[%0+]\n", \ | ||
| 251 | "7: addq 1,%2\n" \ | ||
| 252 | " clear.b [%0+]\n", \ | ||
| 253 | " .dword 6b,7b\n") | ||
| 254 | |||
| 255 | #define __asm_copy_from_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 256 | __asm_copy_from_user_8x_cont(to, from, ret, \ | ||
| 257 | " move.w [%1+],$r9\n" \ | ||
| 258 | "6: move.w $r9,[%0+]\n" COPY, \ | ||
| 259 | "7: addq 2,%2\n" \ | ||
| 260 | " clear.w [%0+]\n" FIXUP, \ | ||
| 261 | " .dword 6b,7b\n" TENTRY) | ||
| 262 | |||
| 263 | #define __asm_copy_from_user_10(to, from, ret) \ | ||
| 264 | __asm_copy_from_user_10x_cont(to, from, ret, "", "", "") | ||
| 265 | |||
| 266 | #define __asm_copy_from_user_11(to, from, ret) \ | ||
| 267 | __asm_copy_from_user_10x_cont(to, from, ret, \ | ||
| 268 | " move.b [%1+],$r9\n" \ | ||
| 269 | "8: move.b $r9,[%0+]\n", \ | ||
| 270 | "9: addq 1,%2\n" \ | ||
| 271 | " clear.b [%0+]\n", \ | ||
| 272 | " .dword 8b,9b\n") | ||
| 273 | |||
| 274 | #define __asm_copy_from_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 275 | __asm_copy_from_user_8x_cont(to, from, ret, \ | ||
| 276 | " move.d [%1+],$r9\n" \ | ||
| 277 | "6: move.d $r9,[%0+]\n" COPY, \ | ||
| 278 | "7: addq 4,%2\n" \ | ||
| 279 | " clear.d [%0+]\n" FIXUP, \ | ||
| 280 | " .dword 6b,7b\n" TENTRY) | ||
| 281 | |||
| 282 | #define __asm_copy_from_user_12(to, from, ret) \ | ||
| 283 | __asm_copy_from_user_12x_cont(to, from, ret, "", "", "") | ||
| 284 | |||
| 285 | #define __asm_copy_from_user_13(to, from, ret) \ | ||
| 286 | __asm_copy_from_user_12x_cont(to, from, ret, \ | ||
| 287 | " move.b [%1+],$r9\n" \ | ||
| 288 | "8: move.b $r9,[%0+]\n", \ | ||
| 289 | "9: addq 1,%2\n" \ | ||
| 290 | " clear.b [%0+]\n", \ | ||
| 291 | " .dword 8b,9b\n") | ||
| 292 | |||
| 293 | #define __asm_copy_from_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 294 | __asm_copy_from_user_12x_cont(to, from, ret, \ | ||
| 295 | " move.w [%1+],$r9\n" \ | ||
| 296 | "8: move.w $r9,[%0+]\n" COPY, \ | ||
| 297 | "9: addq 2,%2\n" \ | ||
| 298 | " clear.w [%0+]\n" FIXUP, \ | ||
| 299 | " .dword 8b,9b\n" TENTRY) | ||
| 300 | |||
| 301 | #define __asm_copy_from_user_14(to, from, ret) \ | ||
| 302 | __asm_copy_from_user_14x_cont(to, from, ret, "", "", "") | ||
| 303 | |||
| 304 | #define __asm_copy_from_user_15(to, from, ret) \ | ||
| 305 | __asm_copy_from_user_14x_cont(to, from, ret, \ | ||
| 306 | " move.b [%1+],$r9\n" \ | ||
| 307 | "10: move.b $r9,[%0+]\n", \ | ||
| 308 | "11: addq 1,%2\n" \ | ||
| 309 | " clear.b [%0+]\n", \ | ||
| 310 | " .dword 10b,11b\n") | ||
| 311 | |||
| 312 | #define __asm_copy_from_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 313 | __asm_copy_from_user_12x_cont(to, from, ret, \ | ||
| 314 | " move.d [%1+],$r9\n" \ | ||
| 315 | "8: move.d $r9,[%0+]\n" COPY, \ | ||
| 316 | "9: addq 4,%2\n" \ | ||
| 317 | " clear.d [%0+]\n" FIXUP, \ | ||
| 318 | " .dword 8b,9b\n" TENTRY) | ||
| 319 | |||
| 320 | #define __asm_copy_from_user_16(to, from, ret) \ | ||
| 321 | __asm_copy_from_user_16x_cont(to, from, ret, "", "", "") | ||
| 322 | |||
| 323 | #define __asm_copy_from_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 324 | __asm_copy_from_user_16x_cont(to, from, ret, \ | ||
| 325 | " move.d [%1+],$r9\n" \ | ||
| 326 | "10: move.d $r9,[%0+]\n" COPY, \ | ||
| 327 | "11: addq 4,%2\n" \ | ||
| 328 | " clear.d [%0+]\n" FIXUP, \ | ||
| 329 | " .dword 10b,11b\n" TENTRY) | ||
| 330 | |||
| 331 | #define __asm_copy_from_user_20(to, from, ret) \ | ||
| 332 | __asm_copy_from_user_20x_cont(to, from, ret, "", "", "") | ||
| 333 | |||
| 334 | #define __asm_copy_from_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 335 | __asm_copy_from_user_20x_cont(to, from, ret, \ | ||
| 336 | " move.d [%1+],$r9\n" \ | ||
| 337 | "12: move.d $r9,[%0+]\n" COPY, \ | ||
| 338 | "13: addq 4,%2\n" \ | ||
| 339 | " clear.d [%0+]\n" FIXUP, \ | ||
| 340 | " .dword 12b,13b\n" TENTRY) | ||
| 341 | |||
| 342 | #define __asm_copy_from_user_24(to, from, ret) \ | ||
| 343 | __asm_copy_from_user_24x_cont(to, from, ret, "", "", "") | ||
| 344 | |||
| 345 | /* And now, the to-user ones. */ | ||
| 346 | |||
| 347 | #define __asm_copy_to_user_1(to, from, ret) \ | ||
| 348 | __asm_copy_user_cont(to, from, ret, \ | ||
| 349 | " move.b [%1+],$r9\n" \ | ||
| 350 | " move.b $r9,[%0+]\n2:\n", \ | ||
| 351 | "3: addq 1,%2\n", \ | ||
| 352 | " .dword 2b,3b\n") | ||
| 353 | |||
| 354 | #define __asm_copy_to_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 355 | __asm_copy_user_cont(to, from, ret, \ | ||
| 356 | " move.w [%1+],$r9\n" \ | ||
| 357 | " move.w $r9,[%0+]\n2:\n" COPY, \ | ||
| 358 | "3: addq 2,%2\n" FIXUP, \ | ||
| 359 | " .dword 2b,3b\n" TENTRY) | ||
| 360 | |||
| 361 | #define __asm_copy_to_user_2(to, from, ret) \ | ||
| 362 | __asm_copy_to_user_2x_cont(to, from, ret, "", "", "") | ||
| 363 | |||
| 364 | #define __asm_copy_to_user_3(to, from, ret) \ | ||
| 365 | __asm_copy_to_user_2x_cont(to, from, ret, \ | ||
| 366 | " move.b [%1+],$r9\n" \ | ||
| 367 | " move.b $r9,[%0+]\n4:\n", \ | ||
| 368 | "5: addq 1,%2\n", \ | ||
| 369 | " .dword 4b,5b\n") | ||
| 370 | |||
| 371 | #define __asm_copy_to_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 372 | __asm_copy_user_cont(to, from, ret, \ | ||
| 373 | " move.d [%1+],$r9\n" \ | ||
| 374 | " move.d $r9,[%0+]\n2:\n" COPY, \ | ||
| 375 | "3: addq 4,%2\n" FIXUP, \ | ||
| 376 | " .dword 2b,3b\n" TENTRY) | ||
| 377 | |||
| 378 | #define __asm_copy_to_user_4(to, from, ret) \ | ||
| 379 | __asm_copy_to_user_4x_cont(to, from, ret, "", "", "") | ||
| 380 | |||
| 381 | #define __asm_copy_to_user_5(to, from, ret) \ | ||
| 382 | __asm_copy_to_user_4x_cont(to, from, ret, \ | ||
| 383 | " move.b [%1+],$r9\n" \ | ||
| 384 | " move.b $r9,[%0+]\n4:\n", \ | ||
| 385 | "5: addq 1,%2\n", \ | ||
| 386 | " .dword 4b,5b\n") | ||
| 387 | |||
| 388 | #define __asm_copy_to_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 389 | __asm_copy_to_user_4x_cont(to, from, ret, \ | ||
| 390 | " move.w [%1+],$r9\n" \ | ||
| 391 | " move.w $r9,[%0+]\n4:\n" COPY, \ | ||
| 392 | "5: addq 2,%2\n" FIXUP, \ | ||
| 393 | " .dword 4b,5b\n" TENTRY) | ||
| 394 | |||
| 395 | #define __asm_copy_to_user_6(to, from, ret) \ | ||
| 396 | __asm_copy_to_user_6x_cont(to, from, ret, "", "", "") | ||
| 397 | |||
| 398 | #define __asm_copy_to_user_7(to, from, ret) \ | ||
| 399 | __asm_copy_to_user_6x_cont(to, from, ret, \ | ||
| 400 | " move.b [%1+],$r9\n" \ | ||
| 401 | " move.b $r9,[%0+]\n6:\n", \ | ||
| 402 | "7: addq 1,%2\n", \ | ||
| 403 | " .dword 6b,7b\n") | ||
| 404 | |||
| 405 | #define __asm_copy_to_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 406 | __asm_copy_to_user_4x_cont(to, from, ret, \ | ||
| 407 | " move.d [%1+],$r9\n" \ | ||
| 408 | " move.d $r9,[%0+]\n4:\n" COPY, \ | ||
| 409 | "5: addq 4,%2\n" FIXUP, \ | ||
| 410 | " .dword 4b,5b\n" TENTRY) | ||
| 411 | |||
| 412 | #define __asm_copy_to_user_8(to, from, ret) \ | ||
| 413 | __asm_copy_to_user_8x_cont(to, from, ret, "", "", "") | ||
| 414 | |||
| 415 | #define __asm_copy_to_user_9(to, from, ret) \ | ||
| 416 | __asm_copy_to_user_8x_cont(to, from, ret, \ | ||
| 417 | " move.b [%1+],$r9\n" \ | ||
| 418 | " move.b $r9,[%0+]\n6:\n", \ | ||
| 419 | "7: addq 1,%2\n", \ | ||
| 420 | " .dword 6b,7b\n") | ||
| 421 | |||
| 422 | #define __asm_copy_to_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 423 | __asm_copy_to_user_8x_cont(to, from, ret, \ | ||
| 424 | " move.w [%1+],$r9\n" \ | ||
| 425 | " move.w $r9,[%0+]\n6:\n" COPY, \ | ||
| 426 | "7: addq 2,%2\n" FIXUP, \ | ||
| 427 | " .dword 6b,7b\n" TENTRY) | ||
| 428 | |||
| 429 | #define __asm_copy_to_user_10(to, from, ret) \ | ||
| 430 | __asm_copy_to_user_10x_cont(to, from, ret, "", "", "") | ||
| 431 | |||
| 432 | #define __asm_copy_to_user_11(to, from, ret) \ | ||
| 433 | __asm_copy_to_user_10x_cont(to, from, ret, \ | ||
| 434 | " move.b [%1+],$r9\n" \ | ||
| 435 | " move.b $r9,[%0+]\n8:\n", \ | ||
| 436 | "9: addq 1,%2\n", \ | ||
| 437 | " .dword 8b,9b\n") | ||
| 438 | |||
| 439 | #define __asm_copy_to_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 440 | __asm_copy_to_user_8x_cont(to, from, ret, \ | ||
| 441 | " move.d [%1+],$r9\n" \ | ||
| 442 | " move.d $r9,[%0+]\n6:\n" COPY, \ | ||
| 443 | "7: addq 4,%2\n" FIXUP, \ | ||
| 444 | " .dword 6b,7b\n" TENTRY) | ||
| 445 | |||
| 446 | #define __asm_copy_to_user_12(to, from, ret) \ | ||
| 447 | __asm_copy_to_user_12x_cont(to, from, ret, "", "", "") | ||
| 448 | |||
| 449 | #define __asm_copy_to_user_13(to, from, ret) \ | ||
| 450 | __asm_copy_to_user_12x_cont(to, from, ret, \ | ||
| 451 | " move.b [%1+],$r9\n" \ | ||
| 452 | " move.b $r9,[%0+]\n8:\n", \ | ||
| 453 | "9: addq 1,%2\n", \ | ||
| 454 | " .dword 8b,9b\n") | ||
| 455 | |||
| 456 | #define __asm_copy_to_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 457 | __asm_copy_to_user_12x_cont(to, from, ret, \ | ||
| 458 | " move.w [%1+],$r9\n" \ | ||
| 459 | " move.w $r9,[%0+]\n8:\n" COPY, \ | ||
| 460 | "9: addq 2,%2\n" FIXUP, \ | ||
| 461 | " .dword 8b,9b\n" TENTRY) | ||
| 462 | |||
| 463 | #define __asm_copy_to_user_14(to, from, ret) \ | ||
| 464 | __asm_copy_to_user_14x_cont(to, from, ret, "", "", "") | ||
| 465 | |||
| 466 | #define __asm_copy_to_user_15(to, from, ret) \ | ||
| 467 | __asm_copy_to_user_14x_cont(to, from, ret, \ | ||
| 468 | " move.b [%1+],$r9\n" \ | ||
| 469 | " move.b $r9,[%0+]\n10:\n", \ | ||
| 470 | "11: addq 1,%2\n", \ | ||
| 471 | " .dword 10b,11b\n") | ||
| 472 | |||
| 473 | #define __asm_copy_to_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 474 | __asm_copy_to_user_12x_cont(to, from, ret, \ | ||
| 475 | " move.d [%1+],$r9\n" \ | ||
| 476 | " move.d $r9,[%0+]\n8:\n" COPY, \ | ||
| 477 | "9: addq 4,%2\n" FIXUP, \ | ||
| 478 | " .dword 8b,9b\n" TENTRY) | ||
| 479 | |||
| 480 | #define __asm_copy_to_user_16(to, from, ret) \ | ||
| 481 | __asm_copy_to_user_16x_cont(to, from, ret, "", "", "") | ||
| 482 | |||
| 483 | #define __asm_copy_to_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 484 | __asm_copy_to_user_16x_cont(to, from, ret, \ | ||
| 485 | " move.d [%1+],$r9\n" \ | ||
| 486 | " move.d $r9,[%0+]\n10:\n" COPY, \ | ||
| 487 | "11: addq 4,%2\n" FIXUP, \ | ||
| 488 | " .dword 10b,11b\n" TENTRY) | ||
| 489 | |||
| 490 | #define __asm_copy_to_user_20(to, from, ret) \ | ||
| 491 | __asm_copy_to_user_20x_cont(to, from, ret, "", "", "") | ||
| 492 | |||
| 493 | #define __asm_copy_to_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ | ||
| 494 | __asm_copy_to_user_20x_cont(to, from, ret, \ | ||
| 495 | " move.d [%1+],$r9\n" \ | ||
| 496 | " move.d $r9,[%0+]\n12:\n" COPY, \ | ||
| 497 | "13: addq 4,%2\n" FIXUP, \ | ||
| 498 | " .dword 12b,13b\n" TENTRY) | ||
| 499 | |||
| 500 | #define __asm_copy_to_user_24(to, from, ret) \ | ||
| 501 | __asm_copy_to_user_24x_cont(to, from, ret, "", "", "") | ||
| 502 | |||
| 503 | /* Define a few clearing asms with exception handlers. */ | ||
| 504 | |||
| 505 | /* This frame-asm is like the __asm_copy_user_cont one, but has one less | ||
| 506 | input. */ | ||
| 507 | |||
| 508 | #define __asm_clear(to, ret, CLEAR, FIXUP, TENTRY) \ | ||
| 509 | __asm__ __volatile__ ( \ | ||
| 510 | CLEAR \ | ||
| 511 | "1:\n" \ | ||
| 512 | " .section .fixup,\"ax\"\n" \ | ||
| 513 | FIXUP \ | ||
| 514 | " jump 1b\n" \ | ||
| 515 | " .previous\n" \ | ||
| 516 | " .section __ex_table,\"a\"\n" \ | ||
| 517 | TENTRY \ | ||
| 518 | " .previous" \ | ||
| 519 | : "=r" (to), "=r" (ret) \ | ||
| 520 | : "0" (to), "1" (ret) \ | ||
| 521 | : "memory") | ||
| 522 | |||
| 523 | #define __asm_clear_1(to, ret) \ | ||
| 524 | __asm_clear(to, ret, \ | ||
| 525 | " clear.b [%0+]\n2:\n", \ | ||
| 526 | "3: addq 1,%1\n", \ | ||
| 527 | " .dword 2b,3b\n") | ||
| 528 | |||
| 529 | #define __asm_clear_2(to, ret) \ | ||
| 530 | __asm_clear(to, ret, \ | ||
| 531 | " clear.w [%0+]\n2:\n", \ | ||
| 532 | "3: addq 2,%1\n", \ | ||
| 533 | " .dword 2b,3b\n") | ||
| 534 | |||
| 535 | #define __asm_clear_3(to, ret) \ | ||
| 536 | __asm_clear(to, ret, \ | ||
| 537 | " clear.w [%0+]\n" \ | ||
| 538 | "2: clear.b [%0+]\n3:\n", \ | ||
| 539 | "4: addq 2,%1\n" \ | ||
| 540 | "5: addq 1,%1\n", \ | ||
| 541 | " .dword 2b,4b\n" \ | ||
| 542 | " .dword 3b,5b\n") | ||
| 543 | |||
| 544 | #define __asm_clear_4x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ | ||
| 545 | __asm_clear(to, ret, \ | ||
| 546 | " clear.d [%0+]\n2:\n" CLEAR, \ | ||
| 547 | "3: addq 4,%1\n" FIXUP, \ | ||
| 548 | " .dword 2b,3b\n" TENTRY) | ||
| 549 | |||
| 550 | #define __asm_clear_4(to, ret) \ | ||
| 551 | __asm_clear_4x_cont(to, ret, "", "", "") | ||
| 552 | |||
| 553 | #define __asm_clear_8x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ | ||
| 554 | __asm_clear_4x_cont(to, ret, \ | ||
| 555 | " clear.d [%0+]\n4:\n" CLEAR, \ | ||
| 556 | "5: addq 4,%1\n" FIXUP, \ | ||
| 557 | " .dword 4b,5b\n" TENTRY) | ||
| 558 | |||
| 559 | #define __asm_clear_8(to, ret) \ | ||
| 560 | __asm_clear_8x_cont(to, ret, "", "", "") | ||
| 561 | |||
| 562 | #define __asm_clear_12x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ | ||
| 563 | __asm_clear_8x_cont(to, ret, \ | ||
| 564 | " clear.d [%0+]\n6:\n" CLEAR, \ | ||
| 565 | "7: addq 4,%1\n" FIXUP, \ | ||
| 566 | " .dword 6b,7b\n" TENTRY) | ||
| 567 | |||
| 568 | #define __asm_clear_12(to, ret) \ | ||
| 569 | __asm_clear_12x_cont(to, ret, "", "", "") | ||
| 570 | |||
| 571 | #define __asm_clear_16x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ | ||
| 572 | __asm_clear_12x_cont(to, ret, \ | ||
| 573 | " clear.d [%0+]\n8:\n" CLEAR, \ | ||
| 574 | "9: addq 4,%1\n" FIXUP, \ | ||
| 575 | " .dword 8b,9b\n" TENTRY) | ||
| 576 | |||
| 577 | #define __asm_clear_16(to, ret) \ | ||
| 578 | __asm_clear_16x_cont(to, ret, "", "", "") | ||
| 579 | |||
| 580 | #define __asm_clear_20x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ | ||
| 581 | __asm_clear_16x_cont(to, ret, \ | ||
| 582 | " clear.d [%0+]\n10:\n" CLEAR, \ | ||
| 583 | "11: addq 4,%1\n" FIXUP, \ | ||
| 584 | " .dword 10b,11b\n" TENTRY) | ||
| 585 | |||
| 586 | #define __asm_clear_20(to, ret) \ | ||
| 587 | __asm_clear_20x_cont(to, ret, "", "", "") | ||
| 588 | |||
| 589 | #define __asm_clear_24x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ | ||
| 590 | __asm_clear_20x_cont(to, ret, \ | ||
| 591 | " clear.d [%0+]\n12:\n" CLEAR, \ | ||
| 592 | "13: addq 4,%1\n" FIXUP, \ | ||
| 593 | " .dword 12b,13b\n" TENTRY) | ||
| 594 | |||
| 595 | #define __asm_clear_24(to, ret) \ | ||
| 596 | __asm_clear_24x_cont(to, ret, "", "", "") | ||
| 597 | |||
| 598 | /* | ||
| 599 | * Return the size of a string (including the ending 0) | ||
| 600 | * | ||
| 601 | * Return length of string in userspace including terminating 0 | ||
| 602 | * or 0 for error. Return a value greater than N if too long. | ||
| 603 | */ | ||
| 604 | |||
| 605 | extern inline long | ||
| 606 | strnlen_user(const char *s, long n) | ||
| 607 | { | ||
| 608 | long res, tmp1; | ||
| 609 | |||
| 610 | if (!access_ok(VERIFY_READ, s, 0)) | ||
| 611 | return 0; | ||
| 612 | |||
| 613 | /* | ||
| 614 | * This code is deduced from: | ||
| 615 | * | ||
| 616 | * tmp1 = n; | ||
| 617 | * while (tmp1-- > 0 && *s++) | ||
| 618 | * ; | ||
| 619 | * | ||
| 620 | * res = n - tmp1; | ||
| 621 | * | ||
| 622 | * (with tweaks). | ||
| 623 | */ | ||
| 624 | |||
| 625 | __asm__ __volatile__ ( | ||
| 626 | " move.d %1,$r9\n" | ||
| 627 | "0:\n" | ||
| 628 | " ble 1f\n" | ||
| 629 | " subq 1,$r9\n" | ||
| 630 | |||
| 631 | " test.b [%0+]\n" | ||
| 632 | " bne 0b\n" | ||
| 633 | " test.d $r9\n" | ||
| 634 | "1:\n" | ||
| 635 | " move.d %1,%0\n" | ||
| 636 | " sub.d $r9,%0\n" | ||
| 637 | "2:\n" | ||
| 638 | " .section .fixup,\"ax\"\n" | ||
| 639 | |||
| 640 | "3: clear.d %0\n" | ||
| 641 | " jump 2b\n" | ||
| 642 | |||
| 643 | /* There's one address for a fault at the first move, and | ||
| 644 | two possible PC values for a fault at the second move, | ||
| 645 | being a delay-slot filler. However, the branch-target | ||
| 646 | for the second move is the same as the first address. | ||
| 647 | Just so you don't get confused... */ | ||
| 648 | " .previous\n" | ||
| 649 | " .section __ex_table,\"a\"\n" | ||
| 650 | " .dword 0b,3b\n" | ||
| 651 | " .dword 1b,3b\n" | ||
| 652 | " .previous\n" | ||
| 653 | : "=r" (res), "=r" (tmp1) | ||
| 654 | : "0" (s), "1" (n) | ||
| 655 | : "r9"); | ||
| 656 | |||
| 657 | return res; | ||
| 658 | } | ||
| 659 | |||
| 660 | #endif | ||
diff --git a/include/asm-cris/arch-v10/unistd.h b/include/asm-cris/arch-v10/unistd.h new file mode 100644 index 000000000000..d1a38b9e6264 --- /dev/null +++ b/include/asm-cris/arch-v10/unistd.h | |||
| @@ -0,0 +1,148 @@ | |||
| 1 | #ifndef _ASM_CRIS_ARCH_UNISTD_H_ | ||
| 2 | #define _ASM_CRIS_ARCH_UNISTD_H_ | ||
| 3 | |||
| 4 | /* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */ | ||
| 5 | /* | ||
| 6 | * Don't remove the .ifnc tests; they are an insurance against | ||
| 7 | * any hard-to-spot gcc register allocation bugs. | ||
| 8 | */ | ||
| 9 | #define _syscall0(type,name) \ | ||
| 10 | type name(void) \ | ||
| 11 | { \ | ||
| 12 | register long __a __asm__ ("r10"); \ | ||
| 13 | register long __n_ __asm__ ("r9") = (__NR_##name); \ | ||
| 14 | __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \ | ||
| 15 | ".err\n\t" \ | ||
| 16 | ".endif\n\t" \ | ||
| 17 | "break 13" \ | ||
| 18 | : "=r" (__a) \ | ||
| 19 | : "r" (__n_)); \ | ||
| 20 | if (__a >= 0) \ | ||
| 21 | return (type) __a; \ | ||
| 22 | errno = -__a; \ | ||
| 23 | return (type) -1; \ | ||
| 24 | } | ||
| 25 | |||
| 26 | #define _syscall1(type,name,type1,arg1) \ | ||
| 27 | type name(type1 arg1) \ | ||
| 28 | { \ | ||
| 29 | register long __a __asm__ ("r10") = (long) arg1; \ | ||
| 30 | register long __n_ __asm__ ("r9") = (__NR_##name); \ | ||
| 31 | __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \ | ||
| 32 | ".err\n\t" \ | ||
| 33 | ".endif\n\t" \ | ||
| 34 | "break 13" \ | ||
| 35 | : "=r" (__a) \ | ||
| 36 | : "r" (__n_), "0" (__a)); \ | ||
| 37 | if (__a >= 0) \ | ||
| 38 | return (type) __a; \ | ||
| 39 | errno = -__a; \ | ||
| 40 | return (type) -1; \ | ||
| 41 | } | ||
| 42 | |||
| 43 | #define _syscall2(type,name,type1,arg1,type2,arg2) \ | ||
| 44 | type name(type1 arg1,type2 arg2) \ | ||
| 45 | { \ | ||
| 46 | register long __a __asm__ ("r10") = (long) arg1; \ | ||
| 47 | register long __b __asm__ ("r11") = (long) arg2; \ | ||
| 48 | register long __n_ __asm__ ("r9") = (__NR_##name); \ | ||
| 49 | __asm__ __volatile__ (".ifnc %0%1%3,$r10$r9$r11\n\t" \ | ||
| 50 | ".err\n\t" \ | ||
| 51 | ".endif\n\t" \ | ||
| 52 | "break 13" \ | ||
| 53 | : "=r" (__a) \ | ||
| 54 | : "r" (__n_), "0" (__a), "r" (__b)); \ | ||
| 55 | if (__a >= 0) \ | ||
| 56 | return (type) __a; \ | ||
| 57 | errno = -__a; \ | ||
| 58 | return (type) -1; \ | ||
| 59 | } | ||
| 60 | |||
| 61 | #define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \ | ||
| 62 | type name(type1 arg1,type2 arg2,type3 arg3) \ | ||
| 63 | { \ | ||
| 64 | register long __a __asm__ ("r10") = (long) arg1; \ | ||
| 65 | register long __b __asm__ ("r11") = (long) arg2; \ | ||
| 66 | register long __c __asm__ ("r12") = (long) arg3; \ | ||
| 67 | register long __n_ __asm__ ("r9") = (__NR_##name); \ | ||
| 68 | __asm__ __volatile__ (".ifnc %0%1%3%4,$r10$r9$r11$r12\n\t" \ | ||
| 69 | ".err\n\t" \ | ||
| 70 | ".endif\n\t" \ | ||
| 71 | "break 13" \ | ||
| 72 | : "=r" (__a) \ | ||
| 73 | : "r" (__n_), "0" (__a), "r" (__b), "r" (__c)); \ | ||
| 74 | if (__a >= 0) \ | ||
| 75 | return (type) __a; \ | ||
| 76 | errno = -__a; \ | ||
| 77 | return (type) -1; \ | ||
| 78 | } | ||
| 79 | |||
| 80 | #define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \ | ||
| 81 | type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4) \ | ||
| 82 | { \ | ||
| 83 | register long __a __asm__ ("r10") = (long) arg1; \ | ||
| 84 | register long __b __asm__ ("r11") = (long) arg2; \ | ||
| 85 | register long __c __asm__ ("r12") = (long) arg3; \ | ||
| 86 | register long __d __asm__ ("r13") = (long) arg4; \ | ||
| 87 | register long __n_ __asm__ ("r9") = (__NR_##name); \ | ||
| 88 | __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \ | ||
| 89 | ".err\n\t" \ | ||
| 90 | ".endif\n\t" \ | ||
| 91 | "break 13" \ | ||
| 92 | : "=r" (__a) \ | ||
| 93 | : "r" (__n_), "0" (__a), "r" (__b), \ | ||
| 94 | "r" (__c), "r" (__d)); \ | ||
| 95 | if (__a >= 0) \ | ||
| 96 | return (type) __a; \ | ||
| 97 | errno = -__a; \ | ||
| 98 | return (type) -1; \ | ||
| 99 | } | ||
| 100 | |||
| 101 | #define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ | ||
| 102 | type5,arg5) \ | ||
| 103 | type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5) \ | ||
| 104 | { \ | ||
| 105 | register long __a __asm__ ("r10") = (long) arg1; \ | ||
| 106 | register long __b __asm__ ("r11") = (long) arg2; \ | ||
| 107 | register long __c __asm__ ("r12") = (long) arg3; \ | ||
| 108 | register long __d __asm__ ("r13") = (long) arg4; \ | ||
| 109 | register long __n_ __asm__ ("r9") = (__NR_##name); \ | ||
| 110 | __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \ | ||
| 111 | ".err\n\t" \ | ||
| 112 | ".endif\n\t" \ | ||
| 113 | "move %6,$mof\n\t" \ | ||
| 114 | "break 13" \ | ||
| 115 | : "=r" (__a) \ | ||
| 116 | : "r" (__n_), "0" (__a), "r" (__b), \ | ||
| 117 | "r" (__c), "r" (__d), "g" (arg5)); \ | ||
| 118 | if (__a >= 0) \ | ||
| 119 | return (type) __a; \ | ||
| 120 | errno = -__a; \ | ||
| 121 | return (type) -1; \ | ||
| 122 | } | ||
| 123 | |||
| 124 | #define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ | ||
| 125 | type5,arg5,type6,arg6) \ | ||
| 126 | type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5,type6 arg6) \ | ||
| 127 | { \ | ||
| 128 | register long __a __asm__ ("r10") = (long) arg1; \ | ||
| 129 | register long __b __asm__ ("r11") = (long) arg2; \ | ||
| 130 | register long __c __asm__ ("r12") = (long) arg3; \ | ||
| 131 | register long __d __asm__ ("r13") = (long) arg4; \ | ||
| 132 | register long __n_ __asm__ ("r9") = (__NR_##name); \ | ||
| 133 | __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \ | ||
| 134 | ".err\n\t" \ | ||
| 135 | ".endif\n\t" \ | ||
| 136 | "move %6,$mof\n\tmove %7,$srp\n\t" \ | ||
| 137 | "break 13" \ | ||
| 138 | : "=r" (__a) \ | ||
| 139 | : "r" (__n_), "0" (__a), "r" (__b), \ | ||
| 140 | "r" (__c), "r" (__d), "g" (arg5), "g" (arg6)\ | ||
| 141 | : "srp"); \ | ||
| 142 | if (__a >= 0) \ | ||
| 143 | return (type) __a; \ | ||
| 144 | errno = -__a; \ | ||
| 145 | return (type) -1; \ | ||
| 146 | } | ||
| 147 | |||
| 148 | #endif | ||
diff --git a/include/asm-cris/arch-v10/user.h b/include/asm-cris/arch-v10/user.h new file mode 100644 index 000000000000..9303ea77c915 --- /dev/null +++ b/include/asm-cris/arch-v10/user.h | |||
| @@ -0,0 +1,46 @@ | |||
| 1 | #ifndef __ASM_CRIS_ARCH_USER_H | ||
| 2 | #define __ASM_CRIS_ARCH_USER_H | ||
| 3 | |||
| 4 | /* User mode registers, used for core dumps. In order to keep ELF_NGREG | ||
| 5 | sensible we let all registers be 32 bits. The csr registers are included | ||
| 6 | for future use. */ | ||
| 7 | struct user_regs_struct { | ||
| 8 | unsigned long r0; /* General registers. */ | ||
| 9 | unsigned long r1; | ||
| 10 | unsigned long r2; | ||
| 11 | unsigned long r3; | ||
| 12 | unsigned long r4; | ||
| 13 | unsigned long r5; | ||
| 14 | unsigned long r6; | ||
| 15 | unsigned long r7; | ||
| 16 | unsigned long r8; | ||
| 17 | unsigned long r9; | ||
| 18 | unsigned long r10; | ||
| 19 | unsigned long r11; | ||
| 20 | unsigned long r12; | ||
| 21 | unsigned long r13; | ||
| 22 | unsigned long sp; /* Stack pointer. */ | ||
| 23 | unsigned long pc; /* Program counter. */ | ||
| 24 | unsigned long p0; /* Constant zero (only 8 bits). */ | ||
| 25 | unsigned long vr; /* Version register (only 8 bits). */ | ||
| 26 | unsigned long p2; /* Reserved. */ | ||
| 27 | unsigned long p3; /* Reserved. */ | ||
| 28 | unsigned long p4; /* Constant zero (only 16 bits). */ | ||
| 29 | unsigned long ccr; /* Condition code register (only 16 bits). */ | ||
| 30 | unsigned long p6; /* Reserved. */ | ||
| 31 | unsigned long mof; /* Multiply overflow register. */ | ||
| 32 | unsigned long p8; /* Constant zero. */ | ||
| 33 | unsigned long ibr; /* Not accessible. */ | ||
| 34 | unsigned long irp; /* Not accessible. */ | ||
| 35 | unsigned long srp; /* Subroutine return pointer. */ | ||
| 36 | unsigned long bar; /* Not accessible. */ | ||
| 37 | unsigned long dccr; /* Dword condition code register. */ | ||
| 38 | unsigned long brp; /* Not accessible. */ | ||
| 39 | unsigned long usp; /* User-mode stack pointer. Same as sp when | ||
| 40 | in user mode. */ | ||
| 41 | unsigned long csrinstr; /* Internal status registers. */ | ||
| 42 | unsigned long csraddr; | ||
| 43 | unsigned long csrdata; | ||
| 44 | }; | ||
| 45 | |||
| 46 | #endif | ||
diff --git a/include/asm-cris/atomic.h b/include/asm-cris/atomic.h new file mode 100644 index 000000000000..b3dfea5a71e4 --- /dev/null +++ b/include/asm-cris/atomic.h | |||
| @@ -0,0 +1,150 @@ | |||
| 1 | /* $Id: atomic.h,v 1.3 2001/07/25 16:15:19 bjornw Exp $ */ | ||
| 2 | |||
| 3 | #ifndef __ASM_CRIS_ATOMIC__ | ||
| 4 | #define __ASM_CRIS_ATOMIC__ | ||
| 5 | |||
| 6 | #include <asm/system.h> | ||
| 7 | |||
| 8 | /* | ||
| 9 | * Atomic operations that C can't guarantee us. Useful for | ||
| 10 | * resource counting etc.. | ||
| 11 | */ | ||
| 12 | |||
| 13 | /* | ||
| 14 | * Make sure gcc doesn't try to be clever and move things around | ||
| 15 | * on us. We need to use _exactly_ the address the user gave us, | ||
| 16 | * not some alias that contains the same information. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #define __atomic_fool_gcc(x) (*(struct { int a[100]; } *)x) | ||
| 20 | |||
| 21 | typedef struct { int counter; } atomic_t; | ||
| 22 | |||
| 23 | #define ATOMIC_INIT(i) { (i) } | ||
| 24 | |||
| 25 | #define atomic_read(v) ((v)->counter) | ||
| 26 | #define atomic_set(v,i) (((v)->counter) = (i)) | ||
| 27 | |||
| 28 | /* These should be written in asm but we do it in C for now. */ | ||
| 29 | |||
| 30 | extern __inline__ void atomic_add(int i, volatile atomic_t *v) | ||
| 31 | { | ||
| 32 | unsigned long flags; | ||
| 33 | local_save_flags(flags); | ||
| 34 | local_irq_disable(); | ||
| 35 | v->counter += i; | ||
| 36 | local_irq_restore(flags); | ||
| 37 | } | ||
| 38 | |||
| 39 | extern __inline__ void atomic_sub(int i, volatile atomic_t *v) | ||
| 40 | { | ||
| 41 | unsigned long flags; | ||
| 42 | local_save_flags(flags); | ||
| 43 | local_irq_disable(); | ||
| 44 | v->counter -= i; | ||
| 45 | local_irq_restore(flags); | ||
| 46 | } | ||
| 47 | |||
| 48 | extern __inline__ int atomic_add_return(int i, volatile atomic_t *v) | ||
| 49 | { | ||
| 50 | unsigned long flags; | ||
| 51 | int retval; | ||
| 52 | local_save_flags(flags); | ||
| 53 | local_irq_disable(); | ||
| 54 | retval = (v->counter += i); | ||
| 55 | local_irq_restore(flags); | ||
| 56 | return retval; | ||
| 57 | } | ||
| 58 | |||
| 59 | #define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0) | ||
| 60 | |||
| 61 | extern __inline__ int atomic_sub_return(int i, volatile atomic_t *v) | ||
| 62 | { | ||
| 63 | unsigned long flags; | ||
| 64 | int retval; | ||
| 65 | local_save_flags(flags); | ||
| 66 | local_irq_disable(); | ||
| 67 | retval = (v->counter -= i); | ||
| 68 | local_irq_restore(flags); | ||
| 69 | return retval; | ||
| 70 | } | ||
| 71 | |||
| 72 | extern __inline__ int atomic_sub_and_test(int i, volatile atomic_t *v) | ||
| 73 | { | ||
| 74 | int retval; | ||
| 75 | unsigned long flags; | ||
| 76 | local_save_flags(flags); | ||
| 77 | local_irq_disable(); | ||
| 78 | retval = (v->counter -= i) == 0; | ||
| 79 | local_irq_restore(flags); | ||
| 80 | return retval; | ||
| 81 | } | ||
| 82 | |||
| 83 | extern __inline__ void atomic_inc(volatile atomic_t *v) | ||
| 84 | { | ||
| 85 | unsigned long flags; | ||
| 86 | local_save_flags(flags); | ||
| 87 | local_irq_disable(); | ||
| 88 | (v->counter)++; | ||
| 89 | local_irq_restore(flags); | ||
| 90 | } | ||
| 91 | |||
| 92 | extern __inline__ void atomic_dec(volatile atomic_t *v) | ||
| 93 | { | ||
| 94 | unsigned long flags; | ||
| 95 | local_save_flags(flags); | ||
| 96 | local_irq_disable(); | ||
| 97 | (v->counter)--; | ||
| 98 | local_irq_restore(flags); | ||
| 99 | } | ||
| 100 | |||
| 101 | extern __inline__ int atomic_inc_return(volatile atomic_t *v) | ||
| 102 | { | ||
| 103 | unsigned long flags; | ||
| 104 | int retval; | ||
| 105 | local_save_flags(flags); | ||
| 106 | local_irq_disable(); | ||
| 107 | retval = (v->counter)++; | ||
| 108 | local_irq_restore(flags); | ||
| 109 | return retval; | ||
| 110 | } | ||
| 111 | |||
| 112 | extern __inline__ int atomic_dec_return(volatile atomic_t *v) | ||
| 113 | { | ||
| 114 | unsigned long flags; | ||
| 115 | int retval; | ||
| 116 | local_save_flags(flags); | ||
| 117 | local_irq_disable(); | ||
| 118 | retval = (v->counter)--; | ||
| 119 | local_irq_restore(flags); | ||
| 120 | return retval; | ||
| 121 | } | ||
| 122 | extern __inline__ int atomic_dec_and_test(volatile atomic_t *v) | ||
| 123 | { | ||
| 124 | int retval; | ||
| 125 | unsigned long flags; | ||
| 126 | local_save_flags(flags); | ||
| 127 | local_irq_disable(); | ||
| 128 | retval = --(v->counter) == 0; | ||
| 129 | local_irq_restore(flags); | ||
| 130 | return retval; | ||
| 131 | } | ||
| 132 | |||
| 133 | extern __inline__ int atomic_inc_and_test(volatile atomic_t *v) | ||
| 134 | { | ||
| 135 | int retval; | ||
| 136 | unsigned long flags; | ||
| 137 | local_save_flags(flags); | ||
| 138 | local_irq_disable(); | ||
| 139 | retval = ++(v->counter) == 0; | ||
| 140 | local_irq_restore(flags); | ||
| 141 | return retval; | ||
| 142 | } | ||
| 143 | |||
| 144 | /* Atomic operations are already serializing */ | ||
| 145 | #define smp_mb__before_atomic_dec() barrier() | ||
| 146 | #define smp_mb__after_atomic_dec() barrier() | ||
| 147 | #define smp_mb__before_atomic_inc() barrier() | ||
| 148 | #define smp_mb__after_atomic_inc() barrier() | ||
| 149 | |||
| 150 | #endif | ||
diff --git a/include/asm-cris/axisflashmap.h b/include/asm-cris/axisflashmap.h new file mode 100644 index 000000000000..600bb8715d89 --- /dev/null +++ b/include/asm-cris/axisflashmap.h | |||
| @@ -0,0 +1,43 @@ | |||
| 1 | #ifndef __ASM_AXISFLASHMAP_H | ||
| 2 | #define __ASM_AXISFLASHMAP_H | ||
| 3 | |||
| 4 | /* Bootblock parameters are stored at 0xc000 and has the FLASH_BOOT_MAGIC | ||
| 5 | * as start, it ends with 0xFFFFFFFF */ | ||
| 6 | #define FLASH_BOOT_MAGIC 0xbeefcace | ||
| 7 | #define BOOTPARAM_OFFSET 0xc000 | ||
| 8 | /* apps/bootblocktool is used to read and write the parameters, | ||
| 9 | * and it has nothing to do with the partition table. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #define PARTITION_TABLE_OFFSET 10 | ||
| 13 | #define PARTITION_TABLE_MAGIC 0xbeef /* Not a good magic */ | ||
| 14 | |||
| 15 | /* The partitiontable_head is located at offset +10: */ | ||
| 16 | struct partitiontable_head { | ||
| 17 | __u16 magic; /* PARTITION_TABLE_MAGIC */ | ||
| 18 | __u16 size; /* Length of ptable block (not header) */ | ||
| 19 | __u32 checksum; /* simple longword sum */ | ||
| 20 | }; | ||
| 21 | |||
| 22 | /* And followed by partition table entries */ | ||
| 23 | struct partitiontable_entry { | ||
| 24 | __u32 offset; /* Offset is relative to the sector the ptable is in */ | ||
| 25 | __u32 size; | ||
| 26 | __u32 checksum; /* simple longword sum */ | ||
| 27 | __u16 type; | ||
| 28 | __u16 flags; /* bit 0: ro/rw = 1/0 */ | ||
| 29 | __u32 future0; /* 16 bytes reserved for future use */ | ||
| 30 | __u32 future1; | ||
| 31 | __u32 future2; | ||
| 32 | __u32 future3; | ||
| 33 | }; | ||
| 34 | /* ended by an end marker: */ | ||
| 35 | #define PARTITIONTABLE_END_MARKER 0xFFFFFFFF | ||
| 36 | #define PARTITIONTABLE_END_MARKER_SIZE 4 | ||
| 37 | |||
| 38 | /*#define PARTITION_TYPE_RESCUE 0x0000?*/ /* Not used, maybe it should? */ | ||
| 39 | #define PARTITION_TYPE_PARAM 0x0001 | ||
| 40 | #define PARTITION_TYPE_KERNEL 0x0002 | ||
| 41 | #define PARTITION_TYPE_JFFS 0x0003 | ||
| 42 | |||
| 43 | #endif | ||
diff --git a/include/asm-cris/bitops.h b/include/asm-cris/bitops.h new file mode 100644 index 000000000000..d7861115d731 --- /dev/null +++ b/include/asm-cris/bitops.h | |||
| @@ -0,0 +1,387 @@ | |||
| 1 | /* asm/bitops.h for Linux/CRIS | ||
| 2 | * | ||
| 3 | * TODO: asm versions if speed is needed | ||
| 4 | * | ||
| 5 | * All bit operations return 0 if the bit was cleared before the | ||
| 6 | * operation and != 0 if it was not. | ||
| 7 | * | ||
| 8 | * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef _CRIS_BITOPS_H | ||
| 12 | #define _CRIS_BITOPS_H | ||
| 13 | |||
| 14 | /* Currently this is unsuitable for consumption outside the kernel. */ | ||
| 15 | #ifdef __KERNEL__ | ||
| 16 | |||
| 17 | #include <asm/arch/bitops.h> | ||
| 18 | #include <asm/system.h> | ||
| 19 | #include <linux/compiler.h> | ||
| 20 | |||
| 21 | /* | ||
| 22 | * Some hacks to defeat gcc over-optimizations.. | ||
| 23 | */ | ||
| 24 | struct __dummy { unsigned long a[100]; }; | ||
| 25 | #define ADDR (*(struct __dummy *) addr) | ||
| 26 | #define CONST_ADDR (*(const struct __dummy *) addr) | ||
| 27 | |||
| 28 | /* | ||
| 29 | * set_bit - Atomically set a bit in memory | ||
| 30 | * @nr: the bit to set | ||
| 31 | * @addr: the address to start counting from | ||
| 32 | * | ||
| 33 | * This function is atomic and may not be reordered. See __set_bit() | ||
| 34 | * if you do not require the atomic guarantees. | ||
| 35 | * Note that @nr may be almost arbitrarily large; this function is not | ||
| 36 | * restricted to acting on a single-word quantity. | ||
| 37 | */ | ||
| 38 | |||
| 39 | #define set_bit(nr, addr) (void)test_and_set_bit(nr, addr) | ||
| 40 | |||
| 41 | #define __set_bit(nr, addr) (void)__test_and_set_bit(nr, addr) | ||
| 42 | |||
| 43 | /* | ||
| 44 | * clear_bit - Clears a bit in memory | ||
| 45 | * @nr: Bit to clear | ||
| 46 | * @addr: Address to start counting from | ||
| 47 | * | ||
| 48 | * clear_bit() is atomic and may not be reordered. However, it does | ||
| 49 | * not contain a memory barrier, so if it is used for locking purposes, | ||
| 50 | * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() | ||
| 51 | * in order to ensure changes are visible on other processors. | ||
| 52 | */ | ||
| 53 | |||
| 54 | #define clear_bit(nr, addr) (void)test_and_clear_bit(nr, addr) | ||
| 55 | |||
| 56 | #define __clear_bit(nr, addr) (void)__test_and_clear_bit(nr, addr) | ||
| 57 | |||
| 58 | /* | ||
| 59 | * change_bit - Toggle a bit in memory | ||
| 60 | * @nr: Bit to change | ||
| 61 | * @addr: Address to start counting from | ||
| 62 | * | ||
| 63 | * change_bit() is atomic and may not be reordered. | ||
| 64 | * Note that @nr may be almost arbitrarily large; this function is not | ||
| 65 | * restricted to acting on a single-word quantity. | ||
| 66 | */ | ||
| 67 | |||
| 68 | #define change_bit(nr, addr) (void)test_and_change_bit(nr, addr) | ||
| 69 | |||
| 70 | /* | ||
| 71 | * __change_bit - Toggle a bit in memory | ||
| 72 | * @nr: the bit to change | ||
| 73 | * @addr: the address to start counting from | ||
| 74 | * | ||
| 75 | * Unlike change_bit(), this function is non-atomic and may be reordered. | ||
| 76 | * If it's called on the same region of memory simultaneously, the effect | ||
| 77 | * may be that only one operation succeeds. | ||
| 78 | */ | ||
| 79 | |||
| 80 | #define __change_bit(nr, addr) (void)__test_and_change_bit(nr, addr) | ||
| 81 | |||
| 82 | /** | ||
| 83 | * test_and_set_bit - Set a bit and return its old value | ||
| 84 | * @nr: Bit to set | ||
| 85 | * @addr: Address to count from | ||
| 86 | * | ||
| 87 | * This operation is atomic and cannot be reordered. | ||
| 88 | * It also implies a memory barrier. | ||
| 89 | */ | ||
| 90 | |||
| 91 | extern inline int test_and_set_bit(int nr, void *addr) | ||
| 92 | { | ||
| 93 | unsigned int mask, retval; | ||
| 94 | unsigned long flags; | ||
| 95 | unsigned int *adr = (unsigned int *)addr; | ||
| 96 | |||
| 97 | adr += nr >> 5; | ||
| 98 | mask = 1 << (nr & 0x1f); | ||
| 99 | local_save_flags(flags); | ||
| 100 | local_irq_disable(); | ||
| 101 | retval = (mask & *adr) != 0; | ||
| 102 | *adr |= mask; | ||
| 103 | local_irq_restore(flags); | ||
| 104 | return retval; | ||
| 105 | } | ||
| 106 | |||
| 107 | extern inline int __test_and_set_bit(int nr, void *addr) | ||
| 108 | { | ||
| 109 | unsigned int mask, retval; | ||
| 110 | unsigned int *adr = (unsigned int *)addr; | ||
| 111 | |||
| 112 | adr += nr >> 5; | ||
| 113 | mask = 1 << (nr & 0x1f); | ||
| 114 | retval = (mask & *adr) != 0; | ||
| 115 | *adr |= mask; | ||
| 116 | return retval; | ||
| 117 | } | ||
| 118 | |||
| 119 | /* | ||
| 120 | * clear_bit() doesn't provide any barrier for the compiler. | ||
| 121 | */ | ||
| 122 | #define smp_mb__before_clear_bit() barrier() | ||
| 123 | #define smp_mb__after_clear_bit() barrier() | ||
| 124 | |||
| 125 | /** | ||
| 126 | * test_and_clear_bit - Clear a bit and return its old value | ||
| 127 | * @nr: Bit to clear | ||
| 128 | * @addr: Address to count from | ||
| 129 | * | ||
| 130 | * This operation is atomic and cannot be reordered. | ||
| 131 | * It also implies a memory barrier. | ||
| 132 | */ | ||
| 133 | |||
| 134 | extern inline int test_and_clear_bit(int nr, void *addr) | ||
| 135 | { | ||
| 136 | unsigned int mask, retval; | ||
| 137 | unsigned long flags; | ||
| 138 | unsigned int *adr = (unsigned int *)addr; | ||
| 139 | |||
| 140 | adr += nr >> 5; | ||
| 141 | mask = 1 << (nr & 0x1f); | ||
| 142 | local_save_flags(flags); | ||
| 143 | local_irq_disable(); | ||
| 144 | retval = (mask & *adr) != 0; | ||
| 145 | *adr &= ~mask; | ||
| 146 | local_irq_restore(flags); | ||
| 147 | return retval; | ||
| 148 | } | ||
| 149 | |||
| 150 | /** | ||
| 151 | * __test_and_clear_bit - Clear a bit and return its old value | ||
| 152 | * @nr: Bit to clear | ||
| 153 | * @addr: Address to count from | ||
| 154 | * | ||
| 155 | * This operation is non-atomic and can be reordered. | ||
| 156 | * If two examples of this operation race, one can appear to succeed | ||
| 157 | * but actually fail. You must protect multiple accesses with a lock. | ||
| 158 | */ | ||
| 159 | |||
| 160 | extern inline int __test_and_clear_bit(int nr, void *addr) | ||
| 161 | { | ||
| 162 | unsigned int mask, retval; | ||
| 163 | unsigned int *adr = (unsigned int *)addr; | ||
| 164 | |||
| 165 | adr += nr >> 5; | ||
| 166 | mask = 1 << (nr & 0x1f); | ||
| 167 | retval = (mask & *adr) != 0; | ||
| 168 | *adr &= ~mask; | ||
| 169 | return retval; | ||
| 170 | } | ||
| 171 | /** | ||
| 172 | * test_and_change_bit - Change a bit and return its old value | ||
| 173 | * @nr: Bit to change | ||
| 174 | * @addr: Address to count from | ||
| 175 | * | ||
| 176 | * This operation is atomic and cannot be reordered. | ||
| 177 | * It also implies a memory barrier. | ||
| 178 | */ | ||
| 179 | |||
| 180 | extern inline int test_and_change_bit(int nr, void *addr) | ||
| 181 | { | ||
| 182 | unsigned int mask, retval; | ||
| 183 | unsigned long flags; | ||
| 184 | unsigned int *adr = (unsigned int *)addr; | ||
| 185 | adr += nr >> 5; | ||
| 186 | mask = 1 << (nr & 0x1f); | ||
| 187 | local_save_flags(flags); | ||
| 188 | local_irq_disable(); | ||
| 189 | retval = (mask & *adr) != 0; | ||
| 190 | *adr ^= mask; | ||
| 191 | local_irq_restore(flags); | ||
| 192 | return retval; | ||
| 193 | } | ||
| 194 | |||
| 195 | /* WARNING: non atomic and it can be reordered! */ | ||
| 196 | |||
| 197 | extern inline int __test_and_change_bit(int nr, void *addr) | ||
| 198 | { | ||
| 199 | unsigned int mask, retval; | ||
| 200 | unsigned int *adr = (unsigned int *)addr; | ||
| 201 | |||
| 202 | adr += nr >> 5; | ||
| 203 | mask = 1 << (nr & 0x1f); | ||
| 204 | retval = (mask & *adr) != 0; | ||
| 205 | *adr ^= mask; | ||
| 206 | |||
| 207 | return retval; | ||
| 208 | } | ||
| 209 | |||
| 210 | /** | ||
| 211 | * test_bit - Determine whether a bit is set | ||
| 212 | * @nr: bit number to test | ||
| 213 | * @addr: Address to start counting from | ||
| 214 | * | ||
| 215 | * This routine doesn't need to be atomic. | ||
| 216 | */ | ||
| 217 | |||
| 218 | extern inline int test_bit(int nr, const void *addr) | ||
| 219 | { | ||
| 220 | unsigned int mask; | ||
| 221 | unsigned int *adr = (unsigned int *)addr; | ||
| 222 | |||
| 223 | adr += nr >> 5; | ||
| 224 | mask = 1 << (nr & 0x1f); | ||
| 225 | return ((mask & *adr) != 0); | ||
| 226 | } | ||
| 227 | |||
| 228 | /* | ||
| 229 | * Find-bit routines.. | ||
| 230 | */ | ||
| 231 | |||
| 232 | /* | ||
| 233 | * Since we define it "external", it collides with the built-in | ||
| 234 | * definition, which doesn't have the same semantics. We don't want to | ||
| 235 | * use -fno-builtin, so just hide the name ffs. | ||
| 236 | */ | ||
| 237 | #define ffs kernel_ffs | ||
| 238 | |||
| 239 | /* | ||
| 240 | * fls: find last bit set. | ||
| 241 | */ | ||
| 242 | |||
| 243 | #define fls(x) generic_fls(x) | ||
| 244 | |||
| 245 | /* | ||
| 246 | * hweightN - returns the hamming weight of a N-bit word | ||
| 247 | * @x: the word to weigh | ||
| 248 | * | ||
| 249 | * The Hamming Weight of a number is the total number of bits set in it. | ||
| 250 | */ | ||
| 251 | |||
| 252 | #define hweight32(x) generic_hweight32(x) | ||
| 253 | #define hweight16(x) generic_hweight16(x) | ||
| 254 | #define hweight8(x) generic_hweight8(x) | ||
| 255 | |||
| 256 | /** | ||
| 257 | * find_next_zero_bit - find the first zero bit in a memory region | ||
| 258 | * @addr: The address to base the search on | ||
| 259 | * @offset: The bitnumber to start searching at | ||
| 260 | * @size: The maximum size to search | ||
| 261 | */ | ||
| 262 | extern inline int find_next_zero_bit (void * addr, int size, int offset) | ||
| 263 | { | ||
| 264 | unsigned long *p = ((unsigned long *) addr) + (offset >> 5); | ||
| 265 | unsigned long result = offset & ~31UL; | ||
| 266 | unsigned long tmp; | ||
| 267 | |||
| 268 | if (offset >= size) | ||
| 269 | return size; | ||
| 270 | size -= result; | ||
| 271 | offset &= 31UL; | ||
| 272 | if (offset) { | ||
| 273 | tmp = *(p++); | ||
| 274 | tmp |= ~0UL >> (32-offset); | ||
| 275 | if (size < 32) | ||
| 276 | goto found_first; | ||
| 277 | if (~tmp) | ||
| 278 | goto found_middle; | ||
| 279 | size -= 32; | ||
| 280 | result += 32; | ||
| 281 | } | ||
| 282 | while (size & ~31UL) { | ||
| 283 | if (~(tmp = *(p++))) | ||
| 284 | goto found_middle; | ||
| 285 | result += 32; | ||
| 286 | size -= 32; | ||
| 287 | } | ||
| 288 | if (!size) | ||
| 289 | return result; | ||
| 290 | tmp = *p; | ||
| 291 | |||
| 292 | found_first: | ||
| 293 | tmp |= ~0UL >> size; | ||
| 294 | found_middle: | ||
| 295 | return result + ffz(tmp); | ||
| 296 | } | ||
| 297 | |||
| 298 | /** | ||
| 299 | * find_next_bit - find the first set bit in a memory region | ||
| 300 | * @addr: The address to base the search on | ||
| 301 | * @offset: The bitnumber to start searching at | ||
| 302 | * @size: The maximum size to search | ||
| 303 | */ | ||
| 304 | static __inline__ int find_next_bit(void *addr, int size, int offset) | ||
| 305 | { | ||
| 306 | unsigned long *p = ((unsigned long *) addr) + (offset >> 5); | ||
| 307 | unsigned long result = offset & ~31UL; | ||
| 308 | unsigned long tmp; | ||
| 309 | |||
| 310 | if (offset >= size) | ||
| 311 | return size; | ||
| 312 | size -= result; | ||
| 313 | offset &= 31UL; | ||
| 314 | if (offset) { | ||
| 315 | tmp = *(p++); | ||
| 316 | tmp &= (~0UL << offset); | ||
| 317 | if (size < 32) | ||
| 318 | goto found_first; | ||
| 319 | if (tmp) | ||
| 320 | goto found_middle; | ||
| 321 | size -= 32; | ||
| 322 | result += 32; | ||
| 323 | } | ||
| 324 | while (size & ~31UL) { | ||
| 325 | if ((tmp = *(p++))) | ||
| 326 | goto found_middle; | ||
| 327 | result += 32; | ||
| 328 | size -= 32; | ||
| 329 | } | ||
| 330 | if (!size) | ||
| 331 | return result; | ||
| 332 | tmp = *p; | ||
| 333 | |||
| 334 | found_first: | ||
| 335 | tmp &= (~0UL >> (32 - size)); | ||
| 336 | if (tmp == 0UL) /* Are any bits set? */ | ||
| 337 | return result + size; /* Nope. */ | ||
| 338 | found_middle: | ||
| 339 | return result + __ffs(tmp); | ||
| 340 | } | ||
| 341 | |||
| 342 | /** | ||
| 343 | * find_first_zero_bit - find the first zero bit in a memory region | ||
| 344 | * @addr: The address to start the search at | ||
| 345 | * @size: The maximum size to search | ||
| 346 | * | ||
| 347 | * Returns the bit-number of the first zero bit, not the number of the byte | ||
| 348 | * containing a bit. | ||
| 349 | */ | ||
| 350 | |||
| 351 | #define find_first_zero_bit(addr, size) \ | ||
| 352 | find_next_zero_bit((addr), (size), 0) | ||
| 353 | #define find_first_bit(addr, size) \ | ||
| 354 | find_next_bit((addr), (size), 0) | ||
| 355 | |||
| 356 | #define ext2_set_bit test_and_set_bit | ||
| 357 | #define ext2_set_bit_atomic(l,n,a) test_and_set_bit(n,a) | ||
| 358 | #define ext2_clear_bit test_and_clear_bit | ||
| 359 | #define ext2_clear_bit_atomic(l,n,a) test_and_clear_bit(n,a) | ||
| 360 | #define ext2_test_bit test_bit | ||
| 361 | #define ext2_find_first_zero_bit find_first_zero_bit | ||
| 362 | #define ext2_find_next_zero_bit find_next_zero_bit | ||
| 363 | |||
| 364 | /* Bitmap functions for the minix filesystem. */ | ||
| 365 | #define minix_set_bit(nr,addr) test_and_set_bit(nr,addr) | ||
| 366 | #define minix_clear_bit(nr,addr) test_and_clear_bit(nr,addr) | ||
| 367 | #define minix_test_bit(nr,addr) test_bit(nr,addr) | ||
| 368 | #define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size) | ||
| 369 | |||
| 370 | extern inline int sched_find_first_bit(unsigned long *b) | ||
| 371 | { | ||
| 372 | if (unlikely(b[0])) | ||
| 373 | return __ffs(b[0]); | ||
| 374 | if (unlikely(b[1])) | ||
| 375 | return __ffs(b[1]) + 32; | ||
| 376 | if (unlikely(b[2])) | ||
| 377 | return __ffs(b[2]) + 64; | ||
| 378 | if (unlikely(b[3])) | ||
| 379 | return __ffs(b[3]) + 96; | ||
| 380 | if (b[4]) | ||
| 381 | return __ffs(b[4]) + 128; | ||
| 382 | return __ffs(b[5]) + 32 + 128; | ||
| 383 | } | ||
| 384 | |||
| 385 | #endif /* __KERNEL__ */ | ||
| 386 | |||
| 387 | #endif /* _CRIS_BITOPS_H */ | ||
diff --git a/include/asm-cris/bug.h b/include/asm-cris/bug.h new file mode 100644 index 000000000000..8dd6b23c15d6 --- /dev/null +++ b/include/asm-cris/bug.h | |||
| @@ -0,0 +1,4 @@ | |||
| 1 | #ifndef _CRIS_BUG_H | ||
| 2 | #define _CRIS_BUG_H | ||
| 3 | #include <asm-generic/bug.h> | ||
| 4 | #endif | ||
diff --git a/include/asm-cris/bugs.h b/include/asm-cris/bugs.h new file mode 100644 index 000000000000..c5907aac1007 --- /dev/null +++ b/include/asm-cris/bugs.h | |||
| @@ -0,0 +1,21 @@ | |||
| 1 | /* $Id: bugs.h,v 1.2 2001/01/17 17:03:18 bjornw Exp $ | ||
| 2 | * | ||
| 3 | * include/asm-cris/bugs.h | ||
| 4 | * | ||
| 5 | * Copyright (C) 2001 Axis Communications AB | ||
| 6 | */ | ||
| 7 | |||
| 8 | /* | ||
| 9 | * This is included by init/main.c to check for architecture-dependent bugs. | ||
| 10 | * | ||
| 11 | * Needs: | ||
| 12 | * void check_bugs(void); | ||
| 13 | */ | ||
| 14 | |||
| 15 | static void check_bugs(void) | ||
| 16 | { | ||
| 17 | } | ||
| 18 | |||
| 19 | |||
| 20 | |||
| 21 | |||
diff --git a/include/asm-cris/byteorder.h b/include/asm-cris/byteorder.h new file mode 100644 index 000000000000..a1a222adaa9f --- /dev/null +++ b/include/asm-cris/byteorder.h | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | #ifndef _CRIS_BYTEORDER_H | ||
| 2 | #define _CRIS_BYTEORDER_H | ||
| 3 | |||
| 4 | #ifdef __GNUC__ | ||
| 5 | |||
| 6 | #include <asm/arch/byteorder.h> | ||
| 7 | |||
| 8 | /* defines are necessary because the other files detect the presence | ||
| 9 | * of a defined __arch_swab32, not an inline | ||
| 10 | */ | ||
| 11 | |||
| 12 | #define __arch__swab32(x) ___arch__swab32(x) | ||
| 13 | #define __arch__swab16(x) ___arch__swab16(x) | ||
| 14 | |||
| 15 | #if !defined(__STRICT_ANSI__) || defined(__KERNEL__) | ||
| 16 | # define __BYTEORDER_HAS_U64__ | ||
| 17 | # define __SWAB_64_THRU_32__ | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #endif /* __GNUC__ */ | ||
| 21 | |||
| 22 | #include <linux/byteorder/little_endian.h> | ||
| 23 | |||
| 24 | #endif | ||
| 25 | |||
| 26 | |||
diff --git a/include/asm-cris/cache.h b/include/asm-cris/cache.h new file mode 100644 index 000000000000..46a3b26e205a --- /dev/null +++ b/include/asm-cris/cache.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #ifndef _ASM_CACHE_H | ||
| 2 | #define _ASM_CACHE_H | ||
| 3 | |||
| 4 | #include <asm/arch/cache.h> | ||
| 5 | |||
| 6 | #endif /* _ASM_CACHE_H */ | ||
diff --git a/include/asm-cris/cacheflush.h b/include/asm-cris/cacheflush.h new file mode 100644 index 000000000000..72cc71dffe70 --- /dev/null +++ b/include/asm-cris/cacheflush.h | |||
| @@ -0,0 +1,31 @@ | |||
| 1 | #ifndef _CRIS_CACHEFLUSH_H | ||
| 2 | #define _CRIS_CACHEFLUSH_H | ||
| 3 | |||
| 4 | /* Keep includes the same across arches. */ | ||
| 5 | #include <linux/mm.h> | ||
| 6 | |||
| 7 | /* The cache doesn't need to be flushed when TLB entries change because | ||
| 8 | * the cache is mapped to physical memory, not virtual memory | ||
| 9 | */ | ||
| 10 | #define flush_cache_all() do { } while (0) | ||
| 11 | #define flush_cache_mm(mm) do { } while (0) | ||
| 12 | #define flush_cache_range(vma, start, end) do { } while (0) | ||
| 13 | #define flush_cache_page(vma, vmaddr, pfn) do { } while (0) | ||
| 14 | #define flush_dcache_page(page) do { } while (0) | ||
| 15 | #define flush_dcache_mmap_lock(mapping) do { } while (0) | ||
| 16 | #define flush_dcache_mmap_unlock(mapping) do { } while (0) | ||
| 17 | #define flush_icache_range(start, end) do { } while (0) | ||
| 18 | #define flush_icache_page(vma,pg) do { } while (0) | ||
| 19 | #define flush_icache_user_range(vma,pg,adr,len) do { } while (0) | ||
| 20 | #define flush_cache_vmap(start, end) do { } while (0) | ||
| 21 | #define flush_cache_vunmap(start, end) do { } while (0) | ||
| 22 | |||
| 23 | #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ | ||
| 24 | memcpy(dst, src, len) | ||
| 25 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ | ||
| 26 | memcpy(dst, src, len) | ||
| 27 | |||
| 28 | void global_flush_tlb(void); | ||
| 29 | int change_page_attr(struct page *page, int numpages, pgprot_t prot); | ||
| 30 | |||
| 31 | #endif /* _CRIS_CACHEFLUSH_H */ | ||
diff --git a/include/asm-cris/checksum.h b/include/asm-cris/checksum.h new file mode 100644 index 000000000000..15ca8aec5c63 --- /dev/null +++ b/include/asm-cris/checksum.h | |||
| @@ -0,0 +1,87 @@ | |||
| 1 | /* TODO: csum_tcpudp_magic could be speeded up, and csum_fold as well */ | ||
| 2 | |||
| 3 | #ifndef _CRIS_CHECKSUM_H | ||
| 4 | #define _CRIS_CHECKSUM_H | ||
| 5 | |||
| 6 | #include <asm/arch/checksum.h> | ||
| 7 | |||
| 8 | /* | ||
| 9 | * computes the checksum of a memory block at buff, length len, | ||
| 10 | * and adds in "sum" (32-bit) | ||
| 11 | * | ||
| 12 | * returns a 32-bit number suitable for feeding into itself | ||
| 13 | * or csum_tcpudp_magic | ||
| 14 | * | ||
| 15 | * this function must be called with even lengths, except | ||
| 16 | * for the last fragment, which may be odd | ||
| 17 | * | ||
| 18 | * it's best to have buff aligned on a 32-bit boundary | ||
| 19 | */ | ||
| 20 | unsigned int csum_partial(const unsigned char * buff, int len, unsigned int sum); | ||
| 21 | |||
| 22 | /* | ||
| 23 | * the same as csum_partial, but copies from src while it | ||
| 24 | * checksums | ||
| 25 | * | ||
| 26 | * here even more important to align src and dst on a 32-bit (or even | ||
| 27 | * better 64-bit) boundary | ||
| 28 | */ | ||
| 29 | |||
| 30 | unsigned int csum_partial_copy_nocheck(const char *src, char *dst, | ||
| 31 | int len, unsigned int sum); | ||
| 32 | |||
| 33 | /* | ||
| 34 | * Fold a partial checksum into a word | ||
| 35 | */ | ||
| 36 | |||
| 37 | extern inline unsigned int csum_fold(unsigned int sum) | ||
| 38 | { | ||
| 39 | /* the while loop is unnecessary really, it's always enough with two | ||
| 40 | iterations */ | ||
| 41 | |||
| 42 | while(sum >> 16) | ||
| 43 | sum = (sum & 0xffff) + (sum >> 16); /* add in end-around carry */ | ||
| 44 | |||
| 45 | return ~sum; | ||
| 46 | } | ||
| 47 | |||
| 48 | extern unsigned int csum_partial_copy_from_user(const char *src, char *dst, | ||
| 49 | int len, unsigned int sum, | ||
| 50 | int *errptr); | ||
| 51 | |||
| 52 | /* | ||
| 53 | * This is a version of ip_compute_csum() optimized for IP headers, | ||
| 54 | * which always checksum on 4 octet boundaries. | ||
| 55 | * | ||
| 56 | */ | ||
| 57 | |||
| 58 | extern inline unsigned short ip_fast_csum(unsigned char * iph, | ||
| 59 | unsigned int ihl) | ||
| 60 | { | ||
| 61 | return csum_fold(csum_partial(iph, ihl * 4, 0)); | ||
| 62 | } | ||
| 63 | |||
| 64 | /* | ||
| 65 | * computes the checksum of the TCP/UDP pseudo-header | ||
| 66 | * returns a 16-bit checksum, already complemented | ||
| 67 | */ | ||
| 68 | |||
| 69 | extern inline unsigned short int csum_tcpudp_magic(unsigned long saddr, | ||
| 70 | unsigned long daddr, | ||
| 71 | unsigned short len, | ||
| 72 | unsigned short proto, | ||
| 73 | unsigned int sum) | ||
| 74 | { | ||
| 75 | return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum)); | ||
| 76 | } | ||
| 77 | |||
| 78 | /* | ||
| 79 | * this routine is used for miscellaneous IP-like checksums, mainly | ||
| 80 | * in icmp.c | ||
| 81 | */ | ||
| 82 | |||
| 83 | extern inline unsigned short ip_compute_csum(unsigned char * buff, int len) { | ||
| 84 | return csum_fold (csum_partial(buff, len, 0)); | ||
| 85 | } | ||
| 86 | |||
| 87 | #endif | ||
diff --git a/include/asm-cris/cputime.h b/include/asm-cris/cputime.h new file mode 100644 index 000000000000..4446a65656fa --- /dev/null +++ b/include/asm-cris/cputime.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #ifndef __CRIS_CPUTIME_H | ||
| 2 | #define __CRIS_CPUTIME_H | ||
| 3 | |||
| 4 | #include <asm-generic/cputime.h> | ||
| 5 | |||
| 6 | #endif /* __CRIS_CPUTIME_H */ | ||
diff --git a/include/asm-cris/current.h b/include/asm-cris/current.h new file mode 100644 index 000000000000..dce69c99da39 --- /dev/null +++ b/include/asm-cris/current.h | |||
| @@ -0,0 +1,15 @@ | |||
| 1 | #ifndef _CRIS_CURRENT_H | ||
| 2 | #define _CRIS_CURRENT_H | ||
| 3 | |||
| 4 | #include <linux/thread_info.h> | ||
| 5 | |||
| 6 | struct task_struct; | ||
| 7 | |||
| 8 | extern inline struct task_struct * get_current(void) | ||
| 9 | { | ||
| 10 | return current_thread_info()->task; | ||
| 11 | } | ||
| 12 | |||
| 13 | #define current get_current() | ||
| 14 | |||
| 15 | #endif /* !(_CRIS_CURRENT_H) */ | ||
diff --git a/include/asm-cris/delay.h b/include/asm-cris/delay.h new file mode 100644 index 000000000000..efc41aad4845 --- /dev/null +++ b/include/asm-cris/delay.h | |||
| @@ -0,0 +1,24 @@ | |||
| 1 | #ifndef _CRIS_DELAY_H | ||
| 2 | #define _CRIS_DELAY_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * Copyright (C) 1998-2002 Axis Communications AB | ||
| 6 | * | ||
| 7 | * Delay routines, using a pre-computed "loops_per_second" value. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #include <asm/arch/delay.h> | ||
| 11 | |||
| 12 | /* Use only for very small delays ( < 1 msec). */ | ||
| 13 | |||
| 14 | extern unsigned long loops_per_usec; /* arch/cris/mm/init.c */ | ||
| 15 | |||
| 16 | extern __inline__ void udelay(unsigned long usecs) | ||
| 17 | { | ||
| 18 | __delay(usecs * loops_per_usec); | ||
| 19 | } | ||
| 20 | |||
| 21 | #endif /* defined(_CRIS_DELAY_H) */ | ||
| 22 | |||
| 23 | |||
| 24 | |||
diff --git a/include/asm-cris/div64.h b/include/asm-cris/div64.h new file mode 100644 index 000000000000..6cd978cefb28 --- /dev/null +++ b/include/asm-cris/div64.h | |||
| @@ -0,0 +1 @@ | |||
| #include <asm-generic/div64.h> | |||
diff --git a/include/asm-cris/dma-mapping.h b/include/asm-cris/dma-mapping.h new file mode 100644 index 000000000000..0d770f60127a --- /dev/null +++ b/include/asm-cris/dma-mapping.h | |||
| @@ -0,0 +1,125 @@ | |||
| 1 | #ifndef _ASM_CRIS_DMA_MAPPING_H | ||
| 2 | #define _ASM_CRIS_DMA_MAPPING_H | ||
| 3 | |||
| 4 | #include "scatterlist.h" | ||
| 5 | |||
| 6 | static inline int | ||
| 7 | dma_supported(struct device *dev, u64 mask) | ||
| 8 | { | ||
| 9 | BUG(); | ||
| 10 | return 0; | ||
| 11 | } | ||
| 12 | |||
| 13 | static inline int | ||
| 14 | dma_set_mask(struct device *dev, u64 dma_mask) | ||
| 15 | { | ||
| 16 | BUG(); | ||
| 17 | return 1; | ||
| 18 | } | ||
| 19 | |||
| 20 | static inline void * | ||
| 21 | dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, | ||
| 22 | int flag) | ||
| 23 | { | ||
| 24 | BUG(); | ||
| 25 | return NULL; | ||
| 26 | } | ||
| 27 | |||
| 28 | static inline void | ||
| 29 | dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, | ||
| 30 | dma_addr_t dma_handle) | ||
| 31 | { | ||
| 32 | BUG(); | ||
| 33 | } | ||
| 34 | |||
| 35 | static inline dma_addr_t | ||
| 36 | dma_map_single(struct device *dev, void *cpu_addr, size_t size, | ||
| 37 | enum dma_data_direction direction) | ||
| 38 | { | ||
| 39 | BUG(); | ||
| 40 | return 0; | ||
| 41 | } | ||
| 42 | |||
| 43 | static inline void | ||
| 44 | dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, | ||
| 45 | enum dma_data_direction direction) | ||
| 46 | { | ||
| 47 | BUG(); | ||
| 48 | } | ||
| 49 | |||
| 50 | static inline dma_addr_t | ||
| 51 | dma_map_page(struct device *dev, struct page *page, | ||
| 52 | unsigned long offset, size_t size, | ||
| 53 | enum dma_data_direction direction) | ||
| 54 | { | ||
| 55 | BUG(); | ||
| 56 | return 0; | ||
| 57 | } | ||
| 58 | |||
| 59 | static inline void | ||
| 60 | dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size, | ||
| 61 | enum dma_data_direction direction) | ||
| 62 | { | ||
| 63 | BUG(); | ||
| 64 | } | ||
| 65 | |||
| 66 | static inline int | ||
| 67 | dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, | ||
| 68 | enum dma_data_direction direction) | ||
| 69 | { | ||
| 70 | BUG(); | ||
| 71 | return 1; | ||
| 72 | } | ||
| 73 | |||
| 74 | static inline void | ||
| 75 | dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, | ||
| 76 | enum dma_data_direction direction) | ||
| 77 | { | ||
| 78 | BUG(); | ||
| 79 | } | ||
| 80 | |||
| 81 | static inline void | ||
| 82 | dma_sync_single(struct device *dev, dma_addr_t dma_handle, size_t size, | ||
| 83 | enum dma_data_direction direction) | ||
| 84 | { | ||
| 85 | BUG(); | ||
| 86 | } | ||
| 87 | |||
| 88 | static inline void | ||
| 89 | dma_sync_sg(struct device *dev, struct scatterlist *sg, int nelems, | ||
| 90 | enum dma_data_direction direction) | ||
| 91 | { | ||
| 92 | BUG(); | ||
| 93 | } | ||
| 94 | |||
| 95 | /* Now for the API extensions over the pci_ one */ | ||
| 96 | |||
| 97 | #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) | ||
| 98 | #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) | ||
| 99 | #define dma_is_consistent(d) (1) | ||
| 100 | |||
| 101 | static inline int | ||
| 102 | dma_get_cache_alignment(void) | ||
| 103 | { | ||
| 104 | /* no easy way to get cache size on all processors, so return | ||
| 105 | * the maximum possible, to be safe */ | ||
| 106 | return (1 << L1_CACHE_SHIFT_MAX); | ||
| 107 | } | ||
| 108 | |||
| 109 | static inline void | ||
| 110 | dma_sync_single_range(struct device *dev, dma_addr_t dma_handle, | ||
| 111 | unsigned long offset, size_t size, | ||
| 112 | enum dma_data_direction direction) | ||
| 113 | { | ||
| 114 | BUG(); | ||
| 115 | } | ||
| 116 | |||
| 117 | static inline void | ||
| 118 | dma_cache_sync(void *vaddr, size_t size, | ||
| 119 | enum dma_data_direction direction) | ||
| 120 | { | ||
| 121 | BUG(); | ||
| 122 | } | ||
| 123 | |||
| 124 | #endif | ||
| 125 | |||
diff --git a/include/asm-cris/dma.h b/include/asm-cris/dma.h new file mode 100644 index 000000000000..c229fac35cdc --- /dev/null +++ b/include/asm-cris/dma.h | |||
| @@ -0,0 +1,13 @@ | |||
| 1 | /* $Id: dma.h,v 1.2 2001/05/09 12:17:42 johana Exp $ */ | ||
| 2 | |||
| 3 | #ifndef _ASM_DMA_H | ||
| 4 | #define _ASM_DMA_H | ||
| 5 | |||
| 6 | #include <asm/arch/dma.h> | ||
| 7 | |||
| 8 | /* it's useless on the Etrax, but unfortunately needed by the new | ||
| 9 | bootmem allocator (but this should do it for this) */ | ||
| 10 | |||
| 11 | #define MAX_DMA_ADDRESS PAGE_OFFSET | ||
| 12 | |||
| 13 | #endif /* _ASM_DMA_H */ | ||
diff --git a/include/asm-cris/elf.h b/include/asm-cris/elf.h new file mode 100644 index 000000000000..d37fd5c4a567 --- /dev/null +++ b/include/asm-cris/elf.h | |||
| @@ -0,0 +1,61 @@ | |||
| 1 | #ifndef __ASMCRIS_ELF_H | ||
| 2 | #define __ASMCRIS_ELF_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * ELF register definitions.. | ||
| 6 | */ | ||
| 7 | |||
| 8 | #include <asm/arch/elf.h> | ||
| 9 | #include <asm/user.h> | ||
| 10 | |||
| 11 | typedef unsigned long elf_greg_t; | ||
| 12 | |||
| 13 | /* Note that NGREG is defined to ELF_NGREG in include/linux/elfcore.h, and is | ||
| 14 | thus exposed to user-space. */ | ||
| 15 | #define ELF_NGREG (sizeof (struct user_regs_struct) / sizeof(elf_greg_t)) | ||
| 16 | typedef elf_greg_t elf_gregset_t[ELF_NGREG]; | ||
| 17 | |||
| 18 | /* A placeholder; CRIS does not have any fp regs. */ | ||
| 19 | typedef unsigned long elf_fpregset_t; | ||
| 20 | |||
| 21 | /* | ||
| 22 | * This is used to ensure we don't load something for the wrong architecture. | ||
| 23 | */ | ||
| 24 | #define elf_check_arch(x) ( (x)->e_machine == EM_CRIS ) | ||
| 25 | |||
| 26 | /* | ||
| 27 | * These are used to set parameters in the core dumps. | ||
| 28 | */ | ||
| 29 | #define ELF_CLASS ELFCLASS32 | ||
| 30 | #define ELF_DATA ELFDATA2LSB; | ||
| 31 | #define ELF_ARCH EM_CRIS | ||
| 32 | |||
| 33 | #define USE_ELF_CORE_DUMP | ||
| 34 | |||
| 35 | #define ELF_EXEC_PAGESIZE 8192 | ||
| 36 | |||
| 37 | /* This is the location that an ET_DYN program is loaded if exec'ed. Typical | ||
| 38 | use of this is to invoke "./ld.so someprog" to test out a new version of | ||
| 39 | the loader. We need to make sure that it is out of the way of the program | ||
| 40 | that it will "exec", and that there is sufficient room for the brk. */ | ||
| 41 | |||
| 42 | #define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3) | ||
| 43 | |||
| 44 | /* This yields a mask that user programs can use to figure out what | ||
| 45 | instruction set this CPU supports. This could be done in user space, | ||
| 46 | but it's not easy, and we've already done it here. */ | ||
| 47 | |||
| 48 | #define ELF_HWCAP (0) | ||
| 49 | |||
| 50 | /* This yields a string that ld.so will use to load implementation | ||
| 51 | specific libraries for optimization. This is more specific in | ||
| 52 | intent than poking at uname or /proc/cpuinfo. | ||
| 53 | */ | ||
| 54 | |||
| 55 | #define ELF_PLATFORM (NULL) | ||
| 56 | |||
| 57 | #ifdef __KERNEL__ | ||
| 58 | #define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX) | ||
| 59 | #endif | ||
| 60 | |||
| 61 | #endif | ||
diff --git a/include/asm-cris/errno.h b/include/asm-cris/errno.h new file mode 100644 index 000000000000..2bf5eb5fa773 --- /dev/null +++ b/include/asm-cris/errno.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #ifndef _CRIS_ERRNO_H | ||
| 2 | #define _CRIS_ERRNO_H | ||
| 3 | |||
| 4 | #include <asm-generic/errno.h> | ||
| 5 | |||
| 6 | #endif | ||
diff --git a/include/asm-cris/eshlibld.h b/include/asm-cris/eshlibld.h new file mode 100644 index 000000000000..2b577cde17eb --- /dev/null +++ b/include/asm-cris/eshlibld.h | |||
| @@ -0,0 +1,114 @@ | |||
| 1 | /*!************************************************************************** | ||
| 2 | *! | ||
| 3 | *! FILE NAME : eshlibld.h | ||
| 4 | *! | ||
| 5 | *! DESCRIPTION: Prototypes for exported shared library functions | ||
| 6 | *! | ||
| 7 | *! FUNCTIONS : perform_cris_aout_relocations, shlibmod_fork, shlibmod_exit | ||
| 8 | *! (EXPORTED) | ||
| 9 | *! | ||
| 10 | *!--------------------------------------------------------------------------- | ||
| 11 | *! | ||
| 12 | *! (C) Copyright 1998, 1999 Axis Communications AB, LUND, SWEDEN | ||
| 13 | *! | ||
| 14 | *!**************************************************************************/ | ||
| 15 | /* $Id: eshlibld.h,v 1.2 2001/02/23 13:47:33 bjornw Exp $ */ | ||
| 16 | |||
| 17 | #ifndef _cris_relocate_h | ||
| 18 | #define _cris_relocate_h | ||
| 19 | |||
| 20 | /* Please note that this file is also compiled into the xsim simulator. | ||
| 21 | Try to avoid breaking its double use (only works on a little-endian | ||
| 22 | 32-bit machine such as the i386 anyway). | ||
| 23 | |||
| 24 | Use __KERNEL__ when you're about to use kernel functions, | ||
| 25 | (which you should not do here anyway, since this file is | ||
| 26 | used by glibc). | ||
| 27 | Use defined(__KERNEL__) || defined(__elinux__) when doing | ||
| 28 | things that only makes sense on an elinux system. | ||
| 29 | Use __CRIS__ when you're about to do (really) CRIS-specific code. | ||
| 30 | */ | ||
| 31 | |||
| 32 | /* We have dependencies all over the place for the host system | ||
| 33 | for xsim being a linux system, so let's not pretend anything | ||
| 34 | else with #ifdef:s here until fixed. */ | ||
| 35 | #include <linux/config.h> | ||
| 36 | #include <linux/limits.h> | ||
| 37 | |||
| 38 | /* Maybe do sanity checking if file input. */ | ||
| 39 | #undef SANITYCHECK_RELOC | ||
| 40 | |||
| 41 | /* Maybe output debug messages. */ | ||
| 42 | #undef RELOC_DEBUG | ||
| 43 | |||
| 44 | /* Maybe we want to share core as well as disk space. | ||
| 45 | Mainly depends on the config macro CONFIG_SHARE_SHLIB_CORE, but it is | ||
| 46 | assumed that we want to share code when debugging (exposes more | ||
| 47 | trouble). */ | ||
| 48 | #ifndef SHARE_LIB_CORE | ||
| 49 | # if (defined(__KERNEL__) || !defined(RELOC_DEBUG)) \ | ||
| 50 | && !defined(CONFIG_SHARE_SHLIB_CORE) | ||
| 51 | # define SHARE_LIB_CORE 0 | ||
| 52 | # else | ||
| 53 | # define SHARE_LIB_CORE 1 | ||
| 54 | # endif /* __KERNEL__ etc */ | ||
| 55 | #endif /* SHARE_LIB_CORE */ | ||
| 56 | |||
| 57 | |||
| 58 | /* Main exported function; supposed to be called when the program a.out | ||
| 59 | has been read in. */ | ||
| 60 | extern int | ||
| 61 | perform_cris_aout_relocations(unsigned long text, unsigned long tlength, | ||
| 62 | unsigned long data, unsigned long dlength, | ||
| 63 | unsigned long baddr, unsigned long blength, | ||
| 64 | |||
| 65 | /* These may be zero when there's "perfect" | ||
| 66 | position-independent code. */ | ||
| 67 | unsigned char *trel, unsigned long tsrel, | ||
| 68 | unsigned long dsrel, | ||
| 69 | |||
| 70 | /* These will be zero at a first try, to see | ||
| 71 | if code is statically linked. Else a | ||
| 72 | second try, with the symbol table and | ||
| 73 | string table nonzero should be done. */ | ||
| 74 | unsigned char *symbols, unsigned long symlength, | ||
| 75 | unsigned char *strings, unsigned long stringlength, | ||
| 76 | |||
| 77 | /* These will only be used when symbol table | ||
| 78 | information is present. */ | ||
| 79 | char **env, int envc, | ||
| 80 | int euid, int is_suid); | ||
| 81 | |||
| 82 | |||
| 83 | #ifdef RELOC_DEBUG | ||
| 84 | /* Task-specific debug stuff. */ | ||
| 85 | struct task_reloc_debug { | ||
| 86 | struct memdebug *alloclast; | ||
| 87 | unsigned long alloc_total; | ||
| 88 | unsigned long export_total; | ||
| 89 | }; | ||
| 90 | #endif /* RELOC_DEBUG */ | ||
| 91 | |||
| 92 | #if SHARE_LIB_CORE | ||
| 93 | |||
| 94 | /* When code (and some very specific data) is shared and not just | ||
| 95 | dynamically linked, we need to export hooks for exec beginning and | ||
| 96 | end. */ | ||
| 97 | |||
| 98 | struct shlibdep; | ||
| 99 | |||
| 100 | extern void | ||
| 101 | shlibmod_exit(struct shlibdep **deps); | ||
| 102 | |||
| 103 | /* Returns 0 if failure, nonzero for ok. */ | ||
| 104 | extern int | ||
| 105 | shlibmod_fork(struct shlibdep **deps); | ||
| 106 | |||
| 107 | #else /* ! SHARE_LIB_CORE */ | ||
| 108 | # define shlibmod_exit(x) | ||
| 109 | # define shlibmod_fork(x) 1 | ||
| 110 | #endif /* ! SHARE_LIB_CORE */ | ||
| 111 | |||
| 112 | #endif _cris_relocate_h | ||
| 113 | /********************** END OF FILE eshlibld.h *****************************/ | ||
| 114 | |||
diff --git a/include/asm-cris/ethernet.h b/include/asm-cris/ethernet.h new file mode 100644 index 000000000000..30da58a7d00d --- /dev/null +++ b/include/asm-cris/ethernet.h | |||
| @@ -0,0 +1,18 @@ | |||
| 1 | /* | ||
| 2 | * ioctl defines for ethernet driver | ||
| 3 | * | ||
| 4 | * Copyright (c) 2001 Axis Communications AB | ||
| 5 | * | ||
| 6 | * Author: Mikael Starvik | ||
| 7 | * | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef _CRIS_ETHERNET_H | ||
| 11 | #define _CRIS_ETHERNET_H | ||
| 12 | #define SET_ETH_SPEED_AUTO SIOCDEVPRIVATE /* Auto neg speed */ | ||
| 13 | #define SET_ETH_SPEED_10 SIOCDEVPRIVATE+1 /* 10 Mbps */ | ||
| 14 | #define SET_ETH_SPEED_100 SIOCDEVPRIVATE+2 /* 100 Mbps. */ | ||
| 15 | #define SET_ETH_DUPLEX_AUTO SIOCDEVPRIVATE+3 /* Auto neg duplex */ | ||
| 16 | #define SET_ETH_DUPLEX_HALF SIOCDEVPRIVATE+4 /* Full duplex */ | ||
| 17 | #define SET_ETH_DUPLEX_FULL SIOCDEVPRIVATE+5 /* Half duplex */ | ||
| 18 | #endif /* _CRIS_ETHERNET_H */ | ||
diff --git a/include/asm-cris/etraxgpio.h b/include/asm-cris/etraxgpio.h new file mode 100644 index 000000000000..cf04af9635cc --- /dev/null +++ b/include/asm-cris/etraxgpio.h | |||
| @@ -0,0 +1,104 @@ | |||
| 1 | /* $Id: etraxgpio.h,v 1.8 2002/06/17 15:53:07 johana Exp $ */ | ||
| 2 | /* | ||
| 3 | * The following devices are accessable using this driver using | ||
| 4 | * GPIO_MAJOR (120) and a couple of minor numbers: | ||
| 5 | * For ETRAX 100LX (ARCH_V10): | ||
| 6 | * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction | ||
| 7 | * /dev/gpiob minor 1, 8 bit GPIO, each bit can change direction | ||
| 8 | * /dev/leds minor 2, Access to leds depending on kernelconfig | ||
| 9 | * /dev/gpiog minor 3 | ||
| 10 | g0dir, g8_15dir, g16_23dir, g24 dir configurable in R_GEN_CONFIG | ||
| 11 | g1-g7 and g25-g31 is both input and outputs but on different pins | ||
| 12 | Also note that some bits change pins depending on what interfaces | ||
| 13 | are enabled. | ||
| 14 | * | ||
| 15 | * | ||
| 16 | * For ETRAX 200 (ARCH_V32): | ||
| 17 | * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction | ||
| 18 | * /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction | ||
| 19 | * /dev/gpioc minor 2, 18 bit GPIO, each bit can change direction | ||
| 20 | * /dev/gpiod minor 3, 18 bit GPIO, each bit can change direction | ||
| 21 | * /dev/gpioe minor 4, 18 bit GPIO, each bit can change direction | ||
| 22 | * /dev/leds minor 5, Access to leds depending on kernelconfig | ||
| 23 | * | ||
| 24 | */ | ||
| 25 | #ifndef _ASM_ETRAXGPIO_H | ||
| 26 | #define _ASM_ETRAXGPIO_H | ||
| 27 | |||
| 28 | #include <linux/config.h> | ||
| 29 | /* etraxgpio _IOC_TYPE, bits 8 to 15 in ioctl cmd */ | ||
| 30 | #ifdef CONFIG_ETRAX_ARCH_V10 | ||
| 31 | #define ETRAXGPIO_IOCTYPE 43 | ||
| 32 | #define GPIO_MINOR_A 0 | ||
| 33 | #define GPIO_MINOR_B 1 | ||
| 34 | #define GPIO_MINOR_LEDS 2 | ||
| 35 | #define GPIO_MINOR_G 3 | ||
| 36 | #define GPIO_MINOR_LAST 3 | ||
| 37 | #endif | ||
| 38 | #ifdef CONFIG_ETRAX_ARCH_V32 | ||
| 39 | #define ETRAXGPIO_IOCTYPE 43 | ||
| 40 | #define GPIO_MINOR_A 0 | ||
| 41 | #define GPIO_MINOR_B 1 | ||
| 42 | #define GPIO_MINOR_C 2 | ||
| 43 | #define GPIO_MINOR_D 3 | ||
| 44 | #define GPIO_MINOR_E 4 | ||
| 45 | #define GPIO_MINOR_LEDS 5 | ||
| 46 | #define GPIO_MINOR_LAST 5 | ||
| 47 | #endif | ||
| 48 | |||
| 49 | /* supported ioctl _IOC_NR's */ | ||
| 50 | |||
| 51 | #define IO_READBITS 0x1 /* read and return current port bits (obsolete) */ | ||
| 52 | #define IO_SETBITS 0x2 /* set the bits marked by 1 in the argument */ | ||
| 53 | #define IO_CLRBITS 0x3 /* clear the bits marked by 1 in the argument */ | ||
| 54 | |||
| 55 | /* the alarm is waited for by select() */ | ||
| 56 | |||
| 57 | #define IO_HIGHALARM 0x4 /* set alarm on high for bits marked by 1 */ | ||
| 58 | #define IO_LOWALARM 0x5 /* set alarm on low for bits marked by 1 */ | ||
| 59 | #define IO_CLRALARM 0x6 /* clear alarm for bits marked by 1 */ | ||
| 60 | |||
| 61 | /* LED ioctl */ | ||
| 62 | #define IO_LEDACTIVE_SET 0x7 /* set active led | ||
| 63 | * 0=off, 1=green, 2=red, 3=yellow */ | ||
| 64 | |||
| 65 | /* GPIO direction ioctl's */ | ||
| 66 | #define IO_READDIR 0x8 /* Read direction 0=input 1=output (obsolete) */ | ||
| 67 | #define IO_SETINPUT 0x9 /* Set direction for bits set, 0=unchanged 1=input, | ||
| 68 | returns mask with current inputs (obsolete) */ | ||
| 69 | #define IO_SETOUTPUT 0xA /* Set direction for bits set, 0=unchanged 1=output, | ||
| 70 | returns mask with current outputs (obsolete)*/ | ||
| 71 | |||
| 72 | /* LED ioctl extended */ | ||
| 73 | #define IO_LED_SETBIT 0xB | ||
| 74 | #define IO_LED_CLRBIT 0xC | ||
| 75 | |||
| 76 | /* SHUTDOWN ioctl */ | ||
| 77 | #define IO_SHUTDOWN 0xD | ||
| 78 | #define IO_GET_PWR_BT 0xE | ||
| 79 | |||
| 80 | /* Bit toggling in driver settings */ | ||
| 81 | /* bit set in low byte0 is CLK mask (0x00FF), | ||
| 82 | bit set in byte1 is DATA mask (0xFF00) | ||
| 83 | msb, data_mask[7:0] , clk_mask[7:0] | ||
| 84 | */ | ||
| 85 | #define IO_CFG_WRITE_MODE 0xF | ||
| 86 | #define IO_CFG_WRITE_MODE_VALUE(msb, data_mask, clk_mask) \ | ||
| 87 | ( (((msb)&1) << 16) | (((data_mask) &0xFF) << 8) | ((clk_mask) & 0xFF) ) | ||
| 88 | |||
| 89 | /* The following 4 ioctl's take a pointer as argument and handles | ||
| 90 | * 32 bit ports (port G) properly. | ||
| 91 | * These replaces IO_READBITS,IO_SETINPUT AND IO_SETOUTPUT | ||
| 92 | */ | ||
| 93 | #define IO_READ_INBITS 0x10 /* *arg is result of reading the input pins */ | ||
| 94 | #define IO_READ_OUTBITS 0x11 /* *arg is result of reading the output shadow */ | ||
| 95 | #define IO_SETGET_INPUT 0x12 /* bits set in *arg is set to input, | ||
| 96 | * *arg updated with current input pins. | ||
| 97 | */ | ||
| 98 | #define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output, | ||
| 99 | * *arg updated with current output pins. | ||
| 100 | */ | ||
| 101 | |||
| 102 | |||
| 103 | |||
| 104 | #endif | ||
diff --git a/include/asm-cris/etraxi2c.h b/include/asm-cris/etraxi2c.h new file mode 100644 index 000000000000..e369a7620893 --- /dev/null +++ b/include/asm-cris/etraxi2c.h | |||
| @@ -0,0 +1,36 @@ | |||
| 1 | /* $Id: etraxi2c.h,v 1.1 2001/01/18 15:49:57 bjornw Exp $ */ | ||
| 2 | |||
| 3 | #ifndef _LINUX_ETRAXI2C_H | ||
| 4 | #define _LINUX_ETRAXI2C_H | ||
| 5 | |||
| 6 | /* etraxi2c _IOC_TYPE, bits 8 to 15 in ioctl cmd */ | ||
| 7 | |||
| 8 | #define ETRAXI2C_IOCTYPE 44 | ||
| 9 | |||
| 10 | /* supported ioctl _IOC_NR's */ | ||
| 11 | |||
| 12 | /* in write operations, the argument contains both i2c | ||
| 13 | * slave, register and value. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #define I2C_WRITEARG(slave, reg, value) (((slave) << 16) | ((reg) << 8) | (value)) | ||
| 17 | #define I2C_READARG(slave, reg) (((slave) << 16) | ((reg) << 8)) | ||
| 18 | |||
| 19 | #define I2C_ARGSLAVE(arg) ((arg) >> 16) | ||
| 20 | #define I2C_ARGREG(arg) (((arg) >> 8) & 0xff) | ||
| 21 | #define I2C_ARGVALUE(arg) ((arg) & 0xff) | ||
| 22 | |||
| 23 | #define I2C_WRITEREG 0x1 /* write to an i2c register */ | ||
| 24 | #define I2C_READREG 0x2 /* read from an i2c register */ | ||
| 25 | |||
| 26 | /* | ||
| 27 | EXAMPLE usage: | ||
| 28 | |||
| 29 | i2c_arg = I2C_WRITEARG(STA013_WRITE_ADDR, reg, val); | ||
| 30 | ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_WRITEREG), i2c_arg); | ||
| 31 | |||
| 32 | i2c_arg = I2C_READARG(STA013_READ_ADDR, reg); | ||
| 33 | val = ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_READREG), i2c_arg); | ||
| 34 | |||
| 35 | */ | ||
| 36 | #endif | ||
diff --git a/include/asm-cris/fasttimer.h b/include/asm-cris/fasttimer.h new file mode 100644 index 000000000000..69522028baa5 --- /dev/null +++ b/include/asm-cris/fasttimer.h | |||
| @@ -0,0 +1,44 @@ | |||
| 1 | /* $Id: fasttimer.h,v 1.3 2004/05/14 10:19:19 starvik Exp $ | ||
| 2 | * linux/include/asm-cris/fasttimer.h | ||
| 3 | * | ||
| 4 | * Fast timers for ETRAX100LX | ||
| 5 | * This may be useful in other OS than Linux so use 2 space indentation... | ||
| 6 | * Copyright (C) 2000, 2002 Axis Communications AB | ||
| 7 | */ | ||
| 8 | #include <linux/config.h> | ||
| 9 | #include <linux/time.h> /* struct timeval */ | ||
| 10 | #include <linux/timex.h> | ||
| 11 | |||
| 12 | #ifdef CONFIG_ETRAX_FAST_TIMER | ||
| 13 | |||
| 14 | typedef void fast_timer_function_type(unsigned long); | ||
| 15 | |||
| 16 | struct fast_timer{ /* Close to timer_list */ | ||
| 17 | struct fast_timer *next; | ||
| 18 | struct fast_timer *prev; | ||
| 19 | struct timeval tv_set; | ||
| 20 | struct timeval tv_expires; | ||
| 21 | unsigned long delay_us; | ||
| 22 | fast_timer_function_type *function; | ||
| 23 | unsigned long data; | ||
| 24 | const char *name; | ||
| 25 | }; | ||
| 26 | |||
| 27 | extern struct fast_timer *fast_timer_list; | ||
| 28 | |||
| 29 | void start_one_shot_timer(struct fast_timer *t, | ||
| 30 | fast_timer_function_type *function, | ||
| 31 | unsigned long data, | ||
| 32 | unsigned long delay_us, | ||
| 33 | const char *name); | ||
| 34 | |||
| 35 | int del_fast_timer(struct fast_timer * t); | ||
| 36 | /* return 1 if deleted */ | ||
| 37 | |||
| 38 | |||
| 39 | void schedule_usleep(unsigned long us); | ||
| 40 | |||
| 41 | |||
| 42 | void fast_timer_init(void); | ||
| 43 | |||
| 44 | #endif | ||
diff --git a/include/asm-cris/fcntl.h b/include/asm-cris/fcntl.h new file mode 100644 index 000000000000..61c563242b51 --- /dev/null +++ b/include/asm-cris/fcntl.h | |||
| @@ -0,0 +1,90 @@ | |||
| 1 | #ifndef _CRIS_FCNTL_H | ||
| 2 | #define _CRIS_FCNTL_H | ||
| 3 | |||
| 4 | /* verbatim copy of i386 version */ | ||
| 5 | |||
| 6 | /* open/fcntl - O_SYNC is only implemented on blocks devices and on files | ||
| 7 | located on an ext2 file system */ | ||
| 8 | #define O_ACCMODE 0003 | ||
| 9 | #define O_RDONLY 00 | ||
| 10 | #define O_WRONLY 01 | ||
| 11 | #define O_RDWR 02 | ||
| 12 | #define O_CREAT 0100 /* not fcntl */ | ||
| 13 | #define O_EXCL 0200 /* not fcntl */ | ||
| 14 | #define O_NOCTTY 0400 /* not fcntl */ | ||
| 15 | #define O_TRUNC 01000 /* not fcntl */ | ||
| 16 | #define O_APPEND 02000 | ||
| 17 | #define O_NONBLOCK 04000 | ||
| 18 | #define O_NDELAY O_NONBLOCK | ||
| 19 | #define O_SYNC 010000 | ||
| 20 | #define FASYNC 020000 /* fcntl, for BSD compatibility */ | ||
| 21 | #define O_DIRECT 040000 /* direct disk access hint - currently ignored */ | ||
| 22 | #define O_LARGEFILE 0100000 | ||
| 23 | #define O_DIRECTORY 0200000 /* must be a directory */ | ||
| 24 | #define O_NOFOLLOW 0400000 /* don't follow links */ | ||
| 25 | #define O_NOATIME 01000000 | ||
| 26 | |||
| 27 | #define F_DUPFD 0 /* dup */ | ||
| 28 | #define F_GETFD 1 /* get f_flags */ | ||
| 29 | #define F_SETFD 2 /* set f_flags */ | ||
| 30 | #define F_GETFL 3 /* more flags (cloexec) */ | ||
| 31 | #define F_SETFL 4 | ||
| 32 | #define F_GETLK 5 | ||
| 33 | #define F_SETLK 6 | ||
| 34 | #define F_SETLKW 7 | ||
| 35 | |||
| 36 | #define F_SETOWN 8 /* for sockets. */ | ||
| 37 | #define F_GETOWN 9 /* for sockets. */ | ||
| 38 | #define F_SETSIG 10 /* for sockets. */ | ||
| 39 | #define F_GETSIG 11 /* for sockets. */ | ||
| 40 | |||
| 41 | #define F_GETLK64 12 /* using 'struct flock64' */ | ||
| 42 | #define F_SETLK64 13 | ||
| 43 | #define F_SETLKW64 14 | ||
| 44 | |||
| 45 | /* for F_[GET|SET]FL */ | ||
| 46 | #define FD_CLOEXEC 1 /* actually anything with low bit set goes */ | ||
| 47 | |||
| 48 | /* for posix fcntl() and lockf() */ | ||
| 49 | #define F_RDLCK 0 | ||
| 50 | #define F_WRLCK 1 | ||
| 51 | #define F_UNLCK 2 | ||
| 52 | |||
| 53 | /* for old implementation of bsd flock () */ | ||
| 54 | #define F_EXLCK 4 /* or 3 */ | ||
| 55 | #define F_SHLCK 8 /* or 4 */ | ||
| 56 | |||
| 57 | /* for leases */ | ||
| 58 | #define F_INPROGRESS 16 | ||
| 59 | |||
| 60 | /* operations for bsd flock(), also used by the kernel implementation */ | ||
| 61 | #define LOCK_SH 1 /* shared lock */ | ||
| 62 | #define LOCK_EX 2 /* exclusive lock */ | ||
| 63 | #define LOCK_NB 4 /* or'd with one of the above to prevent | ||
| 64 | blocking */ | ||
| 65 | #define LOCK_UN 8 /* remove lock */ | ||
| 66 | |||
| 67 | #define LOCK_MAND 32 /* This is a mandatory flock */ | ||
| 68 | #define LOCK_READ 64 /* ... Which allows concurrent read operations */ | ||
| 69 | #define LOCK_WRITE 128 /* ... Which allows concurrent write operations */ | ||
| 70 | #define LOCK_RW 192 /* ... Which allows concurrent read & write ops */ | ||
| 71 | |||
| 72 | struct flock { | ||
| 73 | short l_type; | ||
| 74 | short l_whence; | ||
| 75 | off_t l_start; | ||
| 76 | off_t l_len; | ||
| 77 | pid_t l_pid; | ||
| 78 | }; | ||
| 79 | |||
| 80 | struct flock64 { | ||
| 81 | short l_type; | ||
| 82 | short l_whence; | ||
| 83 | loff_t l_start; | ||
| 84 | loff_t l_len; | ||
| 85 | pid_t l_pid; | ||
| 86 | }; | ||
| 87 | |||
| 88 | #define F_LINUX_SPECIFIC_BASE 1024 | ||
| 89 | |||
| 90 | #endif | ||
diff --git a/include/asm-cris/hardirq.h b/include/asm-cris/hardirq.h new file mode 100644 index 000000000000..f4d136228ee1 --- /dev/null +++ b/include/asm-cris/hardirq.h | |||
| @@ -0,0 +1,27 @@ | |||
| 1 | #ifndef __ASM_HARDIRQ_H | ||
| 2 | #define __ASM_HARDIRQ_H | ||
| 3 | |||
| 4 | /* only non-SMP supported */ | ||
| 5 | |||
| 6 | #include <linux/threads.h> | ||
| 7 | #include <linux/cache.h> | ||
| 8 | |||
| 9 | /* entry.S is sensitive to the offsets of these fields */ | ||
| 10 | typedef struct { | ||
| 11 | unsigned int __softirq_pending; | ||
| 12 | } ____cacheline_aligned irq_cpustat_t; | ||
| 13 | |||
| 14 | #include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */ | ||
| 15 | |||
| 16 | #define HARDIRQ_BITS 8 | ||
| 17 | |||
| 18 | /* | ||
| 19 | * The hardirq mask has to be large enough to have | ||
| 20 | * space for potentially all IRQ sources in the system | ||
| 21 | * nesting on a single CPU: | ||
| 22 | */ | ||
| 23 | #if (1 << HARDIRQ_BITS) < NR_IRQS | ||
| 24 | # error HARDIRQ_BITS is too low! | ||
| 25 | #endif | ||
| 26 | |||
| 27 | #endif /* __ASM_HARDIRQ_H */ | ||
diff --git a/include/asm-cris/io.h b/include/asm-cris/io.h new file mode 100644 index 000000000000..1d2b51701e8d --- /dev/null +++ b/include/asm-cris/io.h | |||
| @@ -0,0 +1,100 @@ | |||
| 1 | #ifndef _ASM_CRIS_IO_H | ||
| 2 | #define _ASM_CRIS_IO_H | ||
| 3 | |||
| 4 | #include <asm/page.h> /* for __va, __pa */ | ||
| 5 | #include <asm/arch/io.h> | ||
| 6 | |||
| 7 | /* | ||
| 8 | * Change virtual addresses to physical addresses and vv. | ||
| 9 | */ | ||
| 10 | |||
| 11 | extern inline unsigned long virt_to_phys(volatile void * address) | ||
| 12 | { | ||
| 13 | return __pa(address); | ||
| 14 | } | ||
| 15 | |||
| 16 | extern inline void * phys_to_virt(unsigned long address) | ||
| 17 | { | ||
| 18 | return __va(address); | ||
| 19 | } | ||
| 20 | |||
| 21 | extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags); | ||
| 22 | |||
| 23 | extern inline void * ioremap (unsigned long offset, unsigned long size) | ||
| 24 | { | ||
| 25 | return __ioremap(offset, size, 0); | ||
| 26 | } | ||
| 27 | |||
| 28 | extern void iounmap(void *addr); | ||
| 29 | |||
| 30 | /* | ||
| 31 | * IO bus memory addresses are also 1:1 with the physical address | ||
| 32 | */ | ||
| 33 | #define virt_to_bus virt_to_phys | ||
| 34 | #define bus_to_virt phys_to_virt | ||
| 35 | |||
| 36 | /* | ||
| 37 | * readX/writeX() are used to access memory mapped devices. On some | ||
| 38 | * architectures the memory mapped IO stuff needs to be accessed | ||
| 39 | * differently. On the CRIS architecture, we just read/write the | ||
| 40 | * memory location directly. | ||
| 41 | */ | ||
| 42 | #define readb(addr) (*(volatile unsigned char *) (addr)) | ||
| 43 | #define readw(addr) (*(volatile unsigned short *) (addr)) | ||
| 44 | #define readl(addr) (*(volatile unsigned int *) (addr)) | ||
| 45 | #define readb_relaxed(addr) readb(addr) | ||
| 46 | #define readw_relaxed(addr) readw(addr) | ||
| 47 | #define readl_relaxed(addr) readl(addr) | ||
| 48 | #define __raw_readb readb | ||
| 49 | #define __raw_readw readw | ||
| 50 | #define __raw_readl readl | ||
| 51 | |||
| 52 | #define writeb(b,addr) ((*(volatile unsigned char *) (addr)) = (b)) | ||
| 53 | #define writew(b,addr) ((*(volatile unsigned short *) (addr)) = (b)) | ||
| 54 | #define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b)) | ||
| 55 | #define __raw_writeb writeb | ||
| 56 | #define __raw_writew writew | ||
| 57 | #define __raw_writel writel | ||
| 58 | |||
| 59 | #define mmiowb() | ||
| 60 | |||
| 61 | #define memset_io(a,b,c) memset((void *)(a),(b),(c)) | ||
| 62 | #define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) | ||
| 63 | #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) | ||
| 64 | |||
| 65 | /* | ||
| 66 | * Again, CRIS does not require mem IO specific function. | ||
| 67 | */ | ||
| 68 | |||
| 69 | #define eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(void *)(b),(c),(d)) | ||
| 70 | |||
| 71 | /* The following is junk needed for the arch-independent code but which | ||
| 72 | * we never use in the CRIS port | ||
| 73 | */ | ||
| 74 | |||
| 75 | #define IO_SPACE_LIMIT 0xffff | ||
| 76 | #define inb(x) (0) | ||
| 77 | #define inw(x) (0) | ||
| 78 | #define inl(x) (0) | ||
| 79 | #define outb(x,y) | ||
| 80 | #define outw(x,y) | ||
| 81 | #define outl(x,y) | ||
| 82 | #define insb(x,y,z) | ||
| 83 | #define insw(x,y,z) | ||
| 84 | #define insl(x,y,z) | ||
| 85 | #define outsb(x,y,z) | ||
| 86 | #define outsw(x,y,z) | ||
| 87 | #define outsl(x,y,z) | ||
| 88 | |||
| 89 | /* | ||
| 90 | * Convert a physical pointer to a virtual kernel pointer for /dev/mem | ||
| 91 | * access | ||
| 92 | */ | ||
| 93 | #define xlate_dev_mem_ptr(p) __va(p) | ||
| 94 | |||
| 95 | /* | ||
| 96 | * Convert a virtual cached pointer to an uncached pointer | ||
| 97 | */ | ||
| 98 | #define xlate_dev_kmem_ptr(p) p | ||
| 99 | |||
| 100 | #endif | ||
diff --git a/include/asm-cris/ioctl.h b/include/asm-cris/ioctl.h new file mode 100644 index 000000000000..be2d8f667a38 --- /dev/null +++ b/include/asm-cris/ioctl.h | |||
| @@ -0,0 +1,83 @@ | |||
| 1 | /* | ||
| 2 | * linux/ioctl.h for Linux by H.H. Bergman. | ||
| 3 | * | ||
| 4 | * This is the same as the i386 version. | ||
| 5 | */ | ||
| 6 | |||
| 7 | #ifndef _ASMCRIS_IOCTL_H | ||
| 8 | #define _ASMCRIS_IOCTL_H | ||
| 9 | |||
| 10 | /* ioctl command encoding: 32 bits total, command in lower 16 bits, | ||
| 11 | * size of the parameter structure in the lower 14 bits of the | ||
| 12 | * upper 16 bits. | ||
| 13 | * Encoding the size of the parameter structure in the ioctl request | ||
| 14 | * is useful for catching programs compiled with old versions | ||
| 15 | * and to avoid overwriting user space outside the user buffer area. | ||
| 16 | * The highest 2 bits are reserved for indicating the ``access mode''. | ||
| 17 | * NOTE: This limits the max parameter size to 16kB -1 ! | ||
| 18 | */ | ||
| 19 | |||
| 20 | /* | ||
| 21 | * The following is for compatibility across the various Linux | ||
| 22 | * platforms. The i386 ioctl numbering scheme doesn't really enforce | ||
| 23 | * a type field. De facto, however, the top 8 bits of the lower 16 | ||
| 24 | * bits are indeed used as a type field, so we might just as well make | ||
| 25 | * this explicit here. Please be sure to use the decoding macros | ||
| 26 | * below from now on. | ||
| 27 | */ | ||
| 28 | #define _IOC_NRBITS 8 | ||
| 29 | #define _IOC_TYPEBITS 8 | ||
| 30 | #define _IOC_SIZEBITS 14 | ||
| 31 | #define _IOC_DIRBITS 2 | ||
| 32 | |||
| 33 | #define _IOC_NRMASK ((1 << _IOC_NRBITS)-1) | ||
| 34 | #define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1) | ||
| 35 | #define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1) | ||
| 36 | #define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1) | ||
| 37 | |||
| 38 | #define _IOC_NRSHIFT 0 | ||
| 39 | #define _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS) | ||
| 40 | #define _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS) | ||
| 41 | #define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS) | ||
| 42 | |||
| 43 | /* | ||
| 44 | * Direction bits. | ||
| 45 | */ | ||
| 46 | #define _IOC_NONE 0U | ||
| 47 | #define _IOC_WRITE 1U | ||
| 48 | #define _IOC_READ 2U | ||
| 49 | |||
| 50 | #define _IOC(dir,type,nr,size) \ | ||
| 51 | (((dir) << _IOC_DIRSHIFT) | \ | ||
| 52 | ((type) << _IOC_TYPESHIFT) | \ | ||
| 53 | ((nr) << _IOC_NRSHIFT) | \ | ||
| 54 | ((size) << _IOC_SIZESHIFT)) | ||
| 55 | |||
| 56 | /* provoke compile error for invalid uses of size argument */ | ||
| 57 | extern int __invalid_size_argument_for_IOC; | ||
| 58 | #define _IOC_TYPECHECK(t) \ | ||
| 59 | ((sizeof(t) == sizeof(t[1]) && \ | ||
| 60 | sizeof(t) < (1 << _IOC_SIZEBITS)) ? \ | ||
| 61 | sizeof(t) : __invalid_size_argument_for_IOC) | ||
| 62 | |||
| 63 | /* used to create numbers */ | ||
| 64 | #define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0) | ||
| 65 | #define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(size))) | ||
| 66 | #define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size))) | ||
| 67 | #define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size))) | ||
| 68 | |||
| 69 | /* used to decode ioctl numbers.. */ | ||
| 70 | #define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) | ||
| 71 | #define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK) | ||
| 72 | #define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK) | ||
| 73 | #define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK) | ||
| 74 | |||
| 75 | /* ...and for the drivers/sound files... */ | ||
| 76 | |||
| 77 | #define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT) | ||
| 78 | #define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT) | ||
| 79 | #define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT) | ||
| 80 | #define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT) | ||
| 81 | #define IOCSIZE_SHIFT (_IOC_SIZESHIFT) | ||
| 82 | |||
| 83 | #endif /* _ASMCRIS_IOCTL_H */ | ||
diff --git a/include/asm-cris/ioctls.h b/include/asm-cris/ioctls.h new file mode 100644 index 000000000000..97787c3c575f --- /dev/null +++ b/include/asm-cris/ioctls.h | |||
| @@ -0,0 +1,87 @@ | |||
| 1 | #ifndef __ARCH_CRIS_IOCTLS_H__ | ||
| 2 | #define __ARCH_CRIS_IOCTLS_H__ | ||
| 3 | |||
| 4 | /* verbatim copy of asm-i386/ioctls.h */ | ||
| 5 | |||
| 6 | #include <asm/ioctl.h> | ||
| 7 | |||
| 8 | /* 0x54 is just a magic number to make these relatively unique ('T') */ | ||
| 9 | |||
| 10 | #define TCGETS 0x5401 | ||
| 11 | #define TCSETS 0x5402 | ||
| 12 | #define TCSETSW 0x5403 | ||
| 13 | #define TCSETSF 0x5404 | ||
| 14 | #define TCGETA 0x5405 | ||
| 15 | #define TCSETA 0x5406 | ||
| 16 | #define TCSETAW 0x5407 | ||
| 17 | #define TCSETAF 0x5408 | ||
| 18 | #define TCSBRK 0x5409 | ||
| 19 | #define TCXONC 0x540A | ||
| 20 | #define TCFLSH 0x540B | ||
| 21 | #define TIOCEXCL 0x540C | ||
| 22 | #define TIOCNXCL 0x540D | ||
| 23 | #define TIOCSCTTY 0x540E | ||
| 24 | #define TIOCGPGRP 0x540F | ||
| 25 | #define TIOCSPGRP 0x5410 | ||
| 26 | #define TIOCOUTQ 0x5411 | ||
| 27 | #define TIOCSTI 0x5412 | ||
| 28 | #define TIOCGWINSZ 0x5413 | ||
| 29 | #define TIOCSWINSZ 0x5414 | ||
| 30 | #define TIOCMGET 0x5415 | ||
| 31 | #define TIOCMBIS 0x5416 | ||
| 32 | #define TIOCMBIC 0x5417 | ||
| 33 | #define TIOCMSET 0x5418 | ||
| 34 | #define TIOCGSOFTCAR 0x5419 | ||
| 35 | #define TIOCSSOFTCAR 0x541A | ||
| 36 | #define FIONREAD 0x541B | ||
| 37 | #define TIOCINQ FIONREAD | ||
| 38 | #define TIOCLINUX 0x541C | ||
| 39 | #define TIOCCONS 0x541D | ||
| 40 | #define TIOCGSERIAL 0x541E | ||
| 41 | #define TIOCSSERIAL 0x541F | ||
| 42 | #define TIOCPKT 0x5420 | ||
| 43 | #define FIONBIO 0x5421 | ||
| 44 | #define TIOCNOTTY 0x5422 | ||
| 45 | #define TIOCSETD 0x5423 | ||
| 46 | #define TIOCGETD 0x5424 | ||
| 47 | #define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ | ||
| 48 | #define TIOCSBRK 0x5427 /* BSD compatibility */ | ||
| 49 | #define TIOCCBRK 0x5428 /* BSD compatibility */ | ||
| 50 | #define TIOCGSID 0x5429 /* Return the session ID of FD */ | ||
| 51 | #define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ | ||
| 52 | #define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ | ||
| 53 | |||
| 54 | #define FIONCLEX 0x5450 /* these numbers need to be adjusted. */ | ||
| 55 | #define FIOCLEX 0x5451 | ||
| 56 | #define FIOASYNC 0x5452 | ||
| 57 | #define TIOCSERCONFIG 0x5453 | ||
| 58 | #define TIOCSERGWILD 0x5454 | ||
| 59 | #define TIOCSERSWILD 0x5455 | ||
| 60 | #define TIOCGLCKTRMIOS 0x5456 | ||
| 61 | #define TIOCSLCKTRMIOS 0x5457 | ||
| 62 | #define TIOCSERGSTRUCT 0x5458 /* For debugging only */ | ||
| 63 | #define TIOCSERGETLSR 0x5459 /* Get line status register */ | ||
| 64 | #define TIOCSERGETMULTI 0x545A /* Get multiport config */ | ||
| 65 | #define TIOCSERSETMULTI 0x545B /* Set multiport config */ | ||
| 66 | |||
| 67 | #define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */ | ||
| 68 | #define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ | ||
| 69 | #define TIOCGHAYESESP 0x545E /* Get Hayes ESP configuration */ | ||
| 70 | #define TIOCSHAYESESP 0x545F /* Set Hayes ESP configuration */ | ||
| 71 | #define FIOQSIZE 0x5460 | ||
| 72 | |||
| 73 | #define TIOCSERSETRS485 0x5461 /* enable rs-485 */ | ||
| 74 | #define TIOCSERWRRS485 0x5462 /* write rs-485 */ | ||
| 75 | |||
| 76 | /* Used for packet mode */ | ||
| 77 | #define TIOCPKT_DATA 0 | ||
| 78 | #define TIOCPKT_FLUSHREAD 1 | ||
| 79 | #define TIOCPKT_FLUSHWRITE 2 | ||
| 80 | #define TIOCPKT_STOP 4 | ||
| 81 | #define TIOCPKT_START 8 | ||
| 82 | #define TIOCPKT_NOSTOP 16 | ||
| 83 | #define TIOCPKT_DOSTOP 32 | ||
| 84 | |||
| 85 | #define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ | ||
| 86 | |||
| 87 | #endif | ||
diff --git a/include/asm-cris/ipc.h b/include/asm-cris/ipc.h new file mode 100644 index 000000000000..a46e3d9c2a3f --- /dev/null +++ b/include/asm-cris/ipc.h | |||
| @@ -0,0 +1 @@ | |||
| #include <asm-generic/ipc.h> | |||
diff --git a/include/asm-cris/ipcbuf.h b/include/asm-cris/ipcbuf.h new file mode 100644 index 000000000000..8b0c18b02844 --- /dev/null +++ b/include/asm-cris/ipcbuf.h | |||
| @@ -0,0 +1,29 @@ | |||
| 1 | #ifndef __CRIS_IPCBUF_H__ | ||
| 2 | #define __CRIS_IPCBUF_H__ | ||
| 3 | |||
| 4 | /* | ||
| 5 | * The user_ipc_perm structure for CRIS architecture. | ||
| 6 | * Note extra padding because this structure is passed back and forth | ||
| 7 | * between kernel and user space. | ||
| 8 | * | ||
| 9 | * Pad space is left for: | ||
| 10 | * - 32-bit mode_t and seq | ||
| 11 | * - 2 miscellaneous 32-bit values | ||
| 12 | */ | ||
| 13 | |||
| 14 | struct ipc64_perm | ||
| 15 | { | ||
| 16 | __kernel_key_t key; | ||
| 17 | __kernel_uid32_t uid; | ||
| 18 | __kernel_gid32_t gid; | ||
| 19 | __kernel_uid32_t cuid; | ||
| 20 | __kernel_gid32_t cgid; | ||
| 21 | __kernel_mode_t mode; | ||
| 22 | unsigned short __pad1; | ||
| 23 | unsigned short seq; | ||
| 24 | unsigned short __pad2; | ||
| 25 | unsigned long __unused1; | ||
| 26 | unsigned long __unused2; | ||
| 27 | }; | ||
| 28 | |||
| 29 | #endif /* __CRIS_IPCBUF_H__ */ | ||
diff --git a/include/asm-cris/irq.h b/include/asm-cris/irq.h new file mode 100644 index 000000000000..87f342517bb1 --- /dev/null +++ b/include/asm-cris/irq.h | |||
| @@ -0,0 +1,23 @@ | |||
| 1 | #ifndef _ASM_IRQ_H | ||
| 2 | #define _ASM_IRQ_H | ||
| 3 | |||
| 4 | #include <asm/arch/irq.h> | ||
| 5 | |||
| 6 | extern __inline__ int irq_canonicalize(int irq) | ||
| 7 | { | ||
| 8 | return irq; | ||
| 9 | } | ||
| 10 | |||
| 11 | extern void disable_irq(unsigned int); | ||
| 12 | extern void enable_irq(unsigned int); | ||
| 13 | |||
| 14 | #define disable_irq_nosync disable_irq | ||
| 15 | #define enable_irq_nosync enable_irq | ||
| 16 | |||
| 17 | struct irqaction; | ||
| 18 | struct pt_regs; | ||
| 19 | int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *); | ||
| 20 | |||
| 21 | #endif /* _ASM_IRQ_H */ | ||
| 22 | |||
| 23 | |||
diff --git a/include/asm-cris/kmap_types.h b/include/asm-cris/kmap_types.h new file mode 100644 index 000000000000..eec0974c2417 --- /dev/null +++ b/include/asm-cris/kmap_types.h | |||
| @@ -0,0 +1,25 @@ | |||
| 1 | #ifndef _ASM_KMAP_TYPES_H | ||
| 2 | #define _ASM_KMAP_TYPES_H | ||
| 3 | |||
| 4 | /* Dummy header just to define km_type. None of this | ||
| 5 | * is actually used on cris. | ||
| 6 | */ | ||
| 7 | |||
| 8 | enum km_type { | ||
| 9 | KM_BOUNCE_READ, | ||
| 10 | KM_SKB_SUNRPC_DATA, | ||
| 11 | KM_SKB_DATA_SOFTIRQ, | ||
| 12 | KM_USER0, | ||
| 13 | KM_USER1, | ||
| 14 | KM_BIO_SRC_IRQ, | ||
| 15 | KM_BIO_DST_IRQ, | ||
| 16 | KM_PTE0, | ||
| 17 | KM_PTE1, | ||
| 18 | KM_IRQ0, | ||
| 19 | KM_IRQ1, | ||
| 20 | KM_CRYPTO_USER, | ||
| 21 | KM_CRYPTO_SOFTIRQ, | ||
| 22 | KM_TYPE_NR | ||
| 23 | }; | ||
| 24 | |||
| 25 | #endif | ||
diff --git a/include/asm-cris/linkage.h b/include/asm-cris/linkage.h new file mode 100644 index 000000000000..291c2d01c44f --- /dev/null +++ b/include/asm-cris/linkage.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #ifndef __ASM_LINKAGE_H | ||
| 2 | #define __ASM_LINKAGE_H | ||
| 3 | |||
| 4 | /* Nothing to see here... */ | ||
| 5 | |||
| 6 | #endif | ||
diff --git a/include/asm-cris/local.h b/include/asm-cris/local.h new file mode 100644 index 000000000000..c11c530f74d0 --- /dev/null +++ b/include/asm-cris/local.h | |||
| @@ -0,0 +1 @@ | |||
| #include <asm-generic/local.h> | |||
diff --git a/include/asm-cris/mman.h b/include/asm-cris/mman.h new file mode 100644 index 000000000000..8570e72b9502 --- /dev/null +++ b/include/asm-cris/mman.h | |||
| @@ -0,0 +1,45 @@ | |||
| 1 | #ifndef __CRIS_MMAN_H__ | ||
| 2 | #define __CRIS_MMAN_H__ | ||
| 3 | |||
| 4 | /* verbatim copy of asm-i386/ version */ | ||
| 5 | |||
| 6 | #define PROT_READ 0x1 /* page can be read */ | ||
| 7 | #define PROT_WRITE 0x2 /* page can be written */ | ||
| 8 | #define PROT_EXEC 0x4 /* page can be executed */ | ||
| 9 | #define PROT_SEM 0x8 /* page may be used for atomic ops */ | ||
| 10 | #define PROT_NONE 0x0 /* page can not be accessed */ | ||
| 11 | #define PROT_GROWSDOWN 0x01000000 /* mprotect flag: extend change to start of growsdown vma */ | ||
| 12 | #define PROT_GROWSUP 0x02000000 /* mprotect flag: extend change to end of growsup vma */ | ||
| 13 | |||
| 14 | #define MAP_SHARED 0x01 /* Share changes */ | ||
| 15 | #define MAP_PRIVATE 0x02 /* Changes are private */ | ||
| 16 | #define MAP_TYPE 0x0f /* Mask for type of mapping */ | ||
| 17 | #define MAP_FIXED 0x10 /* Interpret addr exactly */ | ||
| 18 | #define MAP_ANONYMOUS 0x20 /* don't use a file */ | ||
| 19 | |||
| 20 | #define MAP_GROWSDOWN 0x0100 /* stack-like segment */ | ||
| 21 | #define MAP_DENYWRITE 0x0800 /* ETXTBSY */ | ||
| 22 | #define MAP_EXECUTABLE 0x1000 /* mark it as an executable */ | ||
| 23 | #define MAP_LOCKED 0x2000 /* pages are locked */ | ||
| 24 | #define MAP_NORESERVE 0x4000 /* don't check for reservations */ | ||
| 25 | #define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */ | ||
| 26 | #define MAP_NONBLOCK 0x10000 /* do not block on IO */ | ||
| 27 | |||
| 28 | #define MS_ASYNC 1 /* sync memory asynchronously */ | ||
| 29 | #define MS_INVALIDATE 2 /* invalidate the caches */ | ||
| 30 | #define MS_SYNC 4 /* synchronous memory sync */ | ||
| 31 | |||
| 32 | #define MCL_CURRENT 1 /* lock all current mappings */ | ||
| 33 | #define MCL_FUTURE 2 /* lock all future mappings */ | ||
| 34 | |||
| 35 | #define MADV_NORMAL 0x0 /* default page-in behavior */ | ||
| 36 | #define MADV_RANDOM 0x1 /* page-in minimum required */ | ||
| 37 | #define MADV_SEQUENTIAL 0x2 /* read-ahead aggressively */ | ||
| 38 | #define MADV_WILLNEED 0x3 /* pre-fault pages */ | ||
| 39 | #define MADV_DONTNEED 0x4 /* discard these pages */ | ||
| 40 | |||
| 41 | /* compatibility flags */ | ||
| 42 | #define MAP_ANON MAP_ANONYMOUS | ||
| 43 | #define MAP_FILE 0 | ||
| 44 | |||
| 45 | #endif /* __CRIS_MMAN_H__ */ | ||
diff --git a/include/asm-cris/mmu.h b/include/asm-cris/mmu.h new file mode 100644 index 000000000000..c40a1bcad06c --- /dev/null +++ b/include/asm-cris/mmu.h | |||
| @@ -0,0 +1,10 @@ | |||
| 1 | /* | ||
| 2 | * CRIS MMU constants and PTE layout | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifndef _CRIS_MMU_H | ||
| 6 | #define _CRIS_MMU_H | ||
| 7 | |||
| 8 | #include <asm/arch/mmu.h> | ||
| 9 | |||
| 10 | #endif | ||
diff --git a/include/asm-cris/mmu_context.h b/include/asm-cris/mmu_context.h new file mode 100644 index 000000000000..f9308c5bbd99 --- /dev/null +++ b/include/asm-cris/mmu_context.h | |||
| @@ -0,0 +1,24 @@ | |||
| 1 | #ifndef __CRIS_MMU_CONTEXT_H | ||
| 2 | #define __CRIS_MMU_CONTEXT_H | ||
| 3 | |||
| 4 | extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm); | ||
| 5 | extern void get_mmu_context(struct mm_struct *mm); | ||
| 6 | extern void destroy_context(struct mm_struct *mm); | ||
| 7 | extern void switch_mm(struct mm_struct *prev, struct mm_struct *next, | ||
| 8 | struct task_struct *tsk); | ||
| 9 | |||
| 10 | #define deactivate_mm(tsk,mm) do { } while (0) | ||
| 11 | |||
| 12 | #define activate_mm(prev,next) switch_mm((prev),(next),NULL) | ||
| 13 | |||
| 14 | /* current active pgd - this is similar to other processors pgd | ||
| 15 | * registers like cr3 on the i386 | ||
| 16 | */ | ||
| 17 | |||
| 18 | extern volatile pgd_t *current_pgd; /* defined in arch/cris/mm/fault.c */ | ||
| 19 | |||
| 20 | static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) | ||
| 21 | { | ||
| 22 | } | ||
| 23 | |||
| 24 | #endif | ||
diff --git a/include/asm-cris/module.h b/include/asm-cris/module.h new file mode 100644 index 000000000000..7ee72311bd78 --- /dev/null +++ b/include/asm-cris/module.h | |||
| @@ -0,0 +1,9 @@ | |||
| 1 | #ifndef _ASM_CRIS_MODULE_H | ||
| 2 | #define _ASM_CRIS_MODULE_H | ||
| 3 | /* cris is simple */ | ||
| 4 | struct mod_arch_specific { }; | ||
| 5 | |||
| 6 | #define Elf_Shdr Elf32_Shdr | ||
| 7 | #define Elf_Sym Elf32_Sym | ||
| 8 | #define Elf_Ehdr Elf32_Ehdr | ||
| 9 | #endif /* _ASM_CRIS_MODULE_H */ | ||
diff --git a/include/asm-cris/msgbuf.h b/include/asm-cris/msgbuf.h new file mode 100644 index 000000000000..ada63df1d574 --- /dev/null +++ b/include/asm-cris/msgbuf.h | |||
| @@ -0,0 +1,33 @@ | |||
| 1 | #ifndef _CRIS_MSGBUF_H | ||
| 2 | #define _CRIS_MSGBUF_H | ||
| 3 | |||
| 4 | /* verbatim copy of asm-i386 version */ | ||
| 5 | |||
| 6 | /* | ||
| 7 | * The msqid64_ds structure for CRIS architecture. | ||
| 8 | * Note extra padding because this structure is passed back and forth | ||
| 9 | * between kernel and user space. | ||
| 10 | * | ||
| 11 | * Pad space is left for: | ||
| 12 | * - 64-bit time_t to solve y2038 problem | ||
| 13 | * - 2 miscellaneous 32-bit values | ||
| 14 | */ | ||
| 15 | |||
| 16 | struct msqid64_ds { | ||
| 17 | struct ipc64_perm msg_perm; | ||
| 18 | __kernel_time_t msg_stime; /* last msgsnd time */ | ||
| 19 | unsigned long __unused1; | ||
| 20 | __kernel_time_t msg_rtime; /* last msgrcv time */ | ||
| 21 | unsigned long __unused2; | ||
| 22 | __kernel_time_t msg_ctime; /* last change time */ | ||
| 23 | unsigned long __unused3; | ||
| 24 | unsigned long msg_cbytes; /* current number of bytes on queue */ | ||
| 25 | unsigned long msg_qnum; /* number of messages in queue */ | ||
| 26 | unsigned long msg_qbytes; /* max number of bytes on queue */ | ||
| 27 | __kernel_pid_t msg_lspid; /* pid of last msgsnd */ | ||
| 28 | __kernel_pid_t msg_lrpid; /* last receive pid */ | ||
| 29 | unsigned long __unused4; | ||
| 30 | unsigned long __unused5; | ||
| 31 | }; | ||
| 32 | |||
| 33 | #endif /* _CRIS_MSGBUF_H */ | ||
diff --git a/include/asm-cris/namei.h b/include/asm-cris/namei.h new file mode 100644 index 000000000000..8a3be7a6d9f6 --- /dev/null +++ b/include/asm-cris/namei.h | |||
| @@ -0,0 +1,17 @@ | |||
| 1 | /* $Id: namei.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ | ||
| 2 | * linux/include/asm-cris/namei.h | ||
| 3 | * | ||
| 4 | * Included from linux/fs/namei.c | ||
| 5 | */ | ||
| 6 | |||
| 7 | #ifndef __CRIS_NAMEI_H | ||
| 8 | #define __CRIS_NAMEI_H | ||
| 9 | |||
| 10 | /* used to find file-system prefixes for doing emulations | ||
| 11 | * see for example asm-sparc/namei.h | ||
| 12 | * we don't use it... | ||
| 13 | */ | ||
| 14 | |||
| 15 | #define __emul_prefix() NULL | ||
| 16 | |||
| 17 | #endif /* __CRIS_NAMEI_H */ | ||
diff --git a/include/asm-cris/page.h b/include/asm-cris/page.h new file mode 100644 index 000000000000..ddd8915e41e6 --- /dev/null +++ b/include/asm-cris/page.h | |||
| @@ -0,0 +1,105 @@ | |||
| 1 | #ifndef _CRIS_PAGE_H | ||
| 2 | #define _CRIS_PAGE_H | ||
| 3 | |||
| 4 | #include <linux/config.h> | ||
| 5 | #include <asm/arch/page.h> | ||
| 6 | |||
| 7 | /* PAGE_SHIFT determines the page size */ | ||
| 8 | #define PAGE_SHIFT 13 | ||
| 9 | #ifndef __ASSEMBLY__ | ||
| 10 | #define PAGE_SIZE (1UL << PAGE_SHIFT) | ||
| 11 | #else | ||
| 12 | #define PAGE_SIZE (1 << PAGE_SHIFT) | ||
| 13 | #endif | ||
| 14 | #define PAGE_MASK (~(PAGE_SIZE-1)) | ||
| 15 | |||
| 16 | #ifdef __KERNEL__ | ||
| 17 | |||
| 18 | #define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) | ||
| 19 | #define copy_page(to,from) memcpy((void *)(to), (void *)(from), PAGE_SIZE) | ||
| 20 | |||
| 21 | #define clear_user_page(page, vaddr, pg) clear_page(page) | ||
| 22 | #define copy_user_page(to, from, vaddr, pg) copy_page(to, from) | ||
| 23 | |||
| 24 | #define alloc_zeroed_user_highpage(vma, vaddr) alloc_page_vma(GFP_HIGHUSER | __GFP_ZERO, vma, vaddr) | ||
| 25 | #define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE | ||
| 26 | |||
| 27 | /* | ||
| 28 | * These are used to make use of C type-checking.. | ||
| 29 | */ | ||
| 30 | #ifndef __ASSEMBLY__ | ||
| 31 | typedef struct { unsigned long pte; } pte_t; | ||
| 32 | typedef struct { unsigned long pmd; } pmd_t; | ||
| 33 | typedef struct { unsigned long pgd; } pgd_t; | ||
| 34 | typedef struct { unsigned long pgprot; } pgprot_t; | ||
| 35 | #endif | ||
| 36 | |||
| 37 | #define pte_val(x) ((x).pte) | ||
| 38 | #define pmd_val(x) ((x).pmd) | ||
| 39 | #define pgd_val(x) ((x).pgd) | ||
| 40 | #define pgprot_val(x) ((x).pgprot) | ||
| 41 | |||
| 42 | #define __pte(x) ((pte_t) { (x) } ) | ||
| 43 | #define __pmd(x) ((pmd_t) { (x) } ) | ||
| 44 | #define __pgd(x) ((pgd_t) { (x) } ) | ||
| 45 | #define __pgprot(x) ((pgprot_t) { (x) } ) | ||
| 46 | |||
| 47 | /* On CRIS the PFN numbers doesn't start at 0 so we have to compensate */ | ||
| 48 | /* for that before indexing into the page table starting at mem_map */ | ||
| 49 | #define pfn_to_page(pfn) (mem_map + ((pfn) - (PAGE_OFFSET >> PAGE_SHIFT))) | ||
| 50 | #define page_to_pfn(page) ((unsigned long)((page) - mem_map) + (PAGE_OFFSET >> PAGE_SHIFT)) | ||
| 51 | #define pfn_valid(pfn) (((pfn) - (PAGE_OFFSET >> PAGE_SHIFT)) < max_mapnr) | ||
| 52 | |||
| 53 | /* to index into the page map. our pages all start at physical addr PAGE_OFFSET so | ||
| 54 | * we can let the map start there. notice that we subtract PAGE_OFFSET because | ||
| 55 | * we start our mem_map there - in other ports they map mem_map physically and | ||
| 56 | * use __pa instead. in our system both the physical and virtual address of DRAM | ||
| 57 | * is too high to let mem_map start at 0, so we do it this way instead (similar | ||
| 58 | * to arm and m68k I think) | ||
| 59 | */ | ||
| 60 | |||
| 61 | #define virt_to_page(kaddr) (mem_map + (((unsigned long)(kaddr) - PAGE_OFFSET) >> PAGE_SHIFT)) | ||
| 62 | #define VALID_PAGE(page) (((page) - mem_map) < max_mapnr) | ||
| 63 | #define virt_addr_valid(kaddr) pfn_valid((unsigned)(kaddr) >> PAGE_SHIFT) | ||
| 64 | |||
| 65 | /* convert a page (based on mem_map and forward) to a physical address | ||
| 66 | * do this by figuring out the virtual address and then use __pa | ||
| 67 | */ | ||
| 68 | |||
| 69 | #define page_to_phys(page) __pa((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET) | ||
| 70 | |||
| 71 | /* to align the pointer to the (next) page boundary */ | ||
| 72 | #define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK) | ||
| 73 | |||
| 74 | #ifndef __ASSEMBLY__ | ||
| 75 | |||
| 76 | #define BUG() do { \ | ||
| 77 | printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \ | ||
| 78 | } while (0) | ||
| 79 | |||
| 80 | #define PAGE_BUG(page) do { \ | ||
| 81 | BUG(); \ | ||
| 82 | } while (0) | ||
| 83 | |||
| 84 | /* Pure 2^n version of get_order */ | ||
| 85 | static inline int get_order(unsigned long size) | ||
| 86 | { | ||
| 87 | int order; | ||
| 88 | |||
| 89 | size = (size-1) >> (PAGE_SHIFT-1); | ||
| 90 | order = -1; | ||
| 91 | do { | ||
| 92 | size >>= 1; | ||
| 93 | order++; | ||
| 94 | } while (size); | ||
| 95 | return order; | ||
| 96 | } | ||
| 97 | #endif /* __ASSEMBLY__ */ | ||
| 98 | |||
| 99 | #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ | ||
| 100 | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) | ||
| 101 | |||
| 102 | #endif /* __KERNEL__ */ | ||
| 103 | |||
| 104 | #endif /* _CRIS_PAGE_H */ | ||
| 105 | |||
diff --git a/include/asm-cris/param.h b/include/asm-cris/param.h new file mode 100644 index 000000000000..b24972639832 --- /dev/null +++ b/include/asm-cris/param.h | |||
| @@ -0,0 +1,23 @@ | |||
| 1 | #ifndef _ASMCRIS_PARAM_H | ||
| 2 | #define _ASMCRIS_PARAM_H | ||
| 3 | |||
| 4 | /* Currently we assume that HZ=100 is good for CRIS. */ | ||
| 5 | #ifdef __KERNEL__ | ||
| 6 | # define HZ 100 /* Internal kernel timer frequency */ | ||
| 7 | # define USER_HZ 100 /* .. some user interfaces are in "ticks" */ | ||
| 8 | # define CLOCKS_PER_SEC (USER_HZ) /* like times() */ | ||
| 9 | #endif | ||
| 10 | |||
| 11 | #ifndef HZ | ||
| 12 | #define HZ 100 | ||
| 13 | #endif | ||
| 14 | |||
| 15 | #define EXEC_PAGESIZE 8192 | ||
| 16 | |||
| 17 | #ifndef NOGROUP | ||
| 18 | #define NOGROUP (-1) | ||
| 19 | #endif | ||
| 20 | |||
| 21 | #define MAXHOSTNAMELEN 64 /* max length of hostname */ | ||
| 22 | |||
| 23 | #endif | ||
diff --git a/include/asm-cris/pci.h b/include/asm-cris/pci.h new file mode 100644 index 000000000000..c61041531889 --- /dev/null +++ b/include/asm-cris/pci.h | |||
| @@ -0,0 +1,13 @@ | |||
| 1 | #ifndef __ASM_CRIS_PCI_H | ||
| 2 | #define __ASM_CRIS_PCI_H | ||
| 3 | |||
| 4 | #include <asm/scatterlist.h> | ||
| 5 | #include <asm-generic/pci-dma-compat.h> | ||
| 6 | |||
| 7 | /* ETRAX chips don't have a PCI bus. This file is just here because some stupid .c code | ||
| 8 | * includes it even if CONFIG_PCI is not set. | ||
| 9 | */ | ||
| 10 | #define PCI_DMA_BUS_IS_PHYS (1) | ||
| 11 | |||
| 12 | #endif /* __ASM_CRIS_PCI_H */ | ||
| 13 | |||
diff --git a/include/asm-cris/percpu.h b/include/asm-cris/percpu.h new file mode 100644 index 000000000000..6db9b43cf80a --- /dev/null +++ b/include/asm-cris/percpu.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #ifndef _CRIS_PERCPU_H | ||
| 2 | #define _CRIS_PERCPU_H | ||
| 3 | |||
| 4 | #include <asm-generic/percpu.h> | ||
| 5 | |||
| 6 | #endif /* _CRIS_PERCPU_H */ | ||
diff --git a/include/asm-cris/pgalloc.h b/include/asm-cris/pgalloc.h new file mode 100644 index 000000000000..b202e62ed6e0 --- /dev/null +++ b/include/asm-cris/pgalloc.h | |||
| @@ -0,0 +1,62 @@ | |||
| 1 | #ifndef _CRIS_PGALLOC_H | ||
| 2 | #define _CRIS_PGALLOC_H | ||
| 3 | |||
| 4 | #include <linux/threads.h> | ||
| 5 | #include <linux/mm.h> | ||
| 6 | |||
| 7 | #define pmd_populate_kernel(mm, pmd, pte) pmd_set(pmd, pte) | ||
| 8 | #define pmd_populate(mm, pmd, pte) pmd_set(pmd, page_address(pte)) | ||
| 9 | |||
| 10 | /* | ||
| 11 | * Allocate and free page tables. | ||
| 12 | */ | ||
| 13 | |||
| 14 | extern inline pgd_t *pgd_alloc (struct mm_struct *mm) | ||
| 15 | { | ||
| 16 | return (pgd_t *)get_zeroed_page(GFP_KERNEL); | ||
| 17 | } | ||
| 18 | |||
| 19 | extern inline void pgd_free (pgd_t *pgd) | ||
| 20 | { | ||
| 21 | free_page((unsigned long)pgd); | ||
| 22 | } | ||
| 23 | |||
| 24 | extern inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address) | ||
| 25 | { | ||
| 26 | pte_t *pte = (pte_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO); | ||
| 27 | return pte; | ||
| 28 | } | ||
| 29 | |||
| 30 | extern inline struct page *pte_alloc_one(struct mm_struct *mm, unsigned long address) | ||
| 31 | { | ||
| 32 | struct page *pte; | ||
| 33 | pte = alloc_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, 0); | ||
| 34 | return pte; | ||
| 35 | } | ||
| 36 | |||
| 37 | extern inline void pte_free_kernel(pte_t *pte) | ||
| 38 | { | ||
| 39 | free_page((unsigned long)pte); | ||
| 40 | } | ||
| 41 | |||
| 42 | extern inline void pte_free(struct page *pte) | ||
| 43 | { | ||
| 44 | __free_page(pte); | ||
| 45 | } | ||
| 46 | |||
| 47 | |||
| 48 | #define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte)) | ||
| 49 | |||
| 50 | /* | ||
| 51 | * We don't have any real pmd's, and this code never triggers because | ||
| 52 | * the pgd will always be present.. | ||
| 53 | */ | ||
| 54 | |||
| 55 | #define pmd_alloc_one(mm, addr) ({ BUG(); ((pmd_t *)2); }) | ||
| 56 | #define pmd_free(x) do { } while (0) | ||
| 57 | #define __pmd_free_tlb(tlb,x) do { } while (0) | ||
| 58 | #define pgd_populate(mm, pmd, pte) BUG() | ||
| 59 | |||
| 60 | #define check_pgt_cache() do { } while (0) | ||
| 61 | |||
| 62 | #endif | ||
diff --git a/include/asm-cris/pgtable.h b/include/asm-cris/pgtable.h new file mode 100644 index 000000000000..957dd92d108d --- /dev/null +++ b/include/asm-cris/pgtable.h | |||
| @@ -0,0 +1,352 @@ | |||
| 1 | /* | ||
| 2 | * CRIS pgtable.h - macros and functions to manipulate page tables. | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifndef _CRIS_PGTABLE_H | ||
| 6 | #define _CRIS_PGTABLE_H | ||
| 7 | |||
| 8 | #include <asm-generic/4level-fixup.h> | ||
| 9 | |||
| 10 | #ifndef __ASSEMBLY__ | ||
| 11 | #include <linux/config.h> | ||
| 12 | #include <linux/sched.h> | ||
| 13 | #include <asm/mmu.h> | ||
| 14 | #endif | ||
| 15 | #include <asm/arch/pgtable.h> | ||
| 16 | |||
| 17 | /* | ||
| 18 | * The Linux memory management assumes a three-level page table setup. On | ||
| 19 | * CRIS, we use that, but "fold" the mid level into the top-level page | ||
| 20 | * table. Since the MMU TLB is software loaded through an interrupt, it | ||
| 21 | * supports any page table structure, so we could have used a three-level | ||
| 22 | * setup, but for the amounts of memory we normally use, a two-level is | ||
| 23 | * probably more efficient. | ||
| 24 | * | ||
| 25 | * This file contains the functions and defines necessary to modify and use | ||
| 26 | * the CRIS page table tree. | ||
| 27 | */ | ||
| 28 | #ifndef __ASSEMBLY__ | ||
| 29 | extern void paging_init(void); | ||
| 30 | #endif | ||
| 31 | |||
| 32 | /* Certain architectures need to do special things when pte's | ||
| 33 | * within a page table are directly modified. Thus, the following | ||
| 34 | * hook is made available. | ||
| 35 | */ | ||
| 36 | #define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval)) | ||
| 37 | #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) | ||
| 38 | |||
| 39 | /* | ||
| 40 | * (pmds are folded into pgds so this doesn't get actually called, | ||
| 41 | * but the define is needed for a generic inline function.) | ||
| 42 | */ | ||
| 43 | #define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval) | ||
| 44 | #define set_pgd(pgdptr, pgdval) (*(pgdptr) = pgdval) | ||
| 45 | |||
| 46 | /* PMD_SHIFT determines the size of the area a second-level page table can | ||
| 47 | * map. It is equal to the page size times the number of PTE's that fit in | ||
| 48 | * a PMD page. A PTE is 4-bytes in CRIS. Hence the following number. | ||
| 49 | */ | ||
| 50 | |||
| 51 | #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-2)) | ||
| 52 | #define PMD_SIZE (1UL << PMD_SHIFT) | ||
| 53 | #define PMD_MASK (~(PMD_SIZE-1)) | ||
| 54 | |||
| 55 | /* PGDIR_SHIFT determines what a third-level page table entry can map. | ||
| 56 | * Since we fold into a two-level structure, this is the same as PMD_SHIFT. | ||
| 57 | */ | ||
| 58 | |||
| 59 | #define PGDIR_SHIFT PMD_SHIFT | ||
| 60 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) | ||
| 61 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | ||
| 62 | |||
| 63 | /* | ||
| 64 | * entries per page directory level: we use a two-level, so | ||
| 65 | * we don't really have any PMD directory physically. | ||
| 66 | * pointers are 4 bytes so we can use the page size and | ||
| 67 | * divide it by 4 (shift by 2). | ||
| 68 | */ | ||
| 69 | #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-2)) | ||
| 70 | #define PTRS_PER_PMD 1 | ||
| 71 | #define PTRS_PER_PGD (1UL << (PAGE_SHIFT-2)) | ||
| 72 | |||
| 73 | /* calculate how many PGD entries a user-level program can use | ||
| 74 | * the first mappable virtual address is 0 | ||
| 75 | * (TASK_SIZE is the maximum virtual address space) | ||
| 76 | */ | ||
| 77 | |||
| 78 | #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE) | ||
| 79 | #define FIRST_USER_PGD_NR 0 | ||
| 80 | |||
| 81 | /* zero page used for uninitialized stuff */ | ||
| 82 | #ifndef __ASSEMBLY__ | ||
| 83 | extern unsigned long empty_zero_page; | ||
| 84 | #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) | ||
| 85 | #endif | ||
| 86 | |||
| 87 | /* number of bits that fit into a memory pointer */ | ||
| 88 | #define BITS_PER_PTR (8*sizeof(unsigned long)) | ||
| 89 | |||
| 90 | /* to align the pointer to a pointer address */ | ||
| 91 | #define PTR_MASK (~(sizeof(void*)-1)) | ||
| 92 | |||
| 93 | /* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */ | ||
| 94 | /* 64-bit machines, beware! SRB. */ | ||
| 95 | #define SIZEOF_PTR_LOG2 2 | ||
| 96 | |||
| 97 | /* to find an entry in a page-table */ | ||
| 98 | #define PAGE_PTR(address) \ | ||
| 99 | ((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK) | ||
| 100 | |||
| 101 | /* to set the page-dir */ | ||
| 102 | #define SET_PAGE_DIR(tsk,pgdir) | ||
| 103 | |||
| 104 | #define pte_none(x) (!pte_val(x)) | ||
| 105 | #define pte_present(x) (pte_val(x) & _PAGE_PRESENT) | ||
| 106 | #define pte_clear(mm,addr,xp) do { pte_val(*(xp)) = 0; } while (0) | ||
| 107 | |||
| 108 | #define pmd_none(x) (!pmd_val(x)) | ||
| 109 | /* by removing the _PAGE_KERNEL bit from the comparision, the same pmd_bad | ||
| 110 | * works for both _PAGE_TABLE and _KERNPG_TABLE pmd entries. | ||
| 111 | */ | ||
| 112 | #define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_KERNEL)) != _PAGE_TABLE) | ||
| 113 | #define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT) | ||
| 114 | #define pmd_clear(xp) do { pmd_val(*(xp)) = 0; } while (0) | ||
| 115 | |||
| 116 | #ifndef __ASSEMBLY__ | ||
| 117 | |||
| 118 | /* | ||
| 119 | * The "pgd_xxx()" functions here are trivial for a folded two-level | ||
| 120 | * setup: the pgd is never bad, and a pmd always exists (as it's folded | ||
| 121 | * into the pgd entry) | ||
| 122 | */ | ||
| 123 | extern inline int pgd_none(pgd_t pgd) { return 0; } | ||
| 124 | extern inline int pgd_bad(pgd_t pgd) { return 0; } | ||
| 125 | extern inline int pgd_present(pgd_t pgd) { return 1; } | ||
| 126 | extern inline void pgd_clear(pgd_t * pgdp) { } | ||
| 127 | |||
| 128 | /* | ||
| 129 | * The following only work if pte_present() is true. | ||
| 130 | * Undefined behaviour if not.. | ||
| 131 | */ | ||
| 132 | |||
| 133 | extern inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_READ; } | ||
| 134 | extern inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; } | ||
| 135 | extern inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_READ; } | ||
| 136 | extern inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; } | ||
| 137 | extern inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } | ||
| 138 | extern inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } | ||
| 139 | |||
| 140 | extern inline pte_t pte_wrprotect(pte_t pte) | ||
| 141 | { | ||
| 142 | pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE); | ||
| 143 | return pte; | ||
| 144 | } | ||
| 145 | |||
| 146 | extern inline pte_t pte_rdprotect(pte_t pte) | ||
| 147 | { | ||
| 148 | pte_val(pte) &= ~(_PAGE_READ | _PAGE_SILENT_READ); | ||
| 149 | return pte; | ||
| 150 | } | ||
| 151 | |||
| 152 | extern inline pte_t pte_exprotect(pte_t pte) | ||
| 153 | { | ||
| 154 | pte_val(pte) &= ~(_PAGE_READ | _PAGE_SILENT_READ); | ||
| 155 | return pte; | ||
| 156 | } | ||
| 157 | |||
| 158 | extern inline pte_t pte_mkclean(pte_t pte) | ||
| 159 | { | ||
| 160 | pte_val(pte) &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE); | ||
| 161 | return pte; | ||
| 162 | } | ||
| 163 | |||
| 164 | extern inline pte_t pte_mkold(pte_t pte) | ||
| 165 | { | ||
| 166 | pte_val(pte) &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ); | ||
| 167 | return pte; | ||
| 168 | } | ||
| 169 | |||
| 170 | extern inline pte_t pte_mkwrite(pte_t pte) | ||
| 171 | { | ||
| 172 | pte_val(pte) |= _PAGE_WRITE; | ||
| 173 | if (pte_val(pte) & _PAGE_MODIFIED) | ||
| 174 | pte_val(pte) |= _PAGE_SILENT_WRITE; | ||
| 175 | return pte; | ||
| 176 | } | ||
| 177 | |||
| 178 | extern inline pte_t pte_mkread(pte_t pte) | ||
| 179 | { | ||
| 180 | pte_val(pte) |= _PAGE_READ; | ||
| 181 | if (pte_val(pte) & _PAGE_ACCESSED) | ||
| 182 | pte_val(pte) |= _PAGE_SILENT_READ; | ||
| 183 | return pte; | ||
| 184 | } | ||
| 185 | |||
| 186 | extern inline pte_t pte_mkexec(pte_t pte) | ||
| 187 | { | ||
| 188 | pte_val(pte) |= _PAGE_READ; | ||
| 189 | if (pte_val(pte) & _PAGE_ACCESSED) | ||
| 190 | pte_val(pte) |= _PAGE_SILENT_READ; | ||
| 191 | return pte; | ||
| 192 | } | ||
| 193 | |||
| 194 | extern inline pte_t pte_mkdirty(pte_t pte) | ||
| 195 | { | ||
| 196 | pte_val(pte) |= _PAGE_MODIFIED; | ||
| 197 | if (pte_val(pte) & _PAGE_WRITE) | ||
| 198 | pte_val(pte) |= _PAGE_SILENT_WRITE; | ||
| 199 | return pte; | ||
| 200 | } | ||
| 201 | |||
| 202 | extern inline pte_t pte_mkyoung(pte_t pte) | ||
| 203 | { | ||
| 204 | pte_val(pte) |= _PAGE_ACCESSED; | ||
| 205 | if (pte_val(pte) & _PAGE_READ) | ||
| 206 | { | ||
| 207 | pte_val(pte) |= _PAGE_SILENT_READ; | ||
| 208 | if ((pte_val(pte) & (_PAGE_WRITE | _PAGE_MODIFIED)) == | ||
| 209 | (_PAGE_WRITE | _PAGE_MODIFIED)) | ||
| 210 | pte_val(pte) |= _PAGE_SILENT_WRITE; | ||
| 211 | } | ||
| 212 | return pte; | ||
| 213 | } | ||
| 214 | |||
| 215 | /* | ||
| 216 | * Conversion functions: convert a page and protection to a page entry, | ||
| 217 | * and a page entry and page directory to the page they refer to. | ||
| 218 | */ | ||
| 219 | |||
| 220 | /* What actually goes as arguments to the various functions is less than | ||
| 221 | * obvious, but a rule of thumb is that struct page's goes as struct page *, | ||
| 222 | * really physical DRAM addresses are unsigned long's, and DRAM "virtual" | ||
| 223 | * addresses (the 0xc0xxxxxx's) goes as void *'s. | ||
| 224 | */ | ||
| 225 | |||
| 226 | extern inline pte_t __mk_pte(void * page, pgprot_t pgprot) | ||
| 227 | { | ||
| 228 | pte_t pte; | ||
| 229 | /* the PTE needs a physical address */ | ||
| 230 | pte_val(pte) = __pa(page) | pgprot_val(pgprot); | ||
| 231 | return pte; | ||
| 232 | } | ||
| 233 | |||
| 234 | #define mk_pte(page, pgprot) __mk_pte(page_address(page), (pgprot)) | ||
| 235 | |||
| 236 | #define mk_pte_phys(physpage, pgprot) \ | ||
| 237 | ({ \ | ||
| 238 | pte_t __pte; \ | ||
| 239 | \ | ||
| 240 | pte_val(__pte) = (physpage) + pgprot_val(pgprot); \ | ||
| 241 | __pte; \ | ||
| 242 | }) | ||
| 243 | |||
| 244 | extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot) | ||
| 245 | { pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; } | ||
| 246 | |||
| 247 | |||
| 248 | /* pte_val refers to a page in the 0x4xxxxxxx physical DRAM interval | ||
| 249 | * __pte_page(pte_val) refers to the "virtual" DRAM interval | ||
| 250 | * pte_pagenr refers to the page-number counted starting from the virtual DRAM start | ||
| 251 | */ | ||
| 252 | |||
| 253 | extern inline unsigned long __pte_page(pte_t pte) | ||
| 254 | { | ||
| 255 | /* the PTE contains a physical address */ | ||
| 256 | return (unsigned long)__va(pte_val(pte) & PAGE_MASK); | ||
| 257 | } | ||
| 258 | |||
| 259 | #define pte_pagenr(pte) ((__pte_page(pte) - PAGE_OFFSET) >> PAGE_SHIFT) | ||
| 260 | |||
| 261 | /* permanent address of a page */ | ||
| 262 | |||
| 263 | #define __page_address(page) (PAGE_OFFSET + (((page) - mem_map) << PAGE_SHIFT)) | ||
| 264 | #define pte_page(pte) (mem_map+pte_pagenr(pte)) | ||
| 265 | |||
| 266 | /* only the pte's themselves need to point to physical DRAM (see above) | ||
| 267 | * the pagetable links are purely handled within the kernel SW and thus | ||
| 268 | * don't need the __pa and __va transformations. | ||
| 269 | */ | ||
| 270 | |||
| 271 | extern inline void pmd_set(pmd_t * pmdp, pte_t * ptep) | ||
| 272 | { pmd_val(*pmdp) = _PAGE_TABLE | (unsigned long) ptep; } | ||
| 273 | |||
| 274 | #define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)) | ||
| 275 | #define pmd_page_kernel(pmd) ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK)) | ||
| 276 | |||
| 277 | /* to find an entry in a page-table-directory. */ | ||
| 278 | #define pgd_index(address) ((address >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) | ||
| 279 | |||
| 280 | /* to find an entry in a page-table-directory */ | ||
| 281 | extern inline pgd_t * pgd_offset(struct mm_struct * mm, unsigned long address) | ||
| 282 | { | ||
| 283 | return mm->pgd + pgd_index(address); | ||
| 284 | } | ||
| 285 | |||
| 286 | /* to find an entry in a kernel page-table-directory */ | ||
| 287 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) | ||
| 288 | |||
| 289 | /* Find an entry in the second-level page table.. */ | ||
| 290 | extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address) | ||
| 291 | { | ||
| 292 | return (pmd_t *) dir; | ||
| 293 | } | ||
| 294 | |||
| 295 | /* Find an entry in the third-level page table.. */ | ||
| 296 | #define __pte_offset(address) \ | ||
| 297 | (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) | ||
| 298 | #define pte_offset_kernel(dir, address) \ | ||
| 299 | ((pte_t *) pmd_page_kernel(*(dir)) + __pte_offset(address)) | ||
| 300 | #define pte_offset_map(dir, address) \ | ||
| 301 | ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address)) | ||
| 302 | #define pte_offset_map_nested(dir, address) pte_offset_map(dir, address) | ||
| 303 | |||
| 304 | #define pte_unmap(pte) do { } while (0) | ||
| 305 | #define pte_unmap_nested(pte) do { } while (0) | ||
| 306 | #define pte_pfn(x) ((unsigned long)(__va((x).pte)) >> PAGE_SHIFT) | ||
| 307 | #define pfn_pte(pfn, prot) __pte((__pa((pfn) << PAGE_SHIFT)) | pgprot_val(prot)) | ||
| 308 | |||
| 309 | #define pte_ERROR(e) \ | ||
| 310 | printk("%s:%d: bad pte %p(%08lx).\n", __FILE__, __LINE__, &(e), pte_val(e)) | ||
| 311 | #define pmd_ERROR(e) \ | ||
| 312 | printk("%s:%d: bad pmd %p(%08lx).\n", __FILE__, __LINE__, &(e), pmd_val(e)) | ||
| 313 | #define pgd_ERROR(e) \ | ||
| 314 | printk("%s:%d: bad pgd %p(%08lx).\n", __FILE__, __LINE__, &(e), pgd_val(e)) | ||
| 315 | |||
| 316 | |||
| 317 | extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* defined in head.S */ | ||
| 318 | |||
| 319 | /* | ||
| 320 | * CRIS doesn't have any external MMU info: the kernel page | ||
| 321 | * tables contain all the necessary information. | ||
| 322 | * | ||
| 323 | * Actually I am not sure on what this could be used for. | ||
| 324 | */ | ||
| 325 | extern inline void update_mmu_cache(struct vm_area_struct * vma, | ||
| 326 | unsigned long address, pte_t pte) | ||
| 327 | { | ||
| 328 | } | ||
| 329 | |||
| 330 | /* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */ | ||
| 331 | /* Since the PAGE_PRESENT bit is bit 4, we can use the bits above */ | ||
| 332 | |||
| 333 | #define __swp_type(x) (((x).val >> 5) & 0x7f) | ||
| 334 | #define __swp_offset(x) ((x).val >> 12) | ||
| 335 | #define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 5) | ((offset) << 12) }) | ||
| 336 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | ||
| 337 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) | ||
| 338 | |||
| 339 | #define kern_addr_valid(addr) (1) | ||
| 340 | |||
| 341 | #include <asm-generic/pgtable.h> | ||
| 342 | |||
| 343 | /* | ||
| 344 | * No page table caches to initialise | ||
| 345 | */ | ||
| 346 | #define pgtable_cache_init() do { } while (0) | ||
| 347 | |||
| 348 | #define pte_to_pgoff(x) (pte_val(x) >> 6) | ||
| 349 | #define pgoff_to_pte(x) __pte(((x) << 6) | _PAGE_FILE) | ||
| 350 | |||
| 351 | #endif /* __ASSEMBLY__ */ | ||
| 352 | #endif /* _CRIS_PGTABLE_H */ | ||
diff --git a/include/asm-cris/poll.h b/include/asm-cris/poll.h new file mode 100644 index 000000000000..1c0efc3e4be7 --- /dev/null +++ b/include/asm-cris/poll.h | |||
| @@ -0,0 +1,25 @@ | |||
| 1 | #ifndef __ASM_CRIS_POLL_H | ||
| 2 | #define __ASM_CRIS_POLL_H | ||
| 3 | |||
| 4 | /* taken from asm-alpha */ | ||
| 5 | |||
| 6 | #define POLLIN 1 | ||
| 7 | #define POLLPRI 2 | ||
| 8 | #define POLLOUT 4 | ||
| 9 | #define POLLERR 8 | ||
| 10 | #define POLLHUP 16 | ||
| 11 | #define POLLNVAL 32 | ||
| 12 | #define POLLRDNORM 64 | ||
| 13 | #define POLLRDBAND 128 | ||
| 14 | #define POLLWRNORM 256 | ||
| 15 | #define POLLWRBAND 512 | ||
| 16 | #define POLLMSG 1024 | ||
| 17 | #define POLLREMOVE 4096 | ||
| 18 | |||
| 19 | struct pollfd { | ||
| 20 | int fd; | ||
| 21 | short events; | ||
| 22 | short revents; | ||
| 23 | }; | ||
| 24 | |||
| 25 | #endif | ||
diff --git a/include/asm-cris/posix_types.h b/include/asm-cris/posix_types.h new file mode 100644 index 000000000000..6d26fee4a614 --- /dev/null +++ b/include/asm-cris/posix_types.h | |||
| @@ -0,0 +1,74 @@ | |||
| 1 | /* $Id: posix_types.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */ | ||
| 2 | |||
| 3 | /* We cheat a bit and use our C-coded bitops functions from asm/bitops.h */ | ||
| 4 | /* I guess we should write these in assembler because they are used often. */ | ||
| 5 | |||
| 6 | #ifndef __ARCH_CRIS_POSIX_TYPES_H | ||
| 7 | #define __ARCH_CRIS_POSIX_TYPES_H | ||
| 8 | |||
| 9 | #include <asm/bitops.h> | ||
| 10 | |||
| 11 | /* | ||
| 12 | * This file is generally used by user-level software, so you need to | ||
| 13 | * be a little careful about namespace pollution etc. Also, we cannot | ||
| 14 | * assume GCC is being used. | ||
| 15 | */ | ||
| 16 | |||
| 17 | typedef unsigned long __kernel_ino_t; | ||
| 18 | typedef unsigned short __kernel_mode_t; | ||
| 19 | typedef unsigned short __kernel_nlink_t; | ||
| 20 | typedef long __kernel_off_t; | ||
| 21 | typedef int __kernel_pid_t; | ||
| 22 | typedef unsigned short __kernel_ipc_pid_t; | ||
| 23 | typedef unsigned short __kernel_uid_t; | ||
| 24 | typedef unsigned short __kernel_gid_t; | ||
| 25 | typedef __SIZE_TYPE__ __kernel_size_t; | ||
| 26 | typedef long __kernel_ssize_t; | ||
| 27 | typedef int __kernel_ptrdiff_t; | ||
| 28 | typedef long __kernel_time_t; | ||
| 29 | typedef long __kernel_suseconds_t; | ||
| 30 | typedef long __kernel_clock_t; | ||
| 31 | typedef int __kernel_timer_t; | ||
| 32 | typedef int __kernel_clockid_t; | ||
| 33 | typedef int __kernel_daddr_t; | ||
| 34 | typedef char * __kernel_caddr_t; | ||
| 35 | typedef unsigned short __kernel_uid16_t; | ||
| 36 | typedef unsigned short __kernel_gid16_t; | ||
| 37 | typedef unsigned int __kernel_uid32_t; | ||
| 38 | typedef unsigned int __kernel_gid32_t; | ||
| 39 | |||
| 40 | typedef unsigned short __kernel_old_uid_t; | ||
| 41 | typedef unsigned short __kernel_old_gid_t; | ||
| 42 | typedef unsigned short __kernel_old_dev_t; | ||
| 43 | |||
| 44 | #ifdef __GNUC__ | ||
| 45 | typedef long long __kernel_loff_t; | ||
| 46 | #endif | ||
| 47 | |||
| 48 | typedef struct { | ||
| 49 | #if defined(__KERNEL__) || defined(__USE_ALL) | ||
| 50 | int val[2]; | ||
| 51 | #else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ | ||
| 52 | int __val[2]; | ||
| 53 | #endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ | ||
| 54 | } __kernel_fsid_t; | ||
| 55 | |||
| 56 | /* should this ifdef be here ? */ | ||
| 57 | |||
| 58 | #if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) | ||
| 59 | |||
| 60 | #undef __FD_SET | ||
| 61 | #define __FD_SET(fd,fdsetp) set_bit(fd, (void *)(fdsetp)) | ||
| 62 | |||
| 63 | #undef __FD_CLR | ||
| 64 | #define __FD_CLR(fd,fdsetp) clear_bit(fd, (void *)(fdsetp)) | ||
| 65 | |||
| 66 | #undef __FD_ISSET | ||
| 67 | #define __FD_ISSET(fd,fdsetp) test_bit(fd, (void *)(fdsetp)) | ||
| 68 | |||
| 69 | #undef __FD_ZERO | ||
| 70 | #define __FD_ZERO(fdsetp) memset((void *)(fdsetp), 0, __FDSET_LONGS << 2) | ||
| 71 | |||
| 72 | #endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ | ||
| 73 | |||
| 74 | #endif /* __ARCH_CRIS_POSIX_TYPES_H */ | ||
diff --git a/include/asm-cris/processor.h b/include/asm-cris/processor.h new file mode 100644 index 000000000000..623bdf06d911 --- /dev/null +++ b/include/asm-cris/processor.h | |||
| @@ -0,0 +1,79 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-cris/processor.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2000, 2001 Axis Communications AB | ||
| 5 | * | ||
| 6 | * Authors: Bjorn Wesen Initial version | ||
| 7 | * | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __ASM_CRIS_PROCESSOR_H | ||
| 11 | #define __ASM_CRIS_PROCESSOR_H | ||
| 12 | |||
| 13 | #include <linux/config.h> | ||
| 14 | #include <asm/system.h> | ||
| 15 | #include <asm/page.h> | ||
| 16 | #include <asm/ptrace.h> | ||
| 17 | #include <asm/arch/processor.h> | ||
| 18 | |||
| 19 | /* This decides where the kernel will search for a free chunk of vm | ||
| 20 | * space during mmap's. | ||
| 21 | */ | ||
| 22 | #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) | ||
| 23 | |||
| 24 | /* THREAD_SIZE is the size of the task_struct/kernel_stack combo. | ||
| 25 | * normally, the stack is found by doing something like p + THREAD_SIZE | ||
| 26 | * in CRIS, a page is 8192 bytes, which seems like a sane size | ||
| 27 | */ | ||
| 28 | |||
| 29 | #define THREAD_SIZE PAGE_SIZE | ||
| 30 | #define KERNEL_STACK_SIZE PAGE_SIZE | ||
| 31 | |||
| 32 | /* | ||
| 33 | * At user->kernel entry, the pt_regs struct is stacked on the top of the kernel-stack. | ||
| 34 | * This macro allows us to find those regs for a task. | ||
| 35 | * Notice that subsequent pt_regs stackings, like recursive interrupts occurring while | ||
| 36 | * we're in the kernel, won't affect this - only the first user->kernel transition | ||
| 37 | * registers are reached by this. | ||
| 38 | */ | ||
| 39 | |||
| 40 | #define user_regs(thread_info) (((struct pt_regs *)((unsigned long)(thread_info) + THREAD_SIZE)) - 1) | ||
| 41 | |||
| 42 | /* | ||
| 43 | * Dito but for the currently running task | ||
| 44 | */ | ||
| 45 | |||
| 46 | #define current_regs() user_regs(current->thread_info) | ||
| 47 | |||
| 48 | extern inline void prepare_to_copy(struct task_struct *tsk) | ||
| 49 | { | ||
| 50 | } | ||
| 51 | |||
| 52 | extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); | ||
| 53 | |||
| 54 | unsigned long get_wchan(struct task_struct *p); | ||
| 55 | |||
| 56 | #define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp) | ||
| 57 | |||
| 58 | /* | ||
| 59 | * Free current thread data structures etc.. | ||
| 60 | */ | ||
| 61 | |||
| 62 | extern inline void exit_thread(void) | ||
| 63 | { | ||
| 64 | /* Nothing needs to be done. */ | ||
| 65 | } | ||
| 66 | |||
| 67 | extern unsigned long thread_saved_pc(struct task_struct *tsk); | ||
| 68 | |||
| 69 | /* Free all resources held by a thread. */ | ||
| 70 | extern inline void release_thread(struct task_struct *dead_task) | ||
| 71 | { | ||
| 72 | /* Nothing needs to be done. */ | ||
| 73 | } | ||
| 74 | |||
| 75 | #define init_stack (init_thread_union.stack) | ||
| 76 | |||
| 77 | #define cpu_relax() barrier() | ||
| 78 | |||
| 79 | #endif /* __ASM_CRIS_PROCESSOR_H */ | ||
diff --git a/include/asm-cris/ptrace.h b/include/asm-cris/ptrace.h new file mode 100644 index 000000000000..7a8c2880e487 --- /dev/null +++ b/include/asm-cris/ptrace.h | |||
| @@ -0,0 +1,12 @@ | |||
| 1 | #ifndef _CRIS_PTRACE_H | ||
| 2 | #define _CRIS_PTRACE_H | ||
| 3 | |||
| 4 | #include <asm/arch/ptrace.h> | ||
| 5 | |||
| 6 | #ifdef __KERNEL__ | ||
| 7 | /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ | ||
| 8 | #define PTRACE_GETREGS 12 | ||
| 9 | #define PTRACE_SETREGS 13 | ||
| 10 | #endif | ||
| 11 | |||
| 12 | #endif /* _CRIS_PTRACE_H */ | ||
diff --git a/include/asm-cris/resource.h b/include/asm-cris/resource.h new file mode 100644 index 000000000000..b5d29448de4e --- /dev/null +++ b/include/asm-cris/resource.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #ifndef _CRIS_RESOURCE_H | ||
| 2 | #define _CRIS_RESOURCE_H | ||
| 3 | |||
| 4 | #include <asm-generic/resource.h> | ||
| 5 | |||
| 6 | #endif | ||
diff --git a/include/asm-cris/rs485.h b/include/asm-cris/rs485.h new file mode 100644 index 000000000000..c331c51b0c2b --- /dev/null +++ b/include/asm-cris/rs485.h | |||
| @@ -0,0 +1,20 @@ | |||
| 1 | /* RS-485 structures */ | ||
| 2 | |||
| 3 | /* RS-485 support */ | ||
| 4 | /* Used with ioctl() TIOCSERSETRS485 */ | ||
| 5 | struct rs485_control { | ||
| 6 | unsigned short rts_on_send; | ||
| 7 | unsigned short rts_after_sent; | ||
| 8 | unsigned long delay_rts_before_send; | ||
| 9 | unsigned short enabled; | ||
| 10 | #ifdef __KERNEL__ | ||
| 11 | int disable_serial_loopback; | ||
| 12 | #endif | ||
| 13 | }; | ||
| 14 | |||
| 15 | /* Used with ioctl() TIOCSERWRRS485 */ | ||
| 16 | struct rs485_write { | ||
| 17 | unsigned short outc_size; | ||
| 18 | unsigned char *outc; | ||
| 19 | }; | ||
| 20 | |||
diff --git a/include/asm-cris/rtc.h b/include/asm-cris/rtc.h new file mode 100644 index 000000000000..97c13039834a --- /dev/null +++ b/include/asm-cris/rtc.h | |||
| @@ -0,0 +1,107 @@ | |||
| 1 | /* $Id: rtc.h,v 1.7 2002/11/04 07:32:09 starvik Exp $ */ | ||
| 2 | |||
| 3 | #ifndef __RTC_H__ | ||
| 4 | #define __RTC_H__ | ||
| 5 | |||
| 6 | |||
| 7 | #include <linux/config.h> | ||
| 8 | |||
| 9 | #ifdef CONFIG_ETRAX_DS1302 | ||
| 10 | /* Dallas DS1302 clock/calendar register numbers. */ | ||
| 11 | # define RTC_SECONDS 0 | ||
| 12 | # define RTC_MINUTES 1 | ||
| 13 | # define RTC_HOURS 2 | ||
| 14 | # define RTC_DAY_OF_MONTH 3 | ||
| 15 | # define RTC_MONTH 4 | ||
| 16 | # define RTC_WEEKDAY 5 | ||
| 17 | # define RTC_YEAR 6 | ||
| 18 | # define RTC_CONTROL 7 | ||
| 19 | |||
| 20 | /* Bits in CONTROL register. */ | ||
| 21 | # define RTC_CONTROL_WRITEPROTECT 0x80 | ||
| 22 | # define RTC_TRICKLECHARGER 8 | ||
| 23 | |||
| 24 | /* Bits in TRICKLECHARGER register TCS TCS TCS TCS DS DS RS RS. */ | ||
| 25 | # define RTC_TCR_PATTERN 0xA0 /* 1010xxxx */ | ||
| 26 | # define RTC_TCR_1DIOD 0x04 /* xxxx01xx */ | ||
| 27 | # define RTC_TCR_2DIOD 0x08 /* xxxx10xx */ | ||
| 28 | # define RTC_TCR_DISABLED 0x00 /* xxxxxx00 Disabled */ | ||
| 29 | # define RTC_TCR_2KOHM 0x01 /* xxxxxx01 2KOhm */ | ||
| 30 | # define RTC_TCR_4KOHM 0x02 /* xxxxxx10 4kOhm */ | ||
| 31 | # define RTC_TCR_8KOHM 0x03 /* xxxxxx11 8kOhm */ | ||
| 32 | |||
| 33 | #elif defined(CONFIG_ETRAX_PCF8563) | ||
| 34 | /* I2C bus slave registers. */ | ||
| 35 | # define RTC_I2C_READ 0xa3 | ||
| 36 | # define RTC_I2C_WRITE 0xa2 | ||
| 37 | |||
| 38 | /* Phillips PCF8563 registers. */ | ||
| 39 | # define RTC_CONTROL1 0x00 /* Control/Status register 1. */ | ||
| 40 | # define RTC_CONTROL2 0x01 /* Control/Status register 2. */ | ||
| 41 | # define RTC_CLOCKOUT_FREQ 0x0d /* CLKOUT frequency. */ | ||
| 42 | # define RTC_TIMER_CONTROL 0x0e /* Timer control. */ | ||
| 43 | # define RTC_TIMER_CNTDOWN 0x0f /* Timer countdown. */ | ||
| 44 | |||
| 45 | /* BCD encoded clock registers. */ | ||
| 46 | # define RTC_SECONDS 0x02 | ||
| 47 | # define RTC_MINUTES 0x03 | ||
| 48 | # define RTC_HOURS 0x04 | ||
| 49 | # define RTC_DAY_OF_MONTH 0x05 | ||
| 50 | # define RTC_WEEKDAY 0x06 /* Not coded in BCD! */ | ||
| 51 | # define RTC_MONTH 0x07 | ||
| 52 | # define RTC_YEAR 0x08 | ||
| 53 | # define RTC_MINUTE_ALARM 0x09 | ||
| 54 | # define RTC_HOUR_ALARM 0x0a | ||
| 55 | # define RTC_DAY_ALARM 0x0b | ||
| 56 | # define RTC_WEEKDAY_ALARM 0x0c | ||
| 57 | |||
| 58 | #endif | ||
| 59 | |||
| 60 | #ifdef CONFIG_ETRAX_DS1302 | ||
| 61 | extern unsigned char ds1302_readreg(int reg); | ||
| 62 | extern void ds1302_writereg(int reg, unsigned char val); | ||
| 63 | extern int ds1302_init(void); | ||
| 64 | # define CMOS_READ(x) ds1302_readreg(x) | ||
| 65 | # define CMOS_WRITE(val,reg) ds1302_writereg(reg,val) | ||
| 66 | # define RTC_INIT() ds1302_init() | ||
| 67 | #elif defined(CONFIG_ETRAX_PCF8563) | ||
| 68 | extern unsigned char pcf8563_readreg(int reg); | ||
| 69 | extern void pcf8563_writereg(int reg, unsigned char val); | ||
| 70 | extern int pcf8563_init(void); | ||
| 71 | # define CMOS_READ(x) pcf8563_readreg(x) | ||
| 72 | # define CMOS_WRITE(val,reg) pcf8563_writereg(reg,val) | ||
| 73 | # define RTC_INIT() pcf8563_init() | ||
| 74 | #else | ||
| 75 | /* No RTC configured so we shouldn't try to access any. */ | ||
| 76 | # define CMOS_READ(x) 42 | ||
| 77 | # define CMOS_WRITE(x,y) | ||
| 78 | # define RTC_INIT() (-1) | ||
| 79 | #endif | ||
| 80 | |||
| 81 | /* | ||
| 82 | * The struct used to pass data via the following ioctl. Similar to the | ||
| 83 | * struct tm in <time.h>, but it needs to be here so that the kernel | ||
| 84 | * source is self contained, allowing cross-compiles, etc. etc. | ||
| 85 | */ | ||
| 86 | struct rtc_time { | ||
| 87 | int tm_sec; | ||
| 88 | int tm_min; | ||
| 89 | int tm_hour; | ||
| 90 | int tm_mday; | ||
| 91 | int tm_mon; | ||
| 92 | int tm_year; | ||
| 93 | int tm_wday; | ||
| 94 | int tm_yday; | ||
| 95 | int tm_isdst; | ||
| 96 | }; | ||
| 97 | |||
| 98 | /* ioctl() calls that are permitted to the /dev/rtc interface. */ | ||
| 99 | #define RTC_MAGIC 'p' | ||
| 100 | #define RTC_RD_TIME _IOR(RTC_MAGIC, 0x09, struct rtc_time) /* Read RTC time. */ | ||
| 101 | #define RTC_SET_TIME _IOW(RTC_MAGIC, 0x0a, struct rtc_time) /* Set RTC time. */ | ||
| 102 | #define RTC_SET_CHARGE _IOW(RTC_MAGIC, 0x0b, int) | ||
| 103 | #define RTC_VLOW_RD _IOR(RTC_MAGIC, 0x11, int) /* Voltage Low detector */ | ||
| 104 | #define RTC_VLOW_SET _IO(RTC_MAGIC, 0x12) /* Clear voltage low information */ | ||
| 105 | #define RTC_MAX_IOCTL 0x12 | ||
| 106 | |||
| 107 | #endif /* __RTC_H__ */ | ||
diff --git a/include/asm-cris/scatterlist.h b/include/asm-cris/scatterlist.h new file mode 100644 index 000000000000..4bdc44c4ac3d --- /dev/null +++ b/include/asm-cris/scatterlist.h | |||
| @@ -0,0 +1,20 @@ | |||
| 1 | #ifndef __ASM_CRIS_SCATTERLIST_H | ||
| 2 | #define __ASM_CRIS_SCATTERLIST_H | ||
| 3 | |||
| 4 | struct scatterlist { | ||
| 5 | char * address; /* Location data is to be transferred to */ | ||
| 6 | unsigned int length; | ||
| 7 | |||
| 8 | /* The following is i386 highmem junk - not used by us */ | ||
| 9 | struct page * page; /* Location for highmem page, if any */ | ||
| 10 | unsigned int offset;/* for highmem, page offset */ | ||
| 11 | |||
| 12 | }; | ||
| 13 | |||
| 14 | #define sg_dma_address(sg) ((sg)->address) | ||
| 15 | #define sg_dma_len(sg) ((sg)->length) | ||
| 16 | /* i386 junk */ | ||
| 17 | |||
| 18 | #define ISA_DMA_THRESHOLD (0x1fffffff) | ||
| 19 | |||
| 20 | #endif /* !(__ASM_CRIS_SCATTERLIST_H) */ | ||
diff --git a/include/asm-cris/sections.h b/include/asm-cris/sections.h new file mode 100644 index 000000000000..2c998ce8967b --- /dev/null +++ b/include/asm-cris/sections.h | |||
| @@ -0,0 +1,7 @@ | |||
| 1 | #ifndef _CRIS_SECTIONS_H | ||
| 2 | #define _CRIS_SECTIONS_H | ||
| 3 | |||
| 4 | /* nothing to see, move along */ | ||
| 5 | #include <asm-generic/sections.h> | ||
| 6 | |||
| 7 | #endif | ||
diff --git a/include/asm-cris/segment.h b/include/asm-cris/segment.h new file mode 100644 index 000000000000..c067513beaaf --- /dev/null +++ b/include/asm-cris/segment.h | |||
| @@ -0,0 +1,8 @@ | |||
| 1 | #ifndef _ASM_SEGMENT_H | ||
| 2 | #define _ASM_SEGMENT_H | ||
| 3 | |||
| 4 | typedef struct { | ||
| 5 | unsigned long seg; | ||
| 6 | } mm_segment_t; | ||
| 7 | |||
| 8 | #endif | ||
diff --git a/include/asm-cris/semaphore-helper.h b/include/asm-cris/semaphore-helper.h new file mode 100644 index 000000000000..dbd0f30b85b6 --- /dev/null +++ b/include/asm-cris/semaphore-helper.h | |||
| @@ -0,0 +1,81 @@ | |||
| 1 | /* $Id: semaphore-helper.h,v 1.3 2001/03/26 15:00:33 orjanf Exp $ | ||
| 2 | * | ||
| 3 | * SMP- and interrupt-safe semaphores helper functions. Generic versions, no | ||
| 4 | * optimizations whatsoever... | ||
| 5 | * | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifndef _ASM_SEMAPHORE_HELPER_H | ||
| 9 | #define _ASM_SEMAPHORE_HELPER_H | ||
| 10 | |||
| 11 | #include <asm/atomic.h> | ||
| 12 | #include <linux/errno.h> | ||
| 13 | |||
| 14 | #define read(a) ((a)->counter) | ||
| 15 | #define inc(a) (((a)->counter)++) | ||
| 16 | #define dec(a) (((a)->counter)--) | ||
| 17 | |||
| 18 | #define count_inc(a) ((*(a))++) | ||
| 19 | |||
| 20 | /* | ||
| 21 | * These two _must_ execute atomically wrt each other. | ||
| 22 | */ | ||
| 23 | extern inline void wake_one_more(struct semaphore * sem) | ||
| 24 | { | ||
| 25 | atomic_inc(&sem->waking); | ||
| 26 | } | ||
| 27 | |||
| 28 | extern inline int waking_non_zero(struct semaphore *sem) | ||
| 29 | { | ||
| 30 | unsigned long flags; | ||
| 31 | int ret = 0; | ||
| 32 | |||
| 33 | local_save_flags(flags); | ||
| 34 | local_irq_disable(); | ||
| 35 | if (read(&sem->waking) > 0) { | ||
| 36 | dec(&sem->waking); | ||
| 37 | ret = 1; | ||
| 38 | } | ||
| 39 | local_irq_restore(flags); | ||
| 40 | return ret; | ||
| 41 | } | ||
| 42 | |||
| 43 | extern inline int waking_non_zero_interruptible(struct semaphore *sem, | ||
| 44 | struct task_struct *tsk) | ||
| 45 | { | ||
| 46 | int ret = 0; | ||
| 47 | unsigned long flags; | ||
| 48 | |||
| 49 | local_save_flags(flags); | ||
| 50 | local_irq_disable(); | ||
| 51 | if (read(&sem->waking) > 0) { | ||
| 52 | dec(&sem->waking); | ||
| 53 | ret = 1; | ||
| 54 | } else if (signal_pending(tsk)) { | ||
| 55 | inc(&sem->count); | ||
| 56 | ret = -EINTR; | ||
| 57 | } | ||
| 58 | local_irq_restore(flags); | ||
| 59 | return ret; | ||
| 60 | } | ||
| 61 | |||
| 62 | extern inline int waking_non_zero_trylock(struct semaphore *sem) | ||
| 63 | { | ||
| 64 | int ret = 1; | ||
| 65 | unsigned long flags; | ||
| 66 | |||
| 67 | local_save_flags(flags); | ||
| 68 | local_irq_disable(); | ||
| 69 | if (read(&sem->waking) <= 0) | ||
| 70 | inc(&sem->count); | ||
| 71 | else { | ||
| 72 | dec(&sem->waking); | ||
| 73 | ret = 0; | ||
| 74 | } | ||
| 75 | local_irq_restore(flags); | ||
| 76 | return ret; | ||
| 77 | } | ||
| 78 | |||
| 79 | #endif /* _ASM_SEMAPHORE_HELPER_H */ | ||
| 80 | |||
| 81 | |||
diff --git a/include/asm-cris/semaphore.h b/include/asm-cris/semaphore.h new file mode 100644 index 000000000000..605aa7eaaaf8 --- /dev/null +++ b/include/asm-cris/semaphore.h | |||
| @@ -0,0 +1,142 @@ | |||
| 1 | /* $Id: semaphore.h,v 1.3 2001/05/08 13:54:09 bjornw Exp $ */ | ||
| 2 | |||
| 3 | /* On the i386 these are coded in asm, perhaps we should as well. Later.. */ | ||
| 4 | |||
| 5 | #ifndef _CRIS_SEMAPHORE_H | ||
| 6 | #define _CRIS_SEMAPHORE_H | ||
| 7 | |||
| 8 | #define RW_LOCK_BIAS 0x01000000 | ||
| 9 | |||
| 10 | #include <linux/wait.h> | ||
| 11 | #include <linux/spinlock.h> | ||
| 12 | #include <linux/rwsem.h> | ||
| 13 | |||
| 14 | #include <asm/system.h> | ||
| 15 | #include <asm/atomic.h> | ||
| 16 | |||
| 17 | /* | ||
| 18 | * CRIS semaphores, implemented in C-only so far. | ||
| 19 | */ | ||
| 20 | |||
| 21 | int printk(const char *fmt, ...); | ||
| 22 | |||
| 23 | struct semaphore { | ||
| 24 | atomic_t count; | ||
| 25 | atomic_t waking; | ||
| 26 | wait_queue_head_t wait; | ||
| 27 | }; | ||
| 28 | |||
| 29 | #define __SEMAPHORE_INITIALIZER(name, n) \ | ||
| 30 | { \ | ||
| 31 | .count = ATOMIC_INIT(n), \ | ||
| 32 | .waking = ATOMIC_INIT(0), \ | ||
| 33 | .wait = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait) \ | ||
| 34 | } | ||
| 35 | |||
| 36 | #define __MUTEX_INITIALIZER(name) \ | ||
| 37 | __SEMAPHORE_INITIALIZER(name,1) | ||
| 38 | |||
| 39 | #define __DECLARE_SEMAPHORE_GENERIC(name,count) \ | ||
| 40 | struct semaphore name = __SEMAPHORE_INITIALIZER(name,count) | ||
| 41 | |||
| 42 | #define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name,1) | ||
| 43 | #define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name,0) | ||
| 44 | |||
| 45 | extern inline void sema_init(struct semaphore *sem, int val) | ||
| 46 | { | ||
| 47 | *sem = (struct semaphore)__SEMAPHORE_INITIALIZER((*sem),val); | ||
| 48 | } | ||
| 49 | |||
| 50 | extern inline void init_MUTEX (struct semaphore *sem) | ||
| 51 | { | ||
| 52 | sema_init(sem, 1); | ||
| 53 | } | ||
| 54 | |||
| 55 | extern inline void init_MUTEX_LOCKED (struct semaphore *sem) | ||
| 56 | { | ||
| 57 | sema_init(sem, 0); | ||
| 58 | } | ||
| 59 | |||
| 60 | extern void __down(struct semaphore * sem); | ||
| 61 | extern int __down_interruptible(struct semaphore * sem); | ||
| 62 | extern int __down_trylock(struct semaphore * sem); | ||
| 63 | extern void __up(struct semaphore * sem); | ||
| 64 | |||
| 65 | /* notice - we probably can do cli/sti here instead of saving */ | ||
| 66 | |||
| 67 | extern inline void down(struct semaphore * sem) | ||
| 68 | { | ||
| 69 | unsigned long flags; | ||
| 70 | int failed; | ||
| 71 | |||
| 72 | might_sleep(); | ||
| 73 | |||
| 74 | /* atomically decrement the semaphores count, and if its negative, we wait */ | ||
| 75 | local_save_flags(flags); | ||
| 76 | local_irq_disable(); | ||
| 77 | failed = --(sem->count.counter) < 0; | ||
| 78 | local_irq_restore(flags); | ||
| 79 | if(failed) { | ||
| 80 | __down(sem); | ||
| 81 | } | ||
| 82 | } | ||
| 83 | |||
| 84 | /* | ||
| 85 | * This version waits in interruptible state so that the waiting | ||
| 86 | * process can be killed. The down_interruptible routine | ||
| 87 | * returns negative for signalled and zero for semaphore acquired. | ||
| 88 | */ | ||
| 89 | |||
| 90 | extern inline int down_interruptible(struct semaphore * sem) | ||
| 91 | { | ||
| 92 | unsigned long flags; | ||
| 93 | int failed; | ||
| 94 | |||
| 95 | might_sleep(); | ||
| 96 | |||
| 97 | /* atomically decrement the semaphores count, and if its negative, we wait */ | ||
| 98 | local_save_flags(flags); | ||
| 99 | local_irq_disable(); | ||
| 100 | failed = --(sem->count.counter) < 0; | ||
| 101 | local_irq_restore(flags); | ||
| 102 | if(failed) | ||
| 103 | failed = __down_interruptible(sem); | ||
| 104 | return(failed); | ||
| 105 | } | ||
| 106 | |||
| 107 | extern inline int down_trylock(struct semaphore * sem) | ||
| 108 | { | ||
| 109 | unsigned long flags; | ||
| 110 | int failed; | ||
| 111 | |||
| 112 | local_save_flags(flags); | ||
| 113 | local_irq_disable(); | ||
| 114 | failed = --(sem->count.counter) < 0; | ||
| 115 | local_irq_restore(flags); | ||
| 116 | if(failed) | ||
| 117 | failed = __down_trylock(sem); | ||
| 118 | return(failed); | ||
| 119 | } | ||
| 120 | |||
| 121 | /* | ||
| 122 | * Note! This is subtle. We jump to wake people up only if | ||
| 123 | * the semaphore was negative (== somebody was waiting on it). | ||
| 124 | * The default case (no contention) will result in NO | ||
| 125 | * jumps for both down() and up(). | ||
| 126 | */ | ||
| 127 | extern inline void up(struct semaphore * sem) | ||
| 128 | { | ||
| 129 | unsigned long flags; | ||
| 130 | int wakeup; | ||
| 131 | |||
| 132 | /* atomically increment the semaphores count, and if it was negative, we wake people */ | ||
| 133 | local_save_flags(flags); | ||
| 134 | local_irq_disable(); | ||
| 135 | wakeup = ++(sem->count.counter) <= 0; | ||
| 136 | local_irq_restore(flags); | ||
| 137 | if(wakeup) { | ||
| 138 | __up(sem); | ||
| 139 | } | ||
| 140 | } | ||
| 141 | |||
| 142 | #endif | ||
diff --git a/include/asm-cris/sembuf.h b/include/asm-cris/sembuf.h new file mode 100644 index 000000000000..7fed9843796d --- /dev/null +++ b/include/asm-cris/sembuf.h | |||
| @@ -0,0 +1,25 @@ | |||
| 1 | #ifndef _CRIS_SEMBUF_H | ||
| 2 | #define _CRIS_SEMBUF_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * The semid64_ds structure for CRIS architecture. | ||
| 6 | * Note extra padding because this structure is passed back and forth | ||
| 7 | * between kernel and user space. | ||
| 8 | * | ||
| 9 | * Pad space is left for: | ||
| 10 | * - 64-bit time_t to solve y2038 problem | ||
| 11 | * - 2 miscellaneous 32-bit values | ||
| 12 | */ | ||
| 13 | |||
| 14 | struct semid64_ds { | ||
| 15 | struct ipc64_perm sem_perm; /* permissions .. see ipc.h */ | ||
| 16 | __kernel_time_t sem_otime; /* last semop time */ | ||
| 17 | unsigned long __unused1; | ||
| 18 | __kernel_time_t sem_ctime; /* last change time */ | ||
| 19 | unsigned long __unused2; | ||
| 20 | unsigned long sem_nsems; /* no. of semaphores in array */ | ||
| 21 | unsigned long __unused3; | ||
| 22 | unsigned long __unused4; | ||
| 23 | }; | ||
| 24 | |||
| 25 | #endif /* _CRIS_SEMBUF_H */ | ||
diff --git a/include/asm-cris/setup.h b/include/asm-cris/setup.h new file mode 100644 index 000000000000..b90728652d1a --- /dev/null +++ b/include/asm-cris/setup.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #ifndef _CRIS_SETUP_H | ||
| 2 | #define _CRIS_SETUP_H | ||
| 3 | |||
| 4 | #define COMMAND_LINE_SIZE 256 | ||
| 5 | |||
| 6 | #endif | ||
diff --git a/include/asm-cris/shmbuf.h b/include/asm-cris/shmbuf.h new file mode 100644 index 000000000000..3239e3f000e8 --- /dev/null +++ b/include/asm-cris/shmbuf.h | |||
| @@ -0,0 +1,42 @@ | |||
| 1 | #ifndef _CRIS_SHMBUF_H | ||
| 2 | #define _CRIS_SHMBUF_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * The shmid64_ds structure for CRIS architecture (same as for i386) | ||
| 6 | * Note extra padding because this structure is passed back and forth | ||
| 7 | * between kernel and user space. | ||
| 8 | * | ||
| 9 | * Pad space is left for: | ||
| 10 | * - 64-bit time_t to solve y2038 problem | ||
| 11 | * - 2 miscellaneous 32-bit values | ||
| 12 | */ | ||
| 13 | |||
| 14 | struct shmid64_ds { | ||
| 15 | struct ipc64_perm shm_perm; /* operation perms */ | ||
| 16 | size_t shm_segsz; /* size of segment (bytes) */ | ||
| 17 | __kernel_time_t shm_atime; /* last attach time */ | ||
| 18 | unsigned long __unused1; | ||
| 19 | __kernel_time_t shm_dtime; /* last detach time */ | ||
| 20 | unsigned long __unused2; | ||
| 21 | __kernel_time_t shm_ctime; /* last change time */ | ||
| 22 | unsigned long __unused3; | ||
| 23 | __kernel_pid_t shm_cpid; /* pid of creator */ | ||
| 24 | __kernel_pid_t shm_lpid; /* pid of last operator */ | ||
| 25 | unsigned long shm_nattch; /* no. of current attaches */ | ||
| 26 | unsigned long __unused4; | ||
| 27 | unsigned long __unused5; | ||
| 28 | }; | ||
| 29 | |||
| 30 | struct shminfo64 { | ||
| 31 | unsigned long shmmax; | ||
| 32 | unsigned long shmmin; | ||
| 33 | unsigned long shmmni; | ||
| 34 | unsigned long shmseg; | ||
| 35 | unsigned long shmall; | ||
| 36 | unsigned long __unused1; | ||
| 37 | unsigned long __unused2; | ||
| 38 | unsigned long __unused3; | ||
| 39 | unsigned long __unused4; | ||
| 40 | }; | ||
| 41 | |||
| 42 | #endif /* _CRIS_SHMBUF_H */ | ||
diff --git a/include/asm-cris/shmparam.h b/include/asm-cris/shmparam.h new file mode 100644 index 000000000000..d29d12270687 --- /dev/null +++ b/include/asm-cris/shmparam.h | |||
| @@ -0,0 +1,8 @@ | |||
| 1 | #ifndef _ASM_CRIS_SHMPARAM_H | ||
| 2 | #define _ASM_CRIS_SHMPARAM_H | ||
| 3 | |||
| 4 | /* same as asm-i386/ version.. */ | ||
| 5 | |||
| 6 | #define SHMLBA PAGE_SIZE /* attach addr a multiple of this */ | ||
| 7 | |||
| 8 | #endif /* _ASM_CRIS_SHMPARAM_H */ | ||
diff --git a/include/asm-cris/sigcontext.h b/include/asm-cris/sigcontext.h new file mode 100644 index 000000000000..a1d634e120df --- /dev/null +++ b/include/asm-cris/sigcontext.h | |||
| @@ -0,0 +1,24 @@ | |||
| 1 | /* $Id: sigcontext.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */ | ||
| 2 | |||
| 3 | #ifndef _ASM_CRIS_SIGCONTEXT_H | ||
| 4 | #define _ASM_CRIS_SIGCONTEXT_H | ||
| 5 | |||
| 6 | #include <asm/ptrace.h> | ||
| 7 | |||
| 8 | /* This struct is saved by setup_frame in signal.c, to keep the current context while | ||
| 9 | a signal handler is executed. It's restored by sys_sigreturn. | ||
| 10 | |||
| 11 | To keep things simple, we use pt_regs here even though normally you just specify | ||
| 12 | the list of regs to save. Then we can use copy_from_user on the entire regs instead | ||
| 13 | of a bunch of get_user's as well... | ||
| 14 | |||
| 15 | */ | ||
| 16 | |||
| 17 | struct sigcontext { | ||
| 18 | struct pt_regs regs; /* needs to be first */ | ||
| 19 | unsigned long oldmask; | ||
| 20 | unsigned long usp; /* usp before stacking this gunk on it */ | ||
| 21 | }; | ||
| 22 | |||
| 23 | #endif | ||
| 24 | |||
diff --git a/include/asm-cris/siginfo.h b/include/asm-cris/siginfo.h new file mode 100644 index 000000000000..c1cd6d16928b --- /dev/null +++ b/include/asm-cris/siginfo.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #ifndef _CRIS_SIGINFO_H | ||
| 2 | #define _CRIS_SIGINFO_H | ||
| 3 | |||
| 4 | #include <asm-generic/siginfo.h> | ||
| 5 | |||
| 6 | #endif | ||
diff --git a/include/asm-cris/signal.h b/include/asm-cris/signal.h new file mode 100644 index 000000000000..3f187ec4800a --- /dev/null +++ b/include/asm-cris/signal.h | |||
| @@ -0,0 +1,188 @@ | |||
| 1 | #ifndef _ASM_CRIS_SIGNAL_H | ||
| 2 | #define _ASM_CRIS_SIGNAL_H | ||
| 3 | |||
| 4 | #include <linux/types.h> | ||
| 5 | |||
| 6 | /* Avoid too many header ordering problems. */ | ||
| 7 | struct siginfo; | ||
| 8 | |||
| 9 | #ifdef __KERNEL__ | ||
| 10 | /* Most things should be clean enough to redefine this at will, if care | ||
| 11 | is taken to make libc match. */ | ||
| 12 | |||
| 13 | #define _NSIG 64 | ||
| 14 | #define _NSIG_BPW 32 | ||
| 15 | #define _NSIG_WORDS (_NSIG / _NSIG_BPW) | ||
| 16 | |||
| 17 | typedef unsigned long old_sigset_t; /* at least 32 bits */ | ||
| 18 | |||
| 19 | typedef struct { | ||
| 20 | unsigned long sig[_NSIG_WORDS]; | ||
| 21 | } sigset_t; | ||
| 22 | |||
| 23 | #else | ||
| 24 | /* Here we must cater to libcs that poke about in kernel headers. */ | ||
| 25 | |||
| 26 | #define NSIG 32 | ||
| 27 | typedef unsigned long sigset_t; | ||
| 28 | |||
| 29 | #endif /* __KERNEL__ */ | ||
| 30 | |||
| 31 | #define SIGHUP 1 | ||
| 32 | #define SIGINT 2 | ||
| 33 | #define SIGQUIT 3 | ||
| 34 | #define SIGILL 4 | ||
| 35 | #define SIGTRAP 5 | ||
| 36 | #define SIGABRT 6 | ||
| 37 | #define SIGIOT 6 | ||
| 38 | #define SIGBUS 7 | ||
| 39 | #define SIGFPE 8 | ||
| 40 | #define SIGKILL 9 | ||
| 41 | #define SIGUSR1 10 | ||
| 42 | #define SIGSEGV 11 | ||
| 43 | #define SIGUSR2 12 | ||
| 44 | #define SIGPIPE 13 | ||
| 45 | #define SIGALRM 14 | ||
| 46 | #define SIGTERM 15 | ||
| 47 | #define SIGSTKFLT 16 | ||
| 48 | #define SIGCHLD 17 | ||
| 49 | #define SIGCONT 18 | ||
| 50 | #define SIGSTOP 19 | ||
| 51 | #define SIGTSTP 20 | ||
| 52 | #define SIGTTIN 21 | ||
| 53 | #define SIGTTOU 22 | ||
| 54 | #define SIGURG 23 | ||
| 55 | #define SIGXCPU 24 | ||
| 56 | #define SIGXFSZ 25 | ||
| 57 | #define SIGVTALRM 26 | ||
| 58 | #define SIGPROF 27 | ||
| 59 | #define SIGWINCH 28 | ||
| 60 | #define SIGIO 29 | ||
| 61 | #define SIGPOLL SIGIO | ||
| 62 | /* | ||
| 63 | #define SIGLOST 29 | ||
| 64 | */ | ||
| 65 | #define SIGPWR 30 | ||
| 66 | #define SIGSYS 31 | ||
| 67 | #define SIGUNUSED 31 | ||
| 68 | |||
| 69 | /* These should not be considered constants from userland. */ | ||
| 70 | #define SIGRTMIN 32 | ||
| 71 | #define SIGRTMAX _NSIG | ||
| 72 | |||
| 73 | /* | ||
| 74 | * SA_FLAGS values: | ||
| 75 | * | ||
| 76 | * SA_ONSTACK indicates that a registered stack_t will be used. | ||
| 77 | * SA_INTERRUPT is a no-op, but left due to historical reasons. Use the | ||
| 78 | * SA_RESTART flag to get restarting signals (which were the default long ago) | ||
| 79 | * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. | ||
| 80 | * SA_RESETHAND clears the handler when the signal is delivered. | ||
| 81 | * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. | ||
| 82 | * SA_NODEFER prevents the current signal from being masked in the handler. | ||
| 83 | * | ||
| 84 | * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single | ||
| 85 | * Unix names RESETHAND and NODEFER respectively. | ||
| 86 | */ | ||
| 87 | |||
| 88 | #define SA_NOCLDSTOP 0x00000001u | ||
| 89 | #define SA_NOCLDWAIT 0x00000002u | ||
| 90 | #define SA_SIGINFO 0x00000004u | ||
| 91 | #define SA_ONSTACK 0x08000000u | ||
| 92 | #define SA_RESTART 0x10000000u | ||
| 93 | #define SA_NODEFER 0x40000000u | ||
| 94 | #define SA_RESETHAND 0x80000000u | ||
| 95 | |||
| 96 | #define SA_NOMASK SA_NODEFER | ||
| 97 | #define SA_ONESHOT SA_RESETHAND | ||
| 98 | #define SA_INTERRUPT 0x20000000 /* dummy -- ignored */ | ||
| 99 | |||
| 100 | #define SA_RESTORER 0x04000000 | ||
| 101 | |||
| 102 | /* | ||
| 103 | * sigaltstack controls | ||
| 104 | */ | ||
| 105 | #define SS_ONSTACK 1 | ||
| 106 | #define SS_DISABLE 2 | ||
| 107 | |||
| 108 | #define MINSIGSTKSZ 2048 | ||
| 109 | #define SIGSTKSZ 8192 | ||
| 110 | |||
| 111 | #ifdef __KERNEL__ | ||
| 112 | |||
| 113 | /* | ||
| 114 | * These values of sa_flags are used only by the kernel as part of the | ||
| 115 | * irq handling routines. | ||
| 116 | * | ||
| 117 | * SA_INTERRUPT is also used by the irq handling routines. | ||
| 118 | * SA_SHIRQ is for shared interrupt support | ||
| 119 | */ | ||
| 120 | #define SA_PROBE SA_ONESHOT | ||
| 121 | #define SA_SAMPLE_RANDOM SA_RESTART | ||
| 122 | #define SA_SHIRQ 0x04000000 | ||
| 123 | #endif | ||
| 124 | |||
| 125 | #define SIG_BLOCK 0 /* for blocking signals */ | ||
| 126 | #define SIG_UNBLOCK 1 /* for unblocking signals */ | ||
| 127 | #define SIG_SETMASK 2 /* for setting the signal mask */ | ||
| 128 | |||
| 129 | /* Type of a signal handler. */ | ||
| 130 | typedef void (*__sighandler_t)(int); | ||
| 131 | |||
| 132 | #define SIG_DFL ((__sighandler_t)0) /* default signal handling */ | ||
| 133 | #define SIG_IGN ((__sighandler_t)1) /* ignore signal */ | ||
| 134 | #define SIG_ERR ((__sighandler_t)-1) /* error return from signal */ | ||
| 135 | |||
| 136 | #ifdef __KERNEL__ | ||
| 137 | struct old_sigaction { | ||
| 138 | __sighandler_t sa_handler; | ||
| 139 | old_sigset_t sa_mask; | ||
| 140 | unsigned long sa_flags; | ||
| 141 | void (*sa_restorer)(void); | ||
| 142 | }; | ||
| 143 | |||
| 144 | struct sigaction { | ||
| 145 | __sighandler_t sa_handler; | ||
| 146 | unsigned long sa_flags; | ||
| 147 | void (*sa_restorer)(void); | ||
| 148 | sigset_t sa_mask; /* mask last for extensibility */ | ||
| 149 | }; | ||
| 150 | |||
| 151 | struct k_sigaction { | ||
| 152 | struct sigaction sa; | ||
| 153 | }; | ||
| 154 | #else | ||
| 155 | /* Here we must cater to libcs that poke about in kernel headers. */ | ||
| 156 | |||
| 157 | struct sigaction { | ||
| 158 | union { | ||
| 159 | __sighandler_t _sa_handler; | ||
| 160 | void (*_sa_sigaction)(int, struct siginfo *, void *); | ||
| 161 | } _u; | ||
| 162 | sigset_t sa_mask; | ||
| 163 | unsigned long sa_flags; | ||
| 164 | void (*sa_restorer)(void); | ||
| 165 | }; | ||
| 166 | |||
| 167 | #define sa_handler _u._sa_handler | ||
| 168 | #define sa_sigaction _u._sa_sigaction | ||
| 169 | |||
| 170 | #endif /* __KERNEL__ */ | ||
| 171 | |||
| 172 | typedef struct sigaltstack { | ||
| 173 | void *ss_sp; | ||
| 174 | int ss_flags; | ||
| 175 | size_t ss_size; | ||
| 176 | } stack_t; | ||
| 177 | |||
| 178 | #ifdef __KERNEL__ | ||
| 179 | #include <asm/sigcontext.h> | ||
| 180 | |||
| 181 | /* here we could define asm-optimized sigaddset, sigdelset etc. operations. | ||
| 182 | * if we don't, generic ones are used from linux/signal.h | ||
| 183 | */ | ||
| 184 | #define ptrace_signal_deliver(regs, cookie) do { } while (0) | ||
| 185 | |||
| 186 | #endif /* __KERNEL__ */ | ||
| 187 | |||
| 188 | #endif | ||
diff --git a/include/asm-cris/smp.h b/include/asm-cris/smp.h new file mode 100644 index 000000000000..c2f4feaa041d --- /dev/null +++ b/include/asm-cris/smp.h | |||
| @@ -0,0 +1,4 @@ | |||
| 1 | #ifndef __ASM_SMP_H | ||
| 2 | #define __ASM_SMP_H | ||
| 3 | |||
| 4 | #endif | ||
diff --git a/include/asm-cris/socket.h b/include/asm-cris/socket.h new file mode 100644 index 000000000000..f159b4f165f7 --- /dev/null +++ b/include/asm-cris/socket.h | |||
| @@ -0,0 +1,54 @@ | |||
| 1 | #ifndef _ASM_SOCKET_H | ||
| 2 | #define _ASM_SOCKET_H | ||
| 3 | |||
| 4 | /* almost the same as asm-i386/socket.h */ | ||
| 5 | |||
| 6 | #include <asm/sockios.h> | ||
| 7 | |||
| 8 | /* For setsockoptions(2) */ | ||
| 9 | #define SOL_SOCKET 1 | ||
| 10 | |||
| 11 | #define SO_DEBUG 1 | ||
| 12 | #define SO_REUSEADDR 2 | ||
| 13 | #define SO_TYPE 3 | ||
| 14 | #define SO_ERROR 4 | ||
| 15 | #define SO_DONTROUTE 5 | ||
| 16 | #define SO_BROADCAST 6 | ||
| 17 | #define SO_SNDBUF 7 | ||
| 18 | #define SO_RCVBUF 8 | ||
| 19 | #define SO_KEEPALIVE 9 | ||
| 20 | #define SO_OOBINLINE 10 | ||
| 21 | #define SO_NO_CHECK 11 | ||
| 22 | #define SO_PRIORITY 12 | ||
| 23 | #define SO_LINGER 13 | ||
| 24 | #define SO_BSDCOMPAT 14 | ||
| 25 | /* To add :#define SO_REUSEPORT 15 */ | ||
| 26 | #define SO_PASSCRED 16 | ||
| 27 | #define SO_PEERCRED 17 | ||
| 28 | #define SO_RCVLOWAT 18 | ||
| 29 | #define SO_SNDLOWAT 19 | ||
| 30 | #define SO_RCVTIMEO 20 | ||
| 31 | #define SO_SNDTIMEO 21 | ||
| 32 | |||
| 33 | /* Security levels - as per NRL IPv6 - don't actually do anything */ | ||
| 34 | #define SO_SECURITY_AUTHENTICATION 22 | ||
| 35 | #define SO_SECURITY_ENCRYPTION_TRANSPORT 23 | ||
| 36 | #define SO_SECURITY_ENCRYPTION_NETWORK 24 | ||
| 37 | |||
| 38 | #define SO_BINDTODEVICE 25 | ||
| 39 | |||
| 40 | /* Socket filtering */ | ||
| 41 | #define SO_ATTACH_FILTER 26 | ||
| 42 | #define SO_DETACH_FILTER 27 | ||
| 43 | |||
| 44 | #define SO_PEERNAME 28 | ||
| 45 | #define SO_TIMESTAMP 29 | ||
| 46 | #define SCM_TIMESTAMP SO_TIMESTAMP | ||
| 47 | |||
| 48 | #define SO_ACCEPTCONN 30 | ||
| 49 | |||
| 50 | #define SO_PEERSEC 31 | ||
| 51 | |||
| 52 | #endif /* _ASM_SOCKET_H */ | ||
| 53 | |||
| 54 | |||
diff --git a/include/asm-cris/sockios.h b/include/asm-cris/sockios.h new file mode 100644 index 000000000000..6c4012f0b29f --- /dev/null +++ b/include/asm-cris/sockios.h | |||
| @@ -0,0 +1,12 @@ | |||
| 1 | #ifndef __ARCH_CRIS_SOCKIOS__ | ||
| 2 | #define __ARCH_CRIS_SOCKIOS__ | ||
| 3 | |||
| 4 | /* Socket-level I/O control calls. */ | ||
| 5 | #define FIOSETOWN 0x8901 | ||
| 6 | #define SIOCSPGRP 0x8902 | ||
| 7 | #define FIOGETOWN 0x8903 | ||
| 8 | #define SIOCGPGRP 0x8904 | ||
| 9 | #define SIOCATMARK 0x8905 | ||
| 10 | #define SIOCGSTAMP 0x8906 /* Get stamp */ | ||
| 11 | |||
| 12 | #endif | ||
diff --git a/include/asm-cris/stat.h b/include/asm-cris/stat.h new file mode 100644 index 000000000000..9e558cc3c43b --- /dev/null +++ b/include/asm-cris/stat.h | |||
| @@ -0,0 +1,81 @@ | |||
| 1 | #ifndef _CRIS_STAT_H | ||
| 2 | #define _CRIS_STAT_H | ||
| 3 | |||
| 4 | /* Keep this a verbatim copy of i386 version; tweak CRIS-specific bits in | ||
| 5 | the kernel if necessary. */ | ||
| 6 | |||
| 7 | struct __old_kernel_stat { | ||
| 8 | unsigned short st_dev; | ||
| 9 | unsigned short st_ino; | ||
| 10 | unsigned short st_mode; | ||
| 11 | unsigned short st_nlink; | ||
| 12 | unsigned short st_uid; | ||
| 13 | unsigned short st_gid; | ||
| 14 | unsigned short st_rdev; | ||
| 15 | unsigned long st_size; | ||
| 16 | unsigned long st_atime; | ||
| 17 | unsigned long st_mtime; | ||
| 18 | unsigned long st_ctime; | ||
| 19 | }; | ||
| 20 | |||
| 21 | #define STAT_HAVE_NSEC 1 | ||
| 22 | |||
| 23 | struct stat { | ||
| 24 | unsigned long st_dev; | ||
| 25 | unsigned long st_ino; | ||
| 26 | unsigned short st_mode; | ||
| 27 | unsigned short st_nlink; | ||
| 28 | unsigned short st_uid; | ||
| 29 | unsigned short st_gid; | ||
| 30 | unsigned long st_rdev; | ||
| 31 | unsigned long st_size; | ||
| 32 | unsigned long st_blksize; | ||
| 33 | unsigned long st_blocks; | ||
| 34 | unsigned long st_atime; | ||
| 35 | unsigned long st_atime_nsec; | ||
| 36 | unsigned long st_mtime; | ||
| 37 | unsigned long st_mtime_nsec; | ||
| 38 | unsigned long st_ctime; | ||
| 39 | unsigned long st_ctime_nsec; | ||
| 40 | unsigned long __unused4; | ||
| 41 | unsigned long __unused5; | ||
| 42 | }; | ||
| 43 | |||
| 44 | /* This matches struct stat64 in glibc2.1, hence the absolutely | ||
| 45 | * insane amounts of padding around dev_t's. | ||
| 46 | */ | ||
| 47 | struct stat64 { | ||
| 48 | unsigned long long st_dev; | ||
| 49 | unsigned char __pad0[4]; | ||
| 50 | |||
| 51 | #define STAT64_HAS_BROKEN_ST_INO 1 | ||
| 52 | unsigned long __st_ino; | ||
| 53 | |||
| 54 | unsigned int st_mode; | ||
| 55 | unsigned int st_nlink; | ||
| 56 | |||
| 57 | unsigned long st_uid; | ||
| 58 | unsigned long st_gid; | ||
| 59 | |||
| 60 | unsigned long long st_rdev; | ||
| 61 | unsigned char __pad3[4]; | ||
| 62 | |||
| 63 | long long st_size; | ||
| 64 | unsigned long st_blksize; | ||
| 65 | |||
| 66 | unsigned long st_blocks; /* Number 512-byte blocks allocated. */ | ||
| 67 | unsigned long __pad4; /* future possible st_blocks high bits */ | ||
| 68 | |||
| 69 | unsigned long st_atime; | ||
| 70 | unsigned long st_atime_nsec; | ||
| 71 | |||
| 72 | unsigned long st_mtime; | ||
| 73 | unsigned long st_mtime_nsec; | ||
| 74 | |||
| 75 | unsigned long st_ctime; | ||
| 76 | unsigned long st_ctime_nsec; /* will be high 32 bits of ctime someday */ | ||
| 77 | |||
| 78 | unsigned long long st_ino; | ||
| 79 | }; | ||
| 80 | |||
| 81 | #endif | ||
diff --git a/include/asm-cris/statfs.h b/include/asm-cris/statfs.h new file mode 100644 index 000000000000..fdaf921844bc --- /dev/null +++ b/include/asm-cris/statfs.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #ifndef _CRIS_STATFS_H | ||
| 2 | #define _CRIS_STATFS_H | ||
| 3 | |||
| 4 | #include <asm-generic/statfs.h> | ||
| 5 | |||
| 6 | #endif | ||
diff --git a/include/asm-cris/string.h b/include/asm-cris/string.h new file mode 100644 index 000000000000..691190e99a27 --- /dev/null +++ b/include/asm-cris/string.h | |||
| @@ -0,0 +1,14 @@ | |||
| 1 | #ifndef _ASM_CRIS_STRING_H | ||
| 2 | #define _ASM_CRIS_STRING_H | ||
| 3 | |||
| 4 | /* the optimized memcpy is in arch/cris/lib/string.c */ | ||
| 5 | |||
| 6 | #define __HAVE_ARCH_MEMCPY | ||
| 7 | extern void *memcpy(void *, const void *, size_t); | ||
| 8 | |||
| 9 | /* New and improved. In arch/cris/lib/memset.c */ | ||
| 10 | |||
| 11 | #define __HAVE_ARCH_MEMSET | ||
| 12 | extern void *memset(void *, int, size_t); | ||
| 13 | |||
| 14 | #endif | ||
diff --git a/include/asm-cris/system.h b/include/asm-cris/system.h new file mode 100644 index 000000000000..e06739806d4e --- /dev/null +++ b/include/asm-cris/system.h | |||
| @@ -0,0 +1,74 @@ | |||
| 1 | #ifndef __ASM_CRIS_SYSTEM_H | ||
| 2 | #define __ASM_CRIS_SYSTEM_H | ||
| 3 | |||
| 4 | #include <asm/arch/system.h> | ||
| 5 | |||
| 6 | /* the switch_to macro calls resume, an asm function in entry.S which does the actual | ||
| 7 | * task switching. | ||
| 8 | */ | ||
| 9 | |||
| 10 | extern struct task_struct *resume(struct task_struct *prev, struct task_struct *next, int); | ||
| 11 | #define prepare_to_switch() do { } while(0) | ||
| 12 | #define switch_to(prev,next,last) last = resume(prev,next, \ | ||
| 13 | (int)&((struct task_struct *)0)->thread) | ||
| 14 | |||
| 15 | #define barrier() __asm__ __volatile__("": : :"memory") | ||
| 16 | #define mb() barrier() | ||
| 17 | #define rmb() mb() | ||
| 18 | #define wmb() mb() | ||
| 19 | #define read_barrier_depends() do { } while(0) | ||
| 20 | #define set_mb(var, value) do { var = value; mb(); } while (0) | ||
| 21 | #define set_wmb(var, value) do { var = value; wmb(); } while (0) | ||
| 22 | |||
| 23 | #ifdef CONFIG_SMP | ||
| 24 | #define smp_mb() mb() | ||
| 25 | #define smp_rmb() rmb() | ||
| 26 | #define smp_wmb() wmb() | ||
| 27 | #define smp_read_barrier_depends() read_barrier_depends() | ||
| 28 | #else | ||
| 29 | #define smp_mb() barrier() | ||
| 30 | #define smp_rmb() barrier() | ||
| 31 | #define smp_wmb() barrier() | ||
| 32 | #define smp_read_barrier_depends() do { } while(0) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #define iret() | ||
| 36 | |||
| 37 | /* | ||
| 38 | * disable hlt during certain critical i/o operations | ||
| 39 | */ | ||
| 40 | #define HAVE_DISABLE_HLT | ||
| 41 | void disable_hlt(void); | ||
| 42 | void enable_hlt(void); | ||
| 43 | |||
| 44 | extern inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size) | ||
| 45 | { | ||
| 46 | /* since Etrax doesn't have any atomic xchg instructions, we need to disable | ||
| 47 | irq's (if enabled) and do it with move.d's */ | ||
| 48 | unsigned long flags,temp; | ||
| 49 | local_save_flags(flags); /* save flags, including irq enable bit */ | ||
| 50 | local_irq_disable(); /* shut off irq's */ | ||
| 51 | switch (size) { | ||
| 52 | case 1: | ||
| 53 | *((unsigned char *)&temp) = x; | ||
| 54 | x = *(unsigned char *)ptr; | ||
| 55 | *(unsigned char *)ptr = *((unsigned char *)&temp); | ||
| 56 | break; | ||
| 57 | case 2: | ||
| 58 | *((unsigned short *)&temp) = x; | ||
| 59 | x = *(unsigned short *)ptr; | ||
| 60 | *(unsigned short *)ptr = *((unsigned short *)&temp); | ||
| 61 | break; | ||
| 62 | case 4: | ||
| 63 | temp = x; | ||
| 64 | x = *(unsigned long *)ptr; | ||
| 65 | *(unsigned long *)ptr = temp; | ||
| 66 | break; | ||
| 67 | } | ||
| 68 | local_irq_restore(flags); /* restore irq enable bit */ | ||
| 69 | return x; | ||
| 70 | } | ||
| 71 | |||
| 72 | #define arch_align_stack(x) (x) | ||
| 73 | |||
| 74 | #endif | ||
diff --git a/include/asm-cris/termbits.h b/include/asm-cris/termbits.h new file mode 100644 index 000000000000..16d9a491fdb3 --- /dev/null +++ b/include/asm-cris/termbits.h | |||
| @@ -0,0 +1,198 @@ | |||
| 1 | /* $Id: termbits.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */ | ||
| 2 | |||
| 3 | #ifndef __ARCH_ETRAX100_TERMBITS_H__ | ||
| 4 | #define __ARCH_ETRAX100_TERMBITS_H__ | ||
| 5 | |||
| 6 | #include <linux/posix_types.h> | ||
| 7 | |||
| 8 | typedef unsigned char cc_t; | ||
| 9 | typedef unsigned int speed_t; | ||
| 10 | typedef unsigned int tcflag_t; | ||
| 11 | |||
| 12 | #define NCCS 19 | ||
| 13 | struct termios { | ||
| 14 | tcflag_t c_iflag; /* input mode flags */ | ||
| 15 | tcflag_t c_oflag; /* output mode flags */ | ||
| 16 | tcflag_t c_cflag; /* control mode flags */ | ||
| 17 | tcflag_t c_lflag; /* local mode flags */ | ||
| 18 | cc_t c_line; /* line discipline */ | ||
| 19 | cc_t c_cc[NCCS]; /* control characters */ | ||
| 20 | }; | ||
| 21 | |||
| 22 | /* c_cc characters */ | ||
| 23 | #define VINTR 0 | ||
| 24 | #define VQUIT 1 | ||
| 25 | #define VERASE 2 | ||
| 26 | #define VKILL 3 | ||
| 27 | #define VEOF 4 | ||
| 28 | #define VTIME 5 | ||
| 29 | #define VMIN 6 | ||
| 30 | #define VSWTC 7 | ||
| 31 | #define VSTART 8 | ||
| 32 | #define VSTOP 9 | ||
| 33 | #define VSUSP 10 | ||
| 34 | #define VEOL 11 | ||
| 35 | #define VREPRINT 12 | ||
| 36 | #define VDISCARD 13 | ||
| 37 | #define VWERASE 14 | ||
| 38 | #define VLNEXT 15 | ||
| 39 | #define VEOL2 16 | ||
| 40 | |||
| 41 | /* c_iflag bits */ | ||
| 42 | #define IGNBRK 0000001 | ||
| 43 | #define BRKINT 0000002 | ||
| 44 | #define IGNPAR 0000004 | ||
| 45 | #define PARMRK 0000010 | ||
| 46 | #define INPCK 0000020 | ||
| 47 | #define ISTRIP 0000040 | ||
| 48 | #define INLCR 0000100 | ||
| 49 | #define IGNCR 0000200 | ||
| 50 | #define ICRNL 0000400 | ||
| 51 | #define IUCLC 0001000 | ||
| 52 | #define IXON 0002000 | ||
| 53 | #define IXANY 0004000 | ||
| 54 | #define IXOFF 0010000 | ||
| 55 | #define IMAXBEL 0020000 | ||
| 56 | #define IUTF8 0040000 | ||
| 57 | |||
| 58 | /* c_oflag bits */ | ||
| 59 | #define OPOST 0000001 | ||
| 60 | #define OLCUC 0000002 | ||
| 61 | #define ONLCR 0000004 | ||
| 62 | #define OCRNL 0000010 | ||
| 63 | #define ONOCR 0000020 | ||
| 64 | #define ONLRET 0000040 | ||
| 65 | #define OFILL 0000100 | ||
| 66 | #define OFDEL 0000200 | ||
| 67 | #define NLDLY 0000400 | ||
| 68 | #define NL0 0000000 | ||
| 69 | #define NL1 0000400 | ||
| 70 | #define CRDLY 0003000 | ||
| 71 | #define CR0 0000000 | ||
| 72 | #define CR1 0001000 | ||
| 73 | #define CR2 0002000 | ||
| 74 | #define CR3 0003000 | ||
| 75 | #define TABDLY 0014000 | ||
| 76 | #define TAB0 0000000 | ||
| 77 | #define TAB1 0004000 | ||
| 78 | #define TAB2 0010000 | ||
| 79 | #define TAB3 0014000 | ||
| 80 | #define XTABS 0014000 | ||
| 81 | #define BSDLY 0020000 | ||
| 82 | #define BS0 0000000 | ||
| 83 | #define BS1 0020000 | ||
| 84 | #define VTDLY 0040000 | ||
| 85 | #define VT0 0000000 | ||
| 86 | #define VT1 0040000 | ||
| 87 | #define FFDLY 0100000 | ||
| 88 | #define FF0 0000000 | ||
| 89 | #define FF1 0100000 | ||
| 90 | |||
| 91 | /* c_cflag bit meaning */ | ||
| 92 | /* | ||
| 93 | * 3 2 1 | ||
| 94 | * 10 987 654 321 098 765 432 109 876 543 210 | ||
| 95 | * | | ||| CBAUD | ||
| 96 | * obaud | ||
| 97 | * | ||
| 98 | * ||CSIZE | ||
| 99 | * | ||
| 100 | * |CSTOP | ||
| 101 | * |CREAD | ||
| 102 | * |CPARENB | ||
| 103 | * | ||
| 104 | * |CPARODD | ||
| 105 | * |HUPCL | ||
| 106 | * |CLOCAL | ||
| 107 | * |CBAUDEX | ||
| 108 | * 10 987 654 321 098 765 432 109 876 543 210 | ||
| 109 | * | || || CIBAUD, IBSHIFT=16 | ||
| 110 | * ibaud | ||
| 111 | * |CMSPAR | ||
| 112 | * | CRTSCTS | ||
| 113 | * x x xxx xxx x x xx Free bits | ||
| 114 | */ | ||
| 115 | |||
| 116 | #define CBAUD 0010017 | ||
| 117 | #define B0 0000000 /* hang up */ | ||
| 118 | #define B50 0000001 | ||
| 119 | #define B75 0000002 | ||
| 120 | #define B110 0000003 | ||
| 121 | #define B134 0000004 | ||
| 122 | #define B150 0000005 | ||
| 123 | #define B200 0000006 | ||
| 124 | #define B300 0000007 | ||
| 125 | #define B600 0000010 | ||
| 126 | #define B1200 0000011 | ||
| 127 | #define B1800 0000012 | ||
| 128 | #define B2400 0000013 | ||
| 129 | #define B4800 0000014 | ||
| 130 | #define B9600 0000015 | ||
| 131 | #define B19200 0000016 | ||
| 132 | #define B38400 0000017 | ||
| 133 | #define EXTA B19200 | ||
| 134 | #define EXTB B38400 | ||
| 135 | #define CSIZE 0000060 | ||
| 136 | #define CS5 0000000 | ||
| 137 | #define CS6 0000020 | ||
| 138 | #define CS7 0000040 | ||
| 139 | #define CS8 0000060 | ||
| 140 | #define CSTOPB 0000100 | ||
| 141 | #define CREAD 0000200 | ||
| 142 | #define PARENB 0000400 | ||
| 143 | #define PARODD 0001000 | ||
| 144 | #define HUPCL 0002000 | ||
| 145 | #define CLOCAL 0004000 | ||
| 146 | #define CBAUDEX 0010000 | ||
| 147 | #define B57600 0010001 | ||
| 148 | #define B115200 0010002 | ||
| 149 | #define B230400 0010003 | ||
| 150 | #define B460800 0010004 | ||
| 151 | /* etrax supports these additional three baud rates */ | ||
| 152 | #define B921600 0010005 | ||
| 153 | #define B1843200 0010006 | ||
| 154 | #define B6250000 0010007 | ||
| 155 | /* etrax 200 supports this as well */ | ||
| 156 | #define B12500000 0010010 | ||
| 157 | #define CIBAUD 002003600000 /* input baud rate (used in v32) */ | ||
| 158 | /* The values for CIBAUD bits are the same as the values for CBAUD and CBAUDEX | ||
| 159 | * shifted left IBSHIFT bits. | ||
| 160 | */ | ||
| 161 | #define IBSHIFT 16 | ||
| 162 | #define CMSPAR 010000000000 /* mark or space (stick) parity - PARODD=space*/ | ||
| 163 | #define CRTSCTS 020000000000 /* flow control */ | ||
| 164 | |||
| 165 | /* c_lflag bits */ | ||
| 166 | #define ISIG 0000001 | ||
| 167 | #define ICANON 0000002 | ||
| 168 | #define XCASE 0000004 | ||
| 169 | #define ECHO 0000010 | ||
| 170 | #define ECHOE 0000020 | ||
| 171 | #define ECHOK 0000040 | ||
| 172 | #define ECHONL 0000100 | ||
| 173 | #define NOFLSH 0000200 | ||
| 174 | #define TOSTOP 0000400 | ||
| 175 | #define ECHOCTL 0001000 | ||
| 176 | #define ECHOPRT 0002000 | ||
| 177 | #define ECHOKE 0004000 | ||
| 178 | #define FLUSHO 0010000 | ||
| 179 | #define PENDIN 0040000 | ||
| 180 | #define IEXTEN 0100000 | ||
| 181 | |||
| 182 | /* tcflow() and TCXONC use these */ | ||
| 183 | #define TCOOFF 0 | ||
| 184 | #define TCOON 1 | ||
| 185 | #define TCIOFF 2 | ||
| 186 | #define TCION 3 | ||
| 187 | |||
| 188 | /* tcflush() and TCFLSH use these */ | ||
| 189 | #define TCIFLUSH 0 | ||
| 190 | #define TCOFLUSH 1 | ||
| 191 | #define TCIOFLUSH 2 | ||
| 192 | |||
| 193 | /* tcsetattr uses these */ | ||
| 194 | #define TCSANOW 0 | ||
| 195 | #define TCSADRAIN 1 | ||
| 196 | #define TCSAFLUSH 2 | ||
| 197 | |||
| 198 | #endif | ||
diff --git a/include/asm-cris/termios.h b/include/asm-cris/termios.h new file mode 100644 index 000000000000..5ce1023c5d7b --- /dev/null +++ b/include/asm-cris/termios.h | |||
| @@ -0,0 +1,107 @@ | |||
| 1 | #ifndef _CRIS_TERMIOS_H | ||
| 2 | #define _CRIS_TERMIOS_H | ||
| 3 | |||
| 4 | #include <asm/termbits.h> | ||
| 5 | #include <asm/ioctls.h> | ||
| 6 | #include <asm/rs485.h> | ||
| 7 | |||
| 8 | struct winsize { | ||
| 9 | unsigned short ws_row; | ||
| 10 | unsigned short ws_col; | ||
| 11 | unsigned short ws_xpixel; | ||
| 12 | unsigned short ws_ypixel; | ||
| 13 | }; | ||
| 14 | |||
| 15 | #define NCC 8 | ||
| 16 | struct termio { | ||
| 17 | unsigned short c_iflag; /* input mode flags */ | ||
| 18 | unsigned short c_oflag; /* output mode flags */ | ||
| 19 | unsigned short c_cflag; /* control mode flags */ | ||
| 20 | unsigned short c_lflag; /* local mode flags */ | ||
| 21 | unsigned char c_line; /* line discipline */ | ||
| 22 | unsigned char c_cc[NCC]; /* control characters */ | ||
| 23 | }; | ||
| 24 | |||
| 25 | /* modem lines */ | ||
| 26 | #define TIOCM_LE 0x001 | ||
| 27 | #define TIOCM_DTR 0x002 | ||
| 28 | #define TIOCM_RTS 0x004 | ||
| 29 | #define TIOCM_ST 0x008 | ||
| 30 | #define TIOCM_SR 0x010 | ||
| 31 | #define TIOCM_CTS 0x020 | ||
| 32 | #define TIOCM_CAR 0x040 | ||
| 33 | #define TIOCM_RNG 0x080 | ||
| 34 | #define TIOCM_DSR 0x100 | ||
| 35 | #define TIOCM_CD TIOCM_CAR | ||
| 36 | #define TIOCM_RI TIOCM_RNG | ||
| 37 | #define TIOCM_OUT1 0x2000 | ||
| 38 | #define TIOCM_OUT2 0x4000 | ||
| 39 | #define TIOCM_LOOP 0x8000 | ||
| 40 | |||
| 41 | /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ | ||
| 42 | |||
| 43 | /* line disciplines */ | ||
| 44 | #define N_TTY 0 | ||
| 45 | #define N_SLIP 1 | ||
| 46 | #define N_MOUSE 2 | ||
| 47 | #define N_PPP 3 | ||
| 48 | #define N_STRIP 4 | ||
| 49 | #define N_AX25 5 | ||
| 50 | #define N_X25 6 /* X.25 async */ | ||
| 51 | #define N_6PACK 7 | ||
| 52 | #define N_MASC 8 /* Reserved for Mobitex module <kaz@cafe.net> */ | ||
| 53 | #define N_R3964 9 /* Reserved for Simatic R3964 module */ | ||
| 54 | #define N_PROFIBUS_FDL 10 /* Reserved for Profibus <Dave@mvhi.com> */ | ||
| 55 | #define N_IRDA 11 /* Linux IR - http://irda.sourceforge.net/ */ | ||
| 56 | #define N_SMSBLOCK 12 /* SMS block mode - for talking to GSM data cards about SMS messages */ | ||
| 57 | #define N_HDLC 13 /* synchronous HDLC */ | ||
| 58 | #define N_SYNC_PPP 14 /* synchronous PPP */ | ||
| 59 | #define N_BT 15 /* bluetooth */ | ||
| 60 | |||
| 61 | #ifdef __KERNEL__ | ||
| 62 | |||
| 63 | /* intr=^C quit=^\ erase=del kill=^U | ||
| 64 | eof=^D vtime=\0 vmin=\1 sxtc=\0 | ||
| 65 | start=^Q stop=^S susp=^Z eol=\0 | ||
| 66 | reprint=^R discard=^U werase=^W lnext=^V | ||
| 67 | eol2=\0 | ||
| 68 | */ | ||
| 69 | #define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0" | ||
| 70 | |||
| 71 | /* | ||
| 72 | * Translate a "termio" structure into a "termios". Ugh. | ||
| 73 | */ | ||
| 74 | #define SET_LOW_TERMIOS_BITS(termios, termio, x) { \ | ||
| 75 | unsigned short __tmp; \ | ||
| 76 | get_user(__tmp,&(termio)->x); \ | ||
| 77 | *(unsigned short *) &(termios)->x = __tmp; \ | ||
| 78 | } | ||
| 79 | |||
| 80 | #define user_termio_to_kernel_termios(termios, termio) \ | ||
| 81 | ({ \ | ||
| 82 | SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \ | ||
| 83 | SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \ | ||
| 84 | SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \ | ||
| 85 | SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \ | ||
| 86 | copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \ | ||
| 87 | }) | ||
| 88 | |||
| 89 | /* | ||
| 90 | * Translate a "termios" structure into a "termio". Ugh. | ||
| 91 | */ | ||
| 92 | #define kernel_termios_to_user_termio(termio, termios) \ | ||
| 93 | ({ \ | ||
| 94 | put_user((termios)->c_iflag, &(termio)->c_iflag); \ | ||
| 95 | put_user((termios)->c_oflag, &(termio)->c_oflag); \ | ||
| 96 | put_user((termios)->c_cflag, &(termio)->c_cflag); \ | ||
| 97 | put_user((termios)->c_lflag, &(termio)->c_lflag); \ | ||
| 98 | put_user((termios)->c_line, &(termio)->c_line); \ | ||
| 99 | copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ | ||
| 100 | }) | ||
| 101 | |||
| 102 | #define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios)) | ||
| 103 | #define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios)) | ||
| 104 | |||
| 105 | #endif /* __KERNEL__ */ | ||
| 106 | |||
| 107 | #endif /* _CRIS_TERMIOS_H */ | ||
diff --git a/include/asm-cris/thread_info.h b/include/asm-cris/thread_info.h new file mode 100644 index 000000000000..53193feb0826 --- /dev/null +++ b/include/asm-cris/thread_info.h | |||
| @@ -0,0 +1,101 @@ | |||
| 1 | /* thread_info.h: CRIS low-level thread information | ||
| 2 | * | ||
| 3 | * Copyright (C) 2002 David Howells (dhowells@redhat.com) | ||
| 4 | * - Incorporating suggestions made by Linus Torvalds and Dave Miller | ||
| 5 | * | ||
| 6 | * CRIS port by Axis Communications | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef _ASM_THREAD_INFO_H | ||
| 10 | #define _ASM_THREAD_INFO_H | ||
| 11 | |||
| 12 | #ifdef __KERNEL__ | ||
| 13 | |||
| 14 | #ifndef __ASSEMBLY__ | ||
| 15 | #include <asm/types.h> | ||
| 16 | #include <asm/processor.h> | ||
| 17 | #include <asm/arch/thread_info.h> | ||
| 18 | #include <asm/segment.h> | ||
| 19 | #endif | ||
| 20 | |||
| 21 | |||
| 22 | /* | ||
| 23 | * low level task data that entry.S needs immediate access to | ||
| 24 | * - this struct should fit entirely inside of one cache line | ||
| 25 | * - this struct shares the supervisor stack pages | ||
| 26 | * - if the contents of this structure are changed, the assembly constants must also be changed | ||
| 27 | */ | ||
| 28 | #ifndef __ASSEMBLY__ | ||
| 29 | struct thread_info { | ||
| 30 | struct task_struct *task; /* main task structure */ | ||
| 31 | struct exec_domain *exec_domain; /* execution domain */ | ||
| 32 | unsigned long flags; /* low level flags */ | ||
| 33 | __u32 cpu; /* current CPU */ | ||
| 34 | __s32 preempt_count; /* 0 => preemptable, <0 => BUG */ | ||
| 35 | |||
| 36 | mm_segment_t addr_limit; /* thread address space: | ||
| 37 | 0-0xBFFFFFFF for user-thead | ||
| 38 | 0-0xFFFFFFFF for kernel-thread | ||
| 39 | */ | ||
| 40 | struct restart_block restart_block; | ||
| 41 | __u8 supervisor_stack[0]; | ||
| 42 | }; | ||
| 43 | |||
| 44 | #endif | ||
| 45 | |||
| 46 | #define PREEMPT_ACTIVE 0x4000000 | ||
| 47 | |||
| 48 | /* | ||
| 49 | * macros/functions for gaining access to the thread information structure | ||
| 50 | * | ||
| 51 | * preempt_count needs to be 1 initially, until the scheduler is functional. | ||
| 52 | */ | ||
| 53 | #ifndef __ASSEMBLY__ | ||
| 54 | #define INIT_THREAD_INFO(tsk) \ | ||
| 55 | { \ | ||
| 56 | .task = &tsk, \ | ||
| 57 | .exec_domain = &default_exec_domain, \ | ||
| 58 | .flags = 0, \ | ||
| 59 | .cpu = 0, \ | ||
| 60 | .preempt_count = 1, \ | ||
| 61 | .addr_limit = KERNEL_DS, \ | ||
| 62 | .restart_block = { \ | ||
| 63 | .fn = do_no_restart_syscall, \ | ||
| 64 | }, \ | ||
| 65 | } | ||
| 66 | |||
| 67 | #define init_thread_info (init_thread_union.thread_info) | ||
| 68 | |||
| 69 | /* thread information allocation */ | ||
| 70 | #define alloc_thread_info(tsk) ((struct thread_info *) __get_free_pages(GFP_KERNEL,1)) | ||
| 71 | #define free_thread_info(ti) free_pages((unsigned long) (ti), 1) | ||
| 72 | #define get_thread_info(ti) get_task_struct((ti)->task) | ||
| 73 | #define put_thread_info(ti) put_task_struct((ti)->task) | ||
| 74 | |||
| 75 | #endif /* !__ASSEMBLY__ */ | ||
| 76 | |||
| 77 | /* | ||
| 78 | * thread information flags | ||
| 79 | * - these are process state flags that various assembly files may need to access | ||
| 80 | * - pending work-to-be-done flags are in LSW | ||
| 81 | * - other flags in MSW | ||
| 82 | */ | ||
| 83 | #define TIF_SYSCALL_TRACE 0 /* syscall trace active */ | ||
| 84 | #define TIF_NOTIFY_RESUME 1 /* resumption notification requested */ | ||
| 85 | #define TIF_SIGPENDING 2 /* signal pending */ | ||
| 86 | #define TIF_NEED_RESCHED 3 /* rescheduling necessary */ | ||
| 87 | #define TIF_POLLING_NRFLAG 16 /* true if poll_idle() is polling TIF_NEED_RESCHED */ | ||
| 88 | #define TIF_MEMDIE 17 | ||
| 89 | |||
| 90 | #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) | ||
| 91 | #define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) | ||
| 92 | #define _TIF_SIGPENDING (1<<TIF_SIGPENDING) | ||
| 93 | #define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) | ||
| 94 | #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) | ||
| 95 | |||
| 96 | #define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */ | ||
| 97 | #define _TIF_ALLWORK_MASK 0x0000FFFF /* work to do on any return to u-space */ | ||
| 98 | |||
| 99 | #endif /* __KERNEL__ */ | ||
| 100 | |||
| 101 | #endif /* _ASM_THREAD_INFO_H */ | ||
diff --git a/include/asm-cris/timex.h b/include/asm-cris/timex.h new file mode 100644 index 000000000000..375c41af47de --- /dev/null +++ b/include/asm-cris/timex.h | |||
| @@ -0,0 +1,24 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-cris/timex.h | ||
| 3 | * | ||
| 4 | * CRIS architecture timex specifications | ||
| 5 | */ | ||
| 6 | |||
| 7 | #ifndef _ASM_CRIS_TIMEX_H | ||
| 8 | #define _ASM_CRIS_TIMEX_H | ||
| 9 | |||
| 10 | #include <asm/arch/timex.h> | ||
| 11 | |||
| 12 | /* | ||
| 13 | * We don't have a cycle-counter.. but we do not support SMP anyway where this is | ||
| 14 | * used so it does not matter. | ||
| 15 | */ | ||
| 16 | |||
| 17 | typedef unsigned int cycles_t; | ||
| 18 | |||
| 19 | extern inline cycles_t get_cycles(void) | ||
| 20 | { | ||
| 21 | return 0; | ||
| 22 | } | ||
| 23 | |||
| 24 | #endif | ||
diff --git a/include/asm-cris/tlb.h b/include/asm-cris/tlb.h new file mode 100644 index 000000000000..6cc26debe40f --- /dev/null +++ b/include/asm-cris/tlb.h | |||
| @@ -0,0 +1,17 @@ | |||
| 1 | #ifndef _CRIS_TLB_H | ||
| 2 | #define _CRIS_TLB_H | ||
| 3 | |||
| 4 | #include <asm/arch/tlb.h> | ||
| 5 | |||
| 6 | /* | ||
| 7 | * cris doesn't need any special per-pte or | ||
| 8 | * per-vma handling.. | ||
| 9 | */ | ||
| 10 | #define tlb_start_vma(tlb, vma) do { } while (0) | ||
| 11 | #define tlb_end_vma(tlb, vma) do { } while (0) | ||
| 12 | #define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0) | ||
| 13 | |||
| 14 | #define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) | ||
| 15 | #include <asm-generic/tlb.h> | ||
| 16 | |||
| 17 | #endif | ||
diff --git a/include/asm-cris/tlbflush.h b/include/asm-cris/tlbflush.h new file mode 100644 index 000000000000..1781fe1a32f6 --- /dev/null +++ b/include/asm-cris/tlbflush.h | |||
| @@ -0,0 +1,43 @@ | |||
| 1 | #ifndef _CRIS_TLBFLUSH_H | ||
| 2 | #define _CRIS_TLBFLUSH_H | ||
| 3 | |||
| 4 | #include <linux/config.h> | ||
| 5 | #include <linux/mm.h> | ||
| 6 | #include <asm/processor.h> | ||
| 7 | #include <asm/pgtable.h> | ||
| 8 | #include <asm/pgalloc.h> | ||
| 9 | |||
| 10 | /* | ||
| 11 | * TLB flushing (implemented in arch/cris/mm/tlb.c): | ||
| 12 | * | ||
| 13 | * - flush_tlb() flushes the current mm struct TLBs | ||
| 14 | * - flush_tlb_all() flushes all processes TLBs | ||
| 15 | * - flush_tlb_mm(mm) flushes the specified mm context TLB's | ||
| 16 | * - flush_tlb_page(vma, vmaddr) flushes one page | ||
| 17 | * - flush_tlb_range(mm, start, end) flushes a range of pages | ||
| 18 | * | ||
| 19 | */ | ||
| 20 | |||
| 21 | extern void flush_tlb_all(void); | ||
| 22 | extern void flush_tlb_mm(struct mm_struct *mm); | ||
| 23 | extern void flush_tlb_page(struct vm_area_struct *vma, | ||
| 24 | unsigned long addr); | ||
| 25 | extern void flush_tlb_range(struct vm_area_struct *vma, | ||
| 26 | unsigned long start, | ||
| 27 | unsigned long end); | ||
| 28 | |||
| 29 | extern inline void flush_tlb_pgtables(struct mm_struct *mm, | ||
| 30 | unsigned long start, unsigned long end) | ||
| 31 | { | ||
| 32 | /* CRIS does not keep any page table caches in TLB */ | ||
| 33 | } | ||
| 34 | |||
| 35 | |||
| 36 | extern inline void flush_tlb(void) | ||
| 37 | { | ||
| 38 | flush_tlb_mm(current->mm); | ||
| 39 | } | ||
| 40 | |||
| 41 | #define flush_tlb_kernel_range(start, end) flush_tlb_all() | ||
| 42 | |||
| 43 | #endif /* _CRIS_TLBFLUSH_H */ | ||
diff --git a/include/asm-cris/topology.h b/include/asm-cris/topology.h new file mode 100644 index 000000000000..2ac613d32a89 --- /dev/null +++ b/include/asm-cris/topology.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #ifndef _ASM_CRIS_TOPOLOGY_H | ||
| 2 | #define _ASM_CRIS_TOPOLOGY_H | ||
| 3 | |||
| 4 | #include <asm-generic/topology.h> | ||
| 5 | |||
| 6 | #endif /* _ASM_CRIS_TOPOLOGY_H */ | ||
diff --git a/include/asm-cris/types.h b/include/asm-cris/types.h new file mode 100644 index 000000000000..41a0d450ba1d --- /dev/null +++ b/include/asm-cris/types.h | |||
| @@ -0,0 +1,61 @@ | |||
| 1 | #ifndef _ETRAX_TYPES_H | ||
| 2 | #define _ETRAX_TYPES_H | ||
| 3 | |||
| 4 | #ifndef __ASSEMBLY__ | ||
| 5 | |||
| 6 | typedef unsigned short umode_t; | ||
| 7 | |||
| 8 | /* | ||
| 9 | * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the | ||
| 10 | * header files exported to user space | ||
| 11 | */ | ||
| 12 | |||
| 13 | typedef __signed__ char __s8; | ||
| 14 | typedef unsigned char __u8; | ||
| 15 | |||
| 16 | typedef __signed__ short __s16; | ||
| 17 | typedef unsigned short __u16; | ||
| 18 | |||
| 19 | typedef __signed__ int __s32; | ||
| 20 | typedef unsigned int __u32; | ||
| 21 | |||
| 22 | #if defined(__GNUC__) && !defined(__STRICT_ANSI__) | ||
| 23 | typedef __signed__ long long __s64; | ||
| 24 | typedef unsigned long long __u64; | ||
| 25 | #endif | ||
| 26 | |||
| 27 | #endif /* __ASSEMBLY__ */ | ||
| 28 | |||
| 29 | /* | ||
| 30 | * These aren't exported outside the kernel to avoid name space clashes | ||
| 31 | */ | ||
| 32 | #ifdef __KERNEL__ | ||
| 33 | |||
| 34 | #define BITS_PER_LONG 32 | ||
| 35 | |||
| 36 | #ifndef __ASSEMBLY__ | ||
| 37 | |||
| 38 | typedef signed char s8; | ||
| 39 | typedef unsigned char u8; | ||
| 40 | |||
| 41 | typedef signed short s16; | ||
| 42 | typedef unsigned short u16; | ||
| 43 | |||
| 44 | typedef signed int s32; | ||
| 45 | typedef unsigned int u32; | ||
| 46 | |||
| 47 | typedef signed long long s64; | ||
| 48 | typedef unsigned long long u64; | ||
| 49 | |||
| 50 | /* Dma addresses are 32-bits wide, just like our other addresses. */ | ||
| 51 | |||
| 52 | typedef u32 dma_addr_t; | ||
| 53 | typedef u32 dma64_addr_t; | ||
| 54 | |||
| 55 | typedef unsigned int kmem_bufctl_t; | ||
| 56 | |||
| 57 | #endif /* __ASSEMBLY__ */ | ||
| 58 | |||
| 59 | #endif /* __KERNEL__ */ | ||
| 60 | |||
| 61 | #endif | ||
diff --git a/include/asm-cris/uaccess.h b/include/asm-cris/uaccess.h new file mode 100644 index 000000000000..6db17221fd9e --- /dev/null +++ b/include/asm-cris/uaccess.h | |||
| @@ -0,0 +1,446 @@ | |||
| 1 | /* | ||
| 2 | * Authors: Bjorn Wesen (bjornw@axis.com) | ||
| 3 | * Hans-Peter Nilsson (hp@axis.com) | ||
| 4 | * | ||
| 5 | * $Log: uaccess.h,v $ | ||
| 6 | * Revision 1.8 2001/10/29 13:01:48 bjornw | ||
| 7 | * Removed unused variable tmp2 in strnlen_user | ||
| 8 | * | ||
| 9 | * Revision 1.7 2001/10/02 12:44:52 hp | ||
| 10 | * Add support for 64-bit put_user/get_user | ||
| 11 | * | ||
| 12 | * Revision 1.6 2001/10/01 14:51:17 bjornw | ||
| 13 | * Added register prefixes and removed underscores | ||
| 14 | * | ||
| 15 | * Revision 1.5 2000/10/25 03:33:21 hp | ||
| 16 | * - Provide implementation for everything else but get_user and put_user; | ||
| 17 | * copying inline to/from user for constant length 0..16, 20, 24, and | ||
| 18 | * clearing for 0..4, 8, 12, 16, 20, 24, strncpy_from_user and strnlen_user | ||
| 19 | * always inline. | ||
| 20 | * - Constraints for destination addr in get_user cannot be memory, only reg. | ||
| 21 | * - Correct labels for PC at expected fault points. | ||
| 22 | * - Nits with assembly code. | ||
| 23 | * - Don't use statement expressions without value; use "do {} while (0)". | ||
| 24 | * - Return correct values from __generic_... functions. | ||
| 25 | * | ||
| 26 | * Revision 1.4 2000/09/12 16:28:25 bjornw | ||
| 27 | * * Removed comments from the get/put user asm code | ||
| 28 | * * Constrains for destination addr in put_user cannot be memory, only reg | ||
| 29 | * | ||
| 30 | * Revision 1.3 2000/09/12 14:30:20 bjornw | ||
| 31 | * MAX_ADDR_USER does not exist anymore | ||
| 32 | * | ||
| 33 | * Revision 1.2 2000/07/13 15:52:48 bjornw | ||
| 34 | * New user-access functions | ||
| 35 | * | ||
| 36 | * Revision 1.1.1.1 2000/07/10 16:32:31 bjornw | ||
| 37 | * CRIS architecture, working draft | ||
| 38 | * | ||
| 39 | * | ||
| 40 | * | ||
| 41 | */ | ||
| 42 | |||
| 43 | /* Asm:s have been tweaked (within the domain of correctness) to give | ||
| 44 | satisfactory results for "gcc version 2.96 20000427 (experimental)". | ||
| 45 | |||
| 46 | Check regularly... | ||
| 47 | |||
| 48 | Register $r9 is chosen for temporaries, being a call-clobbered register | ||
| 49 | first in line to be used (notably for local blocks), not colliding with | ||
| 50 | parameter registers. */ | ||
| 51 | |||
| 52 | #ifndef _CRIS_UACCESS_H | ||
| 53 | #define _CRIS_UACCESS_H | ||
| 54 | |||
| 55 | #ifndef __ASSEMBLY__ | ||
| 56 | #include <linux/sched.h> | ||
| 57 | #include <linux/errno.h> | ||
| 58 | #include <asm/processor.h> | ||
| 59 | #include <asm/page.h> | ||
| 60 | |||
| 61 | #define VERIFY_READ 0 | ||
| 62 | #define VERIFY_WRITE 1 | ||
| 63 | |||
| 64 | /* | ||
| 65 | * The fs value determines whether argument validity checking should be | ||
| 66 | * performed or not. If get_fs() == USER_DS, checking is performed, with | ||
| 67 | * get_fs() == KERNEL_DS, checking is bypassed. | ||
| 68 | * | ||
| 69 | * For historical reasons, these macros are grossly misnamed. | ||
| 70 | */ | ||
| 71 | |||
| 72 | #define MAKE_MM_SEG(s) ((mm_segment_t) { (s) }) | ||
| 73 | |||
| 74 | /* addr_limit is the maximum accessible address for the task. we misuse | ||
| 75 | * the KERNEL_DS and USER_DS values to both assign and compare the | ||
| 76 | * addr_limit values through the equally misnamed get/set_fs macros. | ||
| 77 | * (see above) | ||
| 78 | */ | ||
| 79 | |||
| 80 | #define KERNEL_DS MAKE_MM_SEG(0xFFFFFFFF) | ||
| 81 | #define USER_DS MAKE_MM_SEG(TASK_SIZE) | ||
| 82 | |||
| 83 | #define get_ds() (KERNEL_DS) | ||
| 84 | #define get_fs() (current_thread_info()->addr_limit) | ||
| 85 | #define set_fs(x) (current_thread_info()->addr_limit = (x)) | ||
| 86 | |||
| 87 | #define segment_eq(a,b) ((a).seg == (b).seg) | ||
| 88 | |||
| 89 | #define __kernel_ok (segment_eq(get_fs(), KERNEL_DS)) | ||
| 90 | #define __user_ok(addr,size) (((size) <= TASK_SIZE)&&((addr) <= TASK_SIZE-(size))) | ||
| 91 | #define __access_ok(addr,size) (__kernel_ok || __user_ok((addr),(size))) | ||
| 92 | #define access_ok(type,addr,size) __access_ok((unsigned long)(addr),(size)) | ||
| 93 | |||
| 94 | /* this function will go away soon - use access_ok() instead */ | ||
| 95 | extern inline int __deprecated verify_area(int type, const void __user * addr, unsigned long size) | ||
| 96 | { | ||
| 97 | return access_ok(type,addr,size) ? 0 : -EFAULT; | ||
| 98 | } | ||
| 99 | |||
| 100 | |||
| 101 | #include <asm/arch/uaccess.h> | ||
| 102 | |||
| 103 | /* | ||
| 104 | * The exception table consists of pairs of addresses: the first is the | ||
| 105 | * address of an instruction that is allowed to fault, and the second is | ||
| 106 | * the address at which the program should continue. No registers are | ||
| 107 | * modified, so it is entirely up to the continuation code to figure out | ||
| 108 | * what to do. | ||
| 109 | * | ||
| 110 | * All the routines below use bits of fixup code that are out of line | ||
| 111 | * with the main instruction path. This means when everything is well, | ||
| 112 | * we don't even have to jump over them. Further, they do not intrude | ||
| 113 | * on our cache or tlb entries. | ||
| 114 | */ | ||
| 115 | |||
| 116 | struct exception_table_entry | ||
| 117 | { | ||
| 118 | unsigned long insn, fixup; | ||
| 119 | }; | ||
| 120 | |||
| 121 | /* | ||
| 122 | * These are the main single-value transfer routines. They automatically | ||
| 123 | * use the right size if we just have the right pointer type. | ||
| 124 | * | ||
| 125 | * This gets kind of ugly. We want to return _two_ values in "get_user()" | ||
| 126 | * and yet we don't want to do any pointers, because that is too much | ||
| 127 | * of a performance impact. Thus we have a few rather ugly macros here, | ||
| 128 | * and hide all the ugliness from the user. | ||
| 129 | * | ||
| 130 | * The "__xxx" versions of the user access functions are versions that | ||
| 131 | * do not verify the address space, that must have been done previously | ||
| 132 | * with a separate "access_ok()" call (this is used when we do multiple | ||
| 133 | * accesses to the same area of user memory). | ||
| 134 | * | ||
| 135 | * As we use the same address space for kernel and user data on | ||
| 136 | * CRIS, we can just do these as direct assignments. (Of course, the | ||
| 137 | * exception handling means that it's no longer "just"...) | ||
| 138 | */ | ||
| 139 | #define get_user(x,ptr) \ | ||
| 140 | __get_user_check((x),(ptr),sizeof(*(ptr))) | ||
| 141 | #define put_user(x,ptr) \ | ||
| 142 | __put_user_check((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr))) | ||
| 143 | |||
| 144 | #define __get_user(x,ptr) \ | ||
| 145 | __get_user_nocheck((x),(ptr),sizeof(*(ptr))) | ||
| 146 | #define __put_user(x,ptr) \ | ||
| 147 | __put_user_nocheck((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr))) | ||
| 148 | |||
| 149 | extern long __put_user_bad(void); | ||
| 150 | |||
| 151 | #define __put_user_size(x,ptr,size,retval) \ | ||
| 152 | do { \ | ||
| 153 | retval = 0; \ | ||
| 154 | switch (size) { \ | ||
| 155 | case 1: __put_user_asm(x,ptr,retval,"move.b"); break; \ | ||
| 156 | case 2: __put_user_asm(x,ptr,retval,"move.w"); break; \ | ||
| 157 | case 4: __put_user_asm(x,ptr,retval,"move.d"); break; \ | ||
| 158 | case 8: __put_user_asm_64(x,ptr,retval); break; \ | ||
| 159 | default: __put_user_bad(); \ | ||
| 160 | } \ | ||
| 161 | } while (0) | ||
| 162 | |||
| 163 | #define __get_user_size(x,ptr,size,retval) \ | ||
| 164 | do { \ | ||
| 165 | retval = 0; \ | ||
| 166 | switch (size) { \ | ||
| 167 | case 1: __get_user_asm(x,ptr,retval,"move.b"); break; \ | ||
| 168 | case 2: __get_user_asm(x,ptr,retval,"move.w"); break; \ | ||
| 169 | case 4: __get_user_asm(x,ptr,retval,"move.d"); break; \ | ||
| 170 | case 8: __get_user_asm_64(x,ptr,retval); break; \ | ||
| 171 | default: (x) = __get_user_bad(); \ | ||
| 172 | } \ | ||
| 173 | } while (0) | ||
| 174 | |||
| 175 | #define __put_user_nocheck(x,ptr,size) \ | ||
| 176 | ({ \ | ||
| 177 | long __pu_err; \ | ||
| 178 | __put_user_size((x),(ptr),(size),__pu_err); \ | ||
| 179 | __pu_err; \ | ||
| 180 | }) | ||
| 181 | |||
| 182 | #define __put_user_check(x,ptr,size) \ | ||
| 183 | ({ \ | ||
| 184 | long __pu_err = -EFAULT; \ | ||
| 185 | __typeof__(*(ptr)) *__pu_addr = (ptr); \ | ||
| 186 | if (access_ok(VERIFY_WRITE,__pu_addr,size)) \ | ||
| 187 | __put_user_size((x),__pu_addr,(size),__pu_err); \ | ||
| 188 | __pu_err; \ | ||
| 189 | }) | ||
| 190 | |||
| 191 | struct __large_struct { unsigned long buf[100]; }; | ||
| 192 | #define __m(x) (*(struct __large_struct *)(x)) | ||
| 193 | |||
| 194 | |||
| 195 | |||
| 196 | #define __get_user_nocheck(x,ptr,size) \ | ||
| 197 | ({ \ | ||
| 198 | long __gu_err, __gu_val; \ | ||
| 199 | __get_user_size(__gu_val,(ptr),(size),__gu_err); \ | ||
| 200 | (x) = (__typeof__(*(ptr)))__gu_val; \ | ||
| 201 | __gu_err; \ | ||
| 202 | }) | ||
| 203 | |||
| 204 | #define __get_user_check(x,ptr,size) \ | ||
| 205 | ({ \ | ||
| 206 | long __gu_err = -EFAULT, __gu_val = 0; \ | ||
| 207 | const __typeof__(*(ptr)) *__gu_addr = (ptr); \ | ||
| 208 | if (access_ok(VERIFY_READ,__gu_addr,size)) \ | ||
| 209 | __get_user_size(__gu_val,__gu_addr,(size),__gu_err); \ | ||
| 210 | (x) = (__typeof__(*(ptr)))__gu_val; \ | ||
| 211 | __gu_err; \ | ||
| 212 | }) | ||
| 213 | |||
| 214 | extern long __get_user_bad(void); | ||
| 215 | |||
| 216 | /* More complex functions. Most are inline, but some call functions that | ||
| 217 | live in lib/usercopy.c */ | ||
| 218 | |||
| 219 | extern unsigned long __copy_user(void *to, const void *from, unsigned long n); | ||
| 220 | extern unsigned long __copy_user_zeroing(void *to, const void *from, unsigned long n); | ||
| 221 | extern unsigned long __do_clear_user(void *to, unsigned long n); | ||
| 222 | |||
| 223 | extern inline unsigned long | ||
| 224 | __generic_copy_to_user(void __user *to, const void *from, unsigned long n) | ||
| 225 | { | ||
| 226 | if (access_ok(VERIFY_WRITE, to, n)) | ||
| 227 | return __copy_user(to,from,n); | ||
| 228 | return n; | ||
| 229 | } | ||
| 230 | |||
| 231 | extern inline unsigned long | ||
| 232 | __generic_copy_from_user(void *to, const void __user *from, unsigned long n) | ||
| 233 | { | ||
| 234 | if (access_ok(VERIFY_READ, from, n)) | ||
| 235 | return __copy_user_zeroing(to,from,n); | ||
| 236 | return n; | ||
| 237 | } | ||
| 238 | |||
| 239 | extern inline unsigned long | ||
| 240 | __generic_clear_user(void __user *to, unsigned long n) | ||
| 241 | { | ||
| 242 | if (access_ok(VERIFY_WRITE, to, n)) | ||
| 243 | return __do_clear_user(to,n); | ||
| 244 | return n; | ||
| 245 | } | ||
| 246 | |||
| 247 | extern inline long | ||
| 248 | __strncpy_from_user(char *dst, const char __user *src, long count) | ||
| 249 | { | ||
| 250 | return __do_strncpy_from_user(dst, src, count); | ||
| 251 | } | ||
| 252 | |||
| 253 | extern inline long | ||
| 254 | strncpy_from_user(char *dst, const char __user *src, long count) | ||
| 255 | { | ||
| 256 | long res = -EFAULT; | ||
| 257 | if (access_ok(VERIFY_READ, src, 1)) | ||
| 258 | res = __do_strncpy_from_user(dst, src, count); | ||
| 259 | return res; | ||
| 260 | } | ||
| 261 | |||
| 262 | |||
| 263 | /* Note that if these expand awfully if made into switch constructs, so | ||
| 264 | don't do that. */ | ||
| 265 | |||
| 266 | extern inline unsigned long | ||
| 267 | __constant_copy_from_user(void *to, const void __user *from, unsigned long n) | ||
| 268 | { | ||
| 269 | unsigned long ret = 0; | ||
| 270 | if (n == 0) | ||
| 271 | ; | ||
| 272 | else if (n == 1) | ||
| 273 | __asm_copy_from_user_1(to, from, ret); | ||
| 274 | else if (n == 2) | ||
| 275 | __asm_copy_from_user_2(to, from, ret); | ||
| 276 | else if (n == 3) | ||
| 277 | __asm_copy_from_user_3(to, from, ret); | ||
| 278 | else if (n == 4) | ||
| 279 | __asm_copy_from_user_4(to, from, ret); | ||
| 280 | else if (n == 5) | ||
| 281 | __asm_copy_from_user_5(to, from, ret); | ||
| 282 | else if (n == 6) | ||
| 283 | __asm_copy_from_user_6(to, from, ret); | ||
| 284 | else if (n == 7) | ||
| 285 | __asm_copy_from_user_7(to, from, ret); | ||
| 286 | else if (n == 8) | ||
| 287 | __asm_copy_from_user_8(to, from, ret); | ||
| 288 | else if (n == 9) | ||
| 289 | __asm_copy_from_user_9(to, from, ret); | ||
| 290 | else if (n == 10) | ||
| 291 | __asm_copy_from_user_10(to, from, ret); | ||
| 292 | else if (n == 11) | ||
| 293 | __asm_copy_from_user_11(to, from, ret); | ||
| 294 | else if (n == 12) | ||
| 295 | __asm_copy_from_user_12(to, from, ret); | ||
| 296 | else if (n == 13) | ||
| 297 | __asm_copy_from_user_13(to, from, ret); | ||
| 298 | else if (n == 14) | ||
| 299 | __asm_copy_from_user_14(to, from, ret); | ||
| 300 | else if (n == 15) | ||
| 301 | __asm_copy_from_user_15(to, from, ret); | ||
| 302 | else if (n == 16) | ||
| 303 | __asm_copy_from_user_16(to, from, ret); | ||
| 304 | else if (n == 20) | ||
| 305 | __asm_copy_from_user_20(to, from, ret); | ||
| 306 | else if (n == 24) | ||
| 307 | __asm_copy_from_user_24(to, from, ret); | ||
| 308 | else | ||
| 309 | ret = __generic_copy_from_user(to, from, n); | ||
| 310 | |||
| 311 | return ret; | ||
| 312 | } | ||
| 313 | |||
| 314 | /* Ditto, don't make a switch out of this. */ | ||
| 315 | |||
| 316 | extern inline unsigned long | ||
| 317 | __constant_copy_to_user(void __user *to, const void *from, unsigned long n) | ||
| 318 | { | ||
| 319 | unsigned long ret = 0; | ||
| 320 | if (n == 0) | ||
| 321 | ; | ||
| 322 | else if (n == 1) | ||
| 323 | __asm_copy_to_user_1(to, from, ret); | ||
| 324 | else if (n == 2) | ||
| 325 | __asm_copy_to_user_2(to, from, ret); | ||
| 326 | else if (n == 3) | ||
| 327 | __asm_copy_to_user_3(to, from, ret); | ||
| 328 | else if (n == 4) | ||
| 329 | __asm_copy_to_user_4(to, from, ret); | ||
| 330 | else if (n == 5) | ||
| 331 | __asm_copy_to_user_5(to, from, ret); | ||
| 332 | else if (n == 6) | ||
| 333 | __asm_copy_to_user_6(to, from, ret); | ||
| 334 | else if (n == 7) | ||
| 335 | __asm_copy_to_user_7(to, from, ret); | ||
| 336 | else if (n == 8) | ||
| 337 | __asm_copy_to_user_8(to, from, ret); | ||
| 338 | else if (n == 9) | ||
| 339 | __asm_copy_to_user_9(to, from, ret); | ||
| 340 | else if (n == 10) | ||
| 341 | __asm_copy_to_user_10(to, from, ret); | ||
| 342 | else if (n == 11) | ||
| 343 | __asm_copy_to_user_11(to, from, ret); | ||
| 344 | else if (n == 12) | ||
| 345 | __asm_copy_to_user_12(to, from, ret); | ||
| 346 | else if (n == 13) | ||
| 347 | __asm_copy_to_user_13(to, from, ret); | ||
| 348 | else if (n == 14) | ||
| 349 | __asm_copy_to_user_14(to, from, ret); | ||
| 350 | else if (n == 15) | ||
| 351 | __asm_copy_to_user_15(to, from, ret); | ||
| 352 | else if (n == 16) | ||
| 353 | __asm_copy_to_user_16(to, from, ret); | ||
| 354 | else if (n == 20) | ||
| 355 | __asm_copy_to_user_20(to, from, ret); | ||
| 356 | else if (n == 24) | ||
| 357 | __asm_copy_to_user_24(to, from, ret); | ||
| 358 | else | ||
| 359 | ret = __generic_copy_to_user(to, from, n); | ||
| 360 | |||
| 361 | return ret; | ||
| 362 | } | ||
| 363 | |||
| 364 | /* No switch, please. */ | ||
| 365 | |||
| 366 | extern inline unsigned long | ||
| 367 | __constant_clear_user(void __user *to, unsigned long n) | ||
| 368 | { | ||
| 369 | unsigned long ret = 0; | ||
| 370 | if (n == 0) | ||
| 371 | ; | ||
| 372 | else if (n == 1) | ||
| 373 | __asm_clear_1(to, ret); | ||
| 374 | else if (n == 2) | ||
| 375 | __asm_clear_2(to, ret); | ||
| 376 | else if (n == 3) | ||
| 377 | __asm_clear_3(to, ret); | ||
| 378 | else if (n == 4) | ||
| 379 | __asm_clear_4(to, ret); | ||
| 380 | else if (n == 8) | ||
| 381 | __asm_clear_8(to, ret); | ||
| 382 | else if (n == 12) | ||
| 383 | __asm_clear_12(to, ret); | ||
| 384 | else if (n == 16) | ||
| 385 | __asm_clear_16(to, ret); | ||
| 386 | else if (n == 20) | ||
| 387 | __asm_clear_20(to, ret); | ||
| 388 | else if (n == 24) | ||
| 389 | __asm_clear_24(to, ret); | ||
| 390 | else | ||
| 391 | ret = __generic_clear_user(to, n); | ||
| 392 | |||
| 393 | return ret; | ||
| 394 | } | ||
| 395 | |||
| 396 | |||
| 397 | #define clear_user(to, n) \ | ||
| 398 | (__builtin_constant_p(n) ? \ | ||
| 399 | __constant_clear_user(to, n) : \ | ||
| 400 | __generic_clear_user(to, n)) | ||
| 401 | |||
| 402 | #define copy_from_user(to, from, n) \ | ||
| 403 | (__builtin_constant_p(n) ? \ | ||
| 404 | __constant_copy_from_user(to, from, n) : \ | ||
| 405 | __generic_copy_from_user(to, from, n)) | ||
| 406 | |||
| 407 | #define copy_to_user(to, from, n) \ | ||
| 408 | (__builtin_constant_p(n) ? \ | ||
| 409 | __constant_copy_to_user(to, from, n) : \ | ||
| 410 | __generic_copy_to_user(to, from, n)) | ||
| 411 | |||
| 412 | /* We let the __ versions of copy_from/to_user inline, because they're often | ||
| 413 | * used in fast paths and have only a small space overhead. | ||
| 414 | */ | ||
| 415 | |||
| 416 | extern inline unsigned long | ||
| 417 | __generic_copy_from_user_nocheck(void *to, const void *from, unsigned long n) | ||
| 418 | { | ||
| 419 | return __copy_user_zeroing(to,from,n); | ||
| 420 | } | ||
| 421 | |||
| 422 | extern inline unsigned long | ||
| 423 | __generic_copy_to_user_nocheck(void *to, const void *from, unsigned long n) | ||
| 424 | { | ||
| 425 | return __copy_user(to,from,n); | ||
| 426 | } | ||
| 427 | |||
| 428 | extern inline unsigned long | ||
| 429 | __generic_clear_user_nocheck(void *to, unsigned long n) | ||
| 430 | { | ||
| 431 | return __do_clear_user(to,n); | ||
| 432 | } | ||
| 433 | |||
| 434 | /* without checking */ | ||
| 435 | |||
| 436 | #define __copy_to_user(to,from,n) __generic_copy_to_user_nocheck((to),(from),(n)) | ||
| 437 | #define __copy_from_user(to,from,n) __generic_copy_from_user_nocheck((to),(from),(n)) | ||
| 438 | #define __copy_to_user_inatomic __copy_to_user | ||
| 439 | #define __copy_from_user_inatomic __copy_from_user | ||
| 440 | #define __clear_user(to,n) __generic_clear_user_nocheck((to),(n)) | ||
| 441 | |||
| 442 | #define strlen_user(str) strnlen_user((str), 0x7ffffffe) | ||
| 443 | |||
| 444 | #endif /* __ASSEMBLY__ */ | ||
| 445 | |||
| 446 | #endif /* _CRIS_UACCESS_H */ | ||
diff --git a/include/asm-cris/ucontext.h b/include/asm-cris/ucontext.h new file mode 100644 index 000000000000..eed6ad5eb3f2 --- /dev/null +++ b/include/asm-cris/ucontext.h | |||
| @@ -0,0 +1,12 @@ | |||
| 1 | #ifndef _ASM_CRIS_UCONTEXT_H | ||
| 2 | #define _ASM_CRIS_UCONTEXT_H | ||
| 3 | |||
| 4 | struct ucontext { | ||
| 5 | unsigned long uc_flags; | ||
| 6 | struct ucontext *uc_link; | ||
| 7 | stack_t uc_stack; | ||
| 8 | struct sigcontext uc_mcontext; | ||
| 9 | sigset_t uc_sigmask; /* mask last for extensibility */ | ||
| 10 | }; | ||
| 11 | |||
| 12 | #endif /* !_ASM_CRIS_UCONTEXT_H */ | ||
diff --git a/include/asm-cris/unaligned.h b/include/asm-cris/unaligned.h new file mode 100644 index 000000000000..7fbbb399f6f1 --- /dev/null +++ b/include/asm-cris/unaligned.h | |||
| @@ -0,0 +1,16 @@ | |||
| 1 | #ifndef __CRIS_UNALIGNED_H | ||
| 2 | #define __CRIS_UNALIGNED_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * CRIS can do unaligned accesses itself. | ||
| 6 | * | ||
| 7 | * The strange macros are there to make sure these can't | ||
| 8 | * be misused in a way that makes them not work on other | ||
| 9 | * architectures where unaligned accesses aren't as simple. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #define get_unaligned(ptr) (*(ptr)) | ||
| 13 | |||
| 14 | #define put_unaligned(val, ptr) ((void)( *(ptr) = (val) )) | ||
| 15 | |||
| 16 | #endif | ||
diff --git a/include/asm-cris/unistd.h b/include/asm-cris/unistd.h new file mode 100644 index 000000000000..e80bf276b101 --- /dev/null +++ b/include/asm-cris/unistd.h | |||
| @@ -0,0 +1,392 @@ | |||
| 1 | #ifndef _ASM_CRIS_UNISTD_H_ | ||
| 2 | #define _ASM_CRIS_UNISTD_H_ | ||
| 3 | |||
| 4 | #include <asm/arch/unistd.h> | ||
| 5 | |||
| 6 | /* | ||
| 7 | * This file contains the system call numbers, and stub macros for libc. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #define __NR_restart_syscall 0 | ||
| 11 | #define __NR_exit 1 | ||
| 12 | #define __NR_fork 2 | ||
| 13 | #define __NR_read 3 | ||
| 14 | #define __NR_write 4 | ||
| 15 | #define __NR_open 5 | ||
| 16 | #define __NR_close 6 | ||
| 17 | #define __NR_waitpid 7 | ||
| 18 | #define __NR_creat 8 | ||
| 19 | #define __NR_link 9 | ||
| 20 | #define __NR_unlink 10 | ||
| 21 | #define __NR_execve 11 | ||
| 22 | #define __NR_chdir 12 | ||
| 23 | #define __NR_time 13 | ||
| 24 | #define __NR_mknod 14 | ||
| 25 | #define __NR_chmod 15 | ||
| 26 | #define __NR_lchown 16 | ||
| 27 | #define __NR_break 17 | ||
| 28 | #define __NR_oldstat 18 | ||
| 29 | #define __NR_lseek 19 | ||
| 30 | #define __NR_getpid 20 | ||
| 31 | #define __NR_mount 21 | ||
| 32 | #define __NR_umount 22 | ||
| 33 | #define __NR_setuid 23 | ||
| 34 | #define __NR_getuid 24 | ||
| 35 | #define __NR_stime 25 | ||
| 36 | #define __NR_ptrace 26 | ||
| 37 | #define __NR_alarm 27 | ||
| 38 | #define __NR_oldfstat 28 | ||
| 39 | #define __NR_pause 29 | ||
| 40 | #define __NR_utime 30 | ||
| 41 | #define __NR_stty 31 | ||
| 42 | #define __NR_gtty 32 | ||
| 43 | #define __NR_access 33 | ||
| 44 | #define __NR_nice 34 | ||
| 45 | #define __NR_ftime 35 | ||
| 46 | #define __NR_sync 36 | ||
| 47 | #define __NR_kill 37 | ||
| 48 | #define __NR_rename 38 | ||
| 49 | #define __NR_mkdir 39 | ||
| 50 | #define __NR_rmdir 40 | ||
| 51 | #define __NR_dup 41 | ||
| 52 | #define __NR_pipe 42 | ||
| 53 | #define __NR_times 43 | ||
| 54 | #define __NR_prof 44 | ||
| 55 | #define __NR_brk 45 | ||
| 56 | #define __NR_setgid 46 | ||
| 57 | #define __NR_getgid 47 | ||
| 58 | #define __NR_signal 48 | ||
| 59 | #define __NR_geteuid 49 | ||
| 60 | #define __NR_getegid 50 | ||
| 61 | #define __NR_acct 51 | ||
| 62 | #define __NR_umount2 52 | ||
| 63 | #define __NR_lock 53 | ||
| 64 | #define __NR_ioctl 54 | ||
| 65 | #define __NR_fcntl 55 | ||
| 66 | #define __NR_mpx 56 | ||
| 67 | #define __NR_setpgid 57 | ||
| 68 | #define __NR_ulimit 58 | ||
| 69 | #define __NR_oldolduname 59 | ||
| 70 | #define __NR_umask 60 | ||
| 71 | #define __NR_chroot 61 | ||
| 72 | #define __NR_ustat 62 | ||
| 73 | #define __NR_dup2 63 | ||
| 74 | #define __NR_getppid 64 | ||
| 75 | #define __NR_getpgrp 65 | ||
| 76 | #define __NR_setsid 66 | ||
| 77 | #define __NR_sigaction 67 | ||
| 78 | #define __NR_sgetmask 68 | ||
| 79 | #define __NR_ssetmask 69 | ||
| 80 | #define __NR_setreuid 70 | ||
| 81 | #define __NR_setregid 71 | ||
| 82 | #define __NR_sigsuspend 72 | ||
| 83 | #define __NR_sigpending 73 | ||
| 84 | #define __NR_sethostname 74 | ||
| 85 | #define __NR_setrlimit 75 | ||
| 86 | #define __NR_getrlimit 76 | ||
| 87 | #define __NR_getrusage 77 | ||
| 88 | #define __NR_gettimeofday 78 | ||
| 89 | #define __NR_settimeofday 79 | ||
| 90 | #define __NR_getgroups 80 | ||
| 91 | #define __NR_setgroups 81 | ||
| 92 | #define __NR_select 82 | ||
| 93 | #define __NR_symlink 83 | ||
| 94 | #define __NR_oldlstat 84 | ||
| 95 | #define __NR_readlink 85 | ||
| 96 | #define __NR_uselib 86 | ||
| 97 | #define __NR_swapon 87 | ||
| 98 | #define __NR_reboot 88 | ||
| 99 | #define __NR_readdir 89 | ||
| 100 | #define __NR_mmap 90 | ||
| 101 | #define __NR_munmap 91 | ||
| 102 | #define __NR_truncate 92 | ||
| 103 | #define __NR_ftruncate 93 | ||
| 104 | #define __NR_fchmod 94 | ||
| 105 | #define __NR_fchown 95 | ||
| 106 | #define __NR_getpriority 96 | ||
| 107 | #define __NR_setpriority 97 | ||
| 108 | #define __NR_profil 98 | ||
| 109 | #define __NR_statfs 99 | ||
| 110 | #define __NR_fstatfs 100 | ||
| 111 | #define __NR_ioperm 101 | ||
| 112 | #define __NR_socketcall 102 | ||
| 113 | #define __NR_syslog 103 | ||
| 114 | #define __NR_setitimer 104 | ||
| 115 | #define __NR_getitimer 105 | ||
| 116 | #define __NR_stat 106 | ||
| 117 | #define __NR_lstat 107 | ||
| 118 | #define __NR_fstat 108 | ||
| 119 | #define __NR_olduname 109 | ||
| 120 | #define __NR_iopl 110 | ||
| 121 | #define __NR_vhangup 111 | ||
| 122 | #define __NR_idle 112 | ||
| 123 | #define __NR_vm86 113 | ||
| 124 | #define __NR_wait4 114 | ||
| 125 | #define __NR_swapoff 115 | ||
| 126 | #define __NR_sysinfo 116 | ||
| 127 | #define __NR_ipc 117 | ||
| 128 | #define __NR_fsync 118 | ||
| 129 | #define __NR_sigreturn 119 | ||
| 130 | #define __NR_clone 120 | ||
| 131 | #define __NR_setdomainname 121 | ||
| 132 | #define __NR_uname 122 | ||
| 133 | #define __NR_modify_ldt 123 | ||
| 134 | #define __NR_adjtimex 124 | ||
| 135 | #define __NR_mprotect 125 | ||
| 136 | #define __NR_sigprocmask 126 | ||
| 137 | #define __NR_create_module 127 | ||
| 138 | #define __NR_init_module 128 | ||
| 139 | #define __NR_delete_module 129 | ||
| 140 | #define __NR_get_kernel_syms 130 | ||
| 141 | #define __NR_quotactl 131 | ||
| 142 | #define __NR_getpgid 132 | ||
| 143 | #define __NR_fchdir 133 | ||
| 144 | #define __NR_bdflush 134 | ||
| 145 | #define __NR_sysfs 135 | ||
| 146 | #define __NR_personality 136 | ||
| 147 | #define __NR_afs_syscall 137 /* Syscall for Andrew File System */ | ||
| 148 | #define __NR_setfsuid 138 | ||
| 149 | #define __NR_setfsgid 139 | ||
| 150 | #define __NR__llseek 140 | ||
| 151 | #define __NR_getdents 141 | ||
| 152 | #define __NR__newselect 142 | ||
| 153 | #define __NR_flock 143 | ||
| 154 | #define __NR_msync 144 | ||
| 155 | #define __NR_readv 145 | ||
| 156 | #define __NR_writev 146 | ||
| 157 | #define __NR_getsid 147 | ||
| 158 | #define __NR_fdatasync 148 | ||
| 159 | #define __NR__sysctl 149 | ||
| 160 | #define __NR_mlock 150 | ||
| 161 | #define __NR_munlock 151 | ||
| 162 | #define __NR_mlockall 152 | ||
| 163 | #define __NR_munlockall 153 | ||
| 164 | #define __NR_sched_setparam 154 | ||
| 165 | #define __NR_sched_getparam 155 | ||
| 166 | #define __NR_sched_setscheduler 156 | ||
| 167 | #define __NR_sched_getscheduler 157 | ||
| 168 | #define __NR_sched_yield 158 | ||
| 169 | #define __NR_sched_get_priority_max 159 | ||
| 170 | #define __NR_sched_get_priority_min 160 | ||
| 171 | #define __NR_sched_rr_get_interval 161 | ||
| 172 | #define __NR_nanosleep 162 | ||
| 173 | #define __NR_mremap 163 | ||
| 174 | #define __NR_setresuid 164 | ||
| 175 | #define __NR_getresuid 165 | ||
| 176 | |||
| 177 | #define __NR_query_module 167 | ||
| 178 | #define __NR_poll 168 | ||
| 179 | #define __NR_nfsservctl 169 | ||
| 180 | #define __NR_setresgid 170 | ||
| 181 | #define __NR_getresgid 171 | ||
| 182 | #define __NR_prctl 172 | ||
| 183 | #define __NR_rt_sigreturn 173 | ||
| 184 | #define __NR_rt_sigaction 174 | ||
| 185 | #define __NR_rt_sigprocmask 175 | ||
| 186 | #define __NR_rt_sigpending 176 | ||
| 187 | #define __NR_rt_sigtimedwait 177 | ||
| 188 | #define __NR_rt_sigqueueinfo 178 | ||
| 189 | #define __NR_rt_sigsuspend 179 | ||
| 190 | #define __NR_pread64 180 | ||
| 191 | #define __NR_pwrite64 181 | ||
| 192 | #define __NR_chown 182 | ||
| 193 | #define __NR_getcwd 183 | ||
| 194 | #define __NR_capget 184 | ||
| 195 | #define __NR_capset 185 | ||
| 196 | #define __NR_sigaltstack 186 | ||
| 197 | #define __NR_sendfile 187 | ||
| 198 | #define __NR_getpmsg 188 /* some people actually want streams */ | ||
| 199 | #define __NR_putpmsg 189 /* some people actually want streams */ | ||
| 200 | #define __NR_vfork 190 | ||
| 201 | #define __NR_ugetrlimit 191 /* SuS compliant getrlimit */ | ||
| 202 | #define __NR_mmap2 192 | ||
| 203 | #define __NR_truncate64 193 | ||
| 204 | #define __NR_ftruncate64 194 | ||
| 205 | #define __NR_stat64 195 | ||
| 206 | #define __NR_lstat64 196 | ||
| 207 | #define __NR_fstat64 197 | ||
| 208 | #define __NR_lchown32 198 | ||
| 209 | #define __NR_getuid32 199 | ||
| 210 | #define __NR_getgid32 200 | ||
| 211 | #define __NR_geteuid32 201 | ||
| 212 | #define __NR_getegid32 202 | ||
| 213 | #define __NR_setreuid32 203 | ||
| 214 | #define __NR_setregid32 204 | ||
| 215 | #define __NR_getgroups32 205 | ||
| 216 | #define __NR_setgroups32 206 | ||
| 217 | #define __NR_fchown32 207 | ||
| 218 | #define __NR_setresuid32 208 | ||
| 219 | #define __NR_getresuid32 209 | ||
| 220 | #define __NR_setresgid32 210 | ||
| 221 | #define __NR_getresgid32 211 | ||
| 222 | #define __NR_chown32 212 | ||
| 223 | #define __NR_setuid32 213 | ||
| 224 | #define __NR_setgid32 214 | ||
| 225 | #define __NR_setfsuid32 215 | ||
| 226 | #define __NR_setfsgid32 216 | ||
| 227 | #define __NR_pivot_root 217 | ||
| 228 | #define __NR_mincore 218 | ||
| 229 | #define __NR_madvise 219 | ||
| 230 | #define __NR_getdents64 220 | ||
| 231 | #define __NR_fcntl64 221 | ||
| 232 | /* 223 is unused */ | ||
| 233 | #define __NR_gettid 224 | ||
| 234 | #define __NR_readahead 225 | ||
| 235 | #define __NR_setxattr 226 | ||
| 236 | #define __NR_lsetxattr 227 | ||
| 237 | #define __NR_fsetxattr 228 | ||
| 238 | #define __NR_getxattr 229 | ||
| 239 | #define __NR_lgetxattr 230 | ||
| 240 | #define __NR_fgetxattr 231 | ||
| 241 | #define __NR_listxattr 232 | ||
| 242 | #define __NR_llistxattr 233 | ||
| 243 | #define __NR_flistxattr 234 | ||
| 244 | #define __NR_removexattr 235 | ||
| 245 | #define __NR_lremovexattr 236 | ||
| 246 | #define __NR_fremovexattr 237 | ||
| 247 | #define __NR_tkill 238 | ||
| 248 | #define __NR_sendfile64 239 | ||
| 249 | #define __NR_futex 240 | ||
| 250 | #define __NR_sched_setaffinity 241 | ||
| 251 | #define __NR_sched_getaffinity 242 | ||
| 252 | #define __NR_set_thread_area 243 | ||
| 253 | #define __NR_get_thread_area 244 | ||
| 254 | #define __NR_io_setup 245 | ||
| 255 | #define __NR_io_destroy 246 | ||
| 256 | #define __NR_io_getevents 247 | ||
| 257 | #define __NR_io_submit 248 | ||
| 258 | #define __NR_io_cancel 249 | ||
| 259 | #define __NR_fadvise64 250 | ||
| 260 | #define __NR_exit_group 252 | ||
| 261 | #define __NR_lookup_dcookie 253 | ||
| 262 | #define __NR_epoll_create 254 | ||
| 263 | #define __NR_epoll_ctl 255 | ||
| 264 | #define __NR_epoll_wait 256 | ||
| 265 | #define __NR_remap_file_pages 257 | ||
| 266 | #define __NR_set_tid_address 258 | ||
| 267 | #define __NR_timer_create 259 | ||
| 268 | #define __NR_timer_settime (__NR_timer_create+1) | ||
| 269 | #define __NR_timer_gettime (__NR_timer_create+2) | ||
| 270 | #define __NR_timer_getoverrun (__NR_timer_create+3) | ||
| 271 | #define __NR_timer_delete (__NR_timer_create+4) | ||
| 272 | #define __NR_clock_settime (__NR_timer_create+5) | ||
| 273 | #define __NR_clock_gettime (__NR_timer_create+6) | ||
| 274 | #define __NR_clock_getres (__NR_timer_create+7) | ||
| 275 | #define __NR_clock_nanosleep (__NR_timer_create+8) | ||
| 276 | #define __NR_statfs64 268 | ||
| 277 | #define __NR_fstatfs64 269 | ||
| 278 | #define __NR_tgkill 270 | ||
| 279 | #define __NR_utimes 271 | ||
| 280 | #define __NR_fadvise64_64 272 | ||
| 281 | #define __NR_vserver 273 | ||
| 282 | #define __NR_mbind 274 | ||
| 283 | #define __NR_get_mempolicy 275 | ||
| 284 | #define __NR_set_mempolicy 276 | ||
| 285 | #define __NR_mq_open 277 | ||
| 286 | #define __NR_mq_unlink (__NR_mq_open+1) | ||
| 287 | #define __NR_mq_timedsend (__NR_mq_open+2) | ||
| 288 | #define __NR_mq_timedreceive (__NR_mq_open+3) | ||
| 289 | #define __NR_mq_notify (__NR_mq_open+4) | ||
| 290 | #define __NR_mq_getsetattr (__NR_mq_open+5) | ||
| 291 | |||
| 292 | #define NR_syscalls 283 | ||
| 293 | |||
| 294 | |||
| 295 | #ifdef __KERNEL__ | ||
| 296 | #define __ARCH_WANT_IPC_PARSE_VERSION | ||
| 297 | #define __ARCH_WANT_OLD_READDIR | ||
| 298 | #define __ARCH_WANT_OLD_STAT | ||
| 299 | #define __ARCH_WANT_STAT64 | ||
| 300 | #define __ARCH_WANT_SYS_ALARM | ||
| 301 | #define __ARCH_WANT_SYS_GETHOSTNAME | ||
| 302 | #define __ARCH_WANT_SYS_PAUSE | ||
| 303 | #define __ARCH_WANT_SYS_SGETMASK | ||
| 304 | #define __ARCH_WANT_SYS_SIGNAL | ||
| 305 | #define __ARCH_WANT_SYS_TIME | ||
| 306 | #define __ARCH_WANT_SYS_UTIME | ||
| 307 | #define __ARCH_WANT_SYS_WAITPID | ||
| 308 | #define __ARCH_WANT_SYS_SOCKETCALL | ||
| 309 | #define __ARCH_WANT_SYS_FADVISE64 | ||
| 310 | #define __ARCH_WANT_SYS_GETPGRP | ||
| 311 | #define __ARCH_WANT_SYS_LLSEEK | ||
| 312 | #define __ARCH_WANT_SYS_NICE | ||
| 313 | #define __ARCH_WANT_SYS_OLD_GETRLIMIT | ||
| 314 | #define __ARCH_WANT_SYS_OLDUMOUNT | ||
| 315 | #define __ARCH_WANT_SYS_SIGPENDING | ||
| 316 | #define __ARCH_WANT_SYS_SIGPROCMASK | ||
| 317 | #define __ARCH_WANT_SYS_RT_SIGACTION | ||
| 318 | #endif | ||
| 319 | |||
| 320 | #ifdef __KERNEL_SYSCALLS__ | ||
| 321 | |||
| 322 | #include <linux/compiler.h> | ||
| 323 | #include <linux/types.h> | ||
| 324 | #include <linux/linkage.h> | ||
| 325 | |||
| 326 | /* | ||
| 327 | * we need this inline - forking from kernel space will result | ||
| 328 | * in NO COPY ON WRITE (!!!), until an execve is executed. This | ||
| 329 | * is no problem, but for the stack. This is handled by not letting | ||
| 330 | * main() use the stack at all after fork(). Thus, no function | ||
| 331 | * calls - which means inline code for fork too, as otherwise we | ||
| 332 | * would use the stack upon exit from 'fork()'. | ||
| 333 | * | ||
| 334 | * Actually only pause and fork are needed inline, so that there | ||
| 335 | * won't be any messing with the stack from main(), but we define | ||
| 336 | * some others too. | ||
| 337 | */ | ||
| 338 | #define __NR__exit __NR_exit | ||
| 339 | extern inline _syscall0(pid_t,setsid) | ||
| 340 | extern inline _syscall3(int,write,int,fd,const char *,buf,off_t,count) | ||
| 341 | extern inline _syscall3(int,read,int,fd,char *,buf,off_t,count) | ||
| 342 | extern inline _syscall3(off_t,lseek,int,fd,off_t,offset,int,count) | ||
| 343 | extern inline _syscall1(int,dup,int,fd) | ||
| 344 | extern inline _syscall3(int,execve,const char *,file,char **,argv,char **,envp) | ||
| 345 | extern inline _syscall3(int,open,const char *,file,int,flag,int,mode) | ||
| 346 | extern inline _syscall1(int,close,int,fd) | ||
| 347 | |||
| 348 | struct pt_regs; | ||
| 349 | asmlinkage long sys_mmap2( | ||
| 350 | unsigned long addr, unsigned long len, | ||
| 351 | unsigned long prot, unsigned long flags, | ||
| 352 | unsigned long fd, unsigned long pgoff); | ||
| 353 | asmlinkage int sys_execve(const char *fname, char **argv, char **envp, | ||
| 354 | long r13, long mof, long srp, struct pt_regs *regs); | ||
| 355 | asmlinkage int sys_clone(unsigned long newusp, unsigned long flags, | ||
| 356 | int* parent_tid, int* child_tid, long mof, long srp, | ||
| 357 | struct pt_regs *regs); | ||
| 358 | asmlinkage int sys_fork(long r10, long r11, long r12, long r13, | ||
| 359 | long mof, long srp, struct pt_regs *regs); | ||
| 360 | asmlinkage int sys_vfork(long r10, long r11, long r12, long r13, | ||
| 361 | long mof, long srp, struct pt_regs *regs); | ||
| 362 | asmlinkage int sys_pipe(unsigned long __user *fildes); | ||
| 363 | asmlinkage int sys_ptrace(long request, long pid, long addr, long data); | ||
| 364 | struct sigaction; | ||
| 365 | asmlinkage long sys_rt_sigaction(int sig, | ||
| 366 | const struct sigaction __user *act, | ||
| 367 | struct sigaction __user *oact, | ||
| 368 | size_t sigsetsize); | ||
| 369 | |||
| 370 | /* | ||
| 371 | * Since we define it "external", it collides with the built-in | ||
| 372 | * definition, which has the "noreturn" attribute and will cause | ||
| 373 | * complaints. We don't want to use -fno-builtin, so just use a | ||
| 374 | * different name when in the kernel. | ||
| 375 | */ | ||
| 376 | #ifdef __KERNEL__ | ||
| 377 | #define _exit kernel_syscall_exit | ||
| 378 | #endif | ||
| 379 | extern inline _syscall1(int,_exit,int,exitcode) | ||
| 380 | extern inline _syscall3(pid_t,waitpid,pid_t,pid,int *,wait_stat,int,options) | ||
| 381 | #endif | ||
| 382 | |||
| 383 | |||
| 384 | /* | ||
| 385 | * "Conditional" syscalls | ||
| 386 | * | ||
| 387 | * What we want is __attribute__((weak,alias("sys_ni_syscall"))), | ||
| 388 | * but it doesn't work on all toolchains, so we just do it by hand | ||
| 389 | */ | ||
| 390 | #define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall") | ||
| 391 | |||
| 392 | #endif /* _ASM_CRIS_UNISTD_H_ */ | ||
diff --git a/include/asm-cris/user.h b/include/asm-cris/user.h new file mode 100644 index 000000000000..2538e2a003df --- /dev/null +++ b/include/asm-cris/user.h | |||
| @@ -0,0 +1,52 @@ | |||
| 1 | #ifndef __ASM_CRIS_USER_H | ||
| 2 | #define __ASM_CRIS_USER_H | ||
| 3 | |||
| 4 | #include <linux/types.h> | ||
| 5 | #include <asm/ptrace.h> | ||
| 6 | #include <asm/page.h> | ||
| 7 | #include <asm/arch/user.h> | ||
| 8 | |||
| 9 | /* | ||
| 10 | * Core file format: The core file is written in such a way that gdb | ||
| 11 | * can understand it and provide useful information to the user (under | ||
| 12 | * linux we use the `trad-core' bfd). The file contents are as follows: | ||
| 13 | * | ||
| 14 | * upage: 1 page consisting of a user struct that tells gdb | ||
| 15 | * what is present in the file. Directly after this is a | ||
| 16 | * copy of the task_struct, which is currently not used by gdb, | ||
| 17 | * but it may come in handy at some point. All of the registers | ||
| 18 | * are stored as part of the upage. The upage should always be | ||
| 19 | * only one page long. | ||
| 20 | * data: The data segment follows next. We use current->end_text to | ||
| 21 | * current->brk to pick up all of the user variables, plus any memory | ||
| 22 | * that may have been sbrk'ed. No attempt is made to determine if a | ||
| 23 | * page is demand-zero or if a page is totally unused, we just cover | ||
| 24 | * the entire range. All of the addresses are rounded in such a way | ||
| 25 | * that an integral number of pages is written. | ||
| 26 | * stack: We need the stack information in order to get a meaningful | ||
| 27 | * backtrace. We need to write the data from usp to | ||
| 28 | * current->start_stack, so we round each of these in order to be able | ||
| 29 | * to write an integer number of pages. | ||
| 30 | */ | ||
| 31 | |||
| 32 | struct user { | ||
| 33 | struct user_regs_struct regs; /* entire machine state */ | ||
| 34 | size_t u_tsize; /* text size (pages) */ | ||
| 35 | size_t u_dsize; /* data size (pages) */ | ||
| 36 | size_t u_ssize; /* stack size (pages) */ | ||
| 37 | unsigned long start_code; /* text starting address */ | ||
| 38 | unsigned long start_data; /* data starting address */ | ||
| 39 | unsigned long start_stack; /* stack starting address */ | ||
| 40 | long int signal; /* signal causing core dump */ | ||
| 41 | struct regs * u_ar0; /* help gdb find registers */ | ||
| 42 | unsigned long magic; /* identifies a core file */ | ||
| 43 | char u_comm[32]; /* user command name */ | ||
| 44 | }; | ||
| 45 | |||
| 46 | #define NBPG PAGE_SIZE | ||
| 47 | #define UPAGES 1 | ||
| 48 | #define HOST_TEXT_START_ADDR (u.start_code) | ||
| 49 | #define HOST_DATA_START_ADDR (u.start_data) | ||
| 50 | #define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG) | ||
| 51 | |||
| 52 | #endif /* __ASM_CRIS_USER_H */ | ||