diff options
author | Jesper Nilsson <jesper.nilsson@axis.com> | 2008-01-25 07:50:27 -0500 |
---|---|---|
committer | Jesper Nilsson <jesper.nilsson@axis.com> | 2008-02-08 05:06:34 -0500 |
commit | 46aac058fe525a2a659e3363fa9bcd7d6bbf2d73 (patch) | |
tree | d5b9556f308d96fd526bbeb022c5a54d66054273 /include/asm-cris | |
parent | f2bbc96a40988f0bb2e67ef21579116870b53c14 (diff) |
CRIS: Add support for ETRAX FS and ARTPEC-3 to etraxgpio.h
The CRIS v32 architectures have more gpio ports and built in PWM.
Diffstat (limited to 'include/asm-cris')
-rw-r--r-- | include/asm-cris/etraxgpio.h | 112 |
1 files changed, 94 insertions, 18 deletions
diff --git a/include/asm-cris/etraxgpio.h b/include/asm-cris/etraxgpio.h index 5d0028dba7c6..9fdb206f318d 100644 --- a/include/asm-cris/etraxgpio.h +++ b/include/asm-cris/etraxgpio.h | |||
@@ -1,25 +1,34 @@ | |||
1 | /* $Id: etraxgpio.h,v 1.8 2002/06/17 15:53:07 johana Exp $ */ | ||
2 | /* | 1 | /* |
3 | * The following devices are accessable using this driver using | 2 | * The following devices are accessable using this driver using |
4 | * GPIO_MAJOR (120) and a couple of minor numbers: | 3 | * GPIO_MAJOR (120) and a couple of minor numbers. |
5 | * For ETRAX 100LX (ARCH_V10): | 4 | * |
5 | * For ETRAX 100LX (CONFIG_ETRAX_ARCH_V10): | ||
6 | * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction | 6 | * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction |
7 | * /dev/gpiob minor 1, 8 bit GPIO, each bit can change direction | 7 | * /dev/gpiob minor 1, 8 bit GPIO, each bit can change direction |
8 | * /dev/leds minor 2, Access to leds depending on kernelconfig | 8 | * /dev/leds minor 2, Access to leds depending on kernelconfig |
9 | * /dev/gpiog minor 3 | 9 | * /dev/gpiog minor 3 |
10 | g0dir, g8_15dir, g16_23dir, g24 dir configurable in R_GEN_CONFIG | 10 | * g0dir, g8_15dir, g16_23dir, g24 dir configurable in R_GEN_CONFIG |
11 | g1-g7 and g25-g31 is both input and outputs but on different pins | 11 | * g1-g7 and g25-g31 is both input and outputs but on different pins |
12 | Also note that some bits change pins depending on what interfaces | 12 | * Also note that some bits change pins depending on what interfaces |
13 | are enabled. | 13 | * are enabled. |
14 | * | 14 | * |
15 | * For ETRAX FS (CONFIG_ETRAXFS): | ||
16 | * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction | ||
17 | * /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction | ||
18 | * /dev/gpioc minor 3, 18 bit GPIO, each bit can change direction | ||
19 | * /dev/gpiod minor 4, 18 bit GPIO, each bit can change direction | ||
20 | * /dev/gpioe minor 5, 18 bit GPIO, each bit can change direction | ||
21 | * /dev/leds minor 2, Access to leds depending on kernelconfig | ||
15 | * | 22 | * |
16 | * For ETRAX FS (ARCH_V32): | 23 | * For ARTPEC-3 (CONFIG_CRIS_MACH_ARTPEC3): |
17 | * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction | 24 | * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction |
18 | * /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction | 25 | * /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction |
19 | * /dev/gpioc minor 2, 18 bit GPIO, each bit can change direction | 26 | * /dev/gpioc minor 3, 18 bit GPIO, each bit can change direction |
20 | * /dev/gpiod minor 3, 18 bit GPIO, each bit can change direction | 27 | * /dev/gpiod minor 4, 18 bit GPIO, each bit can change direction |
21 | * /dev/gpioe minor 4, 18 bit GPIO, each bit can change direction | 28 | * /dev/leds minor 2, Access to leds depending on kernelconfig |
22 | * /dev/leds minor 5, Access to leds depending on kernelconfig | 29 | * /dev/pwm0 minor 16, PWM channel 0 on PA30 |
30 | * /dev/pwm1 minor 17, PWM channel 1 on PA31 | ||
31 | * /dev/pwm2 minor 18, PWM channel 2 on PB26 | ||
23 | * | 32 | * |
24 | */ | 33 | */ |
25 | #ifndef _ASM_ETRAXGPIO_H | 34 | #ifndef _ASM_ETRAXGPIO_H |
@@ -34,7 +43,8 @@ | |||
34 | #define GPIO_MINOR_G 3 | 43 | #define GPIO_MINOR_G 3 |
35 | #define GPIO_MINOR_LAST 3 | 44 | #define GPIO_MINOR_LAST 3 |
36 | #endif | 45 | #endif |
37 | #ifdef CONFIG_ETRAX_ARCH_V32 | 46 | |
47 | #ifdef CONFIG_ETRAXFS | ||
38 | #define ETRAXGPIO_IOCTYPE 43 | 48 | #define ETRAXGPIO_IOCTYPE 43 |
39 | #define GPIO_MINOR_A 0 | 49 | #define GPIO_MINOR_A 0 |
40 | #define GPIO_MINOR_B 1 | 50 | #define GPIO_MINOR_B 1 |
@@ -42,8 +52,32 @@ | |||
42 | #define GPIO_MINOR_C 3 | 52 | #define GPIO_MINOR_C 3 |
43 | #define GPIO_MINOR_D 4 | 53 | #define GPIO_MINOR_D 4 |
44 | #define GPIO_MINOR_E 5 | 54 | #define GPIO_MINOR_E 5 |
55 | #ifdef CONFIG_ETRAX_VIRTUAL_GPIO | ||
56 | #define GPIO_MINOR_V 6 | ||
57 | #define GPIO_MINOR_LAST 6 | ||
58 | #else | ||
45 | #define GPIO_MINOR_LAST 5 | 59 | #define GPIO_MINOR_LAST 5 |
46 | #endif | 60 | #endif |
61 | #endif | ||
62 | |||
63 | #ifdef CONFIG_CRIS_MACH_ARTPEC3 | ||
64 | #define ETRAXGPIO_IOCTYPE 43 | ||
65 | #define GPIO_MINOR_A 0 | ||
66 | #define GPIO_MINOR_B 1 | ||
67 | #define GPIO_MINOR_LEDS 2 | ||
68 | #define GPIO_MINOR_C 3 | ||
69 | #define GPIO_MINOR_D 4 | ||
70 | #ifdef CONFIG_ETRAX_VIRTUAL_GPIO | ||
71 | #define GPIO_MINOR_V 6 | ||
72 | #define GPIO_MINOR_LAST 6 | ||
73 | #else | ||
74 | #define GPIO_MINOR_LAST 4 | ||
75 | #endif | ||
76 | #define GPIO_MINOR_PWM0 16 | ||
77 | #define GPIO_MINOR_PWM1 17 | ||
78 | #define GPIO_MINOR_PWM2 18 | ||
79 | #define GPIO_MINOR_LAST_PWM GPIO_MINOR_PWM2 | ||
80 | #endif | ||
47 | 81 | ||
48 | /* supported ioctl _IOC_NR's */ | 82 | /* supported ioctl _IOC_NR's */ |
49 | 83 | ||
@@ -63,7 +97,7 @@ | |||
63 | 97 | ||
64 | /* GPIO direction ioctl's */ | 98 | /* GPIO direction ioctl's */ |
65 | #define IO_READDIR 0x8 /* Read direction 0=input 1=output (obsolete) */ | 99 | #define IO_READDIR 0x8 /* Read direction 0=input 1=output (obsolete) */ |
66 | #define IO_SETINPUT 0x9 /* Set direction for bits set, 0=unchanged 1=input, | 100 | #define IO_SETINPUT 0x9 /* Set direction for bits set, 0=unchanged 1=input, |
67 | returns mask with current inputs (obsolete) */ | 101 | returns mask with current inputs (obsolete) */ |
68 | #define IO_SETOUTPUT 0xA /* Set direction for bits set, 0=unchanged 1=output, | 102 | #define IO_SETOUTPUT 0xA /* Set direction for bits set, 0=unchanged 1=output, |
69 | returns mask with current outputs (obsolete)*/ | 103 | returns mask with current outputs (obsolete)*/ |
@@ -77,13 +111,13 @@ | |||
77 | #define IO_GET_PWR_BT 0xE | 111 | #define IO_GET_PWR_BT 0xE |
78 | 112 | ||
79 | /* Bit toggling in driver settings */ | 113 | /* Bit toggling in driver settings */ |
80 | /* bit set in low byte0 is CLK mask (0x00FF), | 114 | /* bit set in low byte0 is CLK mask (0x00FF), |
81 | bit set in byte1 is DATA mask (0xFF00) | 115 | bit set in byte1 is DATA mask (0xFF00) |
82 | msb, data_mask[7:0] , clk_mask[7:0] | 116 | msb, data_mask[7:0] , clk_mask[7:0] |
83 | */ | 117 | */ |
84 | #define IO_CFG_WRITE_MODE 0xF | 118 | #define IO_CFG_WRITE_MODE 0xF |
85 | #define IO_CFG_WRITE_MODE_VALUE(msb, data_mask, clk_mask) \ | 119 | #define IO_CFG_WRITE_MODE_VALUE(msb, data_mask, clk_mask) \ |
86 | ( (((msb)&1) << 16) | (((data_mask) &0xFF) << 8) | ((clk_mask) & 0xFF) ) | 120 | ( (((msb)&1) << 16) | (((data_mask) &0xFF) << 8) | ((clk_mask) & 0xFF) ) |
87 | 121 | ||
88 | /* The following 4 ioctl's take a pointer as argument and handles | 122 | /* The following 4 ioctl's take a pointer as argument and handles |
89 | * 32 bit ports (port G) properly. | 123 | * 32 bit ports (port G) properly. |
@@ -98,6 +132,48 @@ | |||
98 | * *arg updated with current output pins. | 132 | * *arg updated with current output pins. |
99 | */ | 133 | */ |
100 | 134 | ||
135 | /* The following ioctl's are applicable to the PWM channels only */ | ||
136 | |||
137 | #define IO_PWM_SET_MODE 0x20 | ||
138 | |||
139 | enum io_pwm_mode { | ||
140 | PWM_OFF = 0, /* disabled, deallocated */ | ||
141 | PWM_STANDARD = 1, /* 390 kHz, duty cycle 0..255/256 */ | ||
142 | PWM_FAST = 2, /* variable freq, w/ 10ns active pulse len */ | ||
143 | PWM_VARFREQ = 3 /* individually configurable high/low periods */ | ||
144 | }; | ||
145 | |||
146 | struct io_pwm_set_mode { | ||
147 | enum io_pwm_mode mode; | ||
148 | }; | ||
149 | |||
150 | /* Only for mode PWM_VARFREQ. Period lo/high set in increments of 10ns | ||
151 | * from 10ns (value = 0) to 81920ns (value = 8191) | ||
152 | * (Resulting frequencies range from 50 MHz (10ns + 10ns) down to | ||
153 | * 6.1 kHz (81920ns + 81920ns) at 50% duty cycle, to 12.2 kHz at min/max duty | ||
154 | * cycle (81920 + 10ns or 10ns + 81920ns, respectively).) | ||
155 | */ | ||
156 | #define IO_PWM_SET_PERIOD 0x21 | ||
157 | |||
158 | struct io_pwm_set_period { | ||
159 | int lo; /* 0..8191 */ | ||
160 | int hi; /* 0..8191 */ | ||
161 | }; | ||
162 | |||
163 | /* Only for modes PWM_STANDARD and PWM_FAST. | ||
164 | * For PWM_STANDARD, set duty cycle of 390 kHz PWM output signal, from | ||
165 | * 0 (value = 0) to 255/256 (value = 255). | ||
166 | * For PWM_FAST, set duty cycle of PWM output signal from | ||
167 | * 0% (value = 0) to 100% (value = 255). Output signal in this mode | ||
168 | * is a 10ns pulse surrounded by a high or low level depending on duty | ||
169 | * cycle (except for 0% and 100% which result in a constant output). | ||
170 | * Resulting output frequency varies from 50 MHz at 50% duty cycle, | ||
171 | * down to 390 kHz at min/max duty cycle. | ||
172 | */ | ||
173 | #define IO_PWM_SET_DUTY 0x22 | ||
101 | 174 | ||
175 | struct io_pwm_set_duty { | ||
176 | int duty; /* 0..255 */ | ||
177 | }; | ||
102 | 178 | ||
103 | #endif | 179 | #endif |