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authorJesper Nilsson <jespern@stork.se.axis.com>2007-11-29 11:21:59 -0500
committerJesper Nilsson <jesper.nilsson@axis.com>2008-02-08 05:06:23 -0500
commit58d083192825c5fbd46fa0b1ff4d1ecc9118b692 (patch)
tree3bd39bf385afe376272d4769c0af321d6e8ed992 /include/asm-cris/arch-v32
parent035e111f9a9b29843bc899f03d56f19d94bebb53 (diff)
CRIS v32: Add hardware dependent include files and defconfigs for ETRAX FS and ARTPEC-3 chips.
The header files describe the hardware registers available in both these chips, note that most of this documentation is automatically generated from the hardware implementation.
Diffstat (limited to 'include/asm-cris/arch-v32')
-rw-r--r--include/asm-cris/arch-v32/mach-a3/arbiter.h34
-rw-r--r--include/asm-cris/arch-v32/mach-a3/dma.h31
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/asm/clkgen_defs_asm.h164
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/asm/ddr2_defs_asm.h266
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/asm/gio_defs_asm.h849
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/asm/pinmux_defs_asm.h572
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/asm/pio_defs_asm.h337
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/asm/reg_map_asm.h99
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/asm/timer_defs_asm.h228
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/clkgen_defs.h159
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/ddr2_defs.h281
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/gio_defs.h837
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect.h46
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect_defs.h341
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_reg_space_asm.h31
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_in_defs_asm.h109
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_out_defs_asm.h276
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cfg_defs_asm.h739
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cpu_defs_asm.h950
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_mpu_defs_asm.h1086
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_spu_defs_asm.h523
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_version_defs_asm.h61
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_reg_space.h31
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_in_defs.h141
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_out_defs.h231
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cfg_defs.h725
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cpu_defs.h522
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_mpu_defs.h648
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_spu_defs.h441
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_version_defs.h96
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/l2cache_defs.h142
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/marb_bar_defs.h482
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/marb_foo_defs.h626
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/pinmux_defs.h312
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/pio_defs.h371
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/reg_map.h103
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/strmux_defs.h120
-rw-r--r--include/asm-cris/arch-v32/mach-a3/hwregs/timer_defs.h265
-rw-r--r--include/asm-cris/arch-v32/mach-a3/memmap.h10
-rw-r--r--include/asm-cris/arch-v32/mach-a3/pinmux.h45
-rw-r--r--include/asm-cris/arch-v32/mach-a3/startup.inc60
-rw-r--r--include/asm-cris/arch-v32/mach-fs/arbiter.h28
-rw-r--r--include/asm-cris/arch-v32/mach-fs/hwregs/asm/bif_core_defs_asm.h319
-rw-r--r--include/asm-cris/arch-v32/mach-fs/hwregs/asm/config_defs_asm.h131
-rw-r--r--include/asm-cris/arch-v32/mach-fs/hwregs/asm/gio_defs_asm.h276
-rw-r--r--include/asm-cris/arch-v32/mach-fs/hwregs/asm/pinmux_defs_asm.h632
-rw-r--r--include/asm-cris/arch-v32/mach-fs/hwregs/asm/reg_map_asm.h96
-rw-r--r--include/asm-cris/arch-v32/mach-fs/hwregs/asm/timer_defs_asm.h229
-rw-r--r--include/asm-cris/arch-v32/mach-fs/hwregs/bif_core_defs.h284
-rw-r--r--include/asm-cris/arch-v32/mach-fs/hwregs/bif_dma_defs.h473
-rw-r--r--include/asm-cris/arch-v32/mach-fs/hwregs/bif_slave_defs.h249
-rw-r--r--include/asm-cris/arch-v32/mach-fs/hwregs/config_defs.h142
-rw-r--r--include/asm-cris/arch-v32/mach-fs/hwregs/gio_defs.h295
-rw-r--r--include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect.h41
-rw-r--r--include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect_defs.h228
-rw-r--r--include/asm-cris/arch-v32/mach-fs/hwregs/marb_bp_defs.h205
-rw-r--r--include/asm-cris/arch-v32/mach-fs/hwregs/marb_defs.h475
-rw-r--r--include/asm-cris/arch-v32/mach-fs/hwregs/pinmux_defs.h357
-rw-r--r--include/asm-cris/arch-v32/mach-fs/hwregs/reg_map.h104
-rw-r--r--include/asm-cris/arch-v32/mach-fs/hwregs/strmux_defs.h127
-rw-r--r--include/asm-cris/arch-v32/mach-fs/hwregs/timer_defs.h266
-rw-r--r--include/asm-cris/arch-v32/mach-fs/pinmux.h38
-rw-r--r--include/asm-cris/arch-v32/mach-fs/startup.inc77
63 files changed, 18462 insertions, 0 deletions
diff --git a/include/asm-cris/arch-v32/mach-a3/arbiter.h b/include/asm-cris/arch-v32/mach-a3/arbiter.h
new file mode 100644
index 000000000000..50a89351e62b
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/arbiter.h
@@ -0,0 +1,34 @@
1#ifndef _ASM_CRIS_ARCH_ARBITER_H
2#define _ASM_CRIS_ARCH_ARBITER_H
3
4#define EXT_REGION 0
5#define INT_REGION 1
6
7typedef void (watch_callback)(void);
8
9enum {
10 arbiter_all_dmas = 0x7fe,
11 arbiter_cpu = 0x1800,
12 arbiter_all_clients = 0x7fff
13};
14
15enum {
16 arbiter_bar_all_clients = 0x1ff
17};
18
19enum {
20 arbiter_all_read = 0x55,
21 arbiter_all_write = 0xaa,
22 arbiter_all_accesses = 0xff
23};
24
25#define MARB_CLIENTS(foo_cli, bar_cli) (((bar_cli) << 16) | (foo_cli))
26
27int crisv32_arbiter_allocate_bandwith(int client, int region,
28 unsigned long bandwidth);
29int crisv32_arbiter_watch(unsigned long start, unsigned long size,
30 unsigned long clients, unsigned long accesses,
31 watch_callback * cb);
32int crisv32_arbiter_unwatch(int id);
33
34#endif
diff --git a/include/asm-cris/arch-v32/mach-a3/dma.h b/include/asm-cris/arch-v32/mach-a3/dma.h
new file mode 100644
index 000000000000..9e8eb13b601d
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/dma.h
@@ -0,0 +1,31 @@
1#ifndef _ASM_ARCH_CRIS_DMA_H
2#define _ASM_ARCH_CRIS_DMA_H
3
4/* Defines for using and allocating dma channels. */
5
6#define MAX_DMA_CHANNELS 12 /* 8 and 10 not used. */
7
8enum dma_owner {
9 dma_eth,
10 dma_ser0,
11 dma_ser1,
12 dma_ser2,
13 dma_ser3,
14 dma_ser4,
15 dma_iop,
16 dma_sser,
17 dma_strp,
18 dma_h264,
19 dma_jpeg
20};
21
22int crisv32_request_dma(unsigned int dmanr, const char *device_id,
23 unsigned options, unsigned bandwidth, enum dma_owner owner);
24void crisv32_free_dma(unsigned int dmanr);
25
26/* Masks used by crisv32_request_dma options: */
27#define DMA_VERBOSE_ON_ERROR 1
28#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR)
29#define DMA_INT_MEM 4
30
31#endif /* _ASM_ARCH_CRIS_DMA_H */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/clkgen_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/clkgen_defs_asm.h
new file mode 100644
index 000000000000..02855adf63e8
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/clkgen_defs_asm.h
@@ -0,0 +1,164 @@
1#ifndef __clkgen_defs_asm_h
2#define __clkgen_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: clkgen.r
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -asm -outfile clkgen_defs_asm.h clkgen.r
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13
14#ifndef REG_FIELD
15#define REG_FIELD( scope, reg, field, value ) \
16 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
17#define REG_FIELD_X_( value, shift ) ((value) << shift)
18#endif
19
20#ifndef REG_STATE
21#define REG_STATE( scope, reg, field, symbolic_value ) \
22 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
23#define REG_STATE_X_( k, shift ) (k << shift)
24#endif
25
26#ifndef REG_MASK
27#define REG_MASK( scope, reg, field ) \
28 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
29#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
30#endif
31
32#ifndef REG_LSB
33#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
34#endif
35
36#ifndef REG_BIT
37#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
38#endif
39
40#ifndef REG_ADDR
41#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
42#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
43#endif
44
45#ifndef REG_ADDR_VECT
46#define REG_ADDR_VECT( scope, inst, reg, index ) \
47 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
48 STRIDE_##scope##_##reg )
49#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
50 ((inst) + offs + (index) * stride)
51#endif
52
53/* Register r_bootsel, scope clkgen, type r */
54#define reg_clkgen_r_bootsel___boot_mode___lsb 0
55#define reg_clkgen_r_bootsel___boot_mode___width 5
56#define reg_clkgen_r_bootsel___intern_main_clk___lsb 5
57#define reg_clkgen_r_bootsel___intern_main_clk___width 1
58#define reg_clkgen_r_bootsel___intern_main_clk___bit 5
59#define reg_clkgen_r_bootsel___extern_usb2_clk___lsb 6
60#define reg_clkgen_r_bootsel___extern_usb2_clk___width 1
61#define reg_clkgen_r_bootsel___extern_usb2_clk___bit 6
62#define reg_clkgen_r_bootsel_offset 0
63
64/* Register rw_clk_ctrl, scope clkgen, type rw */
65#define reg_clkgen_rw_clk_ctrl___pll___lsb 0
66#define reg_clkgen_rw_clk_ctrl___pll___width 1
67#define reg_clkgen_rw_clk_ctrl___pll___bit 0
68#define reg_clkgen_rw_clk_ctrl___cpu___lsb 1
69#define reg_clkgen_rw_clk_ctrl___cpu___width 1
70#define reg_clkgen_rw_clk_ctrl___cpu___bit 1
71#define reg_clkgen_rw_clk_ctrl___iop_usb___lsb 2
72#define reg_clkgen_rw_clk_ctrl___iop_usb___width 1
73#define reg_clkgen_rw_clk_ctrl___iop_usb___bit 2
74#define reg_clkgen_rw_clk_ctrl___vin___lsb 3
75#define reg_clkgen_rw_clk_ctrl___vin___width 1
76#define reg_clkgen_rw_clk_ctrl___vin___bit 3
77#define reg_clkgen_rw_clk_ctrl___sclr___lsb 4
78#define reg_clkgen_rw_clk_ctrl___sclr___width 1
79#define reg_clkgen_rw_clk_ctrl___sclr___bit 4
80#define reg_clkgen_rw_clk_ctrl___h264___lsb 5
81#define reg_clkgen_rw_clk_ctrl___h264___width 1
82#define reg_clkgen_rw_clk_ctrl___h264___bit 5
83#define reg_clkgen_rw_clk_ctrl___ddr2___lsb 6
84#define reg_clkgen_rw_clk_ctrl___ddr2___width 1
85#define reg_clkgen_rw_clk_ctrl___ddr2___bit 6
86#define reg_clkgen_rw_clk_ctrl___vout_hist___lsb 7
87#define reg_clkgen_rw_clk_ctrl___vout_hist___width 1
88#define reg_clkgen_rw_clk_ctrl___vout_hist___bit 7
89#define reg_clkgen_rw_clk_ctrl___eth___lsb 8
90#define reg_clkgen_rw_clk_ctrl___eth___width 1
91#define reg_clkgen_rw_clk_ctrl___eth___bit 8
92#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___lsb 9
93#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___width 1
94#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___bit 9
95#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___lsb 10
96#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___width 1
97#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___bit 10
98#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___lsb 11
99#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___width 1
100#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___bit 11
101#define reg_clkgen_rw_clk_ctrl___jpeg___lsb 12
102#define reg_clkgen_rw_clk_ctrl___jpeg___width 1
103#define reg_clkgen_rw_clk_ctrl___jpeg___bit 12
104#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___lsb 13
105#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___width 1
106#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___bit 13
107#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___lsb 14
108#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___width 1
109#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___bit 14
110#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___lsb 15
111#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___width 1
112#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___bit 15
113#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___lsb 16
114#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___width 1
115#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___bit 16
116#define reg_clkgen_rw_clk_ctrl___dma9_11___lsb 17
117#define reg_clkgen_rw_clk_ctrl___dma9_11___width 1
118#define reg_clkgen_rw_clk_ctrl___dma9_11___bit 17
119#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___lsb 18
120#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___width 1
121#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___bit 18
122#define reg_clkgen_rw_clk_ctrl___sclr_h264___lsb 19
123#define reg_clkgen_rw_clk_ctrl___sclr_h264___width 1
124#define reg_clkgen_rw_clk_ctrl___sclr_h264___bit 19
125#define reg_clkgen_rw_clk_ctrl_offset 4
126
127
128/* Constants */
129#define regk_clkgen_eth1000_rx 0x0000000c
130#define regk_clkgen_eth1000_tx 0x0000000e
131#define regk_clkgen_eth100_rx 0x0000001d
132#define regk_clkgen_eth100_rx_half 0x0000001c
133#define regk_clkgen_eth100_tx 0x0000001f
134#define regk_clkgen_eth100_tx_half 0x0000001e
135#define regk_clkgen_nand_3_2 0x00000000
136#define regk_clkgen_nand_3_2_0x30 0x00000002
137#define regk_clkgen_nand_3_2_0x30_pll 0x00000012
138#define regk_clkgen_nand_3_2_pll 0x00000010
139#define regk_clkgen_nand_3_3 0x00000001
140#define regk_clkgen_nand_3_3_0x30 0x00000003
141#define regk_clkgen_nand_3_3_0x30_pll 0x00000013
142#define regk_clkgen_nand_3_3_pll 0x00000011
143#define regk_clkgen_nand_4_2 0x00000004
144#define regk_clkgen_nand_4_2_0x30 0x00000006
145#define regk_clkgen_nand_4_2_0x30_pll 0x00000016
146#define regk_clkgen_nand_4_2_pll 0x00000014
147#define regk_clkgen_nand_4_3 0x00000005
148#define regk_clkgen_nand_4_3_0x30 0x00000007
149#define regk_clkgen_nand_4_3_0x30_pll 0x00000017
150#define regk_clkgen_nand_4_3_pll 0x00000015
151#define regk_clkgen_nand_5_2 0x00000008
152#define regk_clkgen_nand_5_2_0x30 0x0000000a
153#define regk_clkgen_nand_5_2_0x30_pll 0x0000001a
154#define regk_clkgen_nand_5_2_pll 0x00000018
155#define regk_clkgen_nand_5_3 0x00000009
156#define regk_clkgen_nand_5_3_0x30 0x0000000b
157#define regk_clkgen_nand_5_3_0x30_pll 0x0000001b
158#define regk_clkgen_nand_5_3_pll 0x00000019
159#define regk_clkgen_no 0x00000000
160#define regk_clkgen_rw_clk_ctrl_default 0x00000002
161#define regk_clkgen_ser 0x0000000d
162#define regk_clkgen_ser_pll 0x0000000f
163#define regk_clkgen_yes 0x00000001
164#endif /* __clkgen_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/ddr2_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/ddr2_defs_asm.h
new file mode 100644
index 000000000000..b12be03edacb
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/ddr2_defs_asm.h
@@ -0,0 +1,266 @@
1#ifndef __ddr2_defs_asm_h
2#define __ddr2_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ddr2.r
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -asm -outfile ddr2_defs_asm.h ddr2.r
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13
14#ifndef REG_FIELD
15#define REG_FIELD( scope, reg, field, value ) \
16 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
17#define REG_FIELD_X_( value, shift ) ((value) << shift)
18#endif
19
20#ifndef REG_STATE
21#define REG_STATE( scope, reg, field, symbolic_value ) \
22 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
23#define REG_STATE_X_( k, shift ) (k << shift)
24#endif
25
26#ifndef REG_MASK
27#define REG_MASK( scope, reg, field ) \
28 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
29#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
30#endif
31
32#ifndef REG_LSB
33#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
34#endif
35
36#ifndef REG_BIT
37#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
38#endif
39
40#ifndef REG_ADDR
41#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
42#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
43#endif
44
45#ifndef REG_ADDR_VECT
46#define REG_ADDR_VECT( scope, inst, reg, index ) \
47 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
48 STRIDE_##scope##_##reg )
49#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
50 ((inst) + offs + (index) * stride)
51#endif
52
53/* Register rw_cfg, scope ddr2, type rw */
54#define reg_ddr2_rw_cfg___col_width___lsb 0
55#define reg_ddr2_rw_cfg___col_width___width 4
56#define reg_ddr2_rw_cfg___nr_banks___lsb 4
57#define reg_ddr2_rw_cfg___nr_banks___width 1
58#define reg_ddr2_rw_cfg___nr_banks___bit 4
59#define reg_ddr2_rw_cfg___bw___lsb 5
60#define reg_ddr2_rw_cfg___bw___width 1
61#define reg_ddr2_rw_cfg___bw___bit 5
62#define reg_ddr2_rw_cfg___nr_ref___lsb 6
63#define reg_ddr2_rw_cfg___nr_ref___width 4
64#define reg_ddr2_rw_cfg___ref_interval___lsb 10
65#define reg_ddr2_rw_cfg___ref_interval___width 11
66#define reg_ddr2_rw_cfg___odt_ctrl___lsb 21
67#define reg_ddr2_rw_cfg___odt_ctrl___width 2
68#define reg_ddr2_rw_cfg___odt_mem___lsb 23
69#define reg_ddr2_rw_cfg___odt_mem___width 1
70#define reg_ddr2_rw_cfg___odt_mem___bit 23
71#define reg_ddr2_rw_cfg___imp_strength___lsb 24
72#define reg_ddr2_rw_cfg___imp_strength___width 1
73#define reg_ddr2_rw_cfg___imp_strength___bit 24
74#define reg_ddr2_rw_cfg___auto_imp_cal___lsb 25
75#define reg_ddr2_rw_cfg___auto_imp_cal___width 1
76#define reg_ddr2_rw_cfg___auto_imp_cal___bit 25
77#define reg_ddr2_rw_cfg___imp_cal_override___lsb 26
78#define reg_ddr2_rw_cfg___imp_cal_override___width 1
79#define reg_ddr2_rw_cfg___imp_cal_override___bit 26
80#define reg_ddr2_rw_cfg___dll_override___lsb 27
81#define reg_ddr2_rw_cfg___dll_override___width 1
82#define reg_ddr2_rw_cfg___dll_override___bit 27
83#define reg_ddr2_rw_cfg_offset 0
84
85/* Register rw_timing, scope ddr2, type rw */
86#define reg_ddr2_rw_timing___wr___lsb 0
87#define reg_ddr2_rw_timing___wr___width 3
88#define reg_ddr2_rw_timing___rcd___lsb 3
89#define reg_ddr2_rw_timing___rcd___width 3
90#define reg_ddr2_rw_timing___rp___lsb 6
91#define reg_ddr2_rw_timing___rp___width 3
92#define reg_ddr2_rw_timing___ras___lsb 9
93#define reg_ddr2_rw_timing___ras___width 4
94#define reg_ddr2_rw_timing___rfc___lsb 13
95#define reg_ddr2_rw_timing___rfc___width 7
96#define reg_ddr2_rw_timing___rc___lsb 20
97#define reg_ddr2_rw_timing___rc___width 5
98#define reg_ddr2_rw_timing___rtp___lsb 25
99#define reg_ddr2_rw_timing___rtp___width 2
100#define reg_ddr2_rw_timing___rtw___lsb 27
101#define reg_ddr2_rw_timing___rtw___width 3
102#define reg_ddr2_rw_timing___wtr___lsb 30
103#define reg_ddr2_rw_timing___wtr___width 2
104#define reg_ddr2_rw_timing_offset 4
105
106/* Register rw_latency, scope ddr2, type rw */
107#define reg_ddr2_rw_latency___cas___lsb 0
108#define reg_ddr2_rw_latency___cas___width 3
109#define reg_ddr2_rw_latency___additive___lsb 3
110#define reg_ddr2_rw_latency___additive___width 3
111#define reg_ddr2_rw_latency_offset 8
112
113/* Register rw_phy_cfg, scope ddr2, type rw */
114#define reg_ddr2_rw_phy_cfg___en___lsb 0
115#define reg_ddr2_rw_phy_cfg___en___width 1
116#define reg_ddr2_rw_phy_cfg___en___bit 0
117#define reg_ddr2_rw_phy_cfg_offset 12
118
119/* Register rw_phy_ctrl, scope ddr2, type rw */
120#define reg_ddr2_rw_phy_ctrl___rst___lsb 0
121#define reg_ddr2_rw_phy_ctrl___rst___width 1
122#define reg_ddr2_rw_phy_ctrl___rst___bit 0
123#define reg_ddr2_rw_phy_ctrl___cal_rst___lsb 1
124#define reg_ddr2_rw_phy_ctrl___cal_rst___width 1
125#define reg_ddr2_rw_phy_ctrl___cal_rst___bit 1
126#define reg_ddr2_rw_phy_ctrl___cal_start___lsb 2
127#define reg_ddr2_rw_phy_ctrl___cal_start___width 1
128#define reg_ddr2_rw_phy_ctrl___cal_start___bit 2
129#define reg_ddr2_rw_phy_ctrl_offset 16
130
131/* Register rw_ctrl, scope ddr2, type rw */
132#define reg_ddr2_rw_ctrl___mrs_data___lsb 0
133#define reg_ddr2_rw_ctrl___mrs_data___width 16
134#define reg_ddr2_rw_ctrl___cmd___lsb 16
135#define reg_ddr2_rw_ctrl___cmd___width 8
136#define reg_ddr2_rw_ctrl_offset 20
137
138/* Register rw_pwr_down, scope ddr2, type rw */
139#define reg_ddr2_rw_pwr_down___self_ref___lsb 0
140#define reg_ddr2_rw_pwr_down___self_ref___width 2
141#define reg_ddr2_rw_pwr_down___phy_en___lsb 2
142#define reg_ddr2_rw_pwr_down___phy_en___width 1
143#define reg_ddr2_rw_pwr_down___phy_en___bit 2
144#define reg_ddr2_rw_pwr_down_offset 24
145
146/* Register r_stat, scope ddr2, type r */
147#define reg_ddr2_r_stat___dll_lock___lsb 0
148#define reg_ddr2_r_stat___dll_lock___width 1
149#define reg_ddr2_r_stat___dll_lock___bit 0
150#define reg_ddr2_r_stat___dll_delay_code___lsb 1
151#define reg_ddr2_r_stat___dll_delay_code___width 7
152#define reg_ddr2_r_stat___imp_cal_done___lsb 8
153#define reg_ddr2_r_stat___imp_cal_done___width 1
154#define reg_ddr2_r_stat___imp_cal_done___bit 8
155#define reg_ddr2_r_stat___imp_cal_fault___lsb 9
156#define reg_ddr2_r_stat___imp_cal_fault___width 1
157#define reg_ddr2_r_stat___imp_cal_fault___bit 9
158#define reg_ddr2_r_stat___cal_imp_pu___lsb 10
159#define reg_ddr2_r_stat___cal_imp_pu___width 4
160#define reg_ddr2_r_stat___cal_imp_pd___lsb 14
161#define reg_ddr2_r_stat___cal_imp_pd___width 4
162#define reg_ddr2_r_stat_offset 28
163
164/* Register rw_imp_ctrl, scope ddr2, type rw */
165#define reg_ddr2_rw_imp_ctrl___imp_pu___lsb 0
166#define reg_ddr2_rw_imp_ctrl___imp_pu___width 4
167#define reg_ddr2_rw_imp_ctrl___imp_pd___lsb 4
168#define reg_ddr2_rw_imp_ctrl___imp_pd___width 4
169#define reg_ddr2_rw_imp_ctrl_offset 32
170
171#define STRIDE_ddr2_rw_dll_ctrl 4
172/* Register rw_dll_ctrl, scope ddr2, type rw */
173#define reg_ddr2_rw_dll_ctrl___mode___lsb 0
174#define reg_ddr2_rw_dll_ctrl___mode___width 1
175#define reg_ddr2_rw_dll_ctrl___mode___bit 0
176#define reg_ddr2_rw_dll_ctrl___clk_delay___lsb 1
177#define reg_ddr2_rw_dll_ctrl___clk_delay___width 7
178#define reg_ddr2_rw_dll_ctrl_offset 36
179
180#define STRIDE_ddr2_rw_dqs_dll_ctrl 4
181/* Register rw_dqs_dll_ctrl, scope ddr2, type rw */
182#define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___lsb 0
183#define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___width 7
184#define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___lsb 7
185#define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___width 7
186#define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___lsb 14
187#define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___width 7
188#define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___lsb 21
189#define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___width 7
190#define reg_ddr2_rw_dqs_dll_ctrl_offset 52
191
192
193/* Constants */
194#define regk_ddr2_al0 0x00000000
195#define regk_ddr2_al1 0x00000008
196#define regk_ddr2_al2 0x00000010
197#define regk_ddr2_al3 0x00000018
198#define regk_ddr2_al4 0x00000020
199#define regk_ddr2_auto 0x00000003
200#define regk_ddr2_bank4 0x00000000
201#define regk_ddr2_bank8 0x00000001
202#define regk_ddr2_bl4 0x00000002
203#define regk_ddr2_bl8 0x00000003
204#define regk_ddr2_bt_il 0x00000008
205#define regk_ddr2_bt_seq 0x00000000
206#define regk_ddr2_bw16 0x00000001
207#define regk_ddr2_bw32 0x00000000
208#define regk_ddr2_cas2 0x00000020
209#define regk_ddr2_cas3 0x00000030
210#define regk_ddr2_cas4 0x00000040
211#define regk_ddr2_cas5 0x00000050
212#define regk_ddr2_deselect 0x000000c0
213#define regk_ddr2_dic_weak 0x00000002
214#define regk_ddr2_direct 0x00000001
215#define regk_ddr2_dis 0x00000000
216#define regk_ddr2_dll_dis 0x00000001
217#define regk_ddr2_dll_en 0x00000000
218#define regk_ddr2_dll_rst 0x00000100
219#define regk_ddr2_emrs 0x00000081
220#define regk_ddr2_emrs2 0x00000082
221#define regk_ddr2_emrs3 0x00000083
222#define regk_ddr2_full 0x00000001
223#define regk_ddr2_hi_ref_rate 0x00000080
224#define regk_ddr2_mrs 0x00000080
225#define regk_ddr2_no 0x00000000
226#define regk_ddr2_nop 0x000000b8
227#define regk_ddr2_ocd_adj 0x00000200
228#define regk_ddr2_ocd_default 0x00000380
229#define regk_ddr2_ocd_drive0 0x00000100
230#define regk_ddr2_ocd_drive1 0x00000080
231#define regk_ddr2_ocd_exit 0x00000000
232#define regk_ddr2_odt_dis 0x00000000
233#define regk_ddr2_offs 0x00000000
234#define regk_ddr2_pre 0x00000090
235#define regk_ddr2_pre_all 0x00000400
236#define regk_ddr2_pwr_down_fast 0x00000000
237#define regk_ddr2_pwr_down_slow 0x00001000
238#define regk_ddr2_ref 0x00000088
239#define regk_ddr2_rtt150 0x00000040
240#define regk_ddr2_rtt50 0x00000044
241#define regk_ddr2_rtt75 0x00000004
242#define regk_ddr2_rw_cfg_default 0x00186000
243#define regk_ddr2_rw_dll_ctrl_default 0x00000000
244#define regk_ddr2_rw_dll_ctrl_size 0x00000004
245#define regk_ddr2_rw_dqs_dll_ctrl_default 0x00000000
246#define regk_ddr2_rw_dqs_dll_ctrl_size 0x00000004
247#define regk_ddr2_rw_latency_default 0x00000000
248#define regk_ddr2_rw_phy_cfg_default 0x00000000
249#define regk_ddr2_rw_pwr_down_default 0x00000000
250#define regk_ddr2_rw_timing_default 0x00000000
251#define regk_ddr2_s1Gb 0x0000001a
252#define regk_ddr2_s256Mb 0x0000000f
253#define regk_ddr2_s2Gb 0x00000027
254#define regk_ddr2_s4Gb 0x00000042
255#define regk_ddr2_s512Mb 0x00000015
256#define regk_ddr2_temp0_85 0x00000618
257#define regk_ddr2_temp85_95 0x0000030c
258#define regk_ddr2_term150 0x00000002
259#define regk_ddr2_term50 0x00000003
260#define regk_ddr2_term75 0x00000001
261#define regk_ddr2_test 0x00000080
262#define regk_ddr2_weak 0x00000000
263#define regk_ddr2_wr2 0x00000200
264#define regk_ddr2_wr3 0x00000400
265#define regk_ddr2_yes 0x00000001
266#endif /* __ddr2_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/gio_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/gio_defs_asm.h
new file mode 100644
index 000000000000..df6714fda179
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/gio_defs_asm.h
@@ -0,0 +1,849 @@
1#ifndef __gio_defs_asm_h
2#define __gio_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: gio.r
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -asm -outfile gio_defs_asm.h gio.r
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13
14#ifndef REG_FIELD
15#define REG_FIELD( scope, reg, field, value ) \
16 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
17#define REG_FIELD_X_( value, shift ) ((value) << shift)
18#endif
19
20#ifndef REG_STATE
21#define REG_STATE( scope, reg, field, symbolic_value ) \
22 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
23#define REG_STATE_X_( k, shift ) (k << shift)
24#endif
25
26#ifndef REG_MASK
27#define REG_MASK( scope, reg, field ) \
28 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
29#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
30#endif
31
32#ifndef REG_LSB
33#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
34#endif
35
36#ifndef REG_BIT
37#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
38#endif
39
40#ifndef REG_ADDR
41#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
42#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
43#endif
44
45#ifndef REG_ADDR_VECT
46#define REG_ADDR_VECT( scope, inst, reg, index ) \
47 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
48 STRIDE_##scope##_##reg )
49#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
50 ((inst) + offs + (index) * stride)
51#endif
52
53/* Register r_pa_din, scope gio, type r */
54#define reg_gio_r_pa_din___data___lsb 0
55#define reg_gio_r_pa_din___data___width 32
56#define reg_gio_r_pa_din_offset 0
57
58/* Register rw_pa_dout, scope gio, type rw */
59#define reg_gio_rw_pa_dout___data___lsb 0
60#define reg_gio_rw_pa_dout___data___width 32
61#define reg_gio_rw_pa_dout_offset 4
62
63/* Register rw_pa_oe, scope gio, type rw */
64#define reg_gio_rw_pa_oe___oe___lsb 0
65#define reg_gio_rw_pa_oe___oe___width 32
66#define reg_gio_rw_pa_oe_offset 8
67
68/* Register rw_pa_byte0_dout, scope gio, type rw */
69#define reg_gio_rw_pa_byte0_dout___data___lsb 0
70#define reg_gio_rw_pa_byte0_dout___data___width 8
71#define reg_gio_rw_pa_byte0_dout_offset 12
72
73/* Register rw_pa_byte0_oe, scope gio, type rw */
74#define reg_gio_rw_pa_byte0_oe___oe___lsb 0
75#define reg_gio_rw_pa_byte0_oe___oe___width 8
76#define reg_gio_rw_pa_byte0_oe_offset 16
77
78/* Register rw_pa_byte1_dout, scope gio, type rw */
79#define reg_gio_rw_pa_byte1_dout___data___lsb 0
80#define reg_gio_rw_pa_byte1_dout___data___width 8
81#define reg_gio_rw_pa_byte1_dout_offset 20
82
83/* Register rw_pa_byte1_oe, scope gio, type rw */
84#define reg_gio_rw_pa_byte1_oe___oe___lsb 0
85#define reg_gio_rw_pa_byte1_oe___oe___width 8
86#define reg_gio_rw_pa_byte1_oe_offset 24
87
88/* Register rw_pa_byte2_dout, scope gio, type rw */
89#define reg_gio_rw_pa_byte2_dout___data___lsb 0
90#define reg_gio_rw_pa_byte2_dout___data___width 8
91#define reg_gio_rw_pa_byte2_dout_offset 28
92
93/* Register rw_pa_byte2_oe, scope gio, type rw */
94#define reg_gio_rw_pa_byte2_oe___oe___lsb 0
95#define reg_gio_rw_pa_byte2_oe___oe___width 8
96#define reg_gio_rw_pa_byte2_oe_offset 32
97
98/* Register rw_pa_byte3_dout, scope gio, type rw */
99#define reg_gio_rw_pa_byte3_dout___data___lsb 0
100#define reg_gio_rw_pa_byte3_dout___data___width 8
101#define reg_gio_rw_pa_byte3_dout_offset 36
102
103/* Register rw_pa_byte3_oe, scope gio, type rw */
104#define reg_gio_rw_pa_byte3_oe___oe___lsb 0
105#define reg_gio_rw_pa_byte3_oe___oe___width 8
106#define reg_gio_rw_pa_byte3_oe_offset 40
107
108/* Register r_pb_din, scope gio, type r */
109#define reg_gio_r_pb_din___data___lsb 0
110#define reg_gio_r_pb_din___data___width 32
111#define reg_gio_r_pb_din_offset 44
112
113/* Register rw_pb_dout, scope gio, type rw */
114#define reg_gio_rw_pb_dout___data___lsb 0
115#define reg_gio_rw_pb_dout___data___width 32
116#define reg_gio_rw_pb_dout_offset 48
117
118/* Register rw_pb_oe, scope gio, type rw */
119#define reg_gio_rw_pb_oe___oe___lsb 0
120#define reg_gio_rw_pb_oe___oe___width 32
121#define reg_gio_rw_pb_oe_offset 52
122
123/* Register rw_pb_byte0_dout, scope gio, type rw */
124#define reg_gio_rw_pb_byte0_dout___data___lsb 0
125#define reg_gio_rw_pb_byte0_dout___data___width 8
126#define reg_gio_rw_pb_byte0_dout_offset 56
127
128/* Register rw_pb_byte0_oe, scope gio, type rw */
129#define reg_gio_rw_pb_byte0_oe___oe___lsb 0
130#define reg_gio_rw_pb_byte0_oe___oe___width 8
131#define reg_gio_rw_pb_byte0_oe_offset 60
132
133/* Register rw_pb_byte1_dout, scope gio, type rw */
134#define reg_gio_rw_pb_byte1_dout___data___lsb 0
135#define reg_gio_rw_pb_byte1_dout___data___width 8
136#define reg_gio_rw_pb_byte1_dout_offset 64
137
138/* Register rw_pb_byte1_oe, scope gio, type rw */
139#define reg_gio_rw_pb_byte1_oe___oe___lsb 0
140#define reg_gio_rw_pb_byte1_oe___oe___width 8
141#define reg_gio_rw_pb_byte1_oe_offset 68
142
143/* Register rw_pb_byte2_dout, scope gio, type rw */
144#define reg_gio_rw_pb_byte2_dout___data___lsb 0
145#define reg_gio_rw_pb_byte2_dout___data___width 8
146#define reg_gio_rw_pb_byte2_dout_offset 72
147
148/* Register rw_pb_byte2_oe, scope gio, type rw */
149#define reg_gio_rw_pb_byte2_oe___oe___lsb 0
150#define reg_gio_rw_pb_byte2_oe___oe___width 8
151#define reg_gio_rw_pb_byte2_oe_offset 76
152
153/* Register rw_pb_byte3_dout, scope gio, type rw */
154#define reg_gio_rw_pb_byte3_dout___data___lsb 0
155#define reg_gio_rw_pb_byte3_dout___data___width 8
156#define reg_gio_rw_pb_byte3_dout_offset 80
157
158/* Register rw_pb_byte3_oe, scope gio, type rw */
159#define reg_gio_rw_pb_byte3_oe___oe___lsb 0
160#define reg_gio_rw_pb_byte3_oe___oe___width 8
161#define reg_gio_rw_pb_byte3_oe_offset 84
162
163/* Register r_pc_din, scope gio, type r */
164#define reg_gio_r_pc_din___data___lsb 0
165#define reg_gio_r_pc_din___data___width 16
166#define reg_gio_r_pc_din_offset 88
167
168/* Register rw_pc_dout, scope gio, type rw */
169#define reg_gio_rw_pc_dout___data___lsb 0
170#define reg_gio_rw_pc_dout___data___width 16
171#define reg_gio_rw_pc_dout_offset 92
172
173/* Register rw_pc_oe, scope gio, type rw */
174#define reg_gio_rw_pc_oe___oe___lsb 0
175#define reg_gio_rw_pc_oe___oe___width 16
176#define reg_gio_rw_pc_oe_offset 96
177
178/* Register rw_pc_byte0_dout, scope gio, type rw */
179#define reg_gio_rw_pc_byte0_dout___data___lsb 0
180#define reg_gio_rw_pc_byte0_dout___data___width 8
181#define reg_gio_rw_pc_byte0_dout_offset 100
182
183/* Register rw_pc_byte0_oe, scope gio, type rw */
184#define reg_gio_rw_pc_byte0_oe___oe___lsb 0
185#define reg_gio_rw_pc_byte0_oe___oe___width 8
186#define reg_gio_rw_pc_byte0_oe_offset 104
187
188/* Register rw_pc_byte1_dout, scope gio, type rw */
189#define reg_gio_rw_pc_byte1_dout___data___lsb 0
190#define reg_gio_rw_pc_byte1_dout___data___width 8
191#define reg_gio_rw_pc_byte1_dout_offset 108
192
193/* Register rw_pc_byte1_oe, scope gio, type rw */
194#define reg_gio_rw_pc_byte1_oe___oe___lsb 0
195#define reg_gio_rw_pc_byte1_oe___oe___width 8
196#define reg_gio_rw_pc_byte1_oe_offset 112
197
198/* Register r_pd_din, scope gio, type r */
199#define reg_gio_r_pd_din___data___lsb 0
200#define reg_gio_r_pd_din___data___width 32
201#define reg_gio_r_pd_din_offset 116
202
203/* Register rw_intr_cfg, scope gio, type rw */
204#define reg_gio_rw_intr_cfg___intr0___lsb 0
205#define reg_gio_rw_intr_cfg___intr0___width 3
206#define reg_gio_rw_intr_cfg___intr1___lsb 3
207#define reg_gio_rw_intr_cfg___intr1___width 3
208#define reg_gio_rw_intr_cfg___intr2___lsb 6
209#define reg_gio_rw_intr_cfg___intr2___width 3
210#define reg_gio_rw_intr_cfg___intr3___lsb 9
211#define reg_gio_rw_intr_cfg___intr3___width 3
212#define reg_gio_rw_intr_cfg___intr4___lsb 12
213#define reg_gio_rw_intr_cfg___intr4___width 3
214#define reg_gio_rw_intr_cfg___intr5___lsb 15
215#define reg_gio_rw_intr_cfg___intr5___width 3
216#define reg_gio_rw_intr_cfg___intr6___lsb 18
217#define reg_gio_rw_intr_cfg___intr6___width 3
218#define reg_gio_rw_intr_cfg___intr7___lsb 21
219#define reg_gio_rw_intr_cfg___intr7___width 3
220#define reg_gio_rw_intr_cfg_offset 120
221
222/* Register rw_intr_pins, scope gio, type rw */
223#define reg_gio_rw_intr_pins___intr0___lsb 0
224#define reg_gio_rw_intr_pins___intr0___width 4
225#define reg_gio_rw_intr_pins___intr1___lsb 4
226#define reg_gio_rw_intr_pins___intr1___width 4
227#define reg_gio_rw_intr_pins___intr2___lsb 8
228#define reg_gio_rw_intr_pins___intr2___width 4
229#define reg_gio_rw_intr_pins___intr3___lsb 12
230#define reg_gio_rw_intr_pins___intr3___width 4
231#define reg_gio_rw_intr_pins___intr4___lsb 16
232#define reg_gio_rw_intr_pins___intr4___width 4
233#define reg_gio_rw_intr_pins___intr5___lsb 20
234#define reg_gio_rw_intr_pins___intr5___width 4
235#define reg_gio_rw_intr_pins___intr6___lsb 24
236#define reg_gio_rw_intr_pins___intr6___width 4
237#define reg_gio_rw_intr_pins___intr7___lsb 28
238#define reg_gio_rw_intr_pins___intr7___width 4
239#define reg_gio_rw_intr_pins_offset 124
240
241/* Register rw_intr_mask, scope gio, type rw */
242#define reg_gio_rw_intr_mask___intr0___lsb 0
243#define reg_gio_rw_intr_mask___intr0___width 1
244#define reg_gio_rw_intr_mask___intr0___bit 0
245#define reg_gio_rw_intr_mask___intr1___lsb 1
246#define reg_gio_rw_intr_mask___intr1___width 1
247#define reg_gio_rw_intr_mask___intr1___bit 1
248#define reg_gio_rw_intr_mask___intr2___lsb 2
249#define reg_gio_rw_intr_mask___intr2___width 1
250#define reg_gio_rw_intr_mask___intr2___bit 2
251#define reg_gio_rw_intr_mask___intr3___lsb 3
252#define reg_gio_rw_intr_mask___intr3___width 1
253#define reg_gio_rw_intr_mask___intr3___bit 3
254#define reg_gio_rw_intr_mask___intr4___lsb 4
255#define reg_gio_rw_intr_mask___intr4___width 1
256#define reg_gio_rw_intr_mask___intr4___bit 4
257#define reg_gio_rw_intr_mask___intr5___lsb 5
258#define reg_gio_rw_intr_mask___intr5___width 1
259#define reg_gio_rw_intr_mask___intr5___bit 5
260#define reg_gio_rw_intr_mask___intr6___lsb 6
261#define reg_gio_rw_intr_mask___intr6___width 1
262#define reg_gio_rw_intr_mask___intr6___bit 6
263#define reg_gio_rw_intr_mask___intr7___lsb 7
264#define reg_gio_rw_intr_mask___intr7___width 1
265#define reg_gio_rw_intr_mask___intr7___bit 7
266#define reg_gio_rw_intr_mask___i2c0_done___lsb 8
267#define reg_gio_rw_intr_mask___i2c0_done___width 1
268#define reg_gio_rw_intr_mask___i2c0_done___bit 8
269#define reg_gio_rw_intr_mask___i2c1_done___lsb 9
270#define reg_gio_rw_intr_mask___i2c1_done___width 1
271#define reg_gio_rw_intr_mask___i2c1_done___bit 9
272#define reg_gio_rw_intr_mask_offset 128
273
274/* Register rw_ack_intr, scope gio, type rw */
275#define reg_gio_rw_ack_intr___intr0___lsb 0
276#define reg_gio_rw_ack_intr___intr0___width 1
277#define reg_gio_rw_ack_intr___intr0___bit 0
278#define reg_gio_rw_ack_intr___intr1___lsb 1
279#define reg_gio_rw_ack_intr___intr1___width 1
280#define reg_gio_rw_ack_intr___intr1___bit 1
281#define reg_gio_rw_ack_intr___intr2___lsb 2
282#define reg_gio_rw_ack_intr___intr2___width 1
283#define reg_gio_rw_ack_intr___intr2___bit 2
284#define reg_gio_rw_ack_intr___intr3___lsb 3
285#define reg_gio_rw_ack_intr___intr3___width 1
286#define reg_gio_rw_ack_intr___intr3___bit 3
287#define reg_gio_rw_ack_intr___intr4___lsb 4
288#define reg_gio_rw_ack_intr___intr4___width 1
289#define reg_gio_rw_ack_intr___intr4___bit 4
290#define reg_gio_rw_ack_intr___intr5___lsb 5
291#define reg_gio_rw_ack_intr___intr5___width 1
292#define reg_gio_rw_ack_intr___intr5___bit 5
293#define reg_gio_rw_ack_intr___intr6___lsb 6
294#define reg_gio_rw_ack_intr___intr6___width 1
295#define reg_gio_rw_ack_intr___intr6___bit 6
296#define reg_gio_rw_ack_intr___intr7___lsb 7
297#define reg_gio_rw_ack_intr___intr7___width 1
298#define reg_gio_rw_ack_intr___intr7___bit 7
299#define reg_gio_rw_ack_intr___i2c0_done___lsb 8
300#define reg_gio_rw_ack_intr___i2c0_done___width 1
301#define reg_gio_rw_ack_intr___i2c0_done___bit 8
302#define reg_gio_rw_ack_intr___i2c1_done___lsb 9
303#define reg_gio_rw_ack_intr___i2c1_done___width 1
304#define reg_gio_rw_ack_intr___i2c1_done___bit 9
305#define reg_gio_rw_ack_intr_offset 132
306
307/* Register r_intr, scope gio, type r */
308#define reg_gio_r_intr___intr0___lsb 0
309#define reg_gio_r_intr___intr0___width 1
310#define reg_gio_r_intr___intr0___bit 0
311#define reg_gio_r_intr___intr1___lsb 1
312#define reg_gio_r_intr___intr1___width 1
313#define reg_gio_r_intr___intr1___bit 1
314#define reg_gio_r_intr___intr2___lsb 2
315#define reg_gio_r_intr___intr2___width 1
316#define reg_gio_r_intr___intr2___bit 2
317#define reg_gio_r_intr___intr3___lsb 3
318#define reg_gio_r_intr___intr3___width 1
319#define reg_gio_r_intr___intr3___bit 3
320#define reg_gio_r_intr___intr4___lsb 4
321#define reg_gio_r_intr___intr4___width 1
322#define reg_gio_r_intr___intr4___bit 4
323#define reg_gio_r_intr___intr5___lsb 5
324#define reg_gio_r_intr___intr5___width 1
325#define reg_gio_r_intr___intr5___bit 5
326#define reg_gio_r_intr___intr6___lsb 6
327#define reg_gio_r_intr___intr6___width 1
328#define reg_gio_r_intr___intr6___bit 6
329#define reg_gio_r_intr___intr7___lsb 7
330#define reg_gio_r_intr___intr7___width 1
331#define reg_gio_r_intr___intr7___bit 7
332#define reg_gio_r_intr___i2c0_done___lsb 8
333#define reg_gio_r_intr___i2c0_done___width 1
334#define reg_gio_r_intr___i2c0_done___bit 8
335#define reg_gio_r_intr___i2c1_done___lsb 9
336#define reg_gio_r_intr___i2c1_done___width 1
337#define reg_gio_r_intr___i2c1_done___bit 9
338#define reg_gio_r_intr_offset 136
339
340/* Register r_masked_intr, scope gio, type r */
341#define reg_gio_r_masked_intr___intr0___lsb 0
342#define reg_gio_r_masked_intr___intr0___width 1
343#define reg_gio_r_masked_intr___intr0___bit 0
344#define reg_gio_r_masked_intr___intr1___lsb 1
345#define reg_gio_r_masked_intr___intr1___width 1
346#define reg_gio_r_masked_intr___intr1___bit 1
347#define reg_gio_r_masked_intr___intr2___lsb 2
348#define reg_gio_r_masked_intr___intr2___width 1
349#define reg_gio_r_masked_intr___intr2___bit 2
350#define reg_gio_r_masked_intr___intr3___lsb 3
351#define reg_gio_r_masked_intr___intr3___width 1
352#define reg_gio_r_masked_intr___intr3___bit 3
353#define reg_gio_r_masked_intr___intr4___lsb 4
354#define reg_gio_r_masked_intr___intr4___width 1
355#define reg_gio_r_masked_intr___intr4___bit 4
356#define reg_gio_r_masked_intr___intr5___lsb 5
357#define reg_gio_r_masked_intr___intr5___width 1
358#define reg_gio_r_masked_intr___intr5___bit 5
359#define reg_gio_r_masked_intr___intr6___lsb 6
360#define reg_gio_r_masked_intr___intr6___width 1
361#define reg_gio_r_masked_intr___intr6___bit 6
362#define reg_gio_r_masked_intr___intr7___lsb 7
363#define reg_gio_r_masked_intr___intr7___width 1
364#define reg_gio_r_masked_intr___intr7___bit 7
365#define reg_gio_r_masked_intr___i2c0_done___lsb 8
366#define reg_gio_r_masked_intr___i2c0_done___width 1
367#define reg_gio_r_masked_intr___i2c0_done___bit 8
368#define reg_gio_r_masked_intr___i2c1_done___lsb 9
369#define reg_gio_r_masked_intr___i2c1_done___width 1
370#define reg_gio_r_masked_intr___i2c1_done___bit 9
371#define reg_gio_r_masked_intr_offset 140
372
373/* Register rw_i2c0_start, scope gio, type rw */
374#define reg_gio_rw_i2c0_start___run___lsb 0
375#define reg_gio_rw_i2c0_start___run___width 1
376#define reg_gio_rw_i2c0_start___run___bit 0
377#define reg_gio_rw_i2c0_start_offset 144
378
379/* Register rw_i2c0_cfg, scope gio, type rw */
380#define reg_gio_rw_i2c0_cfg___en___lsb 0
381#define reg_gio_rw_i2c0_cfg___en___width 1
382#define reg_gio_rw_i2c0_cfg___en___bit 0
383#define reg_gio_rw_i2c0_cfg___bit_order___lsb 1
384#define reg_gio_rw_i2c0_cfg___bit_order___width 1
385#define reg_gio_rw_i2c0_cfg___bit_order___bit 1
386#define reg_gio_rw_i2c0_cfg___scl_io___lsb 2
387#define reg_gio_rw_i2c0_cfg___scl_io___width 1
388#define reg_gio_rw_i2c0_cfg___scl_io___bit 2
389#define reg_gio_rw_i2c0_cfg___scl_inv___lsb 3
390#define reg_gio_rw_i2c0_cfg___scl_inv___width 1
391#define reg_gio_rw_i2c0_cfg___scl_inv___bit 3
392#define reg_gio_rw_i2c0_cfg___sda_io___lsb 4
393#define reg_gio_rw_i2c0_cfg___sda_io___width 1
394#define reg_gio_rw_i2c0_cfg___sda_io___bit 4
395#define reg_gio_rw_i2c0_cfg___sda_idle___lsb 5
396#define reg_gio_rw_i2c0_cfg___sda_idle___width 1
397#define reg_gio_rw_i2c0_cfg___sda_idle___bit 5
398#define reg_gio_rw_i2c0_cfg_offset 148
399
400/* Register rw_i2c0_ctrl, scope gio, type rw */
401#define reg_gio_rw_i2c0_ctrl___trf_bits___lsb 0
402#define reg_gio_rw_i2c0_ctrl___trf_bits___width 6
403#define reg_gio_rw_i2c0_ctrl___switch_dir___lsb 6
404#define reg_gio_rw_i2c0_ctrl___switch_dir___width 6
405#define reg_gio_rw_i2c0_ctrl___extra_start___lsb 12
406#define reg_gio_rw_i2c0_ctrl___extra_start___width 3
407#define reg_gio_rw_i2c0_ctrl___early_end___lsb 15
408#define reg_gio_rw_i2c0_ctrl___early_end___width 1
409#define reg_gio_rw_i2c0_ctrl___early_end___bit 15
410#define reg_gio_rw_i2c0_ctrl___start_stop___lsb 16
411#define reg_gio_rw_i2c0_ctrl___start_stop___width 1
412#define reg_gio_rw_i2c0_ctrl___start_stop___bit 16
413#define reg_gio_rw_i2c0_ctrl___ack_dir0___lsb 17
414#define reg_gio_rw_i2c0_ctrl___ack_dir0___width 1
415#define reg_gio_rw_i2c0_ctrl___ack_dir0___bit 17
416#define reg_gio_rw_i2c0_ctrl___ack_dir1___lsb 18
417#define reg_gio_rw_i2c0_ctrl___ack_dir1___width 1
418#define reg_gio_rw_i2c0_ctrl___ack_dir1___bit 18
419#define reg_gio_rw_i2c0_ctrl___ack_dir2___lsb 19
420#define reg_gio_rw_i2c0_ctrl___ack_dir2___width 1
421#define reg_gio_rw_i2c0_ctrl___ack_dir2___bit 19
422#define reg_gio_rw_i2c0_ctrl___ack_dir3___lsb 20
423#define reg_gio_rw_i2c0_ctrl___ack_dir3___width 1
424#define reg_gio_rw_i2c0_ctrl___ack_dir3___bit 20
425#define reg_gio_rw_i2c0_ctrl___ack_dir4___lsb 21
426#define reg_gio_rw_i2c0_ctrl___ack_dir4___width 1
427#define reg_gio_rw_i2c0_ctrl___ack_dir4___bit 21
428#define reg_gio_rw_i2c0_ctrl___ack_dir5___lsb 22
429#define reg_gio_rw_i2c0_ctrl___ack_dir5___width 1
430#define reg_gio_rw_i2c0_ctrl___ack_dir5___bit 22
431#define reg_gio_rw_i2c0_ctrl___ack_bit___lsb 23
432#define reg_gio_rw_i2c0_ctrl___ack_bit___width 1
433#define reg_gio_rw_i2c0_ctrl___ack_bit___bit 23
434#define reg_gio_rw_i2c0_ctrl___start_bit___lsb 24
435#define reg_gio_rw_i2c0_ctrl___start_bit___width 1
436#define reg_gio_rw_i2c0_ctrl___start_bit___bit 24
437#define reg_gio_rw_i2c0_ctrl___freq___lsb 25
438#define reg_gio_rw_i2c0_ctrl___freq___width 2
439#define reg_gio_rw_i2c0_ctrl_offset 152
440
441/* Register rw_i2c0_data, scope gio, type rw */
442#define reg_gio_rw_i2c0_data___data0___lsb 0
443#define reg_gio_rw_i2c0_data___data0___width 8
444#define reg_gio_rw_i2c0_data___data1___lsb 8
445#define reg_gio_rw_i2c0_data___data1___width 8
446#define reg_gio_rw_i2c0_data___data2___lsb 16
447#define reg_gio_rw_i2c0_data___data2___width 8
448#define reg_gio_rw_i2c0_data___data3___lsb 24
449#define reg_gio_rw_i2c0_data___data3___width 8
450#define reg_gio_rw_i2c0_data_offset 156
451
452/* Register rw_i2c0_data2, scope gio, type rw */
453#define reg_gio_rw_i2c0_data2___data4___lsb 0
454#define reg_gio_rw_i2c0_data2___data4___width 8
455#define reg_gio_rw_i2c0_data2___data5___lsb 8
456#define reg_gio_rw_i2c0_data2___data5___width 8
457#define reg_gio_rw_i2c0_data2___start_val___lsb 16
458#define reg_gio_rw_i2c0_data2___start_val___width 6
459#define reg_gio_rw_i2c0_data2___ack_val___lsb 22
460#define reg_gio_rw_i2c0_data2___ack_val___width 6
461#define reg_gio_rw_i2c0_data2_offset 160
462
463/* Register rw_i2c1_start, scope gio, type rw */
464#define reg_gio_rw_i2c1_start___run___lsb 0
465#define reg_gio_rw_i2c1_start___run___width 1
466#define reg_gio_rw_i2c1_start___run___bit 0
467#define reg_gio_rw_i2c1_start_offset 164
468
469/* Register rw_i2c1_cfg, scope gio, type rw */
470#define reg_gio_rw_i2c1_cfg___en___lsb 0
471#define reg_gio_rw_i2c1_cfg___en___width 1
472#define reg_gio_rw_i2c1_cfg___en___bit 0
473#define reg_gio_rw_i2c1_cfg___bit_order___lsb 1
474#define reg_gio_rw_i2c1_cfg___bit_order___width 1
475#define reg_gio_rw_i2c1_cfg___bit_order___bit 1
476#define reg_gio_rw_i2c1_cfg___scl_io___lsb 2
477#define reg_gio_rw_i2c1_cfg___scl_io___width 1
478#define reg_gio_rw_i2c1_cfg___scl_io___bit 2
479#define reg_gio_rw_i2c1_cfg___scl_inv___lsb 3
480#define reg_gio_rw_i2c1_cfg___scl_inv___width 1
481#define reg_gio_rw_i2c1_cfg___scl_inv___bit 3
482#define reg_gio_rw_i2c1_cfg___sda0_io___lsb 4
483#define reg_gio_rw_i2c1_cfg___sda0_io___width 1
484#define reg_gio_rw_i2c1_cfg___sda0_io___bit 4
485#define reg_gio_rw_i2c1_cfg___sda0_idle___lsb 5
486#define reg_gio_rw_i2c1_cfg___sda0_idle___width 1
487#define reg_gio_rw_i2c1_cfg___sda0_idle___bit 5
488#define reg_gio_rw_i2c1_cfg___sda1_io___lsb 6
489#define reg_gio_rw_i2c1_cfg___sda1_io___width 1
490#define reg_gio_rw_i2c1_cfg___sda1_io___bit 6
491#define reg_gio_rw_i2c1_cfg___sda1_idle___lsb 7
492#define reg_gio_rw_i2c1_cfg___sda1_idle___width 1
493#define reg_gio_rw_i2c1_cfg___sda1_idle___bit 7
494#define reg_gio_rw_i2c1_cfg___sda2_io___lsb 8
495#define reg_gio_rw_i2c1_cfg___sda2_io___width 1
496#define reg_gio_rw_i2c1_cfg___sda2_io___bit 8
497#define reg_gio_rw_i2c1_cfg___sda2_idle___lsb 9
498#define reg_gio_rw_i2c1_cfg___sda2_idle___width 1
499#define reg_gio_rw_i2c1_cfg___sda2_idle___bit 9
500#define reg_gio_rw_i2c1_cfg___sda3_io___lsb 10
501#define reg_gio_rw_i2c1_cfg___sda3_io___width 1
502#define reg_gio_rw_i2c1_cfg___sda3_io___bit 10
503#define reg_gio_rw_i2c1_cfg___sda3_idle___lsb 11
504#define reg_gio_rw_i2c1_cfg___sda3_idle___width 1
505#define reg_gio_rw_i2c1_cfg___sda3_idle___bit 11
506#define reg_gio_rw_i2c1_cfg___sda_sel___lsb 12
507#define reg_gio_rw_i2c1_cfg___sda_sel___width 2
508#define reg_gio_rw_i2c1_cfg___sen_idle___lsb 14
509#define reg_gio_rw_i2c1_cfg___sen_idle___width 1
510#define reg_gio_rw_i2c1_cfg___sen_idle___bit 14
511#define reg_gio_rw_i2c1_cfg___sen_inv___lsb 15
512#define reg_gio_rw_i2c1_cfg___sen_inv___width 1
513#define reg_gio_rw_i2c1_cfg___sen_inv___bit 15
514#define reg_gio_rw_i2c1_cfg___sen_sel___lsb 16
515#define reg_gio_rw_i2c1_cfg___sen_sel___width 2
516#define reg_gio_rw_i2c1_cfg_offset 168
517
518/* Register rw_i2c1_ctrl, scope gio, type rw */
519#define reg_gio_rw_i2c1_ctrl___trf_bits___lsb 0
520#define reg_gio_rw_i2c1_ctrl___trf_bits___width 6
521#define reg_gio_rw_i2c1_ctrl___switch_dir___lsb 6
522#define reg_gio_rw_i2c1_ctrl___switch_dir___width 6
523#define reg_gio_rw_i2c1_ctrl___extra_start___lsb 12
524#define reg_gio_rw_i2c1_ctrl___extra_start___width 3
525#define reg_gio_rw_i2c1_ctrl___early_end___lsb 15
526#define reg_gio_rw_i2c1_ctrl___early_end___width 1
527#define reg_gio_rw_i2c1_ctrl___early_end___bit 15
528#define reg_gio_rw_i2c1_ctrl___start_stop___lsb 16
529#define reg_gio_rw_i2c1_ctrl___start_stop___width 1
530#define reg_gio_rw_i2c1_ctrl___start_stop___bit 16
531#define reg_gio_rw_i2c1_ctrl___ack_dir0___lsb 17
532#define reg_gio_rw_i2c1_ctrl___ack_dir0___width 1
533#define reg_gio_rw_i2c1_ctrl___ack_dir0___bit 17
534#define reg_gio_rw_i2c1_ctrl___ack_dir1___lsb 18
535#define reg_gio_rw_i2c1_ctrl___ack_dir1___width 1
536#define reg_gio_rw_i2c1_ctrl___ack_dir1___bit 18
537#define reg_gio_rw_i2c1_ctrl___ack_dir2___lsb 19
538#define reg_gio_rw_i2c1_ctrl___ack_dir2___width 1
539#define reg_gio_rw_i2c1_ctrl___ack_dir2___bit 19
540#define reg_gio_rw_i2c1_ctrl___ack_dir3___lsb 20
541#define reg_gio_rw_i2c1_ctrl___ack_dir3___width 1
542#define reg_gio_rw_i2c1_ctrl___ack_dir3___bit 20
543#define reg_gio_rw_i2c1_ctrl___ack_dir4___lsb 21
544#define reg_gio_rw_i2c1_ctrl___ack_dir4___width 1
545#define reg_gio_rw_i2c1_ctrl___ack_dir4___bit 21
546#define reg_gio_rw_i2c1_ctrl___ack_dir5___lsb 22
547#define reg_gio_rw_i2c1_ctrl___ack_dir5___width 1
548#define reg_gio_rw_i2c1_ctrl___ack_dir5___bit 22
549#define reg_gio_rw_i2c1_ctrl___ack_bit___lsb 23
550#define reg_gio_rw_i2c1_ctrl___ack_bit___width 1
551#define reg_gio_rw_i2c1_ctrl___ack_bit___bit 23
552#define reg_gio_rw_i2c1_ctrl___start_bit___lsb 24
553#define reg_gio_rw_i2c1_ctrl___start_bit___width 1
554#define reg_gio_rw_i2c1_ctrl___start_bit___bit 24
555#define reg_gio_rw_i2c1_ctrl___freq___lsb 25
556#define reg_gio_rw_i2c1_ctrl___freq___width 2
557#define reg_gio_rw_i2c1_ctrl_offset 172
558
559/* Register rw_i2c1_data, scope gio, type rw */
560#define reg_gio_rw_i2c1_data___data0___lsb 0
561#define reg_gio_rw_i2c1_data___data0___width 8
562#define reg_gio_rw_i2c1_data___data1___lsb 8
563#define reg_gio_rw_i2c1_data___data1___width 8
564#define reg_gio_rw_i2c1_data___data2___lsb 16
565#define reg_gio_rw_i2c1_data___data2___width 8
566#define reg_gio_rw_i2c1_data___data3___lsb 24
567#define reg_gio_rw_i2c1_data___data3___width 8
568#define reg_gio_rw_i2c1_data_offset 176
569
570/* Register rw_i2c1_data2, scope gio, type rw */
571#define reg_gio_rw_i2c1_data2___data4___lsb 0
572#define reg_gio_rw_i2c1_data2___data4___width 8
573#define reg_gio_rw_i2c1_data2___data5___lsb 8
574#define reg_gio_rw_i2c1_data2___data5___width 8
575#define reg_gio_rw_i2c1_data2___start_val___lsb 16
576#define reg_gio_rw_i2c1_data2___start_val___width 6
577#define reg_gio_rw_i2c1_data2___ack_val___lsb 22
578#define reg_gio_rw_i2c1_data2___ack_val___width 6
579#define reg_gio_rw_i2c1_data2_offset 180
580
581/* Register r_ppwm_stat, scope gio, type r */
582#define reg_gio_r_ppwm_stat___freq___lsb 0
583#define reg_gio_r_ppwm_stat___freq___width 2
584#define reg_gio_r_ppwm_stat_offset 184
585
586/* Register rw_ppwm_data, scope gio, type rw */
587#define reg_gio_rw_ppwm_data___data___lsb 0
588#define reg_gio_rw_ppwm_data___data___width 8
589#define reg_gio_rw_ppwm_data_offset 188
590
591/* Register rw_pwm0_ctrl, scope gio, type rw */
592#define reg_gio_rw_pwm0_ctrl___mode___lsb 0
593#define reg_gio_rw_pwm0_ctrl___mode___width 2
594#define reg_gio_rw_pwm0_ctrl___ccd_override___lsb 2
595#define reg_gio_rw_pwm0_ctrl___ccd_override___width 1
596#define reg_gio_rw_pwm0_ctrl___ccd_override___bit 2
597#define reg_gio_rw_pwm0_ctrl___ccd_val___lsb 3
598#define reg_gio_rw_pwm0_ctrl___ccd_val___width 1
599#define reg_gio_rw_pwm0_ctrl___ccd_val___bit 3
600#define reg_gio_rw_pwm0_ctrl_offset 192
601
602/* Register rw_pwm0_var, scope gio, type rw */
603#define reg_gio_rw_pwm0_var___lo___lsb 0
604#define reg_gio_rw_pwm0_var___lo___width 13
605#define reg_gio_rw_pwm0_var___hi___lsb 13
606#define reg_gio_rw_pwm0_var___hi___width 13
607#define reg_gio_rw_pwm0_var_offset 196
608
609/* Register rw_pwm0_data, scope gio, type rw */
610#define reg_gio_rw_pwm0_data___data___lsb 0
611#define reg_gio_rw_pwm0_data___data___width 8
612#define reg_gio_rw_pwm0_data_offset 200
613
614/* Register rw_pwm1_ctrl, scope gio, type rw */
615#define reg_gio_rw_pwm1_ctrl___mode___lsb 0
616#define reg_gio_rw_pwm1_ctrl___mode___width 2
617#define reg_gio_rw_pwm1_ctrl___ccd_override___lsb 2
618#define reg_gio_rw_pwm1_ctrl___ccd_override___width 1
619#define reg_gio_rw_pwm1_ctrl___ccd_override___bit 2
620#define reg_gio_rw_pwm1_ctrl___ccd_val___lsb 3
621#define reg_gio_rw_pwm1_ctrl___ccd_val___width 1
622#define reg_gio_rw_pwm1_ctrl___ccd_val___bit 3
623#define reg_gio_rw_pwm1_ctrl_offset 204
624
625/* Register rw_pwm1_var, scope gio, type rw */
626#define reg_gio_rw_pwm1_var___lo___lsb 0
627#define reg_gio_rw_pwm1_var___lo___width 13
628#define reg_gio_rw_pwm1_var___hi___lsb 13
629#define reg_gio_rw_pwm1_var___hi___width 13
630#define reg_gio_rw_pwm1_var_offset 208
631
632/* Register rw_pwm1_data, scope gio, type rw */
633#define reg_gio_rw_pwm1_data___data___lsb 0
634#define reg_gio_rw_pwm1_data___data___width 8
635#define reg_gio_rw_pwm1_data_offset 212
636
637/* Register rw_pwm2_ctrl, scope gio, type rw */
638#define reg_gio_rw_pwm2_ctrl___mode___lsb 0
639#define reg_gio_rw_pwm2_ctrl___mode___width 2
640#define reg_gio_rw_pwm2_ctrl___ccd_override___lsb 2
641#define reg_gio_rw_pwm2_ctrl___ccd_override___width 1
642#define reg_gio_rw_pwm2_ctrl___ccd_override___bit 2
643#define reg_gio_rw_pwm2_ctrl___ccd_val___lsb 3
644#define reg_gio_rw_pwm2_ctrl___ccd_val___width 1
645#define reg_gio_rw_pwm2_ctrl___ccd_val___bit 3
646#define reg_gio_rw_pwm2_ctrl_offset 216
647
648/* Register rw_pwm2_var, scope gio, type rw */
649#define reg_gio_rw_pwm2_var___lo___lsb 0
650#define reg_gio_rw_pwm2_var___lo___width 13
651#define reg_gio_rw_pwm2_var___hi___lsb 13
652#define reg_gio_rw_pwm2_var___hi___width 13
653#define reg_gio_rw_pwm2_var_offset 220
654
655/* Register rw_pwm2_data, scope gio, type rw */
656#define reg_gio_rw_pwm2_data___data___lsb 0
657#define reg_gio_rw_pwm2_data___data___width 8
658#define reg_gio_rw_pwm2_data_offset 224
659
660/* Register rw_pwm_in_cfg, scope gio, type rw */
661#define reg_gio_rw_pwm_in_cfg___pin___lsb 0
662#define reg_gio_rw_pwm_in_cfg___pin___width 3
663#define reg_gio_rw_pwm_in_cfg_offset 228
664
665/* Register r_pwm_in_lo, scope gio, type r */
666#define reg_gio_r_pwm_in_lo___data___lsb 0
667#define reg_gio_r_pwm_in_lo___data___width 32
668#define reg_gio_r_pwm_in_lo_offset 232
669
670/* Register r_pwm_in_hi, scope gio, type r */
671#define reg_gio_r_pwm_in_hi___data___lsb 0
672#define reg_gio_r_pwm_in_hi___data___width 32
673#define reg_gio_r_pwm_in_hi_offset 236
674
675/* Register r_pwm_in_cnt, scope gio, type r */
676#define reg_gio_r_pwm_in_cnt___data___lsb 0
677#define reg_gio_r_pwm_in_cnt___data___width 32
678#define reg_gio_r_pwm_in_cnt_offset 240
679
680
681/* Constants */
682#define regk_gio_anyedge 0x00000007
683#define regk_gio_f100k 0x00000000
684#define regk_gio_f1562 0x00000000
685#define regk_gio_f195 0x00000003
686#define regk_gio_f1m 0x00000002
687#define regk_gio_f390 0x00000002
688#define regk_gio_f400k 0x00000001
689#define regk_gio_f5m 0x00000003
690#define regk_gio_f781 0x00000001
691#define regk_gio_hi 0x00000001
692#define regk_gio_in 0x00000000
693#define regk_gio_intr_pa0 0x00000000
694#define regk_gio_intr_pa1 0x00000000
695#define regk_gio_intr_pa10 0x00000001
696#define regk_gio_intr_pa11 0x00000001
697#define regk_gio_intr_pa12 0x00000001
698#define regk_gio_intr_pa13 0x00000001
699#define regk_gio_intr_pa14 0x00000001
700#define regk_gio_intr_pa15 0x00000001
701#define regk_gio_intr_pa16 0x00000002
702#define regk_gio_intr_pa17 0x00000002
703#define regk_gio_intr_pa18 0x00000002
704#define regk_gio_intr_pa19 0x00000002
705#define regk_gio_intr_pa2 0x00000000
706#define regk_gio_intr_pa20 0x00000002
707#define regk_gio_intr_pa21 0x00000002
708#define regk_gio_intr_pa22 0x00000002
709#define regk_gio_intr_pa23 0x00000002
710#define regk_gio_intr_pa24 0x00000003
711#define regk_gio_intr_pa25 0x00000003
712#define regk_gio_intr_pa26 0x00000003
713#define regk_gio_intr_pa27 0x00000003
714#define regk_gio_intr_pa28 0x00000003
715#define regk_gio_intr_pa29 0x00000003
716#define regk_gio_intr_pa3 0x00000000
717#define regk_gio_intr_pa30 0x00000003
718#define regk_gio_intr_pa31 0x00000003
719#define regk_gio_intr_pa4 0x00000000
720#define regk_gio_intr_pa5 0x00000000
721#define regk_gio_intr_pa6 0x00000000
722#define regk_gio_intr_pa7 0x00000000
723#define regk_gio_intr_pa8 0x00000001
724#define regk_gio_intr_pa9 0x00000001
725#define regk_gio_intr_pb0 0x00000004
726#define regk_gio_intr_pb1 0x00000004
727#define regk_gio_intr_pb10 0x00000005
728#define regk_gio_intr_pb11 0x00000005
729#define regk_gio_intr_pb12 0x00000005
730#define regk_gio_intr_pb13 0x00000005
731#define regk_gio_intr_pb14 0x00000005
732#define regk_gio_intr_pb15 0x00000005
733#define regk_gio_intr_pb16 0x00000006
734#define regk_gio_intr_pb17 0x00000006
735#define regk_gio_intr_pb18 0x00000006
736#define regk_gio_intr_pb19 0x00000006
737#define regk_gio_intr_pb2 0x00000004
738#define regk_gio_intr_pb20 0x00000006
739#define regk_gio_intr_pb21 0x00000006
740#define regk_gio_intr_pb22 0x00000006
741#define regk_gio_intr_pb23 0x00000006
742#define regk_gio_intr_pb24 0x00000007
743#define regk_gio_intr_pb25 0x00000007
744#define regk_gio_intr_pb26 0x00000007
745#define regk_gio_intr_pb27 0x00000007
746#define regk_gio_intr_pb28 0x00000007
747#define regk_gio_intr_pb29 0x00000007
748#define regk_gio_intr_pb3 0x00000004
749#define regk_gio_intr_pb30 0x00000007
750#define regk_gio_intr_pb31 0x00000007
751#define regk_gio_intr_pb4 0x00000004
752#define regk_gio_intr_pb5 0x00000004
753#define regk_gio_intr_pb6 0x00000004
754#define regk_gio_intr_pb7 0x00000004
755#define regk_gio_intr_pb8 0x00000005
756#define regk_gio_intr_pb9 0x00000005
757#define regk_gio_intr_pc0 0x00000008
758#define regk_gio_intr_pc1 0x00000008
759#define regk_gio_intr_pc10 0x00000009
760#define regk_gio_intr_pc11 0x00000009
761#define regk_gio_intr_pc12 0x00000009
762#define regk_gio_intr_pc13 0x00000009
763#define regk_gio_intr_pc14 0x00000009
764#define regk_gio_intr_pc15 0x00000009
765#define regk_gio_intr_pc2 0x00000008
766#define regk_gio_intr_pc3 0x00000008
767#define regk_gio_intr_pc4 0x00000008
768#define regk_gio_intr_pc5 0x00000008
769#define regk_gio_intr_pc6 0x00000008
770#define regk_gio_intr_pc7 0x00000008
771#define regk_gio_intr_pc8 0x00000009
772#define regk_gio_intr_pc9 0x00000009
773#define regk_gio_intr_pd0 0x0000000c
774#define regk_gio_intr_pd1 0x0000000c
775#define regk_gio_intr_pd10 0x0000000d
776#define regk_gio_intr_pd11 0x0000000d
777#define regk_gio_intr_pd12 0x0000000d
778#define regk_gio_intr_pd13 0x0000000d
779#define regk_gio_intr_pd14 0x0000000d
780#define regk_gio_intr_pd15 0x0000000d
781#define regk_gio_intr_pd16 0x0000000e
782#define regk_gio_intr_pd17 0x0000000e
783#define regk_gio_intr_pd18 0x0000000e
784#define regk_gio_intr_pd19 0x0000000e
785#define regk_gio_intr_pd2 0x0000000c
786#define regk_gio_intr_pd20 0x0000000e
787#define regk_gio_intr_pd21 0x0000000e
788#define regk_gio_intr_pd22 0x0000000e
789#define regk_gio_intr_pd23 0x0000000e
790#define regk_gio_intr_pd24 0x0000000f
791#define regk_gio_intr_pd25 0x0000000f
792#define regk_gio_intr_pd26 0x0000000f
793#define regk_gio_intr_pd27 0x0000000f
794#define regk_gio_intr_pd28 0x0000000f
795#define regk_gio_intr_pd29 0x0000000f
796#define regk_gio_intr_pd3 0x0000000c
797#define regk_gio_intr_pd30 0x0000000f
798#define regk_gio_intr_pd31 0x0000000f
799#define regk_gio_intr_pd4 0x0000000c
800#define regk_gio_intr_pd5 0x0000000c
801#define regk_gio_intr_pd6 0x0000000c
802#define regk_gio_intr_pd7 0x0000000c
803#define regk_gio_intr_pd8 0x0000000d
804#define regk_gio_intr_pd9 0x0000000d
805#define regk_gio_lo 0x00000002
806#define regk_gio_lsb 0x00000000
807#define regk_gio_msb 0x00000001
808#define regk_gio_negedge 0x00000006
809#define regk_gio_no 0x00000000
810#define regk_gio_no_switch 0x0000003f
811#define regk_gio_none 0x00000007
812#define regk_gio_off 0x00000000
813#define regk_gio_opendrain 0x00000000
814#define regk_gio_out 0x00000001
815#define regk_gio_posedge 0x00000005
816#define regk_gio_pwm_hfp 0x00000002
817#define regk_gio_pwm_pa0 0x00000001
818#define regk_gio_pwm_pa19 0x00000004
819#define regk_gio_pwm_pa6 0x00000002
820#define regk_gio_pwm_pa7 0x00000003
821#define regk_gio_pwm_pb26 0x00000005
822#define regk_gio_pwm_pd23 0x00000006
823#define regk_gio_pwm_pd31 0x00000007
824#define regk_gio_pwm_std 0x00000001
825#define regk_gio_pwm_var 0x00000003
826#define regk_gio_rw_i2c0_cfg_default 0x00000020
827#define regk_gio_rw_i2c0_ctrl_default 0x00010000
828#define regk_gio_rw_i2c0_start_default 0x00000000
829#define regk_gio_rw_i2c1_cfg_default 0x00000aa0
830#define regk_gio_rw_i2c1_ctrl_default 0x00010000
831#define regk_gio_rw_i2c1_start_default 0x00000000
832#define regk_gio_rw_intr_cfg_default 0x00000000
833#define regk_gio_rw_intr_mask_default 0x00000000
834#define regk_gio_rw_pa_oe_default 0x00000000
835#define regk_gio_rw_pb_oe_default 0x00000000
836#define regk_gio_rw_pc_oe_default 0x00000000
837#define regk_gio_rw_ppwm_data_default 0x00000000
838#define regk_gio_rw_pwm0_ctrl_default 0x00000000
839#define regk_gio_rw_pwm1_ctrl_default 0x00000000
840#define regk_gio_rw_pwm2_ctrl_default 0x00000000
841#define regk_gio_rw_pwm_in_cfg_default 0x00000000
842#define regk_gio_sda0 0x00000000
843#define regk_gio_sda1 0x00000001
844#define regk_gio_sda2 0x00000002
845#define regk_gio_sda3 0x00000003
846#define regk_gio_sen 0x00000000
847#define regk_gio_set 0x00000003
848#define regk_gio_yes 0x00000001
849#endif /* __gio_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pinmux_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pinmux_defs_asm.h
new file mode 100644
index 000000000000..c3dc9c666c46
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pinmux_defs_asm.h
@@ -0,0 +1,572 @@
1#ifndef __pinmux_defs_asm_h
2#define __pinmux_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: pinmux.r
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -asm -outfile pinmux_defs_asm.h pinmux.r
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13
14#ifndef REG_FIELD
15#define REG_FIELD( scope, reg, field, value ) \
16 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
17#define REG_FIELD_X_( value, shift ) ((value) << shift)
18#endif
19
20#ifndef REG_STATE
21#define REG_STATE( scope, reg, field, symbolic_value ) \
22 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
23#define REG_STATE_X_( k, shift ) (k << shift)
24#endif
25
26#ifndef REG_MASK
27#define REG_MASK( scope, reg, field ) \
28 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
29#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
30#endif
31
32#ifndef REG_LSB
33#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
34#endif
35
36#ifndef REG_BIT
37#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
38#endif
39
40#ifndef REG_ADDR
41#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
42#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
43#endif
44
45#ifndef REG_ADDR_VECT
46#define REG_ADDR_VECT( scope, inst, reg, index ) \
47 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
48 STRIDE_##scope##_##reg )
49#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
50 ((inst) + offs + (index) * stride)
51#endif
52
53/* Register rw_hwprot, scope pinmux, type rw */
54#define reg_pinmux_rw_hwprot___eth___lsb 0
55#define reg_pinmux_rw_hwprot___eth___width 1
56#define reg_pinmux_rw_hwprot___eth___bit 0
57#define reg_pinmux_rw_hwprot___eth_mdio___lsb 1
58#define reg_pinmux_rw_hwprot___eth_mdio___width 1
59#define reg_pinmux_rw_hwprot___eth_mdio___bit 1
60#define reg_pinmux_rw_hwprot___geth___lsb 2
61#define reg_pinmux_rw_hwprot___geth___width 1
62#define reg_pinmux_rw_hwprot___geth___bit 2
63#define reg_pinmux_rw_hwprot___tg___lsb 3
64#define reg_pinmux_rw_hwprot___tg___width 1
65#define reg_pinmux_rw_hwprot___tg___bit 3
66#define reg_pinmux_rw_hwprot___tg_clk___lsb 4
67#define reg_pinmux_rw_hwprot___tg_clk___width 1
68#define reg_pinmux_rw_hwprot___tg_clk___bit 4
69#define reg_pinmux_rw_hwprot___vout___lsb 5
70#define reg_pinmux_rw_hwprot___vout___width 1
71#define reg_pinmux_rw_hwprot___vout___bit 5
72#define reg_pinmux_rw_hwprot___vout_sync___lsb 6
73#define reg_pinmux_rw_hwprot___vout_sync___width 1
74#define reg_pinmux_rw_hwprot___vout_sync___bit 6
75#define reg_pinmux_rw_hwprot___ser1___lsb 7
76#define reg_pinmux_rw_hwprot___ser1___width 1
77#define reg_pinmux_rw_hwprot___ser1___bit 7
78#define reg_pinmux_rw_hwprot___ser2___lsb 8
79#define reg_pinmux_rw_hwprot___ser2___width 1
80#define reg_pinmux_rw_hwprot___ser2___bit 8
81#define reg_pinmux_rw_hwprot___ser3___lsb 9
82#define reg_pinmux_rw_hwprot___ser3___width 1
83#define reg_pinmux_rw_hwprot___ser3___bit 9
84#define reg_pinmux_rw_hwprot___ser4___lsb 10
85#define reg_pinmux_rw_hwprot___ser4___width 1
86#define reg_pinmux_rw_hwprot___ser4___bit 10
87#define reg_pinmux_rw_hwprot___sser___lsb 11
88#define reg_pinmux_rw_hwprot___sser___width 1
89#define reg_pinmux_rw_hwprot___sser___bit 11
90#define reg_pinmux_rw_hwprot___pwm0___lsb 12
91#define reg_pinmux_rw_hwprot___pwm0___width 1
92#define reg_pinmux_rw_hwprot___pwm0___bit 12
93#define reg_pinmux_rw_hwprot___pwm1___lsb 13
94#define reg_pinmux_rw_hwprot___pwm1___width 1
95#define reg_pinmux_rw_hwprot___pwm1___bit 13
96#define reg_pinmux_rw_hwprot___pwm2___lsb 14
97#define reg_pinmux_rw_hwprot___pwm2___width 1
98#define reg_pinmux_rw_hwprot___pwm2___bit 14
99#define reg_pinmux_rw_hwprot___timer0___lsb 15
100#define reg_pinmux_rw_hwprot___timer0___width 1
101#define reg_pinmux_rw_hwprot___timer0___bit 15
102#define reg_pinmux_rw_hwprot___timer1___lsb 16
103#define reg_pinmux_rw_hwprot___timer1___width 1
104#define reg_pinmux_rw_hwprot___timer1___bit 16
105#define reg_pinmux_rw_hwprot___pio___lsb 17
106#define reg_pinmux_rw_hwprot___pio___width 1
107#define reg_pinmux_rw_hwprot___pio___bit 17
108#define reg_pinmux_rw_hwprot___i2c0___lsb 18
109#define reg_pinmux_rw_hwprot___i2c0___width 1
110#define reg_pinmux_rw_hwprot___i2c0___bit 18
111#define reg_pinmux_rw_hwprot___i2c1___lsb 19
112#define reg_pinmux_rw_hwprot___i2c1___width 1
113#define reg_pinmux_rw_hwprot___i2c1___bit 19
114#define reg_pinmux_rw_hwprot___i2c1_sda1___lsb 20
115#define reg_pinmux_rw_hwprot___i2c1_sda1___width 1
116#define reg_pinmux_rw_hwprot___i2c1_sda1___bit 20
117#define reg_pinmux_rw_hwprot___i2c1_sda2___lsb 21
118#define reg_pinmux_rw_hwprot___i2c1_sda2___width 1
119#define reg_pinmux_rw_hwprot___i2c1_sda2___bit 21
120#define reg_pinmux_rw_hwprot___i2c1_sda3___lsb 22
121#define reg_pinmux_rw_hwprot___i2c1_sda3___width 1
122#define reg_pinmux_rw_hwprot___i2c1_sda3___bit 22
123#define reg_pinmux_rw_hwprot___i2c1_sen___lsb 23
124#define reg_pinmux_rw_hwprot___i2c1_sen___width 1
125#define reg_pinmux_rw_hwprot___i2c1_sen___bit 23
126#define reg_pinmux_rw_hwprot_offset 0
127
128/* Register rw_gio_pa, scope pinmux, type rw */
129#define reg_pinmux_rw_gio_pa___pa0___lsb 0
130#define reg_pinmux_rw_gio_pa___pa0___width 1
131#define reg_pinmux_rw_gio_pa___pa0___bit 0
132#define reg_pinmux_rw_gio_pa___pa1___lsb 1
133#define reg_pinmux_rw_gio_pa___pa1___width 1
134#define reg_pinmux_rw_gio_pa___pa1___bit 1
135#define reg_pinmux_rw_gio_pa___pa2___lsb 2
136#define reg_pinmux_rw_gio_pa___pa2___width 1
137#define reg_pinmux_rw_gio_pa___pa2___bit 2
138#define reg_pinmux_rw_gio_pa___pa3___lsb 3
139#define reg_pinmux_rw_gio_pa___pa3___width 1
140#define reg_pinmux_rw_gio_pa___pa3___bit 3
141#define reg_pinmux_rw_gio_pa___pa4___lsb 4
142#define reg_pinmux_rw_gio_pa___pa4___width 1
143#define reg_pinmux_rw_gio_pa___pa4___bit 4
144#define reg_pinmux_rw_gio_pa___pa5___lsb 5
145#define reg_pinmux_rw_gio_pa___pa5___width 1
146#define reg_pinmux_rw_gio_pa___pa5___bit 5
147#define reg_pinmux_rw_gio_pa___pa6___lsb 6
148#define reg_pinmux_rw_gio_pa___pa6___width 1
149#define reg_pinmux_rw_gio_pa___pa6___bit 6
150#define reg_pinmux_rw_gio_pa___pa7___lsb 7
151#define reg_pinmux_rw_gio_pa___pa7___width 1
152#define reg_pinmux_rw_gio_pa___pa7___bit 7
153#define reg_pinmux_rw_gio_pa___pa8___lsb 8
154#define reg_pinmux_rw_gio_pa___pa8___width 1
155#define reg_pinmux_rw_gio_pa___pa8___bit 8
156#define reg_pinmux_rw_gio_pa___pa9___lsb 9
157#define reg_pinmux_rw_gio_pa___pa9___width 1
158#define reg_pinmux_rw_gio_pa___pa9___bit 9
159#define reg_pinmux_rw_gio_pa___pa10___lsb 10
160#define reg_pinmux_rw_gio_pa___pa10___width 1
161#define reg_pinmux_rw_gio_pa___pa10___bit 10
162#define reg_pinmux_rw_gio_pa___pa11___lsb 11
163#define reg_pinmux_rw_gio_pa___pa11___width 1
164#define reg_pinmux_rw_gio_pa___pa11___bit 11
165#define reg_pinmux_rw_gio_pa___pa12___lsb 12
166#define reg_pinmux_rw_gio_pa___pa12___width 1
167#define reg_pinmux_rw_gio_pa___pa12___bit 12
168#define reg_pinmux_rw_gio_pa___pa13___lsb 13
169#define reg_pinmux_rw_gio_pa___pa13___width 1
170#define reg_pinmux_rw_gio_pa___pa13___bit 13
171#define reg_pinmux_rw_gio_pa___pa14___lsb 14
172#define reg_pinmux_rw_gio_pa___pa14___width 1
173#define reg_pinmux_rw_gio_pa___pa14___bit 14
174#define reg_pinmux_rw_gio_pa___pa15___lsb 15
175#define reg_pinmux_rw_gio_pa___pa15___width 1
176#define reg_pinmux_rw_gio_pa___pa15___bit 15
177#define reg_pinmux_rw_gio_pa___pa16___lsb 16
178#define reg_pinmux_rw_gio_pa___pa16___width 1
179#define reg_pinmux_rw_gio_pa___pa16___bit 16
180#define reg_pinmux_rw_gio_pa___pa17___lsb 17
181#define reg_pinmux_rw_gio_pa___pa17___width 1
182#define reg_pinmux_rw_gio_pa___pa17___bit 17
183#define reg_pinmux_rw_gio_pa___pa18___lsb 18
184#define reg_pinmux_rw_gio_pa___pa18___width 1
185#define reg_pinmux_rw_gio_pa___pa18___bit 18
186#define reg_pinmux_rw_gio_pa___pa19___lsb 19
187#define reg_pinmux_rw_gio_pa___pa19___width 1
188#define reg_pinmux_rw_gio_pa___pa19___bit 19
189#define reg_pinmux_rw_gio_pa___pa20___lsb 20
190#define reg_pinmux_rw_gio_pa___pa20___width 1
191#define reg_pinmux_rw_gio_pa___pa20___bit 20
192#define reg_pinmux_rw_gio_pa___pa21___lsb 21
193#define reg_pinmux_rw_gio_pa___pa21___width 1
194#define reg_pinmux_rw_gio_pa___pa21___bit 21
195#define reg_pinmux_rw_gio_pa___pa22___lsb 22
196#define reg_pinmux_rw_gio_pa___pa22___width 1
197#define reg_pinmux_rw_gio_pa___pa22___bit 22
198#define reg_pinmux_rw_gio_pa___pa23___lsb 23
199#define reg_pinmux_rw_gio_pa___pa23___width 1
200#define reg_pinmux_rw_gio_pa___pa23___bit 23
201#define reg_pinmux_rw_gio_pa___pa24___lsb 24
202#define reg_pinmux_rw_gio_pa___pa24___width 1
203#define reg_pinmux_rw_gio_pa___pa24___bit 24
204#define reg_pinmux_rw_gio_pa___pa25___lsb 25
205#define reg_pinmux_rw_gio_pa___pa25___width 1
206#define reg_pinmux_rw_gio_pa___pa25___bit 25
207#define reg_pinmux_rw_gio_pa___pa26___lsb 26
208#define reg_pinmux_rw_gio_pa___pa26___width 1
209#define reg_pinmux_rw_gio_pa___pa26___bit 26
210#define reg_pinmux_rw_gio_pa___pa27___lsb 27
211#define reg_pinmux_rw_gio_pa___pa27___width 1
212#define reg_pinmux_rw_gio_pa___pa27___bit 27
213#define reg_pinmux_rw_gio_pa___pa28___lsb 28
214#define reg_pinmux_rw_gio_pa___pa28___width 1
215#define reg_pinmux_rw_gio_pa___pa28___bit 28
216#define reg_pinmux_rw_gio_pa___pa29___lsb 29
217#define reg_pinmux_rw_gio_pa___pa29___width 1
218#define reg_pinmux_rw_gio_pa___pa29___bit 29
219#define reg_pinmux_rw_gio_pa___pa30___lsb 30
220#define reg_pinmux_rw_gio_pa___pa30___width 1
221#define reg_pinmux_rw_gio_pa___pa30___bit 30
222#define reg_pinmux_rw_gio_pa___pa31___lsb 31
223#define reg_pinmux_rw_gio_pa___pa31___width 1
224#define reg_pinmux_rw_gio_pa___pa31___bit 31
225#define reg_pinmux_rw_gio_pa_offset 4
226
227/* Register rw_gio_pb, scope pinmux, type rw */
228#define reg_pinmux_rw_gio_pb___pb0___lsb 0
229#define reg_pinmux_rw_gio_pb___pb0___width 1
230#define reg_pinmux_rw_gio_pb___pb0___bit 0
231#define reg_pinmux_rw_gio_pb___pb1___lsb 1
232#define reg_pinmux_rw_gio_pb___pb1___width 1
233#define reg_pinmux_rw_gio_pb___pb1___bit 1
234#define reg_pinmux_rw_gio_pb___pb2___lsb 2
235#define reg_pinmux_rw_gio_pb___pb2___width 1
236#define reg_pinmux_rw_gio_pb___pb2___bit 2
237#define reg_pinmux_rw_gio_pb___pb3___lsb 3
238#define reg_pinmux_rw_gio_pb___pb3___width 1
239#define reg_pinmux_rw_gio_pb___pb3___bit 3
240#define reg_pinmux_rw_gio_pb___pb4___lsb 4
241#define reg_pinmux_rw_gio_pb___pb4___width 1
242#define reg_pinmux_rw_gio_pb___pb4___bit 4
243#define reg_pinmux_rw_gio_pb___pb5___lsb 5
244#define reg_pinmux_rw_gio_pb___pb5___width 1
245#define reg_pinmux_rw_gio_pb___pb5___bit 5
246#define reg_pinmux_rw_gio_pb___pb6___lsb 6
247#define reg_pinmux_rw_gio_pb___pb6___width 1
248#define reg_pinmux_rw_gio_pb___pb6___bit 6
249#define reg_pinmux_rw_gio_pb___pb7___lsb 7
250#define reg_pinmux_rw_gio_pb___pb7___width 1
251#define reg_pinmux_rw_gio_pb___pb7___bit 7
252#define reg_pinmux_rw_gio_pb___pb8___lsb 8
253#define reg_pinmux_rw_gio_pb___pb8___width 1
254#define reg_pinmux_rw_gio_pb___pb8___bit 8
255#define reg_pinmux_rw_gio_pb___pb9___lsb 9
256#define reg_pinmux_rw_gio_pb___pb9___width 1
257#define reg_pinmux_rw_gio_pb___pb9___bit 9
258#define reg_pinmux_rw_gio_pb___pb10___lsb 10
259#define reg_pinmux_rw_gio_pb___pb10___width 1
260#define reg_pinmux_rw_gio_pb___pb10___bit 10
261#define reg_pinmux_rw_gio_pb___pb11___lsb 11
262#define reg_pinmux_rw_gio_pb___pb11___width 1
263#define reg_pinmux_rw_gio_pb___pb11___bit 11
264#define reg_pinmux_rw_gio_pb___pb12___lsb 12
265#define reg_pinmux_rw_gio_pb___pb12___width 1
266#define reg_pinmux_rw_gio_pb___pb12___bit 12
267#define reg_pinmux_rw_gio_pb___pb13___lsb 13
268#define reg_pinmux_rw_gio_pb___pb13___width 1
269#define reg_pinmux_rw_gio_pb___pb13___bit 13
270#define reg_pinmux_rw_gio_pb___pb14___lsb 14
271#define reg_pinmux_rw_gio_pb___pb14___width 1
272#define reg_pinmux_rw_gio_pb___pb14___bit 14
273#define reg_pinmux_rw_gio_pb___pb15___lsb 15
274#define reg_pinmux_rw_gio_pb___pb15___width 1
275#define reg_pinmux_rw_gio_pb___pb15___bit 15
276#define reg_pinmux_rw_gio_pb___pb16___lsb 16
277#define reg_pinmux_rw_gio_pb___pb16___width 1
278#define reg_pinmux_rw_gio_pb___pb16___bit 16
279#define reg_pinmux_rw_gio_pb___pb17___lsb 17
280#define reg_pinmux_rw_gio_pb___pb17___width 1
281#define reg_pinmux_rw_gio_pb___pb17___bit 17
282#define reg_pinmux_rw_gio_pb___pb18___lsb 18
283#define reg_pinmux_rw_gio_pb___pb18___width 1
284#define reg_pinmux_rw_gio_pb___pb18___bit 18
285#define reg_pinmux_rw_gio_pb___pb19___lsb 19
286#define reg_pinmux_rw_gio_pb___pb19___width 1
287#define reg_pinmux_rw_gio_pb___pb19___bit 19
288#define reg_pinmux_rw_gio_pb___pb20___lsb 20
289#define reg_pinmux_rw_gio_pb___pb20___width 1
290#define reg_pinmux_rw_gio_pb___pb20___bit 20
291#define reg_pinmux_rw_gio_pb___pb21___lsb 21
292#define reg_pinmux_rw_gio_pb___pb21___width 1
293#define reg_pinmux_rw_gio_pb___pb21___bit 21
294#define reg_pinmux_rw_gio_pb___pb22___lsb 22
295#define reg_pinmux_rw_gio_pb___pb22___width 1
296#define reg_pinmux_rw_gio_pb___pb22___bit 22
297#define reg_pinmux_rw_gio_pb___pb23___lsb 23
298#define reg_pinmux_rw_gio_pb___pb23___width 1
299#define reg_pinmux_rw_gio_pb___pb23___bit 23
300#define reg_pinmux_rw_gio_pb___pb24___lsb 24
301#define reg_pinmux_rw_gio_pb___pb24___width 1
302#define reg_pinmux_rw_gio_pb___pb24___bit 24
303#define reg_pinmux_rw_gio_pb___pb25___lsb 25
304#define reg_pinmux_rw_gio_pb___pb25___width 1
305#define reg_pinmux_rw_gio_pb___pb25___bit 25
306#define reg_pinmux_rw_gio_pb___pb26___lsb 26
307#define reg_pinmux_rw_gio_pb___pb26___width 1
308#define reg_pinmux_rw_gio_pb___pb26___bit 26
309#define reg_pinmux_rw_gio_pb___pb27___lsb 27
310#define reg_pinmux_rw_gio_pb___pb27___width 1
311#define reg_pinmux_rw_gio_pb___pb27___bit 27
312#define reg_pinmux_rw_gio_pb___pb28___lsb 28
313#define reg_pinmux_rw_gio_pb___pb28___width 1
314#define reg_pinmux_rw_gio_pb___pb28___bit 28
315#define reg_pinmux_rw_gio_pb___pb29___lsb 29
316#define reg_pinmux_rw_gio_pb___pb29___width 1
317#define reg_pinmux_rw_gio_pb___pb29___bit 29
318#define reg_pinmux_rw_gio_pb___pb30___lsb 30
319#define reg_pinmux_rw_gio_pb___pb30___width 1
320#define reg_pinmux_rw_gio_pb___pb30___bit 30
321#define reg_pinmux_rw_gio_pb___pb31___lsb 31
322#define reg_pinmux_rw_gio_pb___pb31___width 1
323#define reg_pinmux_rw_gio_pb___pb31___bit 31
324#define reg_pinmux_rw_gio_pb_offset 8
325
326/* Register rw_gio_pc, scope pinmux, type rw */
327#define reg_pinmux_rw_gio_pc___pc0___lsb 0
328#define reg_pinmux_rw_gio_pc___pc0___width 1
329#define reg_pinmux_rw_gio_pc___pc0___bit 0
330#define reg_pinmux_rw_gio_pc___pc1___lsb 1
331#define reg_pinmux_rw_gio_pc___pc1___width 1
332#define reg_pinmux_rw_gio_pc___pc1___bit 1
333#define reg_pinmux_rw_gio_pc___pc2___lsb 2
334#define reg_pinmux_rw_gio_pc___pc2___width 1
335#define reg_pinmux_rw_gio_pc___pc2___bit 2
336#define reg_pinmux_rw_gio_pc___pc3___lsb 3
337#define reg_pinmux_rw_gio_pc___pc3___width 1
338#define reg_pinmux_rw_gio_pc___pc3___bit 3
339#define reg_pinmux_rw_gio_pc___pc4___lsb 4
340#define reg_pinmux_rw_gio_pc___pc4___width 1
341#define reg_pinmux_rw_gio_pc___pc4___bit 4
342#define reg_pinmux_rw_gio_pc___pc5___lsb 5
343#define reg_pinmux_rw_gio_pc___pc5___width 1
344#define reg_pinmux_rw_gio_pc___pc5___bit 5
345#define reg_pinmux_rw_gio_pc___pc6___lsb 6
346#define reg_pinmux_rw_gio_pc___pc6___width 1
347#define reg_pinmux_rw_gio_pc___pc6___bit 6
348#define reg_pinmux_rw_gio_pc___pc7___lsb 7
349#define reg_pinmux_rw_gio_pc___pc7___width 1
350#define reg_pinmux_rw_gio_pc___pc7___bit 7
351#define reg_pinmux_rw_gio_pc___pc8___lsb 8
352#define reg_pinmux_rw_gio_pc___pc8___width 1
353#define reg_pinmux_rw_gio_pc___pc8___bit 8
354#define reg_pinmux_rw_gio_pc___pc9___lsb 9
355#define reg_pinmux_rw_gio_pc___pc9___width 1
356#define reg_pinmux_rw_gio_pc___pc9___bit 9
357#define reg_pinmux_rw_gio_pc___pc10___lsb 10
358#define reg_pinmux_rw_gio_pc___pc10___width 1
359#define reg_pinmux_rw_gio_pc___pc10___bit 10
360#define reg_pinmux_rw_gio_pc___pc11___lsb 11
361#define reg_pinmux_rw_gio_pc___pc11___width 1
362#define reg_pinmux_rw_gio_pc___pc11___bit 11
363#define reg_pinmux_rw_gio_pc___pc12___lsb 12
364#define reg_pinmux_rw_gio_pc___pc12___width 1
365#define reg_pinmux_rw_gio_pc___pc12___bit 12
366#define reg_pinmux_rw_gio_pc___pc13___lsb 13
367#define reg_pinmux_rw_gio_pc___pc13___width 1
368#define reg_pinmux_rw_gio_pc___pc13___bit 13
369#define reg_pinmux_rw_gio_pc___pc14___lsb 14
370#define reg_pinmux_rw_gio_pc___pc14___width 1
371#define reg_pinmux_rw_gio_pc___pc14___bit 14
372#define reg_pinmux_rw_gio_pc___pc15___lsb 15
373#define reg_pinmux_rw_gio_pc___pc15___width 1
374#define reg_pinmux_rw_gio_pc___pc15___bit 15
375#define reg_pinmux_rw_gio_pc_offset 12
376
377/* Register rw_iop_pa, scope pinmux, type rw */
378#define reg_pinmux_rw_iop_pa___pa0___lsb 0
379#define reg_pinmux_rw_iop_pa___pa0___width 1
380#define reg_pinmux_rw_iop_pa___pa0___bit 0
381#define reg_pinmux_rw_iop_pa___pa1___lsb 1
382#define reg_pinmux_rw_iop_pa___pa1___width 1
383#define reg_pinmux_rw_iop_pa___pa1___bit 1
384#define reg_pinmux_rw_iop_pa___pa2___lsb 2
385#define reg_pinmux_rw_iop_pa___pa2___width 1
386#define reg_pinmux_rw_iop_pa___pa2___bit 2
387#define reg_pinmux_rw_iop_pa___pa3___lsb 3
388#define reg_pinmux_rw_iop_pa___pa3___width 1
389#define reg_pinmux_rw_iop_pa___pa3___bit 3
390#define reg_pinmux_rw_iop_pa___pa4___lsb 4
391#define reg_pinmux_rw_iop_pa___pa4___width 1
392#define reg_pinmux_rw_iop_pa___pa4___bit 4
393#define reg_pinmux_rw_iop_pa___pa5___lsb 5
394#define reg_pinmux_rw_iop_pa___pa5___width 1
395#define reg_pinmux_rw_iop_pa___pa5___bit 5
396#define reg_pinmux_rw_iop_pa___pa6___lsb 6
397#define reg_pinmux_rw_iop_pa___pa6___width 1
398#define reg_pinmux_rw_iop_pa___pa6___bit 6
399#define reg_pinmux_rw_iop_pa___pa7___lsb 7
400#define reg_pinmux_rw_iop_pa___pa7___width 1
401#define reg_pinmux_rw_iop_pa___pa7___bit 7
402#define reg_pinmux_rw_iop_pa___pa8___lsb 8
403#define reg_pinmux_rw_iop_pa___pa8___width 1
404#define reg_pinmux_rw_iop_pa___pa8___bit 8
405#define reg_pinmux_rw_iop_pa___pa9___lsb 9
406#define reg_pinmux_rw_iop_pa___pa9___width 1
407#define reg_pinmux_rw_iop_pa___pa9___bit 9
408#define reg_pinmux_rw_iop_pa___pa10___lsb 10
409#define reg_pinmux_rw_iop_pa___pa10___width 1
410#define reg_pinmux_rw_iop_pa___pa10___bit 10
411#define reg_pinmux_rw_iop_pa___pa11___lsb 11
412#define reg_pinmux_rw_iop_pa___pa11___width 1
413#define reg_pinmux_rw_iop_pa___pa11___bit 11
414#define reg_pinmux_rw_iop_pa___pa12___lsb 12
415#define reg_pinmux_rw_iop_pa___pa12___width 1
416#define reg_pinmux_rw_iop_pa___pa12___bit 12
417#define reg_pinmux_rw_iop_pa___pa13___lsb 13
418#define reg_pinmux_rw_iop_pa___pa13___width 1
419#define reg_pinmux_rw_iop_pa___pa13___bit 13
420#define reg_pinmux_rw_iop_pa___pa14___lsb 14
421#define reg_pinmux_rw_iop_pa___pa14___width 1
422#define reg_pinmux_rw_iop_pa___pa14___bit 14
423#define reg_pinmux_rw_iop_pa___pa15___lsb 15
424#define reg_pinmux_rw_iop_pa___pa15___width 1
425#define reg_pinmux_rw_iop_pa___pa15___bit 15
426#define reg_pinmux_rw_iop_pa___pa16___lsb 16
427#define reg_pinmux_rw_iop_pa___pa16___width 1
428#define reg_pinmux_rw_iop_pa___pa16___bit 16
429#define reg_pinmux_rw_iop_pa___pa17___lsb 17
430#define reg_pinmux_rw_iop_pa___pa17___width 1
431#define reg_pinmux_rw_iop_pa___pa17___bit 17
432#define reg_pinmux_rw_iop_pa___pa18___lsb 18
433#define reg_pinmux_rw_iop_pa___pa18___width 1
434#define reg_pinmux_rw_iop_pa___pa18___bit 18
435#define reg_pinmux_rw_iop_pa___pa19___lsb 19
436#define reg_pinmux_rw_iop_pa___pa19___width 1
437#define reg_pinmux_rw_iop_pa___pa19___bit 19
438#define reg_pinmux_rw_iop_pa___pa20___lsb 20
439#define reg_pinmux_rw_iop_pa___pa20___width 1
440#define reg_pinmux_rw_iop_pa___pa20___bit 20
441#define reg_pinmux_rw_iop_pa___pa21___lsb 21
442#define reg_pinmux_rw_iop_pa___pa21___width 1
443#define reg_pinmux_rw_iop_pa___pa21___bit 21
444#define reg_pinmux_rw_iop_pa___pa22___lsb 22
445#define reg_pinmux_rw_iop_pa___pa22___width 1
446#define reg_pinmux_rw_iop_pa___pa22___bit 22
447#define reg_pinmux_rw_iop_pa___pa23___lsb 23
448#define reg_pinmux_rw_iop_pa___pa23___width 1
449#define reg_pinmux_rw_iop_pa___pa23___bit 23
450#define reg_pinmux_rw_iop_pa___pa24___lsb 24
451#define reg_pinmux_rw_iop_pa___pa24___width 1
452#define reg_pinmux_rw_iop_pa___pa24___bit 24
453#define reg_pinmux_rw_iop_pa___pa25___lsb 25
454#define reg_pinmux_rw_iop_pa___pa25___width 1
455#define reg_pinmux_rw_iop_pa___pa25___bit 25
456#define reg_pinmux_rw_iop_pa___pa26___lsb 26
457#define reg_pinmux_rw_iop_pa___pa26___width 1
458#define reg_pinmux_rw_iop_pa___pa26___bit 26
459#define reg_pinmux_rw_iop_pa___pa27___lsb 27
460#define reg_pinmux_rw_iop_pa___pa27___width 1
461#define reg_pinmux_rw_iop_pa___pa27___bit 27
462#define reg_pinmux_rw_iop_pa___pa28___lsb 28
463#define reg_pinmux_rw_iop_pa___pa28___width 1
464#define reg_pinmux_rw_iop_pa___pa28___bit 28
465#define reg_pinmux_rw_iop_pa___pa29___lsb 29
466#define reg_pinmux_rw_iop_pa___pa29___width 1
467#define reg_pinmux_rw_iop_pa___pa29___bit 29
468#define reg_pinmux_rw_iop_pa___pa30___lsb 30
469#define reg_pinmux_rw_iop_pa___pa30___width 1
470#define reg_pinmux_rw_iop_pa___pa30___bit 30
471#define reg_pinmux_rw_iop_pa___pa31___lsb 31
472#define reg_pinmux_rw_iop_pa___pa31___width 1
473#define reg_pinmux_rw_iop_pa___pa31___bit 31
474#define reg_pinmux_rw_iop_pa_offset 16
475
476/* Register rw_iop_pb, scope pinmux, type rw */
477#define reg_pinmux_rw_iop_pb___pb0___lsb 0
478#define reg_pinmux_rw_iop_pb___pb0___width 1
479#define reg_pinmux_rw_iop_pb___pb0___bit 0
480#define reg_pinmux_rw_iop_pb___pb1___lsb 1
481#define reg_pinmux_rw_iop_pb___pb1___width 1
482#define reg_pinmux_rw_iop_pb___pb1___bit 1
483#define reg_pinmux_rw_iop_pb___pb2___lsb 2
484#define reg_pinmux_rw_iop_pb___pb2___width 1
485#define reg_pinmux_rw_iop_pb___pb2___bit 2
486#define reg_pinmux_rw_iop_pb___pb3___lsb 3
487#define reg_pinmux_rw_iop_pb___pb3___width 1
488#define reg_pinmux_rw_iop_pb___pb3___bit 3
489#define reg_pinmux_rw_iop_pb___pb4___lsb 4
490#define reg_pinmux_rw_iop_pb___pb4___width 1
491#define reg_pinmux_rw_iop_pb___pb4___bit 4
492#define reg_pinmux_rw_iop_pb___pb5___lsb 5
493#define reg_pinmux_rw_iop_pb___pb5___width 1
494#define reg_pinmux_rw_iop_pb___pb5___bit 5
495#define reg_pinmux_rw_iop_pb___pb6___lsb 6
496#define reg_pinmux_rw_iop_pb___pb6___width 1
497#define reg_pinmux_rw_iop_pb___pb6___bit 6
498#define reg_pinmux_rw_iop_pb___pb7___lsb 7
499#define reg_pinmux_rw_iop_pb___pb7___width 1
500#define reg_pinmux_rw_iop_pb___pb7___bit 7
501#define reg_pinmux_rw_iop_pb_offset 20
502
503/* Register rw_iop_pio, scope pinmux, type rw */
504#define reg_pinmux_rw_iop_pio___d0___lsb 0
505#define reg_pinmux_rw_iop_pio___d0___width 1
506#define reg_pinmux_rw_iop_pio___d0___bit 0
507#define reg_pinmux_rw_iop_pio___d1___lsb 1
508#define reg_pinmux_rw_iop_pio___d1___width 1
509#define reg_pinmux_rw_iop_pio___d1___bit 1
510#define reg_pinmux_rw_iop_pio___d2___lsb 2
511#define reg_pinmux_rw_iop_pio___d2___width 1
512#define reg_pinmux_rw_iop_pio___d2___bit 2
513#define reg_pinmux_rw_iop_pio___d3___lsb 3
514#define reg_pinmux_rw_iop_pio___d3___width 1
515#define reg_pinmux_rw_iop_pio___d3___bit 3
516#define reg_pinmux_rw_iop_pio___d4___lsb 4
517#define reg_pinmux_rw_iop_pio___d4___width 1
518#define reg_pinmux_rw_iop_pio___d4___bit 4
519#define reg_pinmux_rw_iop_pio___d5___lsb 5
520#define reg_pinmux_rw_iop_pio___d5___width 1
521#define reg_pinmux_rw_iop_pio___d5___bit 5
522#define reg_pinmux_rw_iop_pio___d6___lsb 6
523#define reg_pinmux_rw_iop_pio___d6___width 1
524#define reg_pinmux_rw_iop_pio___d6___bit 6
525#define reg_pinmux_rw_iop_pio___d7___lsb 7
526#define reg_pinmux_rw_iop_pio___d7___width 1
527#define reg_pinmux_rw_iop_pio___d7___bit 7
528#define reg_pinmux_rw_iop_pio___rd_n___lsb 8
529#define reg_pinmux_rw_iop_pio___rd_n___width 1
530#define reg_pinmux_rw_iop_pio___rd_n___bit 8
531#define reg_pinmux_rw_iop_pio___wr_n___lsb 9
532#define reg_pinmux_rw_iop_pio___wr_n___width 1
533#define reg_pinmux_rw_iop_pio___wr_n___bit 9
534#define reg_pinmux_rw_iop_pio___a0___lsb 10
535#define reg_pinmux_rw_iop_pio___a0___width 1
536#define reg_pinmux_rw_iop_pio___a0___bit 10
537#define reg_pinmux_rw_iop_pio___a1___lsb 11
538#define reg_pinmux_rw_iop_pio___a1___width 1
539#define reg_pinmux_rw_iop_pio___a1___bit 11
540#define reg_pinmux_rw_iop_pio___ce0_n___lsb 12
541#define reg_pinmux_rw_iop_pio___ce0_n___width 1
542#define reg_pinmux_rw_iop_pio___ce0_n___bit 12
543#define reg_pinmux_rw_iop_pio___ce1_n___lsb 13
544#define reg_pinmux_rw_iop_pio___ce1_n___width 1
545#define reg_pinmux_rw_iop_pio___ce1_n___bit 13
546#define reg_pinmux_rw_iop_pio___ce2_n___lsb 14
547#define reg_pinmux_rw_iop_pio___ce2_n___width 1
548#define reg_pinmux_rw_iop_pio___ce2_n___bit 14
549#define reg_pinmux_rw_iop_pio___rdy___lsb 15
550#define reg_pinmux_rw_iop_pio___rdy___width 1
551#define reg_pinmux_rw_iop_pio___rdy___bit 15
552#define reg_pinmux_rw_iop_pio_offset 24
553
554/* Register rw_iop_usb, scope pinmux, type rw */
555#define reg_pinmux_rw_iop_usb___usb0___lsb 0
556#define reg_pinmux_rw_iop_usb___usb0___width 1
557#define reg_pinmux_rw_iop_usb___usb0___bit 0
558#define reg_pinmux_rw_iop_usb_offset 28
559
560
561/* Constants */
562#define regk_pinmux_no 0x00000000
563#define regk_pinmux_rw_gio_pa_default 0x00000000
564#define regk_pinmux_rw_gio_pb_default 0x00000000
565#define regk_pinmux_rw_gio_pc_default 0x00000000
566#define regk_pinmux_rw_hwprot_default 0x00000000
567#define regk_pinmux_rw_iop_pa_default 0x00000000
568#define regk_pinmux_rw_iop_pb_default 0x00000000
569#define regk_pinmux_rw_iop_pio_default 0x00000000
570#define regk_pinmux_rw_iop_usb_default 0x00000001
571#define regk_pinmux_yes 0x00000001
572#endif /* __pinmux_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pio_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pio_defs_asm.h
new file mode 100644
index 000000000000..3907ef4921c8
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pio_defs_asm.h
@@ -0,0 +1,337 @@
1#ifndef __pio_defs_asm_h
2#define __pio_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: pio.r
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -asm -outfile pio_defs_asm.h pio.r
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13
14#ifndef REG_FIELD
15#define REG_FIELD( scope, reg, field, value ) \
16 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
17#define REG_FIELD_X_( value, shift ) ((value) << shift)
18#endif
19
20#ifndef REG_STATE
21#define REG_STATE( scope, reg, field, symbolic_value ) \
22 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
23#define REG_STATE_X_( k, shift ) (k << shift)
24#endif
25
26#ifndef REG_MASK
27#define REG_MASK( scope, reg, field ) \
28 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
29#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
30#endif
31
32#ifndef REG_LSB
33#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
34#endif
35
36#ifndef REG_BIT
37#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
38#endif
39
40#ifndef REG_ADDR
41#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
42#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
43#endif
44
45#ifndef REG_ADDR_VECT
46#define REG_ADDR_VECT( scope, inst, reg, index ) \
47 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
48 STRIDE_##scope##_##reg )
49#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
50 ((inst) + offs + (index) * stride)
51#endif
52
53/* Register rw_data, scope pio, type rw */
54#define reg_pio_rw_data_offset 64
55
56/* Register rw_io_access0, scope pio, type rw */
57#define reg_pio_rw_io_access0___data___lsb 0
58#define reg_pio_rw_io_access0___data___width 8
59#define reg_pio_rw_io_access0_offset 0
60
61/* Register rw_io_access1, scope pio, type rw */
62#define reg_pio_rw_io_access1___data___lsb 0
63#define reg_pio_rw_io_access1___data___width 8
64#define reg_pio_rw_io_access1_offset 4
65
66/* Register rw_io_access2, scope pio, type rw */
67#define reg_pio_rw_io_access2___data___lsb 0
68#define reg_pio_rw_io_access2___data___width 8
69#define reg_pio_rw_io_access2_offset 8
70
71/* Register rw_io_access3, scope pio, type rw */
72#define reg_pio_rw_io_access3___data___lsb 0
73#define reg_pio_rw_io_access3___data___width 8
74#define reg_pio_rw_io_access3_offset 12
75
76/* Register rw_io_access4, scope pio, type rw */
77#define reg_pio_rw_io_access4___data___lsb 0
78#define reg_pio_rw_io_access4___data___width 8
79#define reg_pio_rw_io_access4_offset 16
80
81/* Register rw_io_access5, scope pio, type rw */
82#define reg_pio_rw_io_access5___data___lsb 0
83#define reg_pio_rw_io_access5___data___width 8
84#define reg_pio_rw_io_access5_offset 20
85
86/* Register rw_io_access6, scope pio, type rw */
87#define reg_pio_rw_io_access6___data___lsb 0
88#define reg_pio_rw_io_access6___data___width 8
89#define reg_pio_rw_io_access6_offset 24
90
91/* Register rw_io_access7, scope pio, type rw */
92#define reg_pio_rw_io_access7___data___lsb 0
93#define reg_pio_rw_io_access7___data___width 8
94#define reg_pio_rw_io_access7_offset 28
95
96/* Register rw_io_access8, scope pio, type rw */
97#define reg_pio_rw_io_access8___data___lsb 0
98#define reg_pio_rw_io_access8___data___width 8
99#define reg_pio_rw_io_access8_offset 32
100
101/* Register rw_io_access9, scope pio, type rw */
102#define reg_pio_rw_io_access9___data___lsb 0
103#define reg_pio_rw_io_access9___data___width 8
104#define reg_pio_rw_io_access9_offset 36
105
106/* Register rw_io_access10, scope pio, type rw */
107#define reg_pio_rw_io_access10___data___lsb 0
108#define reg_pio_rw_io_access10___data___width 8
109#define reg_pio_rw_io_access10_offset 40
110
111/* Register rw_io_access11, scope pio, type rw */
112#define reg_pio_rw_io_access11___data___lsb 0
113#define reg_pio_rw_io_access11___data___width 8
114#define reg_pio_rw_io_access11_offset 44
115
116/* Register rw_io_access12, scope pio, type rw */
117#define reg_pio_rw_io_access12___data___lsb 0
118#define reg_pio_rw_io_access12___data___width 8
119#define reg_pio_rw_io_access12_offset 48
120
121/* Register rw_io_access13, scope pio, type rw */
122#define reg_pio_rw_io_access13___data___lsb 0
123#define reg_pio_rw_io_access13___data___width 8
124#define reg_pio_rw_io_access13_offset 52
125
126/* Register rw_io_access14, scope pio, type rw */
127#define reg_pio_rw_io_access14___data___lsb 0
128#define reg_pio_rw_io_access14___data___width 8
129#define reg_pio_rw_io_access14_offset 56
130
131/* Register rw_io_access15, scope pio, type rw */
132#define reg_pio_rw_io_access15___data___lsb 0
133#define reg_pio_rw_io_access15___data___width 8
134#define reg_pio_rw_io_access15_offset 60
135
136/* Register rw_ce0_cfg, scope pio, type rw */
137#define reg_pio_rw_ce0_cfg___lw___lsb 0
138#define reg_pio_rw_ce0_cfg___lw___width 6
139#define reg_pio_rw_ce0_cfg___ew___lsb 6
140#define reg_pio_rw_ce0_cfg___ew___width 3
141#define reg_pio_rw_ce0_cfg___zw___lsb 9
142#define reg_pio_rw_ce0_cfg___zw___width 3
143#define reg_pio_rw_ce0_cfg___aw___lsb 12
144#define reg_pio_rw_ce0_cfg___aw___width 2
145#define reg_pio_rw_ce0_cfg___mode___lsb 14
146#define reg_pio_rw_ce0_cfg___mode___width 2
147#define reg_pio_rw_ce0_cfg_offset 68
148
149/* Register rw_ce1_cfg, scope pio, type rw */
150#define reg_pio_rw_ce1_cfg___lw___lsb 0
151#define reg_pio_rw_ce1_cfg___lw___width 6
152#define reg_pio_rw_ce1_cfg___ew___lsb 6
153#define reg_pio_rw_ce1_cfg___ew___width 3
154#define reg_pio_rw_ce1_cfg___zw___lsb 9
155#define reg_pio_rw_ce1_cfg___zw___width 3
156#define reg_pio_rw_ce1_cfg___aw___lsb 12
157#define reg_pio_rw_ce1_cfg___aw___width 2
158#define reg_pio_rw_ce1_cfg___mode___lsb 14
159#define reg_pio_rw_ce1_cfg___mode___width 2
160#define reg_pio_rw_ce1_cfg_offset 72
161
162/* Register rw_ce2_cfg, scope pio, type rw */
163#define reg_pio_rw_ce2_cfg___lw___lsb 0
164#define reg_pio_rw_ce2_cfg___lw___width 6
165#define reg_pio_rw_ce2_cfg___ew___lsb 6
166#define reg_pio_rw_ce2_cfg___ew___width 3
167#define reg_pio_rw_ce2_cfg___zw___lsb 9
168#define reg_pio_rw_ce2_cfg___zw___width 3
169#define reg_pio_rw_ce2_cfg___aw___lsb 12
170#define reg_pio_rw_ce2_cfg___aw___width 2
171#define reg_pio_rw_ce2_cfg___mode___lsb 14
172#define reg_pio_rw_ce2_cfg___mode___width 2
173#define reg_pio_rw_ce2_cfg_offset 76
174
175/* Register rw_dout, scope pio, type rw */
176#define reg_pio_rw_dout___data___lsb 0
177#define reg_pio_rw_dout___data___width 8
178#define reg_pio_rw_dout___rd_n___lsb 8
179#define reg_pio_rw_dout___rd_n___width 1
180#define reg_pio_rw_dout___rd_n___bit 8
181#define reg_pio_rw_dout___wr_n___lsb 9
182#define reg_pio_rw_dout___wr_n___width 1
183#define reg_pio_rw_dout___wr_n___bit 9
184#define reg_pio_rw_dout___a0___lsb 10
185#define reg_pio_rw_dout___a0___width 1
186#define reg_pio_rw_dout___a0___bit 10
187#define reg_pio_rw_dout___a1___lsb 11
188#define reg_pio_rw_dout___a1___width 1
189#define reg_pio_rw_dout___a1___bit 11
190#define reg_pio_rw_dout___ce0_n___lsb 12
191#define reg_pio_rw_dout___ce0_n___width 1
192#define reg_pio_rw_dout___ce0_n___bit 12
193#define reg_pio_rw_dout___ce1_n___lsb 13
194#define reg_pio_rw_dout___ce1_n___width 1
195#define reg_pio_rw_dout___ce1_n___bit 13
196#define reg_pio_rw_dout___ce2_n___lsb 14
197#define reg_pio_rw_dout___ce2_n___width 1
198#define reg_pio_rw_dout___ce2_n___bit 14
199#define reg_pio_rw_dout___rdy___lsb 15
200#define reg_pio_rw_dout___rdy___width 1
201#define reg_pio_rw_dout___rdy___bit 15
202#define reg_pio_rw_dout_offset 80
203
204/* Register rw_oe, scope pio, type rw */
205#define reg_pio_rw_oe___data___lsb 0
206#define reg_pio_rw_oe___data___width 8
207#define reg_pio_rw_oe___rd_n___lsb 8
208#define reg_pio_rw_oe___rd_n___width 1
209#define reg_pio_rw_oe___rd_n___bit 8
210#define reg_pio_rw_oe___wr_n___lsb 9
211#define reg_pio_rw_oe___wr_n___width 1
212#define reg_pio_rw_oe___wr_n___bit 9
213#define reg_pio_rw_oe___a0___lsb 10
214#define reg_pio_rw_oe___a0___width 1
215#define reg_pio_rw_oe___a0___bit 10
216#define reg_pio_rw_oe___a1___lsb 11
217#define reg_pio_rw_oe___a1___width 1
218#define reg_pio_rw_oe___a1___bit 11
219#define reg_pio_rw_oe___ce0_n___lsb 12
220#define reg_pio_rw_oe___ce0_n___width 1
221#define reg_pio_rw_oe___ce0_n___bit 12
222#define reg_pio_rw_oe___ce1_n___lsb 13
223#define reg_pio_rw_oe___ce1_n___width 1
224#define reg_pio_rw_oe___ce1_n___bit 13
225#define reg_pio_rw_oe___ce2_n___lsb 14
226#define reg_pio_rw_oe___ce2_n___width 1
227#define reg_pio_rw_oe___ce2_n___bit 14
228#define reg_pio_rw_oe___rdy___lsb 15
229#define reg_pio_rw_oe___rdy___width 1
230#define reg_pio_rw_oe___rdy___bit 15
231#define reg_pio_rw_oe_offset 84
232
233/* Register rw_man_ctrl, scope pio, type rw */
234#define reg_pio_rw_man_ctrl___data___lsb 0
235#define reg_pio_rw_man_ctrl___data___width 8
236#define reg_pio_rw_man_ctrl___rd_n___lsb 8
237#define reg_pio_rw_man_ctrl___rd_n___width 1
238#define reg_pio_rw_man_ctrl___rd_n___bit 8
239#define reg_pio_rw_man_ctrl___wr_n___lsb 9
240#define reg_pio_rw_man_ctrl___wr_n___width 1
241#define reg_pio_rw_man_ctrl___wr_n___bit 9
242#define reg_pio_rw_man_ctrl___a0___lsb 10
243#define reg_pio_rw_man_ctrl___a0___width 1
244#define reg_pio_rw_man_ctrl___a0___bit 10
245#define reg_pio_rw_man_ctrl___a1___lsb 11
246#define reg_pio_rw_man_ctrl___a1___width 1
247#define reg_pio_rw_man_ctrl___a1___bit 11
248#define reg_pio_rw_man_ctrl___ce0_n___lsb 12
249#define reg_pio_rw_man_ctrl___ce0_n___width 1
250#define reg_pio_rw_man_ctrl___ce0_n___bit 12
251#define reg_pio_rw_man_ctrl___ce1_n___lsb 13
252#define reg_pio_rw_man_ctrl___ce1_n___width 1
253#define reg_pio_rw_man_ctrl___ce1_n___bit 13
254#define reg_pio_rw_man_ctrl___ce2_n___lsb 14
255#define reg_pio_rw_man_ctrl___ce2_n___width 1
256#define reg_pio_rw_man_ctrl___ce2_n___bit 14
257#define reg_pio_rw_man_ctrl___rdy___lsb 15
258#define reg_pio_rw_man_ctrl___rdy___width 1
259#define reg_pio_rw_man_ctrl___rdy___bit 15
260#define reg_pio_rw_man_ctrl_offset 88
261
262/* Register r_din, scope pio, type r */
263#define reg_pio_r_din___data___lsb 0
264#define reg_pio_r_din___data___width 8
265#define reg_pio_r_din___rd_n___lsb 8
266#define reg_pio_r_din___rd_n___width 1
267#define reg_pio_r_din___rd_n___bit 8
268#define reg_pio_r_din___wr_n___lsb 9
269#define reg_pio_r_din___wr_n___width 1
270#define reg_pio_r_din___wr_n___bit 9
271#define reg_pio_r_din___a0___lsb 10
272#define reg_pio_r_din___a0___width 1
273#define reg_pio_r_din___a0___bit 10
274#define reg_pio_r_din___a1___lsb 11
275#define reg_pio_r_din___a1___width 1
276#define reg_pio_r_din___a1___bit 11
277#define reg_pio_r_din___ce0_n___lsb 12
278#define reg_pio_r_din___ce0_n___width 1
279#define reg_pio_r_din___ce0_n___bit 12
280#define reg_pio_r_din___ce1_n___lsb 13
281#define reg_pio_r_din___ce1_n___width 1
282#define reg_pio_r_din___ce1_n___bit 13
283#define reg_pio_r_din___ce2_n___lsb 14
284#define reg_pio_r_din___ce2_n___width 1
285#define reg_pio_r_din___ce2_n___bit 14
286#define reg_pio_r_din___rdy___lsb 15
287#define reg_pio_r_din___rdy___width 1
288#define reg_pio_r_din___rdy___bit 15
289#define reg_pio_r_din_offset 92
290
291/* Register r_stat, scope pio, type r */
292#define reg_pio_r_stat___busy___lsb 0
293#define reg_pio_r_stat___busy___width 1
294#define reg_pio_r_stat___busy___bit 0
295#define reg_pio_r_stat_offset 96
296
297/* Register rw_intr_mask, scope pio, type rw */
298#define reg_pio_rw_intr_mask___rdy___lsb 0
299#define reg_pio_rw_intr_mask___rdy___width 1
300#define reg_pio_rw_intr_mask___rdy___bit 0
301#define reg_pio_rw_intr_mask_offset 100
302
303/* Register rw_ack_intr, scope pio, type rw */
304#define reg_pio_rw_ack_intr___rdy___lsb 0
305#define reg_pio_rw_ack_intr___rdy___width 1
306#define reg_pio_rw_ack_intr___rdy___bit 0
307#define reg_pio_rw_ack_intr_offset 104
308
309/* Register r_intr, scope pio, type r */
310#define reg_pio_r_intr___rdy___lsb 0
311#define reg_pio_r_intr___rdy___width 1
312#define reg_pio_r_intr___rdy___bit 0
313#define reg_pio_r_intr_offset 108
314
315/* Register r_masked_intr, scope pio, type r */
316#define reg_pio_r_masked_intr___rdy___lsb 0
317#define reg_pio_r_masked_intr___rdy___width 1
318#define reg_pio_r_masked_intr___rdy___bit 0
319#define reg_pio_r_masked_intr_offset 112
320
321
322/* Constants */
323#define regk_pio_a2 0x00000003
324#define regk_pio_no 0x00000000
325#define regk_pio_normal 0x00000000
326#define regk_pio_rd 0x00000001
327#define regk_pio_rw_ce0_cfg_default 0x00000000
328#define regk_pio_rw_ce1_cfg_default 0x00000000
329#define regk_pio_rw_ce2_cfg_default 0x00000000
330#define regk_pio_rw_intr_mask_default 0x00000000
331#define regk_pio_rw_man_ctrl_default 0x00000000
332#define regk_pio_rw_oe_default 0x00000000
333#define regk_pio_wr 0x00000002
334#define regk_pio_wr_ce2 0x00000003
335#define regk_pio_yes 0x00000001
336#define regk_pio_yes_all 0x000000ff
337#endif /* __pio_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/reg_map_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/reg_map_asm.h
new file mode 100644
index 000000000000..89439e9610e2
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/reg_map_asm.h
@@ -0,0 +1,99 @@
1#ifndef __reg_map_asm_h
2#define __reg_map_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: reg.rmap
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -asm -base 0xb0000000 -map marb_bar.r marb_foo.r ccd_top.r ccd_stat.r ccd_tg.r ccd_dp.r ccd.r iop_sap_in.r iop_sap_out.r iop_sw_cfg.r iop_sw_cpu.r iop_sw_mpu.r iop_sw_spu.r iop_version.r iop_crc_par.r iop_dmc_in.r iop_dmc_out.r iop_fifo_in_extra.r iop_fifo_in.r iop_fifo_out_extra.r iop_fifo_out.r iop_mc.r iop_mpu.r iop_scrc_in.r iop_scrc_out.r iop_spu.r iop_timer_grp.r iop_trigger_grp.r iop.r -outfile reg_map_asm.h reg.rmap
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13#define regi_ccd 0xb0000000
14#define regi_ccd_top 0xb0000000
15#define regi_ccd_dp 0xb0000400
16#define regi_ccd_stat 0xb0000800
17#define regi_ccd_tg 0xb0001000
18#define regi_cfg 0xb0002000
19#define regi_clkgen 0xb0004000
20#define regi_ddr2_ctrl 0xb0006000
21#define regi_dma0 0xb0008000
22#define regi_dma1 0xb000a000
23#define regi_dma11 0xb000c000
24#define regi_dma2 0xb000e000
25#define regi_dma3 0xb0010000
26#define regi_dma4 0xb0012000
27#define regi_dma5 0xb0014000
28#define regi_dma6 0xb0016000
29#define regi_dma7 0xb0018000
30#define regi_dma9 0xb001a000
31#define regi_eth 0xb001c000
32#define regi_gio 0xb0020000
33#define regi_h264 0xb0022000
34#define regi_hist 0xb0026000
35#define regi_iop 0xb0028000
36#define regi_iop_version 0xb0028000
37#define regi_iop_fifo_in_extra 0xb0028040
38#define regi_iop_fifo_out_extra 0xb0028080
39#define regi_iop_trigger_grp0 0xb00280c0
40#define regi_iop_trigger_grp1 0xb0028100
41#define regi_iop_trigger_grp2 0xb0028140
42#define regi_iop_trigger_grp3 0xb0028180
43#define regi_iop_trigger_grp4 0xb00281c0
44#define regi_iop_trigger_grp5 0xb0028200
45#define regi_iop_trigger_grp6 0xb0028240
46#define regi_iop_trigger_grp7 0xb0028280
47#define regi_iop_crc_par 0xb0028300
48#define regi_iop_dmc_in 0xb0028380
49#define regi_iop_dmc_out 0xb0028400
50#define regi_iop_fifo_in 0xb0028480
51#define regi_iop_fifo_out 0xb0028500
52#define regi_iop_scrc_in 0xb0028580
53#define regi_iop_scrc_out 0xb0028600
54#define regi_iop_timer_grp0 0xb0028680
55#define regi_iop_timer_grp1 0xb0028700
56#define regi_iop_sap_in 0xb0028800
57#define regi_iop_sap_out 0xb0028900
58#define regi_iop_spu 0xb0028a00
59#define regi_iop_sw_cfg 0xb0028b00
60#define regi_iop_sw_cpu 0xb0028c00
61#define regi_iop_sw_mpu 0xb0028d00
62#define regi_iop_sw_spu 0xb0028e00
63#define regi_iop_mpu 0xb0029000
64#define regi_irq 0xb002a000
65#define regi_jpeg 0xb002c000
66#define regi_l2cache 0xb0030000
67#define regi_marb_bar 0xb0032000
68#define regi_marb_bar_bp0 0xb0032140
69#define regi_marb_bar_bp1 0xb0032180
70#define regi_marb_bar_bp2 0xb00321c0
71#define regi_marb_bar_bp3 0xb0032200
72#define regi_marb_foo 0xb0034000
73#define regi_marb_foo_bp0 0xb0034280
74#define regi_marb_foo_bp1 0xb00342c0
75#define regi_marb_foo_bp2 0xb0034300
76#define regi_marb_foo_bp3 0xb0034340
77#define regi_pinmux 0xb0038000
78#define regi_pio 0xb0036000
79#define regi_sclr 0xb003a000
80#define regi_sclr_fifo 0xb003c000
81#define regi_ser0 0xb003e000
82#define regi_ser1 0xb0040000
83#define regi_ser2 0xb0042000
84#define regi_ser3 0xb0044000
85#define regi_ser4 0xb0046000
86#define regi_sser 0xb0048000
87#define regi_strcop 0xb004a000
88#define regi_strdma0 0xb004e000
89#define regi_strdma1 0xb0050000
90#define regi_strdma2 0xb0052000
91#define regi_strdma3 0xb0054000
92#define regi_strdma5 0xb0056000
93#define regi_strmux 0xb004c000
94#define regi_timer0 0xb0058000
95#define regi_timer1 0xb005a000
96#define regi_trace 0xb005c000
97#define regi_vin 0xb005e000
98#define regi_vout 0xb0060000
99#endif /* __reg_map_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/timer_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/timer_defs_asm.h
new file mode 100644
index 000000000000..b129e826fc34
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/timer_defs_asm.h
@@ -0,0 +1,228 @@
1#ifndef __timer_defs_asm_h
2#define __timer_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: timer.r
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -asm -outfile timer_defs_asm.h timer.r
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13
14#ifndef REG_FIELD
15#define REG_FIELD( scope, reg, field, value ) \
16 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
17#define REG_FIELD_X_( value, shift ) ((value) << shift)
18#endif
19
20#ifndef REG_STATE
21#define REG_STATE( scope, reg, field, symbolic_value ) \
22 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
23#define REG_STATE_X_( k, shift ) (k << shift)
24#endif
25
26#ifndef REG_MASK
27#define REG_MASK( scope, reg, field ) \
28 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
29#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
30#endif
31
32#ifndef REG_LSB
33#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
34#endif
35
36#ifndef REG_BIT
37#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
38#endif
39
40#ifndef REG_ADDR
41#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
42#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
43#endif
44
45#ifndef REG_ADDR_VECT
46#define REG_ADDR_VECT( scope, inst, reg, index ) \
47 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
48 STRIDE_##scope##_##reg )
49#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
50 ((inst) + offs + (index) * stride)
51#endif
52
53/* Register rw_tmr0_div, scope timer, type rw */
54#define reg_timer_rw_tmr0_div_offset 0
55
56/* Register r_tmr0_data, scope timer, type r */
57#define reg_timer_r_tmr0_data_offset 4
58
59/* Register rw_tmr0_ctrl, scope timer, type rw */
60#define reg_timer_rw_tmr0_ctrl___op___lsb 0
61#define reg_timer_rw_tmr0_ctrl___op___width 2
62#define reg_timer_rw_tmr0_ctrl___freq___lsb 2
63#define reg_timer_rw_tmr0_ctrl___freq___width 3
64#define reg_timer_rw_tmr0_ctrl_offset 8
65
66/* Register rw_tmr1_div, scope timer, type rw */
67#define reg_timer_rw_tmr1_div_offset 16
68
69/* Register r_tmr1_data, scope timer, type r */
70#define reg_timer_r_tmr1_data_offset 20
71
72/* Register rw_tmr1_ctrl, scope timer, type rw */
73#define reg_timer_rw_tmr1_ctrl___op___lsb 0
74#define reg_timer_rw_tmr1_ctrl___op___width 2
75#define reg_timer_rw_tmr1_ctrl___freq___lsb 2
76#define reg_timer_rw_tmr1_ctrl___freq___width 3
77#define reg_timer_rw_tmr1_ctrl_offset 24
78
79/* Register rs_cnt_data, scope timer, type rs */
80#define reg_timer_rs_cnt_data___tmr___lsb 0
81#define reg_timer_rs_cnt_data___tmr___width 24
82#define reg_timer_rs_cnt_data___cnt___lsb 24
83#define reg_timer_rs_cnt_data___cnt___width 8
84#define reg_timer_rs_cnt_data_offset 32
85
86/* Register r_cnt_data, scope timer, type r */
87#define reg_timer_r_cnt_data___tmr___lsb 0
88#define reg_timer_r_cnt_data___tmr___width 24
89#define reg_timer_r_cnt_data___cnt___lsb 24
90#define reg_timer_r_cnt_data___cnt___width 8
91#define reg_timer_r_cnt_data_offset 36
92
93/* Register rw_cnt_cfg, scope timer, type rw */
94#define reg_timer_rw_cnt_cfg___clk___lsb 0
95#define reg_timer_rw_cnt_cfg___clk___width 2
96#define reg_timer_rw_cnt_cfg_offset 40
97
98/* Register rw_trig, scope timer, type rw */
99#define reg_timer_rw_trig_offset 48
100
101/* Register rw_trig_cfg, scope timer, type rw */
102#define reg_timer_rw_trig_cfg___tmr___lsb 0
103#define reg_timer_rw_trig_cfg___tmr___width 2
104#define reg_timer_rw_trig_cfg_offset 52
105
106/* Register r_time, scope timer, type r */
107#define reg_timer_r_time_offset 56
108
109/* Register rw_out, scope timer, type rw */
110#define reg_timer_rw_out___tmr___lsb 0
111#define reg_timer_rw_out___tmr___width 2
112#define reg_timer_rw_out_offset 60
113
114/* Register rw_wd_ctrl, scope timer, type rw */
115#define reg_timer_rw_wd_ctrl___cnt___lsb 0
116#define reg_timer_rw_wd_ctrl___cnt___width 8
117#define reg_timer_rw_wd_ctrl___cmd___lsb 8
118#define reg_timer_rw_wd_ctrl___cmd___width 1
119#define reg_timer_rw_wd_ctrl___cmd___bit 8
120#define reg_timer_rw_wd_ctrl___key___lsb 9
121#define reg_timer_rw_wd_ctrl___key___width 7
122#define reg_timer_rw_wd_ctrl_offset 64
123
124/* Register r_wd_stat, scope timer, type r */
125#define reg_timer_r_wd_stat___cnt___lsb 0
126#define reg_timer_r_wd_stat___cnt___width 8
127#define reg_timer_r_wd_stat___cmd___lsb 8
128#define reg_timer_r_wd_stat___cmd___width 1
129#define reg_timer_r_wd_stat___cmd___bit 8
130#define reg_timer_r_wd_stat_offset 68
131
132/* Register rw_intr_mask, scope timer, type rw */
133#define reg_timer_rw_intr_mask___tmr0___lsb 0
134#define reg_timer_rw_intr_mask___tmr0___width 1
135#define reg_timer_rw_intr_mask___tmr0___bit 0
136#define reg_timer_rw_intr_mask___tmr1___lsb 1
137#define reg_timer_rw_intr_mask___tmr1___width 1
138#define reg_timer_rw_intr_mask___tmr1___bit 1
139#define reg_timer_rw_intr_mask___cnt___lsb 2
140#define reg_timer_rw_intr_mask___cnt___width 1
141#define reg_timer_rw_intr_mask___cnt___bit 2
142#define reg_timer_rw_intr_mask___trig___lsb 3
143#define reg_timer_rw_intr_mask___trig___width 1
144#define reg_timer_rw_intr_mask___trig___bit 3
145#define reg_timer_rw_intr_mask_offset 72
146
147/* Register rw_ack_intr, scope timer, type rw */
148#define reg_timer_rw_ack_intr___tmr0___lsb 0
149#define reg_timer_rw_ack_intr___tmr0___width 1
150#define reg_timer_rw_ack_intr___tmr0___bit 0
151#define reg_timer_rw_ack_intr___tmr1___lsb 1
152#define reg_timer_rw_ack_intr___tmr1___width 1
153#define reg_timer_rw_ack_intr___tmr1___bit 1
154#define reg_timer_rw_ack_intr___cnt___lsb 2
155#define reg_timer_rw_ack_intr___cnt___width 1
156#define reg_timer_rw_ack_intr___cnt___bit 2
157#define reg_timer_rw_ack_intr___trig___lsb 3
158#define reg_timer_rw_ack_intr___trig___width 1
159#define reg_timer_rw_ack_intr___trig___bit 3
160#define reg_timer_rw_ack_intr_offset 76
161
162/* Register r_intr, scope timer, type r */
163#define reg_timer_r_intr___tmr0___lsb 0
164#define reg_timer_r_intr___tmr0___width 1
165#define reg_timer_r_intr___tmr0___bit 0
166#define reg_timer_r_intr___tmr1___lsb 1
167#define reg_timer_r_intr___tmr1___width 1
168#define reg_timer_r_intr___tmr1___bit 1
169#define reg_timer_r_intr___cnt___lsb 2
170#define reg_timer_r_intr___cnt___width 1
171#define reg_timer_r_intr___cnt___bit 2
172#define reg_timer_r_intr___trig___lsb 3
173#define reg_timer_r_intr___trig___width 1
174#define reg_timer_r_intr___trig___bit 3
175#define reg_timer_r_intr_offset 80
176
177/* Register r_masked_intr, scope timer, type r */
178#define reg_timer_r_masked_intr___tmr0___lsb 0
179#define reg_timer_r_masked_intr___tmr0___width 1
180#define reg_timer_r_masked_intr___tmr0___bit 0
181#define reg_timer_r_masked_intr___tmr1___lsb 1
182#define reg_timer_r_masked_intr___tmr1___width 1
183#define reg_timer_r_masked_intr___tmr1___bit 1
184#define reg_timer_r_masked_intr___cnt___lsb 2
185#define reg_timer_r_masked_intr___cnt___width 1
186#define reg_timer_r_masked_intr___cnt___bit 2
187#define reg_timer_r_masked_intr___trig___lsb 3
188#define reg_timer_r_masked_intr___trig___width 1
189#define reg_timer_r_masked_intr___trig___bit 3
190#define reg_timer_r_masked_intr_offset 84
191
192/* Register rw_test, scope timer, type rw */
193#define reg_timer_rw_test___dis___lsb 0
194#define reg_timer_rw_test___dis___width 1
195#define reg_timer_rw_test___dis___bit 0
196#define reg_timer_rw_test___en___lsb 1
197#define reg_timer_rw_test___en___width 1
198#define reg_timer_rw_test___en___bit 1
199#define reg_timer_rw_test_offset 88
200
201
202/* Constants */
203#define regk_timer_ext 0x00000001
204#define regk_timer_f100 0x00000007
205#define regk_timer_f29_493 0x00000004
206#define regk_timer_f32 0x00000005
207#define regk_timer_f32_768 0x00000006
208#define regk_timer_f90 0x00000003
209#define regk_timer_hold 0x00000001
210#define regk_timer_ld 0x00000000
211#define regk_timer_no 0x00000000
212#define regk_timer_off 0x00000000
213#define regk_timer_run 0x00000002
214#define regk_timer_rw_cnt_cfg_default 0x00000000
215#define regk_timer_rw_intr_mask_default 0x00000000
216#define regk_timer_rw_out_default 0x00000000
217#define regk_timer_rw_test_default 0x00000000
218#define regk_timer_rw_tmr0_ctrl_default 0x00000000
219#define regk_timer_rw_tmr1_ctrl_default 0x00000000
220#define regk_timer_rw_trig_cfg_default 0x00000000
221#define regk_timer_start 0x00000001
222#define regk_timer_stop 0x00000000
223#define regk_timer_time 0x00000001
224#define regk_timer_tmr0 0x00000002
225#define regk_timer_tmr1 0x00000003
226#define regk_timer_vclk 0x00000002
227#define regk_timer_yes 0x00000001
228#endif /* __timer_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/clkgen_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/clkgen_defs.h
new file mode 100644
index 000000000000..c1e9ba93b3a3
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/clkgen_defs.h
@@ -0,0 +1,159 @@
1#ifndef __clkgen_defs_h
2#define __clkgen_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: clkgen.r
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -outfile clkgen_defs.h clkgen.r
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13/* Main access macros */
14#ifndef REG_RD
15#define REG_RD( scope, inst, reg ) \
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
18#endif
19
20#ifndef REG_WR
21#define REG_WR( scope, inst, reg, val ) \
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
24#endif
25
26#ifndef REG_RD_VECT
27#define REG_RD_VECT( scope, inst, reg, index ) \
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
31#endif
32
33#ifndef REG_WR_VECT
34#define REG_WR_VECT( scope, inst, reg, index, val ) \
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
38#endif
39
40#ifndef REG_RD_INT
41#define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
43#endif
44
45#ifndef REG_WR_INT
46#define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
48#endif
49
50#ifndef REG_RD_INT_VECT
51#define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
53 (index) * STRIDE_##scope##_##reg )
54#endif
55
56#ifndef REG_WR_INT_VECT
57#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
59 (index) * STRIDE_##scope##_##reg, (val) )
60#endif
61
62#ifndef REG_TYPE_CONV
63#define REG_TYPE_CONV( type, orgtype, val ) \
64 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
65#endif
66
67#ifndef reg_page_size
68#define reg_page_size 8192
69#endif
70
71#ifndef REG_ADDR
72#define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
74#endif
75
76#ifndef REG_ADDR_VECT
77#define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
79 (index) * STRIDE_##scope##_##reg )
80#endif
81
82/* C-code for register scope clkgen */
83
84/* Register r_bootsel, scope clkgen, type r */
85typedef struct {
86 unsigned int boot_mode : 5;
87 unsigned int intern_main_clk : 1;
88 unsigned int extern_usb2_clk : 1;
89 unsigned int dummy1 : 25;
90} reg_clkgen_r_bootsel;
91#define REG_RD_ADDR_clkgen_r_bootsel 0
92
93/* Register rw_clk_ctrl, scope clkgen, type rw */
94typedef struct {
95 unsigned int pll : 1;
96 unsigned int cpu : 1;
97 unsigned int iop_usb : 1;
98 unsigned int vin : 1;
99 unsigned int sclr : 1;
100 unsigned int h264 : 1;
101 unsigned int ddr2 : 1;
102 unsigned int vout_hist : 1;
103 unsigned int eth : 1;
104 unsigned int ccd_tg_200 : 1;
105 unsigned int dma0_1_eth : 1;
106 unsigned int ccd_tg_100 : 1;
107 unsigned int jpeg : 1;
108 unsigned int sser_ser_dma6_7 : 1;
109 unsigned int strdma0_2_video : 1;
110 unsigned int dma2_3_strcop : 1;
111 unsigned int dma4_5_iop : 1;
112 unsigned int dma9_11 : 1;
113 unsigned int memarb_bar_ddr : 1;
114 unsigned int sclr_h264 : 1;
115 unsigned int dummy1 : 12;
116} reg_clkgen_rw_clk_ctrl;
117#define REG_RD_ADDR_clkgen_rw_clk_ctrl 4
118#define REG_WR_ADDR_clkgen_rw_clk_ctrl 4
119
120
121/* Constants */
122enum {
123 regk_clkgen_eth1000_rx = 0x0000000c,
124 regk_clkgen_eth1000_tx = 0x0000000e,
125 regk_clkgen_eth100_rx = 0x0000001d,
126 regk_clkgen_eth100_rx_half = 0x0000001c,
127 regk_clkgen_eth100_tx = 0x0000001f,
128 regk_clkgen_eth100_tx_half = 0x0000001e,
129 regk_clkgen_nand_3_2 = 0x00000000,
130 regk_clkgen_nand_3_2_0x30 = 0x00000002,
131 regk_clkgen_nand_3_2_0x30_pll = 0x00000012,
132 regk_clkgen_nand_3_2_pll = 0x00000010,
133 regk_clkgen_nand_3_3 = 0x00000001,
134 regk_clkgen_nand_3_3_0x30 = 0x00000003,
135 regk_clkgen_nand_3_3_0x30_pll = 0x00000013,
136 regk_clkgen_nand_3_3_pll = 0x00000011,
137 regk_clkgen_nand_4_2 = 0x00000004,
138 regk_clkgen_nand_4_2_0x30 = 0x00000006,
139 regk_clkgen_nand_4_2_0x30_pll = 0x00000016,
140 regk_clkgen_nand_4_2_pll = 0x00000014,
141 regk_clkgen_nand_4_3 = 0x00000005,
142 regk_clkgen_nand_4_3_0x30 = 0x00000007,
143 regk_clkgen_nand_4_3_0x30_pll = 0x00000017,
144 regk_clkgen_nand_4_3_pll = 0x00000015,
145 regk_clkgen_nand_5_2 = 0x00000008,
146 regk_clkgen_nand_5_2_0x30 = 0x0000000a,
147 regk_clkgen_nand_5_2_0x30_pll = 0x0000001a,
148 regk_clkgen_nand_5_2_pll = 0x00000018,
149 regk_clkgen_nand_5_3 = 0x00000009,
150 regk_clkgen_nand_5_3_0x30 = 0x0000000b,
151 regk_clkgen_nand_5_3_0x30_pll = 0x0000001b,
152 regk_clkgen_nand_5_3_pll = 0x00000019,
153 regk_clkgen_no = 0x00000000,
154 regk_clkgen_rw_clk_ctrl_default = 0x00000002,
155 regk_clkgen_ser = 0x0000000d,
156 regk_clkgen_ser_pll = 0x0000000f,
157 regk_clkgen_yes = 0x00000001
158};
159#endif /* __clkgen_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/ddr2_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/ddr2_defs.h
new file mode 100644
index 000000000000..0f30e8bf946d
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/ddr2_defs.h
@@ -0,0 +1,281 @@
1#ifndef __ddr2_defs_h
2#define __ddr2_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ddr2.r
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -outfile ddr2_defs.h ddr2.r
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13/* Main access macros */
14#ifndef REG_RD
15#define REG_RD( scope, inst, reg ) \
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
18#endif
19
20#ifndef REG_WR
21#define REG_WR( scope, inst, reg, val ) \
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
24#endif
25
26#ifndef REG_RD_VECT
27#define REG_RD_VECT( scope, inst, reg, index ) \
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
31#endif
32
33#ifndef REG_WR_VECT
34#define REG_WR_VECT( scope, inst, reg, index, val ) \
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
38#endif
39
40#ifndef REG_RD_INT
41#define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
43#endif
44
45#ifndef REG_WR_INT
46#define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
48#endif
49
50#ifndef REG_RD_INT_VECT
51#define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
53 (index) * STRIDE_##scope##_##reg )
54#endif
55
56#ifndef REG_WR_INT_VECT
57#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
59 (index) * STRIDE_##scope##_##reg, (val) )
60#endif
61
62#ifndef REG_TYPE_CONV
63#define REG_TYPE_CONV( type, orgtype, val ) \
64 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
65#endif
66
67#ifndef reg_page_size
68#define reg_page_size 8192
69#endif
70
71#ifndef REG_ADDR
72#define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
74#endif
75
76#ifndef REG_ADDR_VECT
77#define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
79 (index) * STRIDE_##scope##_##reg )
80#endif
81
82/* C-code for register scope ddr2 */
83
84/* Register rw_cfg, scope ddr2, type rw */
85typedef struct {
86 unsigned int col_width : 4;
87 unsigned int nr_banks : 1;
88 unsigned int bw : 1;
89 unsigned int nr_ref : 4;
90 unsigned int ref_interval : 11;
91 unsigned int odt_ctrl : 2;
92 unsigned int odt_mem : 1;
93 unsigned int imp_strength : 1;
94 unsigned int auto_imp_cal : 1;
95 unsigned int imp_cal_override : 1;
96 unsigned int dll_override : 1;
97 unsigned int dummy1 : 4;
98} reg_ddr2_rw_cfg;
99#define REG_RD_ADDR_ddr2_rw_cfg 0
100#define REG_WR_ADDR_ddr2_rw_cfg 0
101
102/* Register rw_timing, scope ddr2, type rw */
103typedef struct {
104 unsigned int wr : 3;
105 unsigned int rcd : 3;
106 unsigned int rp : 3;
107 unsigned int ras : 4;
108 unsigned int rfc : 7;
109 unsigned int rc : 5;
110 unsigned int rtp : 2;
111 unsigned int rtw : 3;
112 unsigned int wtr : 2;
113} reg_ddr2_rw_timing;
114#define REG_RD_ADDR_ddr2_rw_timing 4
115#define REG_WR_ADDR_ddr2_rw_timing 4
116
117/* Register rw_latency, scope ddr2, type rw */
118typedef struct {
119 unsigned int cas : 3;
120 unsigned int additive : 3;
121 unsigned int dummy1 : 26;
122} reg_ddr2_rw_latency;
123#define REG_RD_ADDR_ddr2_rw_latency 8
124#define REG_WR_ADDR_ddr2_rw_latency 8
125
126/* Register rw_phy_cfg, scope ddr2, type rw */
127typedef struct {
128 unsigned int en : 1;
129 unsigned int dummy1 : 31;
130} reg_ddr2_rw_phy_cfg;
131#define REG_RD_ADDR_ddr2_rw_phy_cfg 12
132#define REG_WR_ADDR_ddr2_rw_phy_cfg 12
133
134/* Register rw_phy_ctrl, scope ddr2, type rw */
135typedef struct {
136 unsigned int rst : 1;
137 unsigned int cal_rst : 1;
138 unsigned int cal_start : 1;
139 unsigned int dummy1 : 29;
140} reg_ddr2_rw_phy_ctrl;
141#define REG_RD_ADDR_ddr2_rw_phy_ctrl 16
142#define REG_WR_ADDR_ddr2_rw_phy_ctrl 16
143
144/* Register rw_ctrl, scope ddr2, type rw */
145typedef struct {
146 unsigned int mrs_data : 16;
147 unsigned int cmd : 8;
148 unsigned int dummy1 : 8;
149} reg_ddr2_rw_ctrl;
150#define REG_RD_ADDR_ddr2_rw_ctrl 20
151#define REG_WR_ADDR_ddr2_rw_ctrl 20
152
153/* Register rw_pwr_down, scope ddr2, type rw */
154typedef struct {
155 unsigned int self_ref : 2;
156 unsigned int phy_en : 1;
157 unsigned int dummy1 : 29;
158} reg_ddr2_rw_pwr_down;
159#define REG_RD_ADDR_ddr2_rw_pwr_down 24
160#define REG_WR_ADDR_ddr2_rw_pwr_down 24
161
162/* Register r_stat, scope ddr2, type r */
163typedef struct {
164 unsigned int dll_lock : 1;
165 unsigned int dll_delay_code : 7;
166 unsigned int imp_cal_done : 1;
167 unsigned int imp_cal_fault : 1;
168 unsigned int cal_imp_pu : 4;
169 unsigned int cal_imp_pd : 4;
170 unsigned int dummy1 : 14;
171} reg_ddr2_r_stat;
172#define REG_RD_ADDR_ddr2_r_stat 28
173
174/* Register rw_imp_ctrl, scope ddr2, type rw */
175typedef struct {
176 unsigned int imp_pu : 4;
177 unsigned int imp_pd : 4;
178 unsigned int dummy1 : 24;
179} reg_ddr2_rw_imp_ctrl;
180#define REG_RD_ADDR_ddr2_rw_imp_ctrl 32
181#define REG_WR_ADDR_ddr2_rw_imp_ctrl 32
182
183#define STRIDE_ddr2_rw_dll_ctrl 4
184/* Register rw_dll_ctrl, scope ddr2, type rw */
185typedef struct {
186 unsigned int mode : 1;
187 unsigned int clk_delay : 7;
188 unsigned int dummy1 : 24;
189} reg_ddr2_rw_dll_ctrl;
190#define REG_RD_ADDR_ddr2_rw_dll_ctrl 36
191#define REG_WR_ADDR_ddr2_rw_dll_ctrl 36
192
193#define STRIDE_ddr2_rw_dqs_dll_ctrl 4
194/* Register rw_dqs_dll_ctrl, scope ddr2, type rw */
195typedef struct {
196 unsigned int dqs90_delay : 7;
197 unsigned int dqs180_delay : 7;
198 unsigned int dqs270_delay : 7;
199 unsigned int dqs360_delay : 7;
200 unsigned int dummy1 : 4;
201} reg_ddr2_rw_dqs_dll_ctrl;
202#define REG_RD_ADDR_ddr2_rw_dqs_dll_ctrl 52
203#define REG_WR_ADDR_ddr2_rw_dqs_dll_ctrl 52
204
205
206/* Constants */
207enum {
208 regk_ddr2_al0 = 0x00000000,
209 regk_ddr2_al1 = 0x00000008,
210 regk_ddr2_al2 = 0x00000010,
211 regk_ddr2_al3 = 0x00000018,
212 regk_ddr2_al4 = 0x00000020,
213 regk_ddr2_auto = 0x00000003,
214 regk_ddr2_bank4 = 0x00000000,
215 regk_ddr2_bank8 = 0x00000001,
216 regk_ddr2_bl4 = 0x00000002,
217 regk_ddr2_bl8 = 0x00000003,
218 regk_ddr2_bt_il = 0x00000008,
219 regk_ddr2_bt_seq = 0x00000000,
220 regk_ddr2_bw16 = 0x00000001,
221 regk_ddr2_bw32 = 0x00000000,
222 regk_ddr2_cas2 = 0x00000020,
223 regk_ddr2_cas3 = 0x00000030,
224 regk_ddr2_cas4 = 0x00000040,
225 regk_ddr2_cas5 = 0x00000050,
226 regk_ddr2_deselect = 0x000000c0,
227 regk_ddr2_dic_weak = 0x00000002,
228 regk_ddr2_direct = 0x00000001,
229 regk_ddr2_dis = 0x00000000,
230 regk_ddr2_dll_dis = 0x00000001,
231 regk_ddr2_dll_en = 0x00000000,
232 regk_ddr2_dll_rst = 0x00000100,
233 regk_ddr2_emrs = 0x00000081,
234 regk_ddr2_emrs2 = 0x00000082,
235 regk_ddr2_emrs3 = 0x00000083,
236 regk_ddr2_full = 0x00000001,
237 regk_ddr2_hi_ref_rate = 0x00000080,
238 regk_ddr2_mrs = 0x00000080,
239 regk_ddr2_no = 0x00000000,
240 regk_ddr2_nop = 0x000000b8,
241 regk_ddr2_ocd_adj = 0x00000200,
242 regk_ddr2_ocd_default = 0x00000380,
243 regk_ddr2_ocd_drive0 = 0x00000100,
244 regk_ddr2_ocd_drive1 = 0x00000080,
245 regk_ddr2_ocd_exit = 0x00000000,
246 regk_ddr2_odt_dis = 0x00000000,
247 regk_ddr2_offs = 0x00000000,
248 regk_ddr2_pre = 0x00000090,
249 regk_ddr2_pre_all = 0x00000400,
250 regk_ddr2_pwr_down_fast = 0x00000000,
251 regk_ddr2_pwr_down_slow = 0x00001000,
252 regk_ddr2_ref = 0x00000088,
253 regk_ddr2_rtt150 = 0x00000040,
254 regk_ddr2_rtt50 = 0x00000044,
255 regk_ddr2_rtt75 = 0x00000004,
256 regk_ddr2_rw_cfg_default = 0x00186000,
257 regk_ddr2_rw_dll_ctrl_default = 0x00000000,
258 regk_ddr2_rw_dll_ctrl_size = 0x00000004,
259 regk_ddr2_rw_dqs_dll_ctrl_default = 0x00000000,
260 regk_ddr2_rw_dqs_dll_ctrl_size = 0x00000004,
261 regk_ddr2_rw_latency_default = 0x00000000,
262 regk_ddr2_rw_phy_cfg_default = 0x00000000,
263 regk_ddr2_rw_pwr_down_default = 0x00000000,
264 regk_ddr2_rw_timing_default = 0x00000000,
265 regk_ddr2_s1Gb = 0x0000001a,
266 regk_ddr2_s256Mb = 0x0000000f,
267 regk_ddr2_s2Gb = 0x00000027,
268 regk_ddr2_s4Gb = 0x00000042,
269 regk_ddr2_s512Mb = 0x00000015,
270 regk_ddr2_temp0_85 = 0x00000618,
271 regk_ddr2_temp85_95 = 0x0000030c,
272 regk_ddr2_term150 = 0x00000002,
273 regk_ddr2_term50 = 0x00000003,
274 regk_ddr2_term75 = 0x00000001,
275 regk_ddr2_test = 0x00000080,
276 regk_ddr2_weak = 0x00000000,
277 regk_ddr2_wr2 = 0x00000200,
278 regk_ddr2_wr3 = 0x00000400,
279 regk_ddr2_yes = 0x00000001
280};
281#endif /* __ddr2_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/gio_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/gio_defs.h
new file mode 100644
index 000000000000..5d88e0db23ae
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/gio_defs.h
@@ -0,0 +1,837 @@
1#ifndef __gio_defs_h
2#define __gio_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: gio.r
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -outfile gio_defs.h gio.r
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13/* Main access macros */
14#ifndef REG_RD
15#define REG_RD( scope, inst, reg ) \
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
18#endif
19
20#ifndef REG_WR
21#define REG_WR( scope, inst, reg, val ) \
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
24#endif
25
26#ifndef REG_RD_VECT
27#define REG_RD_VECT( scope, inst, reg, index ) \
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
31#endif
32
33#ifndef REG_WR_VECT
34#define REG_WR_VECT( scope, inst, reg, index, val ) \
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
38#endif
39
40#ifndef REG_RD_INT
41#define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
43#endif
44
45#ifndef REG_WR_INT
46#define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
48#endif
49
50#ifndef REG_RD_INT_VECT
51#define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
53 (index) * STRIDE_##scope##_##reg )
54#endif
55
56#ifndef REG_WR_INT_VECT
57#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
59 (index) * STRIDE_##scope##_##reg, (val) )
60#endif
61
62#ifndef REG_TYPE_CONV
63#define REG_TYPE_CONV( type, orgtype, val ) \
64 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
65#endif
66
67#ifndef reg_page_size
68#define reg_page_size 8192
69#endif
70
71#ifndef REG_ADDR
72#define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
74#endif
75
76#ifndef REG_ADDR_VECT
77#define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
79 (index) * STRIDE_##scope##_##reg )
80#endif
81
82/* C-code for register scope gio */
83
84/* Register r_pa_din, scope gio, type r */
85typedef struct {
86 unsigned int data : 32;
87} reg_gio_r_pa_din;
88#define REG_RD_ADDR_gio_r_pa_din 0
89
90/* Register rw_pa_dout, scope gio, type rw */
91typedef struct {
92 unsigned int data : 32;
93} reg_gio_rw_pa_dout;
94#define REG_RD_ADDR_gio_rw_pa_dout 4
95#define REG_WR_ADDR_gio_rw_pa_dout 4
96
97/* Register rw_pa_oe, scope gio, type rw */
98typedef struct {
99 unsigned int oe : 32;
100} reg_gio_rw_pa_oe;
101#define REG_RD_ADDR_gio_rw_pa_oe 8
102#define REG_WR_ADDR_gio_rw_pa_oe 8
103
104/* Register rw_pa_byte0_dout, scope gio, type rw */
105typedef struct {
106 unsigned int data : 8;
107 unsigned int dummy1 : 24;
108} reg_gio_rw_pa_byte0_dout;
109#define REG_RD_ADDR_gio_rw_pa_byte0_dout 12
110#define REG_WR_ADDR_gio_rw_pa_byte0_dout 12
111
112/* Register rw_pa_byte0_oe, scope gio, type rw */
113typedef struct {
114 unsigned int oe : 8;
115 unsigned int dummy1 : 24;
116} reg_gio_rw_pa_byte0_oe;
117#define REG_RD_ADDR_gio_rw_pa_byte0_oe 16
118#define REG_WR_ADDR_gio_rw_pa_byte0_oe 16
119
120/* Register rw_pa_byte1_dout, scope gio, type rw */
121typedef struct {
122 unsigned int data : 8;
123 unsigned int dummy1 : 24;
124} reg_gio_rw_pa_byte1_dout;
125#define REG_RD_ADDR_gio_rw_pa_byte1_dout 20
126#define REG_WR_ADDR_gio_rw_pa_byte1_dout 20
127
128/* Register rw_pa_byte1_oe, scope gio, type rw */
129typedef struct {
130 unsigned int oe : 8;
131 unsigned int dummy1 : 24;
132} reg_gio_rw_pa_byte1_oe;
133#define REG_RD_ADDR_gio_rw_pa_byte1_oe 24
134#define REG_WR_ADDR_gio_rw_pa_byte1_oe 24
135
136/* Register rw_pa_byte2_dout, scope gio, type rw */
137typedef struct {
138 unsigned int data : 8;
139 unsigned int dummy1 : 24;
140} reg_gio_rw_pa_byte2_dout;
141#define REG_RD_ADDR_gio_rw_pa_byte2_dout 28
142#define REG_WR_ADDR_gio_rw_pa_byte2_dout 28
143
144/* Register rw_pa_byte2_oe, scope gio, type rw */
145typedef struct {
146 unsigned int oe : 8;
147 unsigned int dummy1 : 24;
148} reg_gio_rw_pa_byte2_oe;
149#define REG_RD_ADDR_gio_rw_pa_byte2_oe 32
150#define REG_WR_ADDR_gio_rw_pa_byte2_oe 32
151
152/* Register rw_pa_byte3_dout, scope gio, type rw */
153typedef struct {
154 unsigned int data : 8;
155 unsigned int dummy1 : 24;
156} reg_gio_rw_pa_byte3_dout;
157#define REG_RD_ADDR_gio_rw_pa_byte3_dout 36
158#define REG_WR_ADDR_gio_rw_pa_byte3_dout 36
159
160/* Register rw_pa_byte3_oe, scope gio, type rw */
161typedef struct {
162 unsigned int oe : 8;
163 unsigned int dummy1 : 24;
164} reg_gio_rw_pa_byte3_oe;
165#define REG_RD_ADDR_gio_rw_pa_byte3_oe 40
166#define REG_WR_ADDR_gio_rw_pa_byte3_oe 40
167
168/* Register r_pb_din, scope gio, type r */
169typedef struct {
170 unsigned int data : 32;
171} reg_gio_r_pb_din;
172#define REG_RD_ADDR_gio_r_pb_din 44
173
174/* Register rw_pb_dout, scope gio, type rw */
175typedef struct {
176 unsigned int data : 32;
177} reg_gio_rw_pb_dout;
178#define REG_RD_ADDR_gio_rw_pb_dout 48
179#define REG_WR_ADDR_gio_rw_pb_dout 48
180
181/* Register rw_pb_oe, scope gio, type rw */
182typedef struct {
183 unsigned int oe : 32;
184} reg_gio_rw_pb_oe;
185#define REG_RD_ADDR_gio_rw_pb_oe 52
186#define REG_WR_ADDR_gio_rw_pb_oe 52
187
188/* Register rw_pb_byte0_dout, scope gio, type rw */
189typedef struct {
190 unsigned int data : 8;
191 unsigned int dummy1 : 24;
192} reg_gio_rw_pb_byte0_dout;
193#define REG_RD_ADDR_gio_rw_pb_byte0_dout 56
194#define REG_WR_ADDR_gio_rw_pb_byte0_dout 56
195
196/* Register rw_pb_byte0_oe, scope gio, type rw */
197typedef struct {
198 unsigned int oe : 8;
199 unsigned int dummy1 : 24;
200} reg_gio_rw_pb_byte0_oe;
201#define REG_RD_ADDR_gio_rw_pb_byte0_oe 60
202#define REG_WR_ADDR_gio_rw_pb_byte0_oe 60
203
204/* Register rw_pb_byte1_dout, scope gio, type rw */
205typedef struct {
206 unsigned int data : 8;
207 unsigned int dummy1 : 24;
208} reg_gio_rw_pb_byte1_dout;
209#define REG_RD_ADDR_gio_rw_pb_byte1_dout 64
210#define REG_WR_ADDR_gio_rw_pb_byte1_dout 64
211
212/* Register rw_pb_byte1_oe, scope gio, type rw */
213typedef struct {
214 unsigned int oe : 8;
215 unsigned int dummy1 : 24;
216} reg_gio_rw_pb_byte1_oe;
217#define REG_RD_ADDR_gio_rw_pb_byte1_oe 68
218#define REG_WR_ADDR_gio_rw_pb_byte1_oe 68
219
220/* Register rw_pb_byte2_dout, scope gio, type rw */
221typedef struct {
222 unsigned int data : 8;
223 unsigned int dummy1 : 24;
224} reg_gio_rw_pb_byte2_dout;
225#define REG_RD_ADDR_gio_rw_pb_byte2_dout 72
226#define REG_WR_ADDR_gio_rw_pb_byte2_dout 72
227
228/* Register rw_pb_byte2_oe, scope gio, type rw */
229typedef struct {
230 unsigned int oe : 8;
231 unsigned int dummy1 : 24;
232} reg_gio_rw_pb_byte2_oe;
233#define REG_RD_ADDR_gio_rw_pb_byte2_oe 76
234#define REG_WR_ADDR_gio_rw_pb_byte2_oe 76
235
236/* Register rw_pb_byte3_dout, scope gio, type rw */
237typedef struct {
238 unsigned int data : 8;
239 unsigned int dummy1 : 24;
240} reg_gio_rw_pb_byte3_dout;
241#define REG_RD_ADDR_gio_rw_pb_byte3_dout 80
242#define REG_WR_ADDR_gio_rw_pb_byte3_dout 80
243
244/* Register rw_pb_byte3_oe, scope gio, type rw */
245typedef struct {
246 unsigned int oe : 8;
247 unsigned int dummy1 : 24;
248} reg_gio_rw_pb_byte3_oe;
249#define REG_RD_ADDR_gio_rw_pb_byte3_oe 84
250#define REG_WR_ADDR_gio_rw_pb_byte3_oe 84
251
252/* Register r_pc_din, scope gio, type r */
253typedef struct {
254 unsigned int data : 16;
255 unsigned int dummy1 : 16;
256} reg_gio_r_pc_din;
257#define REG_RD_ADDR_gio_r_pc_din 88
258
259/* Register rw_pc_dout, scope gio, type rw */
260typedef struct {
261 unsigned int data : 16;
262 unsigned int dummy1 : 16;
263} reg_gio_rw_pc_dout;
264#define REG_RD_ADDR_gio_rw_pc_dout 92
265#define REG_WR_ADDR_gio_rw_pc_dout 92
266
267/* Register rw_pc_oe, scope gio, type rw */
268typedef struct {
269 unsigned int oe : 16;
270 unsigned int dummy1 : 16;
271} reg_gio_rw_pc_oe;
272#define REG_RD_ADDR_gio_rw_pc_oe 96
273#define REG_WR_ADDR_gio_rw_pc_oe 96
274
275/* Register rw_pc_byte0_dout, scope gio, type rw */
276typedef struct {
277 unsigned int data : 8;
278 unsigned int dummy1 : 24;
279} reg_gio_rw_pc_byte0_dout;
280#define REG_RD_ADDR_gio_rw_pc_byte0_dout 100
281#define REG_WR_ADDR_gio_rw_pc_byte0_dout 100
282
283/* Register rw_pc_byte0_oe, scope gio, type rw */
284typedef struct {
285 unsigned int oe : 8;
286 unsigned int dummy1 : 24;
287} reg_gio_rw_pc_byte0_oe;
288#define REG_RD_ADDR_gio_rw_pc_byte0_oe 104
289#define REG_WR_ADDR_gio_rw_pc_byte0_oe 104
290
291/* Register rw_pc_byte1_dout, scope gio, type rw */
292typedef struct {
293 unsigned int data : 8;
294 unsigned int dummy1 : 24;
295} reg_gio_rw_pc_byte1_dout;
296#define REG_RD_ADDR_gio_rw_pc_byte1_dout 108
297#define REG_WR_ADDR_gio_rw_pc_byte1_dout 108
298
299/* Register rw_pc_byte1_oe, scope gio, type rw */
300typedef struct {
301 unsigned int oe : 8;
302 unsigned int dummy1 : 24;
303} reg_gio_rw_pc_byte1_oe;
304#define REG_RD_ADDR_gio_rw_pc_byte1_oe 112
305#define REG_WR_ADDR_gio_rw_pc_byte1_oe 112
306
307/* Register r_pd_din, scope gio, type r */
308typedef struct {
309 unsigned int data : 32;
310} reg_gio_r_pd_din;
311#define REG_RD_ADDR_gio_r_pd_din 116
312
313/* Register rw_intr_cfg, scope gio, type rw */
314typedef struct {
315 unsigned int intr0 : 3;
316 unsigned int intr1 : 3;
317 unsigned int intr2 : 3;
318 unsigned int intr3 : 3;
319 unsigned int intr4 : 3;
320 unsigned int intr5 : 3;
321 unsigned int intr6 : 3;
322 unsigned int intr7 : 3;
323 unsigned int dummy1 : 8;
324} reg_gio_rw_intr_cfg;
325#define REG_RD_ADDR_gio_rw_intr_cfg 120
326#define REG_WR_ADDR_gio_rw_intr_cfg 120
327
328/* Register rw_intr_pins, scope gio, type rw */
329typedef struct {
330 unsigned int intr0 : 4;
331 unsigned int intr1 : 4;
332 unsigned int intr2 : 4;
333 unsigned int intr3 : 4;
334 unsigned int intr4 : 4;
335 unsigned int intr5 : 4;
336 unsigned int intr6 : 4;
337 unsigned int intr7 : 4;
338} reg_gio_rw_intr_pins;
339#define REG_RD_ADDR_gio_rw_intr_pins 124
340#define REG_WR_ADDR_gio_rw_intr_pins 124
341
342/* Register rw_intr_mask, scope gio, type rw */
343typedef struct {
344 unsigned int intr0 : 1;
345 unsigned int intr1 : 1;
346 unsigned int intr2 : 1;
347 unsigned int intr3 : 1;
348 unsigned int intr4 : 1;
349 unsigned int intr5 : 1;
350 unsigned int intr6 : 1;
351 unsigned int intr7 : 1;
352 unsigned int i2c0_done : 1;
353 unsigned int i2c1_done : 1;
354 unsigned int dummy1 : 22;
355} reg_gio_rw_intr_mask;
356#define REG_RD_ADDR_gio_rw_intr_mask 128
357#define REG_WR_ADDR_gio_rw_intr_mask 128
358
359/* Register rw_ack_intr, scope gio, type rw */
360typedef struct {
361 unsigned int intr0 : 1;
362 unsigned int intr1 : 1;
363 unsigned int intr2 : 1;
364 unsigned int intr3 : 1;
365 unsigned int intr4 : 1;
366 unsigned int intr5 : 1;
367 unsigned int intr6 : 1;
368 unsigned int intr7 : 1;
369 unsigned int i2c0_done : 1;
370 unsigned int i2c1_done : 1;
371 unsigned int dummy1 : 22;
372} reg_gio_rw_ack_intr;
373#define REG_RD_ADDR_gio_rw_ack_intr 132
374#define REG_WR_ADDR_gio_rw_ack_intr 132
375
376/* Register r_intr, scope gio, type r */
377typedef struct {
378 unsigned int intr0 : 1;
379 unsigned int intr1 : 1;
380 unsigned int intr2 : 1;
381 unsigned int intr3 : 1;
382 unsigned int intr4 : 1;
383 unsigned int intr5 : 1;
384 unsigned int intr6 : 1;
385 unsigned int intr7 : 1;
386 unsigned int i2c0_done : 1;
387 unsigned int i2c1_done : 1;
388 unsigned int dummy1 : 22;
389} reg_gio_r_intr;
390#define REG_RD_ADDR_gio_r_intr 136
391
392/* Register r_masked_intr, scope gio, type r */
393typedef struct {
394 unsigned int intr0 : 1;
395 unsigned int intr1 : 1;
396 unsigned int intr2 : 1;
397 unsigned int intr3 : 1;
398 unsigned int intr4 : 1;
399 unsigned int intr5 : 1;
400 unsigned int intr6 : 1;
401 unsigned int intr7 : 1;
402 unsigned int i2c0_done : 1;
403 unsigned int i2c1_done : 1;
404 unsigned int dummy1 : 22;
405} reg_gio_r_masked_intr;
406#define REG_RD_ADDR_gio_r_masked_intr 140
407
408/* Register rw_i2c0_start, scope gio, type rw */
409typedef struct {
410 unsigned int run : 1;
411 unsigned int dummy1 : 31;
412} reg_gio_rw_i2c0_start;
413#define REG_RD_ADDR_gio_rw_i2c0_start 144
414#define REG_WR_ADDR_gio_rw_i2c0_start 144
415
416/* Register rw_i2c0_cfg, scope gio, type rw */
417typedef struct {
418 unsigned int en : 1;
419 unsigned int bit_order : 1;
420 unsigned int scl_io : 1;
421 unsigned int scl_inv : 1;
422 unsigned int sda_io : 1;
423 unsigned int sda_idle : 1;
424 unsigned int dummy1 : 26;
425} reg_gio_rw_i2c0_cfg;
426#define REG_RD_ADDR_gio_rw_i2c0_cfg 148
427#define REG_WR_ADDR_gio_rw_i2c0_cfg 148
428
429/* Register rw_i2c0_ctrl, scope gio, type rw */
430typedef struct {
431 unsigned int trf_bits : 6;
432 unsigned int switch_dir : 6;
433 unsigned int extra_start : 3;
434 unsigned int early_end : 1;
435 unsigned int start_stop : 1;
436 unsigned int ack_dir0 : 1;
437 unsigned int ack_dir1 : 1;
438 unsigned int ack_dir2 : 1;
439 unsigned int ack_dir3 : 1;
440 unsigned int ack_dir4 : 1;
441 unsigned int ack_dir5 : 1;
442 unsigned int ack_bit : 1;
443 unsigned int start_bit : 1;
444 unsigned int freq : 2;
445 unsigned int dummy1 : 5;
446} reg_gio_rw_i2c0_ctrl;
447#define REG_RD_ADDR_gio_rw_i2c0_ctrl 152
448#define REG_WR_ADDR_gio_rw_i2c0_ctrl 152
449
450/* Register rw_i2c0_data, scope gio, type rw */
451typedef struct {
452 unsigned int data0 : 8;
453 unsigned int data1 : 8;
454 unsigned int data2 : 8;
455 unsigned int data3 : 8;
456} reg_gio_rw_i2c0_data;
457#define REG_RD_ADDR_gio_rw_i2c0_data 156
458#define REG_WR_ADDR_gio_rw_i2c0_data 156
459
460/* Register rw_i2c0_data2, scope gio, type rw */
461typedef struct {
462 unsigned int data4 : 8;
463 unsigned int data5 : 8;
464 unsigned int start_val : 6;
465 unsigned int ack_val : 6;
466 unsigned int dummy1 : 4;
467} reg_gio_rw_i2c0_data2;
468#define REG_RD_ADDR_gio_rw_i2c0_data2 160
469#define REG_WR_ADDR_gio_rw_i2c0_data2 160
470
471/* Register rw_i2c1_start, scope gio, type rw */
472typedef struct {
473 unsigned int run : 1;
474 unsigned int dummy1 : 31;
475} reg_gio_rw_i2c1_start;
476#define REG_RD_ADDR_gio_rw_i2c1_start 164
477#define REG_WR_ADDR_gio_rw_i2c1_start 164
478
479/* Register rw_i2c1_cfg, scope gio, type rw */
480typedef struct {
481 unsigned int en : 1;
482 unsigned int bit_order : 1;
483 unsigned int scl_io : 1;
484 unsigned int scl_inv : 1;
485 unsigned int sda0_io : 1;
486 unsigned int sda0_idle : 1;
487 unsigned int sda1_io : 1;
488 unsigned int sda1_idle : 1;
489 unsigned int sda2_io : 1;
490 unsigned int sda2_idle : 1;
491 unsigned int sda3_io : 1;
492 unsigned int sda3_idle : 1;
493 unsigned int sda_sel : 2;
494 unsigned int sen_idle : 1;
495 unsigned int sen_inv : 1;
496 unsigned int sen_sel : 2;
497 unsigned int dummy1 : 14;
498} reg_gio_rw_i2c1_cfg;
499#define REG_RD_ADDR_gio_rw_i2c1_cfg 168
500#define REG_WR_ADDR_gio_rw_i2c1_cfg 168
501
502/* Register rw_i2c1_ctrl, scope gio, type rw */
503typedef struct {
504 unsigned int trf_bits : 6;
505 unsigned int switch_dir : 6;
506 unsigned int extra_start : 3;
507 unsigned int early_end : 1;
508 unsigned int start_stop : 1;
509 unsigned int ack_dir0 : 1;
510 unsigned int ack_dir1 : 1;
511 unsigned int ack_dir2 : 1;
512 unsigned int ack_dir3 : 1;
513 unsigned int ack_dir4 : 1;
514 unsigned int ack_dir5 : 1;
515 unsigned int ack_bit : 1;
516 unsigned int start_bit : 1;
517 unsigned int freq : 2;
518 unsigned int dummy1 : 5;
519} reg_gio_rw_i2c1_ctrl;
520#define REG_RD_ADDR_gio_rw_i2c1_ctrl 172
521#define REG_WR_ADDR_gio_rw_i2c1_ctrl 172
522
523/* Register rw_i2c1_data, scope gio, type rw */
524typedef struct {
525 unsigned int data0 : 8;
526 unsigned int data1 : 8;
527 unsigned int data2 : 8;
528 unsigned int data3 : 8;
529} reg_gio_rw_i2c1_data;
530#define REG_RD_ADDR_gio_rw_i2c1_data 176
531#define REG_WR_ADDR_gio_rw_i2c1_data 176
532
533/* Register rw_i2c1_data2, scope gio, type rw */
534typedef struct {
535 unsigned int data4 : 8;
536 unsigned int data5 : 8;
537 unsigned int start_val : 6;
538 unsigned int ack_val : 6;
539 unsigned int dummy1 : 4;
540} reg_gio_rw_i2c1_data2;
541#define REG_RD_ADDR_gio_rw_i2c1_data2 180
542#define REG_WR_ADDR_gio_rw_i2c1_data2 180
543
544/* Register r_ppwm_stat, scope gio, type r */
545typedef struct {
546 unsigned int freq : 2;
547 unsigned int dummy1 : 30;
548} reg_gio_r_ppwm_stat;
549#define REG_RD_ADDR_gio_r_ppwm_stat 184
550
551/* Register rw_ppwm_data, scope gio, type rw */
552typedef struct {
553 unsigned int data : 8;
554 unsigned int dummy1 : 24;
555} reg_gio_rw_ppwm_data;
556#define REG_RD_ADDR_gio_rw_ppwm_data 188
557#define REG_WR_ADDR_gio_rw_ppwm_data 188
558
559/* Register rw_pwm0_ctrl, scope gio, type rw */
560typedef struct {
561 unsigned int mode : 2;
562 unsigned int ccd_override : 1;
563 unsigned int ccd_val : 1;
564 unsigned int dummy1 : 28;
565} reg_gio_rw_pwm0_ctrl;
566#define REG_RD_ADDR_gio_rw_pwm0_ctrl 192
567#define REG_WR_ADDR_gio_rw_pwm0_ctrl 192
568
569/* Register rw_pwm0_var, scope gio, type rw */
570typedef struct {
571 unsigned int lo : 13;
572 unsigned int hi : 13;
573 unsigned int dummy1 : 6;
574} reg_gio_rw_pwm0_var;
575#define REG_RD_ADDR_gio_rw_pwm0_var 196
576#define REG_WR_ADDR_gio_rw_pwm0_var 196
577
578/* Register rw_pwm0_data, scope gio, type rw */
579typedef struct {
580 unsigned int data : 8;
581 unsigned int dummy1 : 24;
582} reg_gio_rw_pwm0_data;
583#define REG_RD_ADDR_gio_rw_pwm0_data 200
584#define REG_WR_ADDR_gio_rw_pwm0_data 200
585
586/* Register rw_pwm1_ctrl, scope gio, type rw */
587typedef struct {
588 unsigned int mode : 2;
589 unsigned int ccd_override : 1;
590 unsigned int ccd_val : 1;
591 unsigned int dummy1 : 28;
592} reg_gio_rw_pwm1_ctrl;
593#define REG_RD_ADDR_gio_rw_pwm1_ctrl 204
594#define REG_WR_ADDR_gio_rw_pwm1_ctrl 204
595
596/* Register rw_pwm1_var, scope gio, type rw */
597typedef struct {
598 unsigned int lo : 13;
599 unsigned int hi : 13;
600 unsigned int dummy1 : 6;
601} reg_gio_rw_pwm1_var;
602#define REG_RD_ADDR_gio_rw_pwm1_var 208
603#define REG_WR_ADDR_gio_rw_pwm1_var 208
604
605/* Register rw_pwm1_data, scope gio, type rw */
606typedef struct {
607 unsigned int data : 8;
608 unsigned int dummy1 : 24;
609} reg_gio_rw_pwm1_data;
610#define REG_RD_ADDR_gio_rw_pwm1_data 212
611#define REG_WR_ADDR_gio_rw_pwm1_data 212
612
613/* Register rw_pwm2_ctrl, scope gio, type rw */
614typedef struct {
615 unsigned int mode : 2;
616 unsigned int ccd_override : 1;
617 unsigned int ccd_val : 1;
618 unsigned int dummy1 : 28;
619} reg_gio_rw_pwm2_ctrl;
620#define REG_RD_ADDR_gio_rw_pwm2_ctrl 216
621#define REG_WR_ADDR_gio_rw_pwm2_ctrl 216
622
623/* Register rw_pwm2_var, scope gio, type rw */
624typedef struct {
625 unsigned int lo : 13;
626 unsigned int hi : 13;
627 unsigned int dummy1 : 6;
628} reg_gio_rw_pwm2_var;
629#define REG_RD_ADDR_gio_rw_pwm2_var 220
630#define REG_WR_ADDR_gio_rw_pwm2_var 220
631
632/* Register rw_pwm2_data, scope gio, type rw */
633typedef struct {
634 unsigned int data : 8;
635 unsigned int dummy1 : 24;
636} reg_gio_rw_pwm2_data;
637#define REG_RD_ADDR_gio_rw_pwm2_data 224
638#define REG_WR_ADDR_gio_rw_pwm2_data 224
639
640/* Register rw_pwm_in_cfg, scope gio, type rw */
641typedef struct {
642 unsigned int pin : 3;
643 unsigned int dummy1 : 29;
644} reg_gio_rw_pwm_in_cfg;
645#define REG_RD_ADDR_gio_rw_pwm_in_cfg 228
646#define REG_WR_ADDR_gio_rw_pwm_in_cfg 228
647
648/* Register r_pwm_in_lo, scope gio, type r */
649typedef struct {
650 unsigned int data : 32;
651} reg_gio_r_pwm_in_lo;
652#define REG_RD_ADDR_gio_r_pwm_in_lo 232
653
654/* Register r_pwm_in_hi, scope gio, type r */
655typedef struct {
656 unsigned int data : 32;
657} reg_gio_r_pwm_in_hi;
658#define REG_RD_ADDR_gio_r_pwm_in_hi 236
659
660/* Register r_pwm_in_cnt, scope gio, type r */
661typedef struct {
662 unsigned int data : 32;
663} reg_gio_r_pwm_in_cnt;
664#define REG_RD_ADDR_gio_r_pwm_in_cnt 240
665
666
667/* Constants */
668enum {
669 regk_gio_anyedge = 0x00000007,
670 regk_gio_f100k = 0x00000000,
671 regk_gio_f1562 = 0x00000000,
672 regk_gio_f195 = 0x00000003,
673 regk_gio_f1m = 0x00000002,
674 regk_gio_f390 = 0x00000002,
675 regk_gio_f400k = 0x00000001,
676 regk_gio_f5m = 0x00000003,
677 regk_gio_f781 = 0x00000001,
678 regk_gio_hi = 0x00000001,
679 regk_gio_in = 0x00000000,
680 regk_gio_intr_pa0 = 0x00000000,
681 regk_gio_intr_pa1 = 0x00000000,
682 regk_gio_intr_pa10 = 0x00000001,
683 regk_gio_intr_pa11 = 0x00000001,
684 regk_gio_intr_pa12 = 0x00000001,
685 regk_gio_intr_pa13 = 0x00000001,
686 regk_gio_intr_pa14 = 0x00000001,
687 regk_gio_intr_pa15 = 0x00000001,
688 regk_gio_intr_pa16 = 0x00000002,
689 regk_gio_intr_pa17 = 0x00000002,
690 regk_gio_intr_pa18 = 0x00000002,
691 regk_gio_intr_pa19 = 0x00000002,
692 regk_gio_intr_pa2 = 0x00000000,
693 regk_gio_intr_pa20 = 0x00000002,
694 regk_gio_intr_pa21 = 0x00000002,
695 regk_gio_intr_pa22 = 0x00000002,
696 regk_gio_intr_pa23 = 0x00000002,
697 regk_gio_intr_pa24 = 0x00000003,
698 regk_gio_intr_pa25 = 0x00000003,
699 regk_gio_intr_pa26 = 0x00000003,
700 regk_gio_intr_pa27 = 0x00000003,
701 regk_gio_intr_pa28 = 0x00000003,
702 regk_gio_intr_pa29 = 0x00000003,
703 regk_gio_intr_pa3 = 0x00000000,
704 regk_gio_intr_pa30 = 0x00000003,
705 regk_gio_intr_pa31 = 0x00000003,
706 regk_gio_intr_pa4 = 0x00000000,
707 regk_gio_intr_pa5 = 0x00000000,
708 regk_gio_intr_pa6 = 0x00000000,
709 regk_gio_intr_pa7 = 0x00000000,
710 regk_gio_intr_pa8 = 0x00000001,
711 regk_gio_intr_pa9 = 0x00000001,
712 regk_gio_intr_pb0 = 0x00000004,
713 regk_gio_intr_pb1 = 0x00000004,
714 regk_gio_intr_pb10 = 0x00000005,
715 regk_gio_intr_pb11 = 0x00000005,
716 regk_gio_intr_pb12 = 0x00000005,
717 regk_gio_intr_pb13 = 0x00000005,
718 regk_gio_intr_pb14 = 0x00000005,
719 regk_gio_intr_pb15 = 0x00000005,
720 regk_gio_intr_pb16 = 0x00000006,
721 regk_gio_intr_pb17 = 0x00000006,
722 regk_gio_intr_pb18 = 0x00000006,
723 regk_gio_intr_pb19 = 0x00000006,
724 regk_gio_intr_pb2 = 0x00000004,
725 regk_gio_intr_pb20 = 0x00000006,
726 regk_gio_intr_pb21 = 0x00000006,
727 regk_gio_intr_pb22 = 0x00000006,
728 regk_gio_intr_pb23 = 0x00000006,
729 regk_gio_intr_pb24 = 0x00000007,
730 regk_gio_intr_pb25 = 0x00000007,
731 regk_gio_intr_pb26 = 0x00000007,
732 regk_gio_intr_pb27 = 0x00000007,
733 regk_gio_intr_pb28 = 0x00000007,
734 regk_gio_intr_pb29 = 0x00000007,
735 regk_gio_intr_pb3 = 0x00000004,
736 regk_gio_intr_pb30 = 0x00000007,
737 regk_gio_intr_pb31 = 0x00000007,
738 regk_gio_intr_pb4 = 0x00000004,
739 regk_gio_intr_pb5 = 0x00000004,
740 regk_gio_intr_pb6 = 0x00000004,
741 regk_gio_intr_pb7 = 0x00000004,
742 regk_gio_intr_pb8 = 0x00000005,
743 regk_gio_intr_pb9 = 0x00000005,
744 regk_gio_intr_pc0 = 0x00000008,
745 regk_gio_intr_pc1 = 0x00000008,
746 regk_gio_intr_pc10 = 0x00000009,
747 regk_gio_intr_pc11 = 0x00000009,
748 regk_gio_intr_pc12 = 0x00000009,
749 regk_gio_intr_pc13 = 0x00000009,
750 regk_gio_intr_pc14 = 0x00000009,
751 regk_gio_intr_pc15 = 0x00000009,
752 regk_gio_intr_pc2 = 0x00000008,
753 regk_gio_intr_pc3 = 0x00000008,
754 regk_gio_intr_pc4 = 0x00000008,
755 regk_gio_intr_pc5 = 0x00000008,
756 regk_gio_intr_pc6 = 0x00000008,
757 regk_gio_intr_pc7 = 0x00000008,
758 regk_gio_intr_pc8 = 0x00000009,
759 regk_gio_intr_pc9 = 0x00000009,
760 regk_gio_intr_pd0 = 0x0000000c,
761 regk_gio_intr_pd1 = 0x0000000c,
762 regk_gio_intr_pd10 = 0x0000000d,
763 regk_gio_intr_pd11 = 0x0000000d,
764 regk_gio_intr_pd12 = 0x0000000d,
765 regk_gio_intr_pd13 = 0x0000000d,
766 regk_gio_intr_pd14 = 0x0000000d,
767 regk_gio_intr_pd15 = 0x0000000d,
768 regk_gio_intr_pd16 = 0x0000000e,
769 regk_gio_intr_pd17 = 0x0000000e,
770 regk_gio_intr_pd18 = 0x0000000e,
771 regk_gio_intr_pd19 = 0x0000000e,
772 regk_gio_intr_pd2 = 0x0000000c,
773 regk_gio_intr_pd20 = 0x0000000e,
774 regk_gio_intr_pd21 = 0x0000000e,
775 regk_gio_intr_pd22 = 0x0000000e,
776 regk_gio_intr_pd23 = 0x0000000e,
777 regk_gio_intr_pd24 = 0x0000000f,
778 regk_gio_intr_pd25 = 0x0000000f,
779 regk_gio_intr_pd26 = 0x0000000f,
780 regk_gio_intr_pd27 = 0x0000000f,
781 regk_gio_intr_pd28 = 0x0000000f,
782 regk_gio_intr_pd29 = 0x0000000f,
783 regk_gio_intr_pd3 = 0x0000000c,
784 regk_gio_intr_pd30 = 0x0000000f,
785 regk_gio_intr_pd31 = 0x0000000f,
786 regk_gio_intr_pd4 = 0x0000000c,
787 regk_gio_intr_pd5 = 0x0000000c,
788 regk_gio_intr_pd6 = 0x0000000c,
789 regk_gio_intr_pd7 = 0x0000000c,
790 regk_gio_intr_pd8 = 0x0000000d,
791 regk_gio_intr_pd9 = 0x0000000d,
792 regk_gio_lo = 0x00000002,
793 regk_gio_lsb = 0x00000000,
794 regk_gio_msb = 0x00000001,
795 regk_gio_negedge = 0x00000006,
796 regk_gio_no = 0x00000000,
797 regk_gio_no_switch = 0x0000003f,
798 regk_gio_none = 0x00000007,
799 regk_gio_off = 0x00000000,
800 regk_gio_opendrain = 0x00000000,
801 regk_gio_out = 0x00000001,
802 regk_gio_posedge = 0x00000005,
803 regk_gio_pwm_hfp = 0x00000002,
804 regk_gio_pwm_pa0 = 0x00000001,
805 regk_gio_pwm_pa19 = 0x00000004,
806 regk_gio_pwm_pa6 = 0x00000002,
807 regk_gio_pwm_pa7 = 0x00000003,
808 regk_gio_pwm_pb26 = 0x00000005,
809 regk_gio_pwm_pd23 = 0x00000006,
810 regk_gio_pwm_pd31 = 0x00000007,
811 regk_gio_pwm_std = 0x00000001,
812 regk_gio_pwm_var = 0x00000003,
813 regk_gio_rw_i2c0_cfg_default = 0x00000020,
814 regk_gio_rw_i2c0_ctrl_default = 0x00010000,
815 regk_gio_rw_i2c0_start_default = 0x00000000,
816 regk_gio_rw_i2c1_cfg_default = 0x00000aa0,
817 regk_gio_rw_i2c1_ctrl_default = 0x00010000,
818 regk_gio_rw_i2c1_start_default = 0x00000000,
819 regk_gio_rw_intr_cfg_default = 0x00000000,
820 regk_gio_rw_intr_mask_default = 0x00000000,
821 regk_gio_rw_pa_oe_default = 0x00000000,
822 regk_gio_rw_pb_oe_default = 0x00000000,
823 regk_gio_rw_pc_oe_default = 0x00000000,
824 regk_gio_rw_ppwm_data_default = 0x00000000,
825 regk_gio_rw_pwm0_ctrl_default = 0x00000000,
826 regk_gio_rw_pwm1_ctrl_default = 0x00000000,
827 regk_gio_rw_pwm2_ctrl_default = 0x00000000,
828 regk_gio_rw_pwm_in_cfg_default = 0x00000000,
829 regk_gio_sda0 = 0x00000000,
830 regk_gio_sda1 = 0x00000001,
831 regk_gio_sda2 = 0x00000002,
832 regk_gio_sda3 = 0x00000003,
833 regk_gio_sen = 0x00000000,
834 regk_gio_set = 0x00000003,
835 regk_gio_yes = 0x00000001
836};
837#endif /* __gio_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect.h b/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect.h
new file mode 100644
index 000000000000..bea699aa480e
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect.h
@@ -0,0 +1,46 @@
1/* Interrupt vector numbers autogenerated by ../../../tools/rdesc/bin/rdes2intr
2 from intr_vect.r */
3
4#ifndef _INTR_VECT_R
5#define _INTR_VECT_R
6#define TIMER0_INTR_VECT 0x31
7#define TIMER1_INTR_VECT 0x32
8#define DMA0_INTR_VECT 0x33
9#define DMA1_INTR_VECT 0x34
10#define DMA2_INTR_VECT 0x35
11#define DMA3_INTR_VECT 0x36
12#define DMA4_INTR_VECT 0x37
13#define DMA5_INTR_VECT 0x38
14#define DMA6_INTR_VECT 0x39
15#define DMA7_INTR_VECT 0x3a
16#define DMA9_INTR_VECT 0x3b
17#define DMA11_INTR_VECT 0x3c
18#define GIO_INTR_VECT 0x3d
19#define IOP0_INTR_VECT 0x3e
20#define IOP1_INTR_VECT 0x3f
21#define SER0_INTR_VECT 0x40
22#define SER1_INTR_VECT 0x41
23#define SER2_INTR_VECT 0x42
24#define SER3_INTR_VECT 0x43
25#define SER4_INTR_VECT 0x44
26#define SSER_INTR_VECT 0x45
27#define STRDMA0_INTR_VECT 0x46
28#define STRDMA1_INTR_VECT 0x47
29#define STRDMA2_INTR_VECT 0x48
30#define STRDMA3_INTR_VECT 0x49
31#define STRDMA5_INTR_VECT 0x4a
32#define VIN_INTR_VECT 0x4b
33#define VOUT_INTR_VECT 0x4c
34#define JPEG_INTR_VECT 0x4d
35#define H264_INTR_VECT 0x4e
36#define HISTO_INTR_VECT 0x4f
37#define CCD_INTR_VECT 0x50
38#define ETH_INTR_VECT 0x51
39#define MEMARB_BAR_INTR_VECT 0x52
40#define MEMARB_FOO_INTR_VECT 0x53
41#define PIO_INTR_VECT 0x54
42#define SCLR_INTR_VECT 0x55
43#define SCLR_FIFO_INTR_VECT 0x56
44#define IPI_INTR_VECT 0x57
45#define NBR_INTR_VECT 0x58
46#endif
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect_defs.h
new file mode 100644
index 000000000000..b820f6347c74
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect_defs.h
@@ -0,0 +1,341 @@
1#ifndef __intr_vect_defs_h
2#define __intr_vect_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: intr_vect.r
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -outfile intr_vect_defs.h intr_vect.r
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13/* Main access macros */
14#ifndef REG_RD
15#define REG_RD( scope, inst, reg ) \
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
18#endif
19
20#ifndef REG_WR
21#define REG_WR( scope, inst, reg, val ) \
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
24#endif
25
26#ifndef REG_RD_VECT
27#define REG_RD_VECT( scope, inst, reg, index ) \
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
31#endif
32
33#ifndef REG_WR_VECT
34#define REG_WR_VECT( scope, inst, reg, index, val ) \
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
38#endif
39
40#ifndef REG_RD_INT
41#define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
43#endif
44
45#ifndef REG_WR_INT
46#define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
48#endif
49
50#ifndef REG_RD_INT_VECT
51#define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
53 (index) * STRIDE_##scope##_##reg )
54#endif
55
56#ifndef REG_WR_INT_VECT
57#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
59 (index) * STRIDE_##scope##_##reg, (val) )
60#endif
61
62#ifndef REG_TYPE_CONV
63#define REG_TYPE_CONV( type, orgtype, val ) \
64 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
65#endif
66
67#ifndef reg_page_size
68#define reg_page_size 8192
69#endif
70
71#ifndef REG_ADDR
72#define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
74#endif
75
76#ifndef REG_ADDR_VECT
77#define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
79 (index) * STRIDE_##scope##_##reg )
80#endif
81
82/* C-code for register scope intr_vect */
83
84
85#define STRIDE_intr_vect_rw_mask 4
86/* Register rw_mask0, scope intr_vect, type rw */
87typedef struct {
88 unsigned int timer0 : 1;
89 unsigned int timer1 : 1;
90 unsigned int dma0 : 1;
91 unsigned int dma1 : 1;
92 unsigned int dma2 : 1;
93 unsigned int dma3 : 1;
94 unsigned int dma4 : 1;
95 unsigned int dma5 : 1;
96 unsigned int dma6 : 1;
97 unsigned int dma7 : 1;
98 unsigned int dma9 : 1;
99 unsigned int dma11 : 1;
100 unsigned int gio : 1;
101 unsigned int iop0 : 1;
102 unsigned int iop1 : 1;
103 unsigned int ser0 : 1;
104 unsigned int ser1 : 1;
105 unsigned int ser2 : 1;
106 unsigned int ser3 : 1;
107 unsigned int ser4 : 1;
108 unsigned int sser : 1;
109 unsigned int strdma0 : 1;
110 unsigned int strdma1 : 1;
111 unsigned int strdma2 : 1;
112 unsigned int strdma3 : 1;
113 unsigned int strdma5 : 1;
114 unsigned int vin : 1;
115 unsigned int vout : 1;
116 unsigned int jpeg : 1;
117 unsigned int h264 : 1;
118 unsigned int histo : 1;
119 unsigned int ccd : 1;
120} reg_intr_vect_rw_mask0;
121#define reg_intr_vect_rw_mask reg_intr_vect_rw_mask0
122#define REG_RD_ADDR_intr_vect_rw_mask 0
123#define REG_WR_ADDR_intr_vect_rw_mask 0
124#define REG_RD_ADDR_intr_vect_rw_mask0 0
125#define REG_WR_ADDR_intr_vect_rw_mask0 0
126
127#define STRIDE_intr_vect_r_vect 4
128/* Register r_vect0, scope intr_vect, type r */
129typedef struct {
130 unsigned int timer0 : 1;
131 unsigned int timer1 : 1;
132 unsigned int dma0 : 1;
133 unsigned int dma1 : 1;
134 unsigned int dma2 : 1;
135 unsigned int dma3 : 1;
136 unsigned int dma4 : 1;
137 unsigned int dma5 : 1;
138 unsigned int dma6 : 1;
139 unsigned int dma7 : 1;
140 unsigned int dma9 : 1;
141 unsigned int dma11 : 1;
142 unsigned int gio : 1;
143 unsigned int iop0 : 1;
144 unsigned int iop1 : 1;
145 unsigned int ser0 : 1;
146 unsigned int ser1 : 1;
147 unsigned int ser2 : 1;
148 unsigned int ser3 : 1;
149 unsigned int ser4 : 1;
150 unsigned int sser : 1;
151 unsigned int strdma0 : 1;
152 unsigned int strdma1 : 1;
153 unsigned int strdma2 : 1;
154 unsigned int strdma3 : 1;
155 unsigned int strdma5 : 1;
156 unsigned int vin : 1;
157 unsigned int vout : 1;
158 unsigned int jpeg : 1;
159 unsigned int h264 : 1;
160 unsigned int histo : 1;
161 unsigned int ccd : 1;
162} reg_intr_vect_r_vect0;
163#define reg_intr_vect_r_vect reg_intr_vect_r_vect0
164#define REG_RD_ADDR_intr_vect_r_vect 8
165#define REG_RD_ADDR_intr_vect_r_vect0 8
166
167#define STRIDE_intr_vect_r_masked_vect 4
168/* Register r_masked_vect0, scope intr_vect, type r */
169typedef struct {
170 unsigned int timer0 : 1;
171 unsigned int timer1 : 1;
172 unsigned int dma0 : 1;
173 unsigned int dma1 : 1;
174 unsigned int dma2 : 1;
175 unsigned int dma3 : 1;
176 unsigned int dma4 : 1;
177 unsigned int dma5 : 1;
178 unsigned int dma6 : 1;
179 unsigned int dma7 : 1;
180 unsigned int dma9 : 1;
181 unsigned int dma11 : 1;
182 unsigned int gio : 1;
183 unsigned int iop0 : 1;
184 unsigned int iop1 : 1;
185 unsigned int ser0 : 1;
186 unsigned int ser1 : 1;
187 unsigned int ser2 : 1;
188 unsigned int ser3 : 1;
189 unsigned int ser4 : 1;
190 unsigned int sser : 1;
191 unsigned int strdma0 : 1;
192 unsigned int strdma1 : 1;
193 unsigned int strdma2 : 1;
194 unsigned int strdma3 : 1;
195 unsigned int strdma5 : 1;
196 unsigned int vin : 1;
197 unsigned int vout : 1;
198 unsigned int jpeg : 1;
199 unsigned int h264 : 1;
200 unsigned int histo : 1;
201 unsigned int ccd : 1;
202} reg_intr_vect_r_masked_vect0;
203#define reg_intr_vect_r_masked_vect reg_intr_masked_vect_r_vect0
204#define REG_RD_ADDR_intr_vect_r_masked_vect0 16
205#define REG_RD_ADDR_intr_vect_r_masked_vect 16
206
207#define STRIDE_intr_vect_rw_xmask 4
208/* Register rw_xmask0, scope intr_vect, type rw */
209typedef struct {
210 unsigned int timer0 : 1;
211 unsigned int timer1 : 1;
212 unsigned int dma0 : 1;
213 unsigned int dma1 : 1;
214 unsigned int dma2 : 1;
215 unsigned int dma3 : 1;
216 unsigned int dma4 : 1;
217 unsigned int dma5 : 1;
218 unsigned int dma6 : 1;
219 unsigned int dma7 : 1;
220 unsigned int dma9 : 1;
221 unsigned int dma11 : 1;
222 unsigned int gio : 1;
223 unsigned int iop0 : 1;
224 unsigned int iop1 : 1;
225 unsigned int ser0 : 1;
226 unsigned int ser1 : 1;
227 unsigned int ser2 : 1;
228 unsigned int ser3 : 1;
229 unsigned int ser4 : 1;
230 unsigned int sser : 1;
231 unsigned int strdma0 : 1;
232 unsigned int strdma1 : 1;
233 unsigned int strdma2 : 1;
234 unsigned int strdma3 : 1;
235 unsigned int strdma5 : 1;
236 unsigned int vin : 1;
237 unsigned int vout : 1;
238 unsigned int jpeg : 1;
239 unsigned int h264 : 1;
240 unsigned int histo : 1;
241 unsigned int ccd : 1;
242} reg_intr_vect_rw_xmask0;
243#define reg_intr_vect_rw_xmask reg_intr_vect_rw_xmask0
244#define REG_RD_ADDR_intr_vect_rw_xmask0 24
245#define REG_WR_ADDR_intr_vect_rw_xmask0 24
246#define REG_RD_ADDR_intr_vect_rw_xmask 24
247#define REG_WR_ADDR_intr_vect_rw_xmask 24
248
249/* Register rw_mask1, scope intr_vect, type rw */
250typedef struct {
251 unsigned int eth : 1;
252 unsigned int memarb_bar : 1;
253 unsigned int memarb_foo : 1;
254 unsigned int pio : 1;
255 unsigned int sclr : 1;
256 unsigned int sclr_fifo : 1;
257 unsigned int dummy1 : 26;
258} reg_intr_vect_rw_mask1;
259#define REG_RD_ADDR_intr_vect_rw_mask1 4
260#define REG_WR_ADDR_intr_vect_rw_mask1 4
261
262/* Register r_vect1, scope intr_vect, type r */
263typedef struct {
264 unsigned int eth : 1;
265 unsigned int memarb_bar : 1;
266 unsigned int memarb_foo : 1;
267 unsigned int pio : 1;
268 unsigned int sclr : 1;
269 unsigned int sclr_fifo : 1;
270 unsigned int dummy1 : 26;
271} reg_intr_vect_r_vect1;
272#define REG_RD_ADDR_intr_vect_r_vect1 12
273
274/* Register r_masked_vect1, scope intr_vect, type r */
275typedef struct {
276 unsigned int eth : 1;
277 unsigned int memarb_bar : 1;
278 unsigned int memarb_foo : 1;
279 unsigned int pio : 1;
280 unsigned int sclr : 1;
281 unsigned int sclr_fifo : 1;
282 unsigned int dummy1 : 26;
283} reg_intr_vect_r_masked_vect1;
284#define REG_RD_ADDR_intr_vect_r_masked_vect1 20
285
286/* Register rw_xmask1, scope intr_vect, type rw */
287typedef struct {
288 unsigned int eth : 1;
289 unsigned int memarb_bar : 1;
290 unsigned int memarb_foo : 1;
291 unsigned int pio : 1;
292 unsigned int sclr : 1;
293 unsigned int sclr_fifo : 1;
294 unsigned int dummy1 : 26;
295} reg_intr_vect_rw_xmask1;
296#define REG_RD_ADDR_intr_vect_rw_xmask1 28
297#define REG_WR_ADDR_intr_vect_rw_xmask1 28
298
299/* Register rw_xmask_ctrl, scope intr_vect, type rw */
300typedef struct {
301 unsigned int en : 1;
302 unsigned int dummy1 : 31;
303} reg_intr_vect_rw_xmask_ctrl;
304#define REG_RD_ADDR_intr_vect_rw_xmask_ctrl 32
305#define REG_WR_ADDR_intr_vect_rw_xmask_ctrl 32
306
307/* Register r_nmi, scope intr_vect, type r */
308typedef struct {
309 unsigned int watchdog0 : 1;
310 unsigned int watchdog1 : 1;
311 unsigned int dummy1 : 30;
312} reg_intr_vect_r_nmi;
313#define REG_RD_ADDR_intr_vect_r_nmi 64
314
315/* Register r_guru, scope intr_vect, type r */
316typedef struct {
317 unsigned int jtag : 1;
318 unsigned int dummy1 : 31;
319} reg_intr_vect_r_guru;
320#define REG_RD_ADDR_intr_vect_r_guru 68
321
322
323/* Register rw_ipi, scope intr_vect, type rw */
324typedef struct
325{
326 unsigned int vector;
327} reg_intr_vect_rw_ipi;
328#define REG_RD_ADDR_intr_vect_rw_ipi 72
329#define REG_WR_ADDR_intr_vect_rw_ipi 72
330
331/* Constants */
332enum {
333 regk_intr_vect_no = 0x00000000,
334 regk_intr_vect_rw_mask0_default = 0x00000000,
335 regk_intr_vect_rw_mask1_default = 0x00000000,
336 regk_intr_vect_rw_xmask0_default = 0x00000000,
337 regk_intr_vect_rw_xmask1_default = 0x00000000,
338 regk_intr_vect_rw_xmask_ctrl_default = 0x00000000,
339 regk_intr_vect_yes = 0x00000001
340};
341#endif /* __intr_vect_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_reg_space_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_reg_space_asm.h
new file mode 100644
index 000000000000..d75a74e90458
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_reg_space_asm.h
@@ -0,0 +1,31 @@
1/* Autogenerated Changes here will be lost!
2 * generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg
3 */
4#define iop_version 0
5#define iop_fifo_in_extra 64
6#define iop_fifo_out_extra 128
7#define iop_trigger_grp0 192
8#define iop_trigger_grp1 256
9#define iop_trigger_grp2 320
10#define iop_trigger_grp3 384
11#define iop_trigger_grp4 448
12#define iop_trigger_grp5 512
13#define iop_trigger_grp6 576
14#define iop_trigger_grp7 640
15#define iop_crc_par 768
16#define iop_dmc_in 896
17#define iop_dmc_out 1024
18#define iop_fifo_in 1152
19#define iop_fifo_out 1280
20#define iop_scrc_in 1408
21#define iop_scrc_out 1536
22#define iop_timer_grp0 1664
23#define iop_timer_grp1 1792
24#define iop_sap_in 2048
25#define iop_sap_out 2304
26#define iop_spu 2560
27#define iop_sw_cfg 2816
28#define iop_sw_cpu 3072
29#define iop_sw_mpu 3328
30#define iop_sw_spu 3584
31#define iop_mpu 4096
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_in_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_in_defs_asm.h
new file mode 100644
index 000000000000..7f90b5a0460d
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_in_defs_asm.h
@@ -0,0 +1,109 @@
1#ifndef __iop_sap_in_defs_asm_h
2#define __iop_sap_in_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: iop_sap_in.r
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_in_defs_asm.h iop_sap_in.r
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13
14#ifndef REG_FIELD
15#define REG_FIELD( scope, reg, field, value ) \
16 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
17#define REG_FIELD_X_( value, shift ) ((value) << shift)
18#endif
19
20#ifndef REG_STATE
21#define REG_STATE( scope, reg, field, symbolic_value ) \
22 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
23#define REG_STATE_X_( k, shift ) (k << shift)
24#endif
25
26#ifndef REG_MASK
27#define REG_MASK( scope, reg, field ) \
28 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
29#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
30#endif
31
32#ifndef REG_LSB
33#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
34#endif
35
36#ifndef REG_BIT
37#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
38#endif
39
40#ifndef REG_ADDR
41#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
42#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
43#endif
44
45#ifndef REG_ADDR_VECT
46#define REG_ADDR_VECT( scope, inst, reg, index ) \
47 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
48 STRIDE_##scope##_##reg )
49#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
50 ((inst) + offs + (index) * stride)
51#endif
52
53#define STRIDE_iop_sap_in_rw_bus_byte 4
54/* Register rw_bus_byte, scope iop_sap_in, type rw */
55#define reg_iop_sap_in_rw_bus_byte___sync_sel___lsb 0
56#define reg_iop_sap_in_rw_bus_byte___sync_sel___width 2
57#define reg_iop_sap_in_rw_bus_byte___sync_ext_src___lsb 2
58#define reg_iop_sap_in_rw_bus_byte___sync_ext_src___width 3
59#define reg_iop_sap_in_rw_bus_byte___sync_edge___lsb 5
60#define reg_iop_sap_in_rw_bus_byte___sync_edge___width 2
61#define reg_iop_sap_in_rw_bus_byte___delay___lsb 7
62#define reg_iop_sap_in_rw_bus_byte___delay___width 2
63#define reg_iop_sap_in_rw_bus_byte_offset 0
64
65#define STRIDE_iop_sap_in_rw_gio 4
66/* Register rw_gio, scope iop_sap_in, type rw */
67#define reg_iop_sap_in_rw_gio___sync_sel___lsb 0
68#define reg_iop_sap_in_rw_gio___sync_sel___width 2
69#define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2
70#define reg_iop_sap_in_rw_gio___sync_ext_src___width 3
71#define reg_iop_sap_in_rw_gio___sync_edge___lsb 5
72#define reg_iop_sap_in_rw_gio___sync_edge___width 2
73#define reg_iop_sap_in_rw_gio___delay___lsb 7
74#define reg_iop_sap_in_rw_gio___delay___width 2
75#define reg_iop_sap_in_rw_gio___logic___lsb 9
76#define reg_iop_sap_in_rw_gio___logic___width 2
77#define reg_iop_sap_in_rw_gio_offset 16
78
79
80/* Constants */
81#define regk_iop_sap_in_and 0x00000002
82#define regk_iop_sap_in_ext_clk200 0x00000003
83#define regk_iop_sap_in_gio0 0x00000000
84#define regk_iop_sap_in_gio12 0x00000003
85#define regk_iop_sap_in_gio16 0x00000004
86#define regk_iop_sap_in_gio20 0x00000005
87#define regk_iop_sap_in_gio24 0x00000006
88#define regk_iop_sap_in_gio28 0x00000007
89#define regk_iop_sap_in_gio4 0x00000001
90#define regk_iop_sap_in_gio8 0x00000002
91#define regk_iop_sap_in_inv 0x00000001
92#define regk_iop_sap_in_neg 0x00000002
93#define regk_iop_sap_in_no 0x00000000
94#define regk_iop_sap_in_no_del_ext_clk200 0x00000002
95#define regk_iop_sap_in_none 0x00000000
96#define regk_iop_sap_in_one 0x00000001
97#define regk_iop_sap_in_or 0x00000003
98#define regk_iop_sap_in_pos 0x00000001
99#define regk_iop_sap_in_pos_neg 0x00000003
100#define regk_iop_sap_in_rw_bus_byte_default 0x00000000
101#define regk_iop_sap_in_rw_bus_byte_size 0x00000004
102#define regk_iop_sap_in_rw_gio_default 0x00000000
103#define regk_iop_sap_in_rw_gio_size 0x00000020
104#define regk_iop_sap_in_timer_grp0_tmr3 0x00000000
105#define regk_iop_sap_in_timer_grp1_tmr3 0x00000001
106#define regk_iop_sap_in_tmr_clk200 0x00000001
107#define regk_iop_sap_in_two 0x00000002
108#define regk_iop_sap_in_two_clk200 0x00000000
109#endif /* __iop_sap_in_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_out_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_out_defs_asm.h
new file mode 100644
index 000000000000..399bd656406b
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_out_defs_asm.h
@@ -0,0 +1,276 @@
1#ifndef __iop_sap_out_defs_asm_h
2#define __iop_sap_out_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: iop_sap_out.r
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_out_defs_asm.h iop_sap_out.r
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13
14#ifndef REG_FIELD
15#define REG_FIELD( scope, reg, field, value ) \
16 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
17#define REG_FIELD_X_( value, shift ) ((value) << shift)
18#endif
19
20#ifndef REG_STATE
21#define REG_STATE( scope, reg, field, symbolic_value ) \
22 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
23#define REG_STATE_X_( k, shift ) (k << shift)
24#endif
25
26#ifndef REG_MASK
27#define REG_MASK( scope, reg, field ) \
28 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
29#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
30#endif
31
32#ifndef REG_LSB
33#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
34#endif
35
36#ifndef REG_BIT
37#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
38#endif
39
40#ifndef REG_ADDR
41#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
42#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
43#endif
44
45#ifndef REG_ADDR_VECT
46#define REG_ADDR_VECT( scope, inst, reg, index ) \
47 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
48 STRIDE_##scope##_##reg )
49#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
50 ((inst) + offs + (index) * stride)
51#endif
52
53/* Register rw_gen_gated, scope iop_sap_out, type rw */
54#define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0
55#define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2
56#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2
57#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2
58#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4
59#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3
60#define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7
61#define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2
62#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9
63#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2
64#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11
65#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3
66#define reg_iop_sap_out_rw_gen_gated_offset 0
67
68/* Register rw_bus, scope iop_sap_out, type rw */
69#define reg_iop_sap_out_rw_bus___byte0_clk_sel___lsb 0
70#define reg_iop_sap_out_rw_bus___byte0_clk_sel___width 2
71#define reg_iop_sap_out_rw_bus___byte0_clk_ext___lsb 2
72#define reg_iop_sap_out_rw_bus___byte0_clk_ext___width 2
73#define reg_iop_sap_out_rw_bus___byte0_gated_clk___lsb 4
74#define reg_iop_sap_out_rw_bus___byte0_gated_clk___width 1
75#define reg_iop_sap_out_rw_bus___byte0_gated_clk___bit 4
76#define reg_iop_sap_out_rw_bus___byte0_clk_inv___lsb 5
77#define reg_iop_sap_out_rw_bus___byte0_clk_inv___width 1
78#define reg_iop_sap_out_rw_bus___byte0_clk_inv___bit 5
79#define reg_iop_sap_out_rw_bus___byte0_delay___lsb 6
80#define reg_iop_sap_out_rw_bus___byte0_delay___width 1
81#define reg_iop_sap_out_rw_bus___byte0_delay___bit 6
82#define reg_iop_sap_out_rw_bus___byte1_clk_sel___lsb 7
83#define reg_iop_sap_out_rw_bus___byte1_clk_sel___width 2
84#define reg_iop_sap_out_rw_bus___byte1_clk_ext___lsb 9
85#define reg_iop_sap_out_rw_bus___byte1_clk_ext___width 2
86#define reg_iop_sap_out_rw_bus___byte1_gated_clk___lsb 11
87#define reg_iop_sap_out_rw_bus___byte1_gated_clk___width 1
88#define reg_iop_sap_out_rw_bus___byte1_gated_clk___bit 11
89#define reg_iop_sap_out_rw_bus___byte1_clk_inv___lsb 12
90#define reg_iop_sap_out_rw_bus___byte1_clk_inv___width 1
91#define reg_iop_sap_out_rw_bus___byte1_clk_inv___bit 12
92#define reg_iop_sap_out_rw_bus___byte1_delay___lsb 13
93#define reg_iop_sap_out_rw_bus___byte1_delay___width 1
94#define reg_iop_sap_out_rw_bus___byte1_delay___bit 13
95#define reg_iop_sap_out_rw_bus___byte2_clk_sel___lsb 14
96#define reg_iop_sap_out_rw_bus___byte2_clk_sel___width 2
97#define reg_iop_sap_out_rw_bus___byte2_clk_ext___lsb 16
98#define reg_iop_sap_out_rw_bus___byte2_clk_ext___width 2
99#define reg_iop_sap_out_rw_bus___byte2_gated_clk___lsb 18
100#define reg_iop_sap_out_rw_bus___byte2_gated_clk___width 1
101#define reg_iop_sap_out_rw_bus___byte2_gated_clk___bit 18
102#define reg_iop_sap_out_rw_bus___byte2_clk_inv___lsb 19
103#define reg_iop_sap_out_rw_bus___byte2_clk_inv___width 1
104#define reg_iop_sap_out_rw_bus___byte2_clk_inv___bit 19
105#define reg_iop_sap_out_rw_bus___byte2_delay___lsb 20
106#define reg_iop_sap_out_rw_bus___byte2_delay___width 1
107#define reg_iop_sap_out_rw_bus___byte2_delay___bit 20
108#define reg_iop_sap_out_rw_bus___byte3_clk_sel___lsb 21
109#define reg_iop_sap_out_rw_bus___byte3_clk_sel___width 2
110#define reg_iop_sap_out_rw_bus___byte3_clk_ext___lsb 23
111#define reg_iop_sap_out_rw_bus___byte3_clk_ext___width 2
112#define reg_iop_sap_out_rw_bus___byte3_gated_clk___lsb 25
113#define reg_iop_sap_out_rw_bus___byte3_gated_clk___width 1
114#define reg_iop_sap_out_rw_bus___byte3_gated_clk___bit 25
115#define reg_iop_sap_out_rw_bus___byte3_clk_inv___lsb 26
116#define reg_iop_sap_out_rw_bus___byte3_clk_inv___width 1
117#define reg_iop_sap_out_rw_bus___byte3_clk_inv___bit 26
118#define reg_iop_sap_out_rw_bus___byte3_delay___lsb 27
119#define reg_iop_sap_out_rw_bus___byte3_delay___width 1
120#define reg_iop_sap_out_rw_bus___byte3_delay___bit 27
121#define reg_iop_sap_out_rw_bus_offset 4
122
123/* Register rw_bus_lo_oe, scope iop_sap_out, type rw */
124#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___lsb 0
125#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___width 2
126#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___lsb 2
127#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___width 2
128#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___lsb 4
129#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___width 1
130#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___bit 4
131#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___lsb 5
132#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___width 1
133#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___bit 5
134#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___lsb 6
135#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___width 1
136#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___bit 6
137#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___lsb 7
138#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___width 2
139#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___lsb 9
140#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___width 2
141#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___lsb 11
142#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___width 2
143#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___lsb 13
144#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___width 2
145#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___lsb 15
146#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___width 1
147#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___bit 15
148#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___lsb 16
149#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___width 1
150#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___bit 16
151#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___lsb 17
152#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___width 1
153#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___bit 17
154#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___lsb 18
155#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___width 2
156#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___lsb 20
157#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___width 2
158#define reg_iop_sap_out_rw_bus_lo_oe_offset 8
159
160/* Register rw_bus_hi_oe, scope iop_sap_out, type rw */
161#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___lsb 0
162#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___width 2
163#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___lsb 2
164#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___width 2
165#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___lsb 4
166#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___width 1
167#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___bit 4
168#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___lsb 5
169#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___width 1
170#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___bit 5
171#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___lsb 6
172#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___width 1
173#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___bit 6
174#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___lsb 7
175#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___width 2
176#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___lsb 9
177#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___width 2
178#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___lsb 11
179#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___width 2
180#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___lsb 13
181#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___width 2
182#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___lsb 15
183#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___width 1
184#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___bit 15
185#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___lsb 16
186#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___width 1
187#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___bit 16
188#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___lsb 17
189#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___width 1
190#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___bit 17
191#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___lsb 18
192#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___width 2
193#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___lsb 20
194#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___width 2
195#define reg_iop_sap_out_rw_bus_hi_oe_offset 12
196
197#define STRIDE_iop_sap_out_rw_gio 4
198/* Register rw_gio, scope iop_sap_out, type rw */
199#define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0
200#define reg_iop_sap_out_rw_gio___out_clk_sel___width 3
201#define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3
202#define reg_iop_sap_out_rw_gio___out_clk_ext___width 2
203#define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 5
204#define reg_iop_sap_out_rw_gio___out_gated_clk___width 1
205#define reg_iop_sap_out_rw_gio___out_gated_clk___bit 5
206#define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 6
207#define reg_iop_sap_out_rw_gio___out_clk_inv___width 1
208#define reg_iop_sap_out_rw_gio___out_clk_inv___bit 6
209#define reg_iop_sap_out_rw_gio___out_delay___lsb 7
210#define reg_iop_sap_out_rw_gio___out_delay___width 1
211#define reg_iop_sap_out_rw_gio___out_delay___bit 7
212#define reg_iop_sap_out_rw_gio___out_logic___lsb 8
213#define reg_iop_sap_out_rw_gio___out_logic___width 2
214#define reg_iop_sap_out_rw_gio___out_logic_src___lsb 10
215#define reg_iop_sap_out_rw_gio___out_logic_src___width 2
216#define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 12
217#define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3
218#define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 15
219#define reg_iop_sap_out_rw_gio___oe_clk_ext___width 2
220#define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17
221#define reg_iop_sap_out_rw_gio___oe_gated_clk___width 1
222#define reg_iop_sap_out_rw_gio___oe_gated_clk___bit 17
223#define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 18
224#define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1
225#define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 18
226#define reg_iop_sap_out_rw_gio___oe_delay___lsb 19
227#define reg_iop_sap_out_rw_gio___oe_delay___width 1
228#define reg_iop_sap_out_rw_gio___oe_delay___bit 19
229#define reg_iop_sap_out_rw_gio___oe_logic___lsb 20
230#define reg_iop_sap_out_rw_gio___oe_logic___width 2
231#define reg_iop_sap_out_rw_gio___oe_logic_src___lsb 22
232#define reg_iop_sap_out_rw_gio___oe_logic_src___width 2
233#define reg_iop_sap_out_rw_gio_offset 16
234
235
236/* Constants */
237#define regk_iop_sap_out_always 0x00000001
238#define regk_iop_sap_out_and 0x00000002
239#define regk_iop_sap_out_clk0 0x00000000
240#define regk_iop_sap_out_clk1 0x00000001
241#define regk_iop_sap_out_clk12 0x00000004
242#define regk_iop_sap_out_clk200 0x00000000
243#define regk_iop_sap_out_ext 0x00000002
244#define regk_iop_sap_out_gated 0x00000003
245#define regk_iop_sap_out_gio0 0x00000000
246#define regk_iop_sap_out_gio1 0x00000000
247#define regk_iop_sap_out_gio16 0x00000002
248#define regk_iop_sap_out_gio17 0x00000002
249#define regk_iop_sap_out_gio24 0x00000003
250#define regk_iop_sap_out_gio25 0x00000003
251#define regk_iop_sap_out_gio8 0x00000001
252#define regk_iop_sap_out_gio9 0x00000001
253#define regk_iop_sap_out_gio_out10 0x00000005
254#define regk_iop_sap_out_gio_out18 0x00000006
255#define regk_iop_sap_out_gio_out2 0x00000004
256#define regk_iop_sap_out_gio_out26 0x00000007
257#define regk_iop_sap_out_inv 0x00000001
258#define regk_iop_sap_out_nand 0x00000003
259#define regk_iop_sap_out_no 0x00000000
260#define regk_iop_sap_out_none 0x00000000
261#define regk_iop_sap_out_one 0x00000001
262#define regk_iop_sap_out_rw_bus_default 0x00000000
263#define regk_iop_sap_out_rw_bus_hi_oe_default 0x00000000
264#define regk_iop_sap_out_rw_bus_lo_oe_default 0x00000000
265#define regk_iop_sap_out_rw_gen_gated_default 0x00000000
266#define regk_iop_sap_out_rw_gio_default 0x00000000
267#define regk_iop_sap_out_rw_gio_size 0x00000020
268#define regk_iop_sap_out_spu_gio6 0x00000002
269#define regk_iop_sap_out_spu_gio7 0x00000003
270#define regk_iop_sap_out_timer_grp0_tmr2 0x00000000
271#define regk_iop_sap_out_timer_grp0_tmr3 0x00000001
272#define regk_iop_sap_out_timer_grp1_tmr2 0x00000002
273#define regk_iop_sap_out_timer_grp1_tmr3 0x00000003
274#define regk_iop_sap_out_tmr200 0x00000001
275#define regk_iop_sap_out_yes 0x00000001
276#endif /* __iop_sap_out_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cfg_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cfg_defs_asm.h
new file mode 100644
index 000000000000..3b3949b51a66
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cfg_defs_asm.h
@@ -0,0 +1,739 @@
1#ifndef __iop_sw_cfg_defs_asm_h
2#define __iop_sw_cfg_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: iop_sw_cfg.r
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cfg_defs_asm.h iop_sw_cfg.r
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13
14#ifndef REG_FIELD
15#define REG_FIELD( scope, reg, field, value ) \
16 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
17#define REG_FIELD_X_( value, shift ) ((value) << shift)
18#endif
19
20#ifndef REG_STATE
21#define REG_STATE( scope, reg, field, symbolic_value ) \
22 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
23#define REG_STATE_X_( k, shift ) (k << shift)
24#endif
25
26#ifndef REG_MASK
27#define REG_MASK( scope, reg, field ) \
28 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
29#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
30#endif
31
32#ifndef REG_LSB
33#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
34#endif
35
36#ifndef REG_BIT
37#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
38#endif
39
40#ifndef REG_ADDR
41#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
42#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
43#endif
44
45#ifndef REG_ADDR_VECT
46#define REG_ADDR_VECT( scope, inst, reg, index ) \
47 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
48 STRIDE_##scope##_##reg )
49#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
50 ((inst) + offs + (index) * stride)
51#endif
52
53/* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */
54#define reg_iop_sw_cfg_rw_crc_par_owner___cfg___lsb 0
55#define reg_iop_sw_cfg_rw_crc_par_owner___cfg___width 2
56#define reg_iop_sw_cfg_rw_crc_par_owner_offset 0
57
58/* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */
59#define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___lsb 0
60#define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___width 2
61#define reg_iop_sw_cfg_rw_dmc_in_owner_offset 4
62
63/* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */
64#define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___lsb 0
65#define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___width 2
66#define reg_iop_sw_cfg_rw_dmc_out_owner_offset 8
67
68/* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */
69#define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___lsb 0
70#define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___width 2
71#define reg_iop_sw_cfg_rw_fifo_in_owner_offset 12
72
73/* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */
74#define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___lsb 0
75#define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___width 2
76#define reg_iop_sw_cfg_rw_fifo_in_extra_owner_offset 16
77
78/* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */
79#define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___lsb 0
80#define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___width 2
81#define reg_iop_sw_cfg_rw_fifo_out_owner_offset 20
82
83/* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */
84#define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___lsb 0
85#define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___width 2
86#define reg_iop_sw_cfg_rw_fifo_out_extra_owner_offset 24
87
88/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
89#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0
90#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2
91#define reg_iop_sw_cfg_rw_sap_in_owner_offset 28
92
93/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
94#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0
95#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2
96#define reg_iop_sw_cfg_rw_sap_out_owner_offset 32
97
98/* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */
99#define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___lsb 0
100#define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___width 2
101#define reg_iop_sw_cfg_rw_scrc_in_owner_offset 36
102
103/* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */
104#define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___lsb 0
105#define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___width 2
106#define reg_iop_sw_cfg_rw_scrc_out_owner_offset 40
107
108/* Register rw_spu_owner, scope iop_sw_cfg, type rw */
109#define reg_iop_sw_cfg_rw_spu_owner___cfg___lsb 0
110#define reg_iop_sw_cfg_rw_spu_owner___cfg___width 1
111#define reg_iop_sw_cfg_rw_spu_owner___cfg___bit 0
112#define reg_iop_sw_cfg_rw_spu_owner_offset 44
113
114/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
115#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0
116#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2
117#define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 48
118
119/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
120#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0
121#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2
122#define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 52
123
124/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
125#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0
126#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2
127#define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 56
128
129/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
130#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0
131#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2
132#define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 60
133
134/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
135#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0
136#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2
137#define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 64
138
139/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
140#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0
141#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2
142#define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 68
143
144/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
145#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0
146#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2
147#define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 72
148
149/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
150#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0
151#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2
152#define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 76
153
154/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
155#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0
156#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2
157#define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 80
158
159/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
160#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0
161#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2
162#define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 84
163
164/* Register rw_bus_mask, scope iop_sw_cfg, type rw */
165#define reg_iop_sw_cfg_rw_bus_mask___byte0___lsb 0
166#define reg_iop_sw_cfg_rw_bus_mask___byte0___width 8
167#define reg_iop_sw_cfg_rw_bus_mask___byte1___lsb 8
168#define reg_iop_sw_cfg_rw_bus_mask___byte1___width 8
169#define reg_iop_sw_cfg_rw_bus_mask___byte2___lsb 16
170#define reg_iop_sw_cfg_rw_bus_mask___byte2___width 8
171#define reg_iop_sw_cfg_rw_bus_mask___byte3___lsb 24
172#define reg_iop_sw_cfg_rw_bus_mask___byte3___width 8
173#define reg_iop_sw_cfg_rw_bus_mask_offset 88
174
175/* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */
176#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___lsb 0
177#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___width 1
178#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___bit 0
179#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___lsb 1
180#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___width 1
181#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___bit 1
182#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___lsb 2
183#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___width 1
184#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___bit 2
185#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___lsb 3
186#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___width 1
187#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___bit 3
188#define reg_iop_sw_cfg_rw_bus_oe_mask_offset 92
189
190/* Register rw_gio_mask, scope iop_sw_cfg, type rw */
191#define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0
192#define reg_iop_sw_cfg_rw_gio_mask___val___width 32
193#define reg_iop_sw_cfg_rw_gio_mask_offset 96
194
195/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
196#define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0
197#define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32
198#define reg_iop_sw_cfg_rw_gio_oe_mask_offset 100
199
200/* Register rw_pinmapping, scope iop_sw_cfg, type rw */
201#define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___lsb 0
202#define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___width 2
203#define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___lsb 2
204#define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___width 2
205#define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___lsb 4
206#define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___width 2
207#define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___lsb 6
208#define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___width 2
209#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 8
210#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2
211#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 10
212#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2
213#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 12
214#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2
215#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 14
216#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2
217#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 16
218#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2
219#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 18
220#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2
221#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 20
222#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2
223#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 22
224#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2
225#define reg_iop_sw_cfg_rw_pinmapping_offset 104
226
227/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
228#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___lsb 0
229#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___width 2
230#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___lsb 2
231#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___width 2
232#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___lsb 4
233#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___width 2
234#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___lsb 6
235#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___width 2
236#define reg_iop_sw_cfg_rw_bus_out_cfg_offset 108
237
238/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
239#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0
240#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 3
241#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 3
242#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 1
243#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___bit 3
244#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 4
245#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 3
246#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 7
247#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 1
248#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___bit 7
249#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 8
250#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 3
251#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 11
252#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 1
253#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___bit 11
254#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 12
255#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 3
256#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 15
257#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 1
258#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___bit 15
259#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 112
260
261/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
262#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0
263#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 3
264#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 3
265#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 1
266#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___bit 3
267#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 4
268#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 3
269#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 7
270#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 1
271#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___bit 7
272#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 8
273#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 3
274#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 11
275#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 1
276#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___bit 11
277#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 12
278#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 3
279#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 15
280#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 1
281#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___bit 15
282#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 116
283
284/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
285#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0
286#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 3
287#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 3
288#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 1
289#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___bit 3
290#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 4
291#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 3
292#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 7
293#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 1
294#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___bit 7
295#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 8
296#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 3
297#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 11
298#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 1
299#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___bit 11
300#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 12
301#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 3
302#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 15
303#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 1
304#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___bit 15
305#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 120
306
307/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */
308#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0
309#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 3
310#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 3
311#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 1
312#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___bit 3
313#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 4
314#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 3
315#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 7
316#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 1
317#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___bit 7
318#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 8
319#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 3
320#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 11
321#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 1
322#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___bit 11
323#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 12
324#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 3
325#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 15
326#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 1
327#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___bit 15
328#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 124
329
330/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */
331#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0
332#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 3
333#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 3
334#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 1
335#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___bit 3
336#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 4
337#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 3
338#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 7
339#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 1
340#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___bit 7
341#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 8
342#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 3
343#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 11
344#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 1
345#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___bit 11
346#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 12
347#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 3
348#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 15
349#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 1
350#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___bit 15
351#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 128
352
353/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */
354#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0
355#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 3
356#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 3
357#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 1
358#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___bit 3
359#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 4
360#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 3
361#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 7
362#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 1
363#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___bit 7
364#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 8
365#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 3
366#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 11
367#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 1
368#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___bit 11
369#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 12
370#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 3
371#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 15
372#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 1
373#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___bit 15
374#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 132
375
376/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */
377#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0
378#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 3
379#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 3
380#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 1
381#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___bit 3
382#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 4
383#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 3
384#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 7
385#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 1
386#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___bit 7
387#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 8
388#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 3
389#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 11
390#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 1
391#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___bit 11
392#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 12
393#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 3
394#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 15
395#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 1
396#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___bit 15
397#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 136
398
399/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */
400#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0
401#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 3
402#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 3
403#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 1
404#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___bit 3
405#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 4
406#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 3
407#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 7
408#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 1
409#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___bit 7
410#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 8
411#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 3
412#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 11
413#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 1
414#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___bit 11
415#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 12
416#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 3
417#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 15
418#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 1
419#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___bit 15
420#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 140
421
422/* Register rw_spu_cfg, scope iop_sw_cfg, type rw */
423#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___lsb 0
424#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___width 1
425#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___bit 0
426#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___lsb 1
427#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___width 1
428#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___bit 1
429#define reg_iop_sw_cfg_rw_spu_cfg_offset 144
430
431/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */
432#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0
433#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3
434#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3
435#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 2
436#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 5
437#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 2
438#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 7
439#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 2
440#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 9
441#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 2
442#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 11
443#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 2
444#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 13
445#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 2
446#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 15
447#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 2
448#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 17
449#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 2
450#define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 148
451
452/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */
453#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0
454#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3
455#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3
456#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 2
457#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 5
458#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 2
459#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 7
460#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 2
461#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 9
462#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 2
463#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 11
464#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 2
465#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 13
466#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 2
467#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 15
468#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 2
469#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 17
470#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 2
471#define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 152
472
473/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */
474#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0
475#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1
476#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0
477#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1
478#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1
479#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1
480#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2
481#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1
482#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2
483#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3
484#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1
485#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3
486#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4
487#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1
488#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4
489#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5
490#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1
491#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5
492#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6
493#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1
494#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6
495#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7
496#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1
497#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7
498#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8
499#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1
500#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8
501#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9
502#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1
503#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9
504#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10
505#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1
506#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10
507#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11
508#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1
509#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11
510#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12
511#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1
512#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12
513#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13
514#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1
515#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13
516#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14
517#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1
518#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14
519#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15
520#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1
521#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15
522#define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 156
523
524/* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */
525#define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___lsb 0
526#define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___width 4
527#define reg_iop_sw_cfg_rw_pdp_cfg___in_src___lsb 4
528#define reg_iop_sw_cfg_rw_pdp_cfg___in_src___width 2
529#define reg_iop_sw_cfg_rw_pdp_cfg___in_size___lsb 6
530#define reg_iop_sw_cfg_rw_pdp_cfg___in_size___width 3
531#define reg_iop_sw_cfg_rw_pdp_cfg___in_last___lsb 9
532#define reg_iop_sw_cfg_rw_pdp_cfg___in_last___width 2
533#define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___lsb 11
534#define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___width 4
535#define reg_iop_sw_cfg_rw_pdp_cfg_offset 160
536
537/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
538#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___lsb 0
539#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___width 3
540#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___lsb 3
541#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___width 3
542#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___lsb 6
543#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___width 2
544#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___lsb 8
545#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___width 3
546#define reg_iop_sw_cfg_rw_sdp_cfg_offset 164
547
548
549/* Constants */
550#define regk_iop_sw_cfg_a 0x00000001
551#define regk_iop_sw_cfg_b 0x00000002
552#define regk_iop_sw_cfg_bus 0x00000000
553#define regk_iop_sw_cfg_bus_rot16 0x00000002
554#define regk_iop_sw_cfg_bus_rot24 0x00000003
555#define regk_iop_sw_cfg_bus_rot8 0x00000001
556#define regk_iop_sw_cfg_clk12 0x00000000
557#define regk_iop_sw_cfg_cpu 0x00000000
558#define regk_iop_sw_cfg_gated_clk0 0x0000000e
559#define regk_iop_sw_cfg_gated_clk1 0x0000000f
560#define regk_iop_sw_cfg_gio0 0x00000004
561#define regk_iop_sw_cfg_gio1 0x00000001
562#define regk_iop_sw_cfg_gio2 0x00000005
563#define regk_iop_sw_cfg_gio3 0x00000002
564#define regk_iop_sw_cfg_gio4 0x00000006
565#define regk_iop_sw_cfg_gio5 0x00000003
566#define regk_iop_sw_cfg_gio6 0x00000007
567#define regk_iop_sw_cfg_gio7 0x00000004
568#define regk_iop_sw_cfg_gio_in18 0x00000002
569#define regk_iop_sw_cfg_gio_in19 0x00000003
570#define regk_iop_sw_cfg_gio_in20 0x00000004
571#define regk_iop_sw_cfg_gio_in21 0x00000005
572#define regk_iop_sw_cfg_gio_in26 0x00000006
573#define regk_iop_sw_cfg_gio_in27 0x00000007
574#define regk_iop_sw_cfg_gio_in4 0x00000000
575#define regk_iop_sw_cfg_gio_in5 0x00000001
576#define regk_iop_sw_cfg_last_timer_grp0_tmr2 0x00000001
577#define regk_iop_sw_cfg_last_timer_grp1_tmr2 0x00000002
578#define regk_iop_sw_cfg_last_timer_grp1_tmr3 0x00000003
579#define regk_iop_sw_cfg_mpu 0x00000001
580#define regk_iop_sw_cfg_none 0x00000000
581#define regk_iop_sw_cfg_pdp_out 0x00000001
582#define regk_iop_sw_cfg_pdp_out_hi 0x00000001
583#define regk_iop_sw_cfg_pdp_out_lo 0x00000000
584#define regk_iop_sw_cfg_rw_bus_mask_default 0x00000000
585#define regk_iop_sw_cfg_rw_bus_oe_mask_default 0x00000000
586#define regk_iop_sw_cfg_rw_bus_out_cfg_default 0x00000000
587#define regk_iop_sw_cfg_rw_crc_par_owner_default 0x00000000
588#define regk_iop_sw_cfg_rw_dmc_in_owner_default 0x00000000
589#define regk_iop_sw_cfg_rw_dmc_out_owner_default 0x00000000
590#define regk_iop_sw_cfg_rw_fifo_in_extra_owner_default 0x00000000
591#define regk_iop_sw_cfg_rw_fifo_in_owner_default 0x00000000
592#define regk_iop_sw_cfg_rw_fifo_out_extra_owner_default 0x00000000
593#define regk_iop_sw_cfg_rw_fifo_out_owner_default 0x00000000
594#define regk_iop_sw_cfg_rw_gio_mask_default 0x00000000
595#define regk_iop_sw_cfg_rw_gio_oe_mask_default 0x00000000
596#define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default 0x00000000
597#define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default 0x00000000
598#define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default 0x00000000
599#define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default 0x00000000
600#define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default 0x00000000
601#define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default 0x00000000
602#define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default 0x00000000
603#define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default 0x00000000
604#define regk_iop_sw_cfg_rw_pdp_cfg_default 0x00000000
605#define regk_iop_sw_cfg_rw_pinmapping_default 0x00555555
606#define regk_iop_sw_cfg_rw_sap_in_owner_default 0x00000000
607#define regk_iop_sw_cfg_rw_sap_out_owner_default 0x00000000
608#define regk_iop_sw_cfg_rw_scrc_in_owner_default 0x00000000
609#define regk_iop_sw_cfg_rw_scrc_out_owner_default 0x00000000
610#define regk_iop_sw_cfg_rw_sdp_cfg_default 0x00000000
611#define regk_iop_sw_cfg_rw_spu_cfg_default 0x00000000
612#define regk_iop_sw_cfg_rw_spu_owner_default 0x00000000
613#define regk_iop_sw_cfg_rw_timer_grp0_cfg_default 0x00000000
614#define regk_iop_sw_cfg_rw_timer_grp0_owner_default 0x00000000
615#define regk_iop_sw_cfg_rw_timer_grp1_cfg_default 0x00000000
616#define regk_iop_sw_cfg_rw_timer_grp1_owner_default 0x00000000
617#define regk_iop_sw_cfg_rw_trigger_grp0_owner_default 0x00000000
618#define regk_iop_sw_cfg_rw_trigger_grp1_owner_default 0x00000000
619#define regk_iop_sw_cfg_rw_trigger_grp2_owner_default 0x00000000
620#define regk_iop_sw_cfg_rw_trigger_grp3_owner_default 0x00000000
621#define regk_iop_sw_cfg_rw_trigger_grp4_owner_default 0x00000000
622#define regk_iop_sw_cfg_rw_trigger_grp5_owner_default 0x00000000
623#define regk_iop_sw_cfg_rw_trigger_grp6_owner_default 0x00000000
624#define regk_iop_sw_cfg_rw_trigger_grp7_owner_default 0x00000000
625#define regk_iop_sw_cfg_rw_trigger_grps_cfg_default 0x00000000
626#define regk_iop_sw_cfg_sdp_out 0x00000004
627#define regk_iop_sw_cfg_size16 0x00000002
628#define regk_iop_sw_cfg_size24 0x00000003
629#define regk_iop_sw_cfg_size32 0x00000004
630#define regk_iop_sw_cfg_size8 0x00000001
631#define regk_iop_sw_cfg_spu 0x00000002
632#define regk_iop_sw_cfg_spu_bus_out0_hi 0x00000002
633#define regk_iop_sw_cfg_spu_bus_out0_lo 0x00000002
634#define regk_iop_sw_cfg_spu_bus_out1_hi 0x00000003
635#define regk_iop_sw_cfg_spu_bus_out1_lo 0x00000003
636#define regk_iop_sw_cfg_spu_g0 0x00000007
637#define regk_iop_sw_cfg_spu_g1 0x00000007
638#define regk_iop_sw_cfg_spu_g2 0x00000007
639#define regk_iop_sw_cfg_spu_g3 0x00000007
640#define regk_iop_sw_cfg_spu_g4 0x00000007
641#define regk_iop_sw_cfg_spu_g5 0x00000007
642#define regk_iop_sw_cfg_spu_g6 0x00000007
643#define regk_iop_sw_cfg_spu_g7 0x00000007
644#define regk_iop_sw_cfg_spu_gio0 0x00000000
645#define regk_iop_sw_cfg_spu_gio1 0x00000001
646#define regk_iop_sw_cfg_spu_gio5 0x00000005
647#define regk_iop_sw_cfg_spu_gio6 0x00000006
648#define regk_iop_sw_cfg_spu_gio7 0x00000007
649#define regk_iop_sw_cfg_spu_gio_out0 0x00000008
650#define regk_iop_sw_cfg_spu_gio_out1 0x00000009
651#define regk_iop_sw_cfg_spu_gio_out2 0x0000000a
652#define regk_iop_sw_cfg_spu_gio_out3 0x0000000b
653#define regk_iop_sw_cfg_spu_gio_out4 0x0000000c
654#define regk_iop_sw_cfg_spu_gio_out5 0x0000000d
655#define regk_iop_sw_cfg_spu_gio_out6 0x0000000e
656#define regk_iop_sw_cfg_spu_gio_out7 0x0000000f
657#define regk_iop_sw_cfg_spu_gioout0 0x00000000
658#define regk_iop_sw_cfg_spu_gioout1 0x00000000
659#define regk_iop_sw_cfg_spu_gioout10 0x00000007
660#define regk_iop_sw_cfg_spu_gioout11 0x00000007
661#define regk_iop_sw_cfg_spu_gioout12 0x00000007
662#define regk_iop_sw_cfg_spu_gioout13 0x00000007
663#define regk_iop_sw_cfg_spu_gioout14 0x00000007
664#define regk_iop_sw_cfg_spu_gioout15 0x00000007
665#define regk_iop_sw_cfg_spu_gioout16 0x00000007
666#define regk_iop_sw_cfg_spu_gioout17 0x00000007
667#define regk_iop_sw_cfg_spu_gioout18 0x00000007
668#define regk_iop_sw_cfg_spu_gioout19 0x00000007
669#define regk_iop_sw_cfg_spu_gioout2 0x00000001
670#define regk_iop_sw_cfg_spu_gioout20 0x00000007
671#define regk_iop_sw_cfg_spu_gioout21 0x00000007
672#define regk_iop_sw_cfg_spu_gioout22 0x00000007
673#define regk_iop_sw_cfg_spu_gioout23 0x00000007
674#define regk_iop_sw_cfg_spu_gioout24 0x00000007
675#define regk_iop_sw_cfg_spu_gioout25 0x00000007
676#define regk_iop_sw_cfg_spu_gioout26 0x00000007
677#define regk_iop_sw_cfg_spu_gioout27 0x00000007
678#define regk_iop_sw_cfg_spu_gioout28 0x00000007
679#define regk_iop_sw_cfg_spu_gioout29 0x00000007
680#define regk_iop_sw_cfg_spu_gioout3 0x00000001
681#define regk_iop_sw_cfg_spu_gioout30 0x00000007
682#define regk_iop_sw_cfg_spu_gioout31 0x00000007
683#define regk_iop_sw_cfg_spu_gioout4 0x00000002
684#define regk_iop_sw_cfg_spu_gioout5 0x00000002
685#define regk_iop_sw_cfg_spu_gioout6 0x00000003
686#define regk_iop_sw_cfg_spu_gioout7 0x00000003
687#define regk_iop_sw_cfg_spu_gioout8 0x00000007
688#define regk_iop_sw_cfg_spu_gioout9 0x00000007
689#define regk_iop_sw_cfg_strb_timer_grp0_tmr0 0x00000001
690#define regk_iop_sw_cfg_strb_timer_grp0_tmr1 0x00000002
691#define regk_iop_sw_cfg_strb_timer_grp1_tmr0 0x00000003
692#define regk_iop_sw_cfg_strb_timer_grp1_tmr1 0x00000002
693#define regk_iop_sw_cfg_timer_grp0 0x00000000
694#define regk_iop_sw_cfg_timer_grp0_rot 0x00000001
695#define regk_iop_sw_cfg_timer_grp0_strb0 0x00000005
696#define regk_iop_sw_cfg_timer_grp0_strb1 0x00000005
697#define regk_iop_sw_cfg_timer_grp0_strb2 0x00000005
698#define regk_iop_sw_cfg_timer_grp0_strb3 0x00000005
699#define regk_iop_sw_cfg_timer_grp0_tmr0 0x00000002
700#define regk_iop_sw_cfg_timer_grp1 0x00000000
701#define regk_iop_sw_cfg_timer_grp1_rot 0x00000001
702#define regk_iop_sw_cfg_timer_grp1_strb0 0x00000006
703#define regk_iop_sw_cfg_timer_grp1_strb1 0x00000006
704#define regk_iop_sw_cfg_timer_grp1_strb2 0x00000006
705#define regk_iop_sw_cfg_timer_grp1_strb3 0x00000006
706#define regk_iop_sw_cfg_timer_grp1_tmr0 0x00000003
707#define regk_iop_sw_cfg_trig0_0 0x00000000
708#define regk_iop_sw_cfg_trig0_1 0x00000000
709#define regk_iop_sw_cfg_trig0_2 0x00000000
710#define regk_iop_sw_cfg_trig0_3 0x00000000
711#define regk_iop_sw_cfg_trig1_0 0x00000000
712#define regk_iop_sw_cfg_trig1_1 0x00000000
713#define regk_iop_sw_cfg_trig1_2 0x00000000
714#define regk_iop_sw_cfg_trig1_3 0x00000000
715#define regk_iop_sw_cfg_trig2_0 0x00000001
716#define regk_iop_sw_cfg_trig2_1 0x00000001
717#define regk_iop_sw_cfg_trig2_2 0x00000001
718#define regk_iop_sw_cfg_trig2_3 0x00000001
719#define regk_iop_sw_cfg_trig3_0 0x00000001
720#define regk_iop_sw_cfg_trig3_1 0x00000001
721#define regk_iop_sw_cfg_trig3_2 0x00000001
722#define regk_iop_sw_cfg_trig3_3 0x00000001
723#define regk_iop_sw_cfg_trig4_0 0x00000002
724#define regk_iop_sw_cfg_trig4_1 0x00000002
725#define regk_iop_sw_cfg_trig4_2 0x00000002
726#define regk_iop_sw_cfg_trig4_3 0x00000002
727#define regk_iop_sw_cfg_trig5_0 0x00000002
728#define regk_iop_sw_cfg_trig5_1 0x00000002
729#define regk_iop_sw_cfg_trig5_2 0x00000002
730#define regk_iop_sw_cfg_trig5_3 0x00000002
731#define regk_iop_sw_cfg_trig6_0 0x00000003
732#define regk_iop_sw_cfg_trig6_1 0x00000003
733#define regk_iop_sw_cfg_trig6_2 0x00000003
734#define regk_iop_sw_cfg_trig6_3 0x00000003
735#define regk_iop_sw_cfg_trig7_0 0x00000003
736#define regk_iop_sw_cfg_trig7_1 0x00000003
737#define regk_iop_sw_cfg_trig7_2 0x00000003
738#define regk_iop_sw_cfg_trig7_3 0x00000003
739#endif /* __iop_sw_cfg_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cpu_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cpu_defs_asm.h
new file mode 100644
index 000000000000..3f4fe1b31815
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cpu_defs_asm.h
@@ -0,0 +1,950 @@
1#ifndef __iop_sw_cpu_defs_asm_h
2#define __iop_sw_cpu_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: iop_sw_cpu.r
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cpu_defs_asm.h iop_sw_cpu.r
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13
14#ifndef REG_FIELD
15#define REG_FIELD( scope, reg, field, value ) \
16 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
17#define REG_FIELD_X_( value, shift ) ((value) << shift)
18#endif
19
20#ifndef REG_STATE
21#define REG_STATE( scope, reg, field, symbolic_value ) \
22 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
23#define REG_STATE_X_( k, shift ) (k << shift)
24#endif
25
26#ifndef REG_MASK
27#define REG_MASK( scope, reg, field ) \
28 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
29#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
30#endif
31
32#ifndef REG_LSB
33#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
34#endif
35
36#ifndef REG_BIT
37#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
38#endif
39
40#ifndef REG_ADDR
41#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
42#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
43#endif
44
45#ifndef REG_ADDR_VECT
46#define REG_ADDR_VECT( scope, inst, reg, index ) \
47 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
48 STRIDE_##scope##_##reg )
49#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
50 ((inst) + offs + (index) * stride)
51#endif
52
53/* Register r_mpu_trace, scope iop_sw_cpu, type r */
54#define reg_iop_sw_cpu_r_mpu_trace_offset 0
55
56/* Register r_spu_trace, scope iop_sw_cpu, type r */
57#define reg_iop_sw_cpu_r_spu_trace_offset 4
58
59/* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */
60#define reg_iop_sw_cpu_r_spu_fsm_trace_offset 8
61
62/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */
63#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0
64#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1
65#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0
66#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1
67#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2
68#define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3
69#define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3
70#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___lsb 6
71#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___width 1
72#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___bit 6
73#define reg_iop_sw_cpu_rw_mc_ctrl_offset 12
74
75/* Register rw_mc_data, scope iop_sw_cpu, type rw */
76#define reg_iop_sw_cpu_rw_mc_data___val___lsb 0
77#define reg_iop_sw_cpu_rw_mc_data___val___width 32
78#define reg_iop_sw_cpu_rw_mc_data_offset 16
79
80/* Register rw_mc_addr, scope iop_sw_cpu, type rw */
81#define reg_iop_sw_cpu_rw_mc_addr_offset 20
82
83/* Register rs_mc_data, scope iop_sw_cpu, type rs */
84#define reg_iop_sw_cpu_rs_mc_data_offset 24
85
86/* Register r_mc_data, scope iop_sw_cpu, type r */
87#define reg_iop_sw_cpu_r_mc_data_offset 28
88
89/* Register r_mc_stat, scope iop_sw_cpu, type r */
90#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0
91#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1
92#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0
93#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1
94#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1
95#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1
96#define reg_iop_sw_cpu_r_mc_stat___busy_spu___lsb 2
97#define reg_iop_sw_cpu_r_mc_stat___busy_spu___width 1
98#define reg_iop_sw_cpu_r_mc_stat___busy_spu___bit 2
99#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 3
100#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1
101#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 3
102#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 4
103#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1
104#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 4
105#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___lsb 5
106#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___width 1
107#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___bit 5
108#define reg_iop_sw_cpu_r_mc_stat_offset 32
109
110/* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */
111#define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___lsb 0
112#define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___width 8
113#define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___lsb 8
114#define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___width 8
115#define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___lsb 16
116#define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___width 8
117#define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___lsb 24
118#define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___width 8
119#define reg_iop_sw_cpu_rw_bus_clr_mask_offset 36
120
121/* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */
122#define reg_iop_sw_cpu_rw_bus_set_mask___byte0___lsb 0
123#define reg_iop_sw_cpu_rw_bus_set_mask___byte0___width 8
124#define reg_iop_sw_cpu_rw_bus_set_mask___byte1___lsb 8
125#define reg_iop_sw_cpu_rw_bus_set_mask___byte1___width 8
126#define reg_iop_sw_cpu_rw_bus_set_mask___byte2___lsb 16
127#define reg_iop_sw_cpu_rw_bus_set_mask___byte2___width 8
128#define reg_iop_sw_cpu_rw_bus_set_mask___byte3___lsb 24
129#define reg_iop_sw_cpu_rw_bus_set_mask___byte3___width 8
130#define reg_iop_sw_cpu_rw_bus_set_mask_offset 40
131
132/* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */
133#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___lsb 0
134#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___width 1
135#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___bit 0
136#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___lsb 1
137#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___width 1
138#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___bit 1
139#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___lsb 2
140#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___width 1
141#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___bit 2
142#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___lsb 3
143#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___width 1
144#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___bit 3
145#define reg_iop_sw_cpu_rw_bus_oe_clr_mask_offset 44
146
147/* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */
148#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___lsb 0
149#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___width 1
150#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___bit 0
151#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___lsb 1
152#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___width 1
153#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___bit 1
154#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___lsb 2
155#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___width 1
156#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___bit 2
157#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___lsb 3
158#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___width 1
159#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___bit 3
160#define reg_iop_sw_cpu_rw_bus_oe_set_mask_offset 48
161
162/* Register r_bus_in, scope iop_sw_cpu, type r */
163#define reg_iop_sw_cpu_r_bus_in_offset 52
164
165/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */
166#define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0
167#define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32
168#define reg_iop_sw_cpu_rw_gio_clr_mask_offset 56
169
170/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */
171#define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0
172#define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32
173#define reg_iop_sw_cpu_rw_gio_set_mask_offset 60
174
175/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */
176#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0
177#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32
178#define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 64
179
180/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */
181#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0
182#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32
183#define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 68
184
185/* Register r_gio_in, scope iop_sw_cpu, type r */
186#define reg_iop_sw_cpu_r_gio_in_offset 72
187
188/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */
189#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0
190#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1
191#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0
192#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1
193#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1
194#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1
195#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2
196#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1
197#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2
198#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3
199#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1
200#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3
201#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4
202#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1
203#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4
204#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5
205#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1
206#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5
207#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6
208#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1
209#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6
210#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7
211#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1
212#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7
213#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8
214#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1
215#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8
216#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9
217#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1
218#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9
219#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10
220#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1
221#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10
222#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11
223#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1
224#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11
225#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12
226#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1
227#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12
228#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13
229#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1
230#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13
231#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14
232#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1
233#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14
234#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15
235#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1
236#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15
237#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___lsb 16
238#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___width 1
239#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___bit 16
240#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___lsb 17
241#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___width 1
242#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___bit 17
243#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___lsb 18
244#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___width 1
245#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___bit 18
246#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___lsb 19
247#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___width 1
248#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___bit 19
249#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___lsb 20
250#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___width 1
251#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___bit 20
252#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___lsb 21
253#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___width 1
254#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___bit 21
255#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___lsb 22
256#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___width 1
257#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___bit 22
258#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___lsb 23
259#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___width 1
260#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___bit 23
261#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___lsb 24
262#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___width 1
263#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___bit 24
264#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___lsb 25
265#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___width 1
266#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___bit 25
267#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___lsb 26
268#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___width 1
269#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___bit 26
270#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___lsb 27
271#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___width 1
272#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___bit 27
273#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___lsb 28
274#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___width 1
275#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___bit 28
276#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___lsb 29
277#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___width 1
278#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___bit 29
279#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___lsb 30
280#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___width 1
281#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___bit 30
282#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___lsb 31
283#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___width 1
284#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___bit 31
285#define reg_iop_sw_cpu_rw_intr0_mask_offset 76
286
287/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */
288#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0
289#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1
290#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0
291#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1
292#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1
293#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1
294#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2
295#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1
296#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2
297#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3
298#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1
299#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3
300#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4
301#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1
302#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4
303#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5
304#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1
305#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5
306#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6
307#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1
308#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6
309#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7
310#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1
311#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7
312#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8
313#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1
314#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8
315#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9
316#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1
317#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9
318#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10
319#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1
320#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10
321#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11
322#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1
323#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11
324#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12
325#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1
326#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12
327#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13
328#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1
329#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13
330#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14
331#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1
332#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14
333#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15
334#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1
335#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15
336#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___lsb 16
337#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___width 1
338#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___bit 16
339#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___lsb 17
340#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___width 1
341#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___bit 17
342#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___lsb 18
343#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___width 1
344#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___bit 18
345#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___lsb 19
346#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___width 1
347#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___bit 19
348#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___lsb 20
349#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___width 1
350#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___bit 20
351#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___lsb 21
352#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___width 1
353#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___bit 21
354#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___lsb 22
355#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___width 1
356#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___bit 22
357#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___lsb 23
358#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___width 1
359#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___bit 23
360#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___lsb 24
361#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___width 1
362#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___bit 24
363#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___lsb 25
364#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___width 1
365#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___bit 25
366#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___lsb 26
367#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___width 1
368#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___bit 26
369#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___lsb 27
370#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___width 1
371#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___bit 27
372#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___lsb 28
373#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___width 1
374#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___bit 28
375#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___lsb 29
376#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___width 1
377#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___bit 29
378#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___lsb 30
379#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___width 1
380#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___bit 30
381#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___lsb 31
382#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___width 1
383#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___bit 31
384#define reg_iop_sw_cpu_rw_ack_intr0_offset 80
385
386/* Register r_intr0, scope iop_sw_cpu, type r */
387#define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0
388#define reg_iop_sw_cpu_r_intr0___mpu_0___width 1
389#define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0
390#define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1
391#define reg_iop_sw_cpu_r_intr0___mpu_1___width 1
392#define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1
393#define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2
394#define reg_iop_sw_cpu_r_intr0___mpu_2___width 1
395#define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2
396#define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3
397#define reg_iop_sw_cpu_r_intr0___mpu_3___width 1
398#define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3
399#define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4
400#define reg_iop_sw_cpu_r_intr0___mpu_4___width 1
401#define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4
402#define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5
403#define reg_iop_sw_cpu_r_intr0___mpu_5___width 1
404#define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5
405#define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6
406#define reg_iop_sw_cpu_r_intr0___mpu_6___width 1
407#define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6
408#define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7
409#define reg_iop_sw_cpu_r_intr0___mpu_7___width 1
410#define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7
411#define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8
412#define reg_iop_sw_cpu_r_intr0___mpu_8___width 1
413#define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8
414#define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9
415#define reg_iop_sw_cpu_r_intr0___mpu_9___width 1
416#define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9
417#define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10
418#define reg_iop_sw_cpu_r_intr0___mpu_10___width 1
419#define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10
420#define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11
421#define reg_iop_sw_cpu_r_intr0___mpu_11___width 1
422#define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11
423#define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12
424#define reg_iop_sw_cpu_r_intr0___mpu_12___width 1
425#define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12
426#define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13
427#define reg_iop_sw_cpu_r_intr0___mpu_13___width 1
428#define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13
429#define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14
430#define reg_iop_sw_cpu_r_intr0___mpu_14___width 1
431#define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14
432#define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15
433#define reg_iop_sw_cpu_r_intr0___mpu_15___width 1
434#define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15
435#define reg_iop_sw_cpu_r_intr0___spu_0___lsb 16
436#define reg_iop_sw_cpu_r_intr0___spu_0___width 1
437#define reg_iop_sw_cpu_r_intr0___spu_0___bit 16
438#define reg_iop_sw_cpu_r_intr0___spu_1___lsb 17
439#define reg_iop_sw_cpu_r_intr0___spu_1___width 1
440#define reg_iop_sw_cpu_r_intr0___spu_1___bit 17
441#define reg_iop_sw_cpu_r_intr0___spu_2___lsb 18
442#define reg_iop_sw_cpu_r_intr0___spu_2___width 1
443#define reg_iop_sw_cpu_r_intr0___spu_2___bit 18
444#define reg_iop_sw_cpu_r_intr0___spu_3___lsb 19
445#define reg_iop_sw_cpu_r_intr0___spu_3___width 1
446#define reg_iop_sw_cpu_r_intr0___spu_3___bit 19
447#define reg_iop_sw_cpu_r_intr0___spu_4___lsb 20
448#define reg_iop_sw_cpu_r_intr0___spu_4___width 1
449#define reg_iop_sw_cpu_r_intr0___spu_4___bit 20
450#define reg_iop_sw_cpu_r_intr0___spu_5___lsb 21
451#define reg_iop_sw_cpu_r_intr0___spu_5___width 1
452#define reg_iop_sw_cpu_r_intr0___spu_5___bit 21
453#define reg_iop_sw_cpu_r_intr0___spu_6___lsb 22
454#define reg_iop_sw_cpu_r_intr0___spu_6___width 1
455#define reg_iop_sw_cpu_r_intr0___spu_6___bit 22
456#define reg_iop_sw_cpu_r_intr0___spu_7___lsb 23
457#define reg_iop_sw_cpu_r_intr0___spu_7___width 1
458#define reg_iop_sw_cpu_r_intr0___spu_7___bit 23
459#define reg_iop_sw_cpu_r_intr0___spu_8___lsb 24
460#define reg_iop_sw_cpu_r_intr0___spu_8___width 1
461#define reg_iop_sw_cpu_r_intr0___spu_8___bit 24
462#define reg_iop_sw_cpu_r_intr0___spu_9___lsb 25
463#define reg_iop_sw_cpu_r_intr0___spu_9___width 1
464#define reg_iop_sw_cpu_r_intr0___spu_9___bit 25
465#define reg_iop_sw_cpu_r_intr0___spu_10___lsb 26
466#define reg_iop_sw_cpu_r_intr0___spu_10___width 1
467#define reg_iop_sw_cpu_r_intr0___spu_10___bit 26
468#define reg_iop_sw_cpu_r_intr0___spu_11___lsb 27
469#define reg_iop_sw_cpu_r_intr0___spu_11___width 1
470#define reg_iop_sw_cpu_r_intr0___spu_11___bit 27
471#define reg_iop_sw_cpu_r_intr0___spu_12___lsb 28
472#define reg_iop_sw_cpu_r_intr0___spu_12___width 1
473#define reg_iop_sw_cpu_r_intr0___spu_12___bit 28
474#define reg_iop_sw_cpu_r_intr0___spu_13___lsb 29
475#define reg_iop_sw_cpu_r_intr0___spu_13___width 1
476#define reg_iop_sw_cpu_r_intr0___spu_13___bit 29
477#define reg_iop_sw_cpu_r_intr0___spu_14___lsb 30
478#define reg_iop_sw_cpu_r_intr0___spu_14___width 1
479#define reg_iop_sw_cpu_r_intr0___spu_14___bit 30
480#define reg_iop_sw_cpu_r_intr0___spu_15___lsb 31
481#define reg_iop_sw_cpu_r_intr0___spu_15___width 1
482#define reg_iop_sw_cpu_r_intr0___spu_15___bit 31
483#define reg_iop_sw_cpu_r_intr0_offset 84
484
485/* Register r_masked_intr0, scope iop_sw_cpu, type r */
486#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0
487#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1
488#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0
489#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1
490#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1
491#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1
492#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2
493#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1
494#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2
495#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3
496#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1
497#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3
498#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4
499#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1
500#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4
501#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5
502#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1
503#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5
504#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6
505#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1
506#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6
507#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7
508#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1
509#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7
510#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8
511#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1
512#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8
513#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9
514#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1
515#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9
516#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10
517#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1
518#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10
519#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11
520#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1
521#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11
522#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12
523#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1
524#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12
525#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13
526#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1
527#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13
528#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14
529#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1
530#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14
531#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15
532#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1
533#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15
534#define reg_iop_sw_cpu_r_masked_intr0___spu_0___lsb 16
535#define reg_iop_sw_cpu_r_masked_intr0___spu_0___width 1
536#define reg_iop_sw_cpu_r_masked_intr0___spu_0___bit 16
537#define reg_iop_sw_cpu_r_masked_intr0___spu_1___lsb 17
538#define reg_iop_sw_cpu_r_masked_intr0___spu_1___width 1
539#define reg_iop_sw_cpu_r_masked_intr0___spu_1___bit 17
540#define reg_iop_sw_cpu_r_masked_intr0___spu_2___lsb 18
541#define reg_iop_sw_cpu_r_masked_intr0___spu_2___width 1
542#define reg_iop_sw_cpu_r_masked_intr0___spu_2___bit 18
543#define reg_iop_sw_cpu_r_masked_intr0___spu_3___lsb 19
544#define reg_iop_sw_cpu_r_masked_intr0___spu_3___width 1
545#define reg_iop_sw_cpu_r_masked_intr0___spu_3___bit 19
546#define reg_iop_sw_cpu_r_masked_intr0___spu_4___lsb 20
547#define reg_iop_sw_cpu_r_masked_intr0___spu_4___width 1
548#define reg_iop_sw_cpu_r_masked_intr0___spu_4___bit 20
549#define reg_iop_sw_cpu_r_masked_intr0___spu_5___lsb 21
550#define reg_iop_sw_cpu_r_masked_intr0___spu_5___width 1
551#define reg_iop_sw_cpu_r_masked_intr0___spu_5___bit 21
552#define reg_iop_sw_cpu_r_masked_intr0___spu_6___lsb 22
553#define reg_iop_sw_cpu_r_masked_intr0___spu_6___width 1
554#define reg_iop_sw_cpu_r_masked_intr0___spu_6___bit 22
555#define reg_iop_sw_cpu_r_masked_intr0___spu_7___lsb 23
556#define reg_iop_sw_cpu_r_masked_intr0___spu_7___width 1
557#define reg_iop_sw_cpu_r_masked_intr0___spu_7___bit 23
558#define reg_iop_sw_cpu_r_masked_intr0___spu_8___lsb 24
559#define reg_iop_sw_cpu_r_masked_intr0___spu_8___width 1
560#define reg_iop_sw_cpu_r_masked_intr0___spu_8___bit 24
561#define reg_iop_sw_cpu_r_masked_intr0___spu_9___lsb 25
562#define reg_iop_sw_cpu_r_masked_intr0___spu_9___width 1
563#define reg_iop_sw_cpu_r_masked_intr0___spu_9___bit 25
564#define reg_iop_sw_cpu_r_masked_intr0___spu_10___lsb 26
565#define reg_iop_sw_cpu_r_masked_intr0___spu_10___width 1
566#define reg_iop_sw_cpu_r_masked_intr0___spu_10___bit 26
567#define reg_iop_sw_cpu_r_masked_intr0___spu_11___lsb 27
568#define reg_iop_sw_cpu_r_masked_intr0___spu_11___width 1
569#define reg_iop_sw_cpu_r_masked_intr0___spu_11___bit 27
570#define reg_iop_sw_cpu_r_masked_intr0___spu_12___lsb 28
571#define reg_iop_sw_cpu_r_masked_intr0___spu_12___width 1
572#define reg_iop_sw_cpu_r_masked_intr0___spu_12___bit 28
573#define reg_iop_sw_cpu_r_masked_intr0___spu_13___lsb 29
574#define reg_iop_sw_cpu_r_masked_intr0___spu_13___width 1
575#define reg_iop_sw_cpu_r_masked_intr0___spu_13___bit 29
576#define reg_iop_sw_cpu_r_masked_intr0___spu_14___lsb 30
577#define reg_iop_sw_cpu_r_masked_intr0___spu_14___width 1
578#define reg_iop_sw_cpu_r_masked_intr0___spu_14___bit 30
579#define reg_iop_sw_cpu_r_masked_intr0___spu_15___lsb 31
580#define reg_iop_sw_cpu_r_masked_intr0___spu_15___width 1
581#define reg_iop_sw_cpu_r_masked_intr0___spu_15___bit 31
582#define reg_iop_sw_cpu_r_masked_intr0_offset 88
583
584/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */
585#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0
586#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1
587#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0
588#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1
589#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1
590#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1
591#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2
592#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1
593#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2
594#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3
595#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1
596#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3
597#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4
598#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1
599#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4
600#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5
601#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1
602#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5
603#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6
604#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1
605#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6
606#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7
607#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1
608#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7
609#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8
610#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1
611#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8
612#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9
613#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1
614#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9
615#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10
616#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1
617#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10
618#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11
619#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1
620#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11
621#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12
622#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1
623#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12
624#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13
625#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1
626#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13
627#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14
628#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1
629#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14
630#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15
631#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1
632#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15
633#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___lsb 16
634#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___width 1
635#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___bit 16
636#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___lsb 17
637#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___width 1
638#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___bit 17
639#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___lsb 18
640#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___width 1
641#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___bit 18
642#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___lsb 19
643#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___width 1
644#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___bit 19
645#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___lsb 20
646#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___width 1
647#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___bit 20
648#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___lsb 21
649#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___width 1
650#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___bit 21
651#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___lsb 22
652#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___width 1
653#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___bit 22
654#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___lsb 23
655#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___width 1
656#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___bit 23
657#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___lsb 24
658#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___width 1
659#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___bit 24
660#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___lsb 25
661#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___width 1
662#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___bit 25
663#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___lsb 26
664#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___width 1
665#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___bit 26
666#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___lsb 27
667#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___width 1
668#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___bit 27
669#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___lsb 28
670#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___width 1
671#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___bit 28
672#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___lsb 29
673#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___width 1
674#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___bit 29
675#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___lsb 30
676#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___width 1
677#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___bit 30
678#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___lsb 31
679#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___width 1
680#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___bit 31
681#define reg_iop_sw_cpu_rw_intr1_mask_offset 92
682
683/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */
684#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0
685#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1
686#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0
687#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1
688#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1
689#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1
690#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2
691#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1
692#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2
693#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3
694#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1
695#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3
696#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4
697#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1
698#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4
699#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5
700#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1
701#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5
702#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6
703#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1
704#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6
705#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7
706#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1
707#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7
708#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8
709#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1
710#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8
711#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9
712#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1
713#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9
714#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10
715#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1
716#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10
717#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11
718#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1
719#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11
720#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12
721#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1
722#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12
723#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13
724#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1
725#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13
726#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14
727#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1
728#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14
729#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15
730#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1
731#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15
732#define reg_iop_sw_cpu_rw_ack_intr1_offset 96
733
734/* Register r_intr1, scope iop_sw_cpu, type r */
735#define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0
736#define reg_iop_sw_cpu_r_intr1___mpu_16___width 1
737#define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0
738#define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1
739#define reg_iop_sw_cpu_r_intr1___mpu_17___width 1
740#define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1
741#define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2
742#define reg_iop_sw_cpu_r_intr1___mpu_18___width 1
743#define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2
744#define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3
745#define reg_iop_sw_cpu_r_intr1___mpu_19___width 1
746#define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3
747#define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4
748#define reg_iop_sw_cpu_r_intr1___mpu_20___width 1
749#define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4
750#define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5
751#define reg_iop_sw_cpu_r_intr1___mpu_21___width 1
752#define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5
753#define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6
754#define reg_iop_sw_cpu_r_intr1___mpu_22___width 1
755#define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6
756#define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7
757#define reg_iop_sw_cpu_r_intr1___mpu_23___width 1
758#define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7
759#define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8
760#define reg_iop_sw_cpu_r_intr1___mpu_24___width 1
761#define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8
762#define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9
763#define reg_iop_sw_cpu_r_intr1___mpu_25___width 1
764#define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9
765#define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10
766#define reg_iop_sw_cpu_r_intr1___mpu_26___width 1
767#define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10
768#define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11
769#define reg_iop_sw_cpu_r_intr1___mpu_27___width 1
770#define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11
771#define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12
772#define reg_iop_sw_cpu_r_intr1___mpu_28___width 1
773#define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12
774#define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13
775#define reg_iop_sw_cpu_r_intr1___mpu_29___width 1
776#define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13
777#define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14
778#define reg_iop_sw_cpu_r_intr1___mpu_30___width 1
779#define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14
780#define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15
781#define reg_iop_sw_cpu_r_intr1___mpu_31___width 1
782#define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15
783#define reg_iop_sw_cpu_r_intr1___dmc_in___lsb 16
784#define reg_iop_sw_cpu_r_intr1___dmc_in___width 1
785#define reg_iop_sw_cpu_r_intr1___dmc_in___bit 16
786#define reg_iop_sw_cpu_r_intr1___dmc_out___lsb 17
787#define reg_iop_sw_cpu_r_intr1___dmc_out___width 1
788#define reg_iop_sw_cpu_r_intr1___dmc_out___bit 17
789#define reg_iop_sw_cpu_r_intr1___fifo_in___lsb 18
790#define reg_iop_sw_cpu_r_intr1___fifo_in___width 1
791#define reg_iop_sw_cpu_r_intr1___fifo_in___bit 18
792#define reg_iop_sw_cpu_r_intr1___fifo_out___lsb 19
793#define reg_iop_sw_cpu_r_intr1___fifo_out___width 1
794#define reg_iop_sw_cpu_r_intr1___fifo_out___bit 19
795#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___lsb 20
796#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___width 1
797#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___bit 20
798#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___lsb 21
799#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___width 1
800#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___bit 21
801#define reg_iop_sw_cpu_r_intr1___trigger_grp0___lsb 22
802#define reg_iop_sw_cpu_r_intr1___trigger_grp0___width 1
803#define reg_iop_sw_cpu_r_intr1___trigger_grp0___bit 22
804#define reg_iop_sw_cpu_r_intr1___trigger_grp1___lsb 23
805#define reg_iop_sw_cpu_r_intr1___trigger_grp1___width 1
806#define reg_iop_sw_cpu_r_intr1___trigger_grp1___bit 23
807#define reg_iop_sw_cpu_r_intr1___trigger_grp2___lsb 24
808#define reg_iop_sw_cpu_r_intr1___trigger_grp2___width 1
809#define reg_iop_sw_cpu_r_intr1___trigger_grp2___bit 24
810#define reg_iop_sw_cpu_r_intr1___trigger_grp3___lsb 25
811#define reg_iop_sw_cpu_r_intr1___trigger_grp3___width 1
812#define reg_iop_sw_cpu_r_intr1___trigger_grp3___bit 25
813#define reg_iop_sw_cpu_r_intr1___trigger_grp4___lsb 26
814#define reg_iop_sw_cpu_r_intr1___trigger_grp4___width 1
815#define reg_iop_sw_cpu_r_intr1___trigger_grp4___bit 26
816#define reg_iop_sw_cpu_r_intr1___trigger_grp5___lsb 27
817#define reg_iop_sw_cpu_r_intr1___trigger_grp5___width 1
818#define reg_iop_sw_cpu_r_intr1___trigger_grp5___bit 27
819#define reg_iop_sw_cpu_r_intr1___trigger_grp6___lsb 28
820#define reg_iop_sw_cpu_r_intr1___trigger_grp6___width 1
821#define reg_iop_sw_cpu_r_intr1___trigger_grp6___bit 28
822#define reg_iop_sw_cpu_r_intr1___trigger_grp7___lsb 29
823#define reg_iop_sw_cpu_r_intr1___trigger_grp7___width 1
824#define reg_iop_sw_cpu_r_intr1___trigger_grp7___bit 29
825#define reg_iop_sw_cpu_r_intr1___timer_grp0___lsb 30
826#define reg_iop_sw_cpu_r_intr1___timer_grp0___width 1
827#define reg_iop_sw_cpu_r_intr1___timer_grp0___bit 30
828#define reg_iop_sw_cpu_r_intr1___timer_grp1___lsb 31
829#define reg_iop_sw_cpu_r_intr1___timer_grp1___width 1
830#define reg_iop_sw_cpu_r_intr1___timer_grp1___bit 31
831#define reg_iop_sw_cpu_r_intr1_offset 100
832
833/* Register r_masked_intr1, scope iop_sw_cpu, type r */
834#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0
835#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1
836#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0
837#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1
838#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1
839#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1
840#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2
841#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1
842#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2
843#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3
844#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1
845#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3
846#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4
847#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1
848#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4
849#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5
850#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1
851#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5
852#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6
853#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1
854#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6
855#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7
856#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1
857#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7
858#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8
859#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1
860#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8
861#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9
862#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1
863#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9
864#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10
865#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1
866#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10
867#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11
868#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1
869#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11
870#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12
871#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1
872#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12
873#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13
874#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1
875#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13
876#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14
877#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1
878#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14
879#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15
880#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1
881#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15
882#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___lsb 16
883#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___width 1
884#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___bit 16
885#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___lsb 17
886#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___width 1
887#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___bit 17
888#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___lsb 18
889#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___width 1
890#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___bit 18
891#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___lsb 19
892#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___width 1
893#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___bit 19
894#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___lsb 20
895#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___width 1
896#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___bit 20
897#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___lsb 21
898#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___width 1
899#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___bit 21
900#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___lsb 22
901#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___width 1
902#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___bit 22
903#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___lsb 23
904#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___width 1
905#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___bit 23
906#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___lsb 24
907#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___width 1
908#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___bit 24
909#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___lsb 25
910#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___width 1
911#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___bit 25
912#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___lsb 26
913#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___width 1
914#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___bit 26
915#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___lsb 27
916#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___width 1
917#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___bit 27
918#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___lsb 28
919#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___width 1
920#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___bit 28
921#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___lsb 29
922#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___width 1
923#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___bit 29
924#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___lsb 30
925#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___width 1
926#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___bit 30
927#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___lsb 31
928#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___width 1
929#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___bit 31
930#define reg_iop_sw_cpu_r_masked_intr1_offset 104
931
932
933/* Constants */
934#define regk_iop_sw_cpu_copy 0x00000000
935#define regk_iop_sw_cpu_no 0x00000000
936#define regk_iop_sw_cpu_rd 0x00000002
937#define regk_iop_sw_cpu_reg_copy 0x00000001
938#define regk_iop_sw_cpu_rw_bus_clr_mask_default 0x00000000
939#define regk_iop_sw_cpu_rw_bus_oe_clr_mask_default 0x00000000
940#define regk_iop_sw_cpu_rw_bus_oe_set_mask_default 0x00000000
941#define regk_iop_sw_cpu_rw_bus_set_mask_default 0x00000000
942#define regk_iop_sw_cpu_rw_gio_clr_mask_default 0x00000000
943#define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default 0x00000000
944#define regk_iop_sw_cpu_rw_gio_oe_set_mask_default 0x00000000
945#define regk_iop_sw_cpu_rw_gio_set_mask_default 0x00000000
946#define regk_iop_sw_cpu_rw_intr0_mask_default 0x00000000
947#define regk_iop_sw_cpu_rw_intr1_mask_default 0x00000000
948#define regk_iop_sw_cpu_wr 0x00000003
949#define regk_iop_sw_cpu_yes 0x00000001
950#endif /* __iop_sw_cpu_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_mpu_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_mpu_defs_asm.h
new file mode 100644
index 000000000000..ffcc83b22d21
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_mpu_defs_asm.h
@@ -0,0 +1,1086 @@
1#ifndef __iop_sw_mpu_defs_asm_h
2#define __iop_sw_mpu_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: iop_sw_mpu.r
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_mpu_defs_asm.h iop_sw_mpu.r
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13
14#ifndef REG_FIELD
15#define REG_FIELD( scope, reg, field, value ) \
16 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
17#define REG_FIELD_X_( value, shift ) ((value) << shift)
18#endif
19
20#ifndef REG_STATE
21#define REG_STATE( scope, reg, field, symbolic_value ) \
22 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
23#define REG_STATE_X_( k, shift ) (k << shift)
24#endif
25
26#ifndef REG_MASK
27#define REG_MASK( scope, reg, field ) \
28 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
29#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
30#endif
31
32#ifndef REG_LSB
33#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
34#endif
35
36#ifndef REG_BIT
37#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
38#endif
39
40#ifndef REG_ADDR
41#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
42#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
43#endif
44
45#ifndef REG_ADDR_VECT
46#define REG_ADDR_VECT( scope, inst, reg, index ) \
47 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
48 STRIDE_##scope##_##reg )
49#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
50 ((inst) + offs + (index) * stride)
51#endif
52
53/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */
54#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___lsb 0
55#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___width 2
56#define reg_iop_sw_mpu_rw_sw_cfg_owner_offset 0
57
58/* Register r_spu_trace, scope iop_sw_mpu, type r */
59#define reg_iop_sw_mpu_r_spu_trace_offset 4
60
61/* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */
62#define reg_iop_sw_mpu_r_spu_fsm_trace_offset 8
63
64/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */
65#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___lsb 0
66#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___width 1
67#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___bit 0
68#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___lsb 1
69#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___width 2
70#define reg_iop_sw_mpu_rw_mc_ctrl___size___lsb 3
71#define reg_iop_sw_mpu_rw_mc_ctrl___size___width 3
72#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___lsb 6
73#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___width 1
74#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___bit 6
75#define reg_iop_sw_mpu_rw_mc_ctrl_offset 12
76
77/* Register rw_mc_data, scope iop_sw_mpu, type rw */
78#define reg_iop_sw_mpu_rw_mc_data___val___lsb 0
79#define reg_iop_sw_mpu_rw_mc_data___val___width 32
80#define reg_iop_sw_mpu_rw_mc_data_offset 16
81
82/* Register rw_mc_addr, scope iop_sw_mpu, type rw */
83#define reg_iop_sw_mpu_rw_mc_addr_offset 20
84
85/* Register rs_mc_data, scope iop_sw_mpu, type rs */
86#define reg_iop_sw_mpu_rs_mc_data_offset 24
87
88/* Register r_mc_data, scope iop_sw_mpu, type r */
89#define reg_iop_sw_mpu_r_mc_data_offset 28
90
91/* Register r_mc_stat, scope iop_sw_mpu, type r */
92#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___lsb 0
93#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___width 1
94#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___bit 0
95#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___lsb 1
96#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___width 1
97#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___bit 1
98#define reg_iop_sw_mpu_r_mc_stat___busy_spu___lsb 2
99#define reg_iop_sw_mpu_r_mc_stat___busy_spu___width 1
100#define reg_iop_sw_mpu_r_mc_stat___busy_spu___bit 2
101#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___lsb 3
102#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___width 1
103#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___bit 3
104#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___lsb 4
105#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___width 1
106#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___bit 4
107#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___lsb 5
108#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___width 1
109#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___bit 5
110#define reg_iop_sw_mpu_r_mc_stat_offset 32
111
112/* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */
113#define reg_iop_sw_mpu_rw_bus_clr_mask___byte0___lsb 0
114#define reg_iop_sw_mpu_rw_bus_clr_mask___byte0___width 8
115#define reg_iop_sw_mpu_rw_bus_clr_mask___byte1___lsb 8
116#define reg_iop_sw_mpu_rw_bus_clr_mask___byte1___width 8
117#define reg_iop_sw_mpu_rw_bus_clr_mask___byte2___lsb 16
118#define reg_iop_sw_mpu_rw_bus_clr_mask___byte2___width 8
119#define reg_iop_sw_mpu_rw_bus_clr_mask___byte3___lsb 24
120#define reg_iop_sw_mpu_rw_bus_clr_mask___byte3___width 8
121#define reg_iop_sw_mpu_rw_bus_clr_mask_offset 36
122
123/* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */
124#define reg_iop_sw_mpu_rw_bus_set_mask___byte0___lsb 0
125#define reg_iop_sw_mpu_rw_bus_set_mask___byte0___width 8
126#define reg_iop_sw_mpu_rw_bus_set_mask___byte1___lsb 8
127#define reg_iop_sw_mpu_rw_bus_set_mask___byte1___width 8
128#define reg_iop_sw_mpu_rw_bus_set_mask___byte2___lsb 16
129#define reg_iop_sw_mpu_rw_bus_set_mask___byte2___width 8
130#define reg_iop_sw_mpu_rw_bus_set_mask___byte3___lsb 24
131#define reg_iop_sw_mpu_rw_bus_set_mask___byte3___width 8
132#define reg_iop_sw_mpu_rw_bus_set_mask_offset 40
133
134/* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */
135#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___lsb 0
136#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___width 1
137#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___bit 0
138#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___lsb 1
139#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___width 1
140#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___bit 1
141#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___lsb 2
142#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___width 1
143#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___bit 2
144#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___lsb 3
145#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___width 1
146#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___bit 3
147#define reg_iop_sw_mpu_rw_bus_oe_clr_mask_offset 44
148
149/* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */
150#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___lsb 0
151#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___width 1
152#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___bit 0
153#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___lsb 1
154#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___width 1
155#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___bit 1
156#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___lsb 2
157#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___width 1
158#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___bit 2
159#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___lsb 3
160#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___width 1
161#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___bit 3
162#define reg_iop_sw_mpu_rw_bus_oe_set_mask_offset 48
163
164/* Register r_bus_in, scope iop_sw_mpu, type r */
165#define reg_iop_sw_mpu_r_bus_in_offset 52
166
167/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */
168#define reg_iop_sw_mpu_rw_gio_clr_mask___val___lsb 0
169#define reg_iop_sw_mpu_rw_gio_clr_mask___val___width 32
170#define reg_iop_sw_mpu_rw_gio_clr_mask_offset 56
171
172/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */
173#define reg_iop_sw_mpu_rw_gio_set_mask___val___lsb 0
174#define reg_iop_sw_mpu_rw_gio_set_mask___val___width 32
175#define reg_iop_sw_mpu_rw_gio_set_mask_offset 60
176
177/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */
178#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___lsb 0
179#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___width 32
180#define reg_iop_sw_mpu_rw_gio_oe_clr_mask_offset 64
181
182/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */
183#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___lsb 0
184#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___width 32
185#define reg_iop_sw_mpu_rw_gio_oe_set_mask_offset 68
186
187/* Register r_gio_in, scope iop_sw_mpu, type r */
188#define reg_iop_sw_mpu_r_gio_in_offset 72
189
190/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */
191#define reg_iop_sw_mpu_rw_cpu_intr___intr0___lsb 0
192#define reg_iop_sw_mpu_rw_cpu_intr___intr0___width 1
193#define reg_iop_sw_mpu_rw_cpu_intr___intr0___bit 0
194#define reg_iop_sw_mpu_rw_cpu_intr___intr1___lsb 1
195#define reg_iop_sw_mpu_rw_cpu_intr___intr1___width 1
196#define reg_iop_sw_mpu_rw_cpu_intr___intr1___bit 1
197#define reg_iop_sw_mpu_rw_cpu_intr___intr2___lsb 2
198#define reg_iop_sw_mpu_rw_cpu_intr___intr2___width 1
199#define reg_iop_sw_mpu_rw_cpu_intr___intr2___bit 2
200#define reg_iop_sw_mpu_rw_cpu_intr___intr3___lsb 3
201#define reg_iop_sw_mpu_rw_cpu_intr___intr3___width 1
202#define reg_iop_sw_mpu_rw_cpu_intr___intr3___bit 3
203#define reg_iop_sw_mpu_rw_cpu_intr___intr4___lsb 4
204#define reg_iop_sw_mpu_rw_cpu_intr___intr4___width 1
205#define reg_iop_sw_mpu_rw_cpu_intr___intr4___bit 4
206#define reg_iop_sw_mpu_rw_cpu_intr___intr5___lsb 5
207#define reg_iop_sw_mpu_rw_cpu_intr___intr5___width 1
208#define reg_iop_sw_mpu_rw_cpu_intr___intr5___bit 5
209#define reg_iop_sw_mpu_rw_cpu_intr___intr6___lsb 6
210#define reg_iop_sw_mpu_rw_cpu_intr___intr6___width 1
211#define reg_iop_sw_mpu_rw_cpu_intr___intr6___bit 6
212#define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7
213#define reg_iop_sw_mpu_rw_cpu_intr___intr7___width 1
214#define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7
215#define reg_iop_sw_mpu_rw_cpu_intr___intr8___lsb 8
216#define reg_iop_sw_mpu_rw_cpu_intr___intr8___width 1
217#define reg_iop_sw_mpu_rw_cpu_intr___intr8___bit 8
218#define reg_iop_sw_mpu_rw_cpu_intr___intr9___lsb 9
219#define reg_iop_sw_mpu_rw_cpu_intr___intr9___width 1
220#define reg_iop_sw_mpu_rw_cpu_intr___intr9___bit 9
221#define reg_iop_sw_mpu_rw_cpu_intr___intr10___lsb 10
222#define reg_iop_sw_mpu_rw_cpu_intr___intr10___width 1
223#define reg_iop_sw_mpu_rw_cpu_intr___intr10___bit 10
224#define reg_iop_sw_mpu_rw_cpu_intr___intr11___lsb 11
225#define reg_iop_sw_mpu_rw_cpu_intr___intr11___width 1
226#define reg_iop_sw_mpu_rw_cpu_intr___intr11___bit 11
227#define reg_iop_sw_mpu_rw_cpu_intr___intr12___lsb 12
228#define reg_iop_sw_mpu_rw_cpu_intr___intr12___width 1
229#define reg_iop_sw_mpu_rw_cpu_intr___intr12___bit 12
230#define reg_iop_sw_mpu_rw_cpu_intr___intr13___lsb 13
231#define reg_iop_sw_mpu_rw_cpu_intr___intr13___width 1
232#define reg_iop_sw_mpu_rw_cpu_intr___intr13___bit 13
233#define reg_iop_sw_mpu_rw_cpu_intr___intr14___lsb 14
234#define reg_iop_sw_mpu_rw_cpu_intr___intr14___width 1
235#define reg_iop_sw_mpu_rw_cpu_intr___intr14___bit 14
236#define reg_iop_sw_mpu_rw_cpu_intr___intr15___lsb 15
237#define reg_iop_sw_mpu_rw_cpu_intr___intr15___width 1
238#define reg_iop_sw_mpu_rw_cpu_intr___intr15___bit 15
239#define reg_iop_sw_mpu_rw_cpu_intr___intr16___lsb 16
240#define reg_iop_sw_mpu_rw_cpu_intr___intr16___width 1
241#define reg_iop_sw_mpu_rw_cpu_intr___intr16___bit 16
242#define reg_iop_sw_mpu_rw_cpu_intr___intr17___lsb 17
243#define reg_iop_sw_mpu_rw_cpu_intr___intr17___width 1
244#define reg_iop_sw_mpu_rw_cpu_intr___intr17___bit 17
245#define reg_iop_sw_mpu_rw_cpu_intr___intr18___lsb 18
246#define reg_iop_sw_mpu_rw_cpu_intr___intr18___width 1
247#define reg_iop_sw_mpu_rw_cpu_intr___intr18___bit 18
248#define reg_iop_sw_mpu_rw_cpu_intr___intr19___lsb 19
249#define reg_iop_sw_mpu_rw_cpu_intr___intr19___width 1
250#define reg_iop_sw_mpu_rw_cpu_intr___intr19___bit 19
251#define reg_iop_sw_mpu_rw_cpu_intr___intr20___lsb 20
252#define reg_iop_sw_mpu_rw_cpu_intr___intr20___width 1
253#define reg_iop_sw_mpu_rw_cpu_intr___intr20___bit 20
254#define reg_iop_sw_mpu_rw_cpu_intr___intr21___lsb 21
255#define reg_iop_sw_mpu_rw_cpu_intr___intr21___width 1
256#define reg_iop_sw_mpu_rw_cpu_intr___intr21___bit 21
257#define reg_iop_sw_mpu_rw_cpu_intr___intr22___lsb 22
258#define reg_iop_sw_mpu_rw_cpu_intr___intr22___width 1
259#define reg_iop_sw_mpu_rw_cpu_intr___intr22___bit 22
260#define reg_iop_sw_mpu_rw_cpu_intr___intr23___lsb 23
261#define reg_iop_sw_mpu_rw_cpu_intr___intr23___width 1
262#define reg_iop_sw_mpu_rw_cpu_intr___intr23___bit 23
263#define reg_iop_sw_mpu_rw_cpu_intr___intr24___lsb 24
264#define reg_iop_sw_mpu_rw_cpu_intr___intr24___width 1
265#define reg_iop_sw_mpu_rw_cpu_intr___intr24___bit 24
266#define reg_iop_sw_mpu_rw_cpu_intr___intr25___lsb 25
267#define reg_iop_sw_mpu_rw_cpu_intr___intr25___width 1
268#define reg_iop_sw_mpu_rw_cpu_intr___intr25___bit 25
269#define reg_iop_sw_mpu_rw_cpu_intr___intr26___lsb 26
270#define reg_iop_sw_mpu_rw_cpu_intr___intr26___width 1
271#define reg_iop_sw_mpu_rw_cpu_intr___intr26___bit 26
272#define reg_iop_sw_mpu_rw_cpu_intr___intr27___lsb 27
273#define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1
274#define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27
275#define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28
276#define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1
277#define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28
278#define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29
279#define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1
280#define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29
281#define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30
282#define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1
283#define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30
284#define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31
285#define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1
286#define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31
287#define reg_iop_sw_mpu_rw_cpu_intr_offset 76
288
289/* Register r_cpu_intr, scope iop_sw_mpu, type r */
290#define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0
291#define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1
292#define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0
293#define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1
294#define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1
295#define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1
296#define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2
297#define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1
298#define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2
299#define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3
300#define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1
301#define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3
302#define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4
303#define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1
304#define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4
305#define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5
306#define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1
307#define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5
308#define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6
309#define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1
310#define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6
311#define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7
312#define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1
313#define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7
314#define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8
315#define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1
316#define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8
317#define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9
318#define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1
319#define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9
320#define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10
321#define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1
322#define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10
323#define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11
324#define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1
325#define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11
326#define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12
327#define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1
328#define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12
329#define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13
330#define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1
331#define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13
332#define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14
333#define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1
334#define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14
335#define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15
336#define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1
337#define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15
338#define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16
339#define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1
340#define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16
341#define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17
342#define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1
343#define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17
344#define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18
345#define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1
346#define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18
347#define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19
348#define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1
349#define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19
350#define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20
351#define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1
352#define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20
353#define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21
354#define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1
355#define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21
356#define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22
357#define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1
358#define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22
359#define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23
360#define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1
361#define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23
362#define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24
363#define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1
364#define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24
365#define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25
366#define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1
367#define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25
368#define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26
369#define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1
370#define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26
371#define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27
372#define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1
373#define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27
374#define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28
375#define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1
376#define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28
377#define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29
378#define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1
379#define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29
380#define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30
381#define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1
382#define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30
383#define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31
384#define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1
385#define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31
386#define reg_iop_sw_mpu_r_cpu_intr_offset 80
387
388/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
389#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___lsb 0
390#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___width 1
391#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___bit 0
392#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 1
393#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1
394#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 1
395#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 2
396#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1
397#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 2
398#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___lsb 3
399#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___width 1
400#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___bit 3
401#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___lsb 4
402#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___width 1
403#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___bit 4
404#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 5
405#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1
406#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 5
407#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 6
408#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1
409#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 6
410#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___lsb 7
411#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___width 1
412#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___bit 7
413#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___lsb 8
414#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___width 1
415#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___bit 8
416#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 9
417#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1
418#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 9
419#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___lsb 10
420#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___width 1
421#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___bit 10
422#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___lsb 11
423#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___width 1
424#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___bit 11
425#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___lsb 12
426#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___width 1
427#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___bit 12
428#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 13
429#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1
430#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 13
431#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___lsb 14
432#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___width 1
433#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___bit 14
434#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___lsb 15
435#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___width 1
436#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___bit 15
437#define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 84
438
439/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
440#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___lsb 0
441#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___width 1
442#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___bit 0
443#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___lsb 4
444#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___width 1
445#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___bit 4
446#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___lsb 8
447#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___width 1
448#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___bit 8
449#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___lsb 12
450#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___width 1
451#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___bit 12
452#define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 88
453
454/* Register r_intr_grp0, scope iop_sw_mpu, type r */
455#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___lsb 0
456#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___width 1
457#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___bit 0
458#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 1
459#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1
460#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 1
461#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 2
462#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1
463#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 2
464#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___lsb 3
465#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___width 1
466#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___bit 3
467#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___lsb 4
468#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___width 1
469#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___bit 4
470#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 5
471#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1
472#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 5
473#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 6
474#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1
475#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 6
476#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___lsb 7
477#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___width 1
478#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___bit 7
479#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___lsb 8
480#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___width 1
481#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___bit 8
482#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 9
483#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1
484#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 9
485#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___lsb 10
486#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___width 1
487#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___bit 10
488#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___lsb 11
489#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___width 1
490#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___bit 11
491#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___lsb 12
492#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___width 1
493#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___bit 12
494#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 13
495#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1
496#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 13
497#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___lsb 14
498#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___width 1
499#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___bit 14
500#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___lsb 15
501#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___width 1
502#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___bit 15
503#define reg_iop_sw_mpu_r_intr_grp0_offset 92
504
505/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */
506#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___lsb 0
507#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___width 1
508#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___bit 0
509#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 1
510#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1
511#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 1
512#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 2
513#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1
514#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 2
515#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___lsb 3
516#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___width 1
517#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___bit 3
518#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___lsb 4
519#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___width 1
520#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___bit 4
521#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 5
522#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1
523#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 5
524#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 6
525#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1
526#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 6
527#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___lsb 7
528#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___width 1
529#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___bit 7
530#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___lsb 8
531#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___width 1
532#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___bit 8
533#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 9
534#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1
535#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 9
536#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___lsb 10
537#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___width 1
538#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___bit 10
539#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___lsb 11
540#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___width 1
541#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___bit 11
542#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___lsb 12
543#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___width 1
544#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___bit 12
545#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 13
546#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1
547#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 13
548#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___lsb 14
549#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___width 1
550#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___bit 14
551#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___lsb 15
552#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___width 1
553#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___bit 15
554#define reg_iop_sw_mpu_r_masked_intr_grp0_offset 96
555
556/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
557#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___lsb 0
558#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___width 1
559#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___bit 0
560#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 1
561#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1
562#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 1
563#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___lsb 2
564#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___width 1
565#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___bit 2
566#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___lsb 3
567#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___width 1
568#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___bit 3
569#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___lsb 4
570#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___width 1
571#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___bit 4
572#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 5
573#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1
574#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 5
575#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___lsb 6
576#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___width 1
577#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___bit 6
578#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___lsb 7
579#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___width 1
580#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___bit 7
581#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___lsb 8
582#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___width 1
583#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___bit 8
584#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 9
585#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1
586#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 9
587#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 10
588#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1
589#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 10
590#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___lsb 11
591#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___width 1
592#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___bit 11
593#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___lsb 12
594#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___width 1
595#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___bit 12
596#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 13
597#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1
598#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 13
599#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 14
600#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1
601#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 14
602#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___lsb 15
603#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___width 1
604#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___bit 15
605#define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 100
606
607/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
608#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___lsb 0
609#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___width 1
610#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___bit 0
611#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___lsb 4
612#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___width 1
613#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___bit 4
614#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___lsb 8
615#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___width 1
616#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___bit 8
617#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___lsb 12
618#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___width 1
619#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___bit 12
620#define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 104
621
622/* Register r_intr_grp1, scope iop_sw_mpu, type r */
623#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___lsb 0
624#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___width 1
625#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___bit 0
626#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 1
627#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1
628#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 1
629#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___lsb 2
630#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___width 1
631#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___bit 2
632#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___lsb 3
633#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___width 1
634#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___bit 3
635#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___lsb 4
636#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___width 1
637#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___bit 4
638#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 5
639#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1
640#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 5
641#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___lsb 6
642#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___width 1
643#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___bit 6
644#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___lsb 7
645#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___width 1
646#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___bit 7
647#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___lsb 8
648#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___width 1
649#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___bit 8
650#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 9
651#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1
652#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 9
653#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 10
654#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1
655#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 10
656#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___lsb 11
657#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___width 1
658#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___bit 11
659#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___lsb 12
660#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___width 1
661#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___bit 12
662#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 13
663#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1
664#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 13
665#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 14
666#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1
667#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 14
668#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___lsb 15
669#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___width 1
670#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___bit 15
671#define reg_iop_sw_mpu_r_intr_grp1_offset 108
672
673/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */
674#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___lsb 0
675#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___width 1
676#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___bit 0
677#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 1
678#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1
679#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 1
680#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___lsb 2
681#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___width 1
682#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___bit 2
683#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___lsb 3
684#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___width 1
685#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___bit 3
686#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___lsb 4
687#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___width 1
688#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___bit 4
689#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 5
690#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1
691#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 5
692#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___lsb 6
693#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___width 1
694#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___bit 6
695#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___lsb 7
696#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___width 1
697#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___bit 7
698#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___lsb 8
699#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___width 1
700#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___bit 8
701#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 9
702#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1
703#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 9
704#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 10
705#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1
706#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 10
707#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___lsb 11
708#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___width 1
709#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___bit 11
710#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___lsb 12
711#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___width 1
712#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___bit 12
713#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 13
714#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1
715#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 13
716#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 14
717#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1
718#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 14
719#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___lsb 15
720#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___width 1
721#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___bit 15
722#define reg_iop_sw_mpu_r_masked_intr_grp1_offset 112
723
724/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
725#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___lsb 0
726#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___width 1
727#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___bit 0
728#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 1
729#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1
730#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 1
731#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 2
732#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1
733#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 2
734#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___lsb 3
735#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___width 1
736#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___bit 3
737#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___lsb 4
738#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___width 1
739#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___bit 4
740#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 5
741#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1
742#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 5
743#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 6
744#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1
745#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 6
746#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___lsb 7
747#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___width 1
748#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___bit 7
749#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___lsb 8
750#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___width 1
751#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___bit 8
752#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 9
753#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1
754#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 9
755#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___lsb 10
756#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___width 1
757#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___bit 10
758#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___lsb 11
759#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___width 1
760#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___bit 11
761#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___lsb 12
762#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___width 1
763#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___bit 12
764#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 13
765#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1
766#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 13
767#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___lsb 14
768#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___width 1
769#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___bit 14
770#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___lsb 15
771#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___width 1
772#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___bit 15
773#define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 116
774
775/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
776#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___lsb 0
777#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___width 1
778#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___bit 0
779#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___lsb 4
780#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___width 1
781#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___bit 4
782#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___lsb 8
783#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___width 1
784#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___bit 8
785#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___lsb 12
786#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___width 1
787#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___bit 12
788#define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 120
789
790/* Register r_intr_grp2, scope iop_sw_mpu, type r */
791#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___lsb 0
792#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___width 1
793#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___bit 0
794#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 1
795#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1
796#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 1
797#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 2
798#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1
799#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 2
800#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___lsb 3
801#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___width 1
802#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___bit 3
803#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___lsb 4
804#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___width 1
805#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___bit 4
806#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 5
807#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1
808#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 5
809#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 6
810#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1
811#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 6
812#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___lsb 7
813#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___width 1
814#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___bit 7
815#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___lsb 8
816#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___width 1
817#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___bit 8
818#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___lsb 9
819#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___width 1
820#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___bit 9
821#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___lsb 10
822#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___width 1
823#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___bit 10
824#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___lsb 11
825#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___width 1
826#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___bit 11
827#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___lsb 12
828#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___width 1
829#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___bit 12
830#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___lsb 13
831#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___width 1
832#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___bit 13
833#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___lsb 14
834#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___width 1
835#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___bit 14
836#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___lsb 15
837#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___width 1
838#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___bit 15
839#define reg_iop_sw_mpu_r_intr_grp2_offset 124
840
841/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */
842#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___lsb 0
843#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___width 1
844#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___bit 0
845#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___lsb 1
846#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___width 1
847#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___bit 1
848#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___lsb 2
849#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___width 1
850#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___bit 2
851#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___lsb 3
852#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___width 1
853#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___bit 3
854#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___lsb 4
855#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___width 1
856#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___bit 4
857#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___lsb 5
858#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___width 1
859#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___bit 5
860#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___lsb 6
861#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___width 1
862#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___bit 6
863#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___lsb 7
864#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___width 1
865#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___bit 7
866#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___lsb 8
867#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___width 1
868#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___bit 8
869#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___lsb 9
870#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___width 1
871#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___bit 9
872#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___lsb 10
873#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___width 1
874#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___bit 10
875#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___lsb 11
876#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___width 1
877#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___bit 11
878#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___lsb 12
879#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___width 1
880#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___bit 12
881#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___lsb 13
882#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___width 1
883#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___bit 13
884#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___lsb 14
885#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___width 1
886#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___bit 14
887#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___lsb 15
888#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___width 1
889#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___bit 15
890#define reg_iop_sw_mpu_r_masked_intr_grp2_offset 128
891
892/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
893#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___lsb 0
894#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___width 1
895#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___bit 0
896#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___lsb 1
897#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___width 1
898#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___bit 1
899#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___lsb 2
900#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___width 1
901#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___bit 2
902#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___lsb 3
903#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___width 1
904#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___bit 3
905#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___lsb 4
906#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___width 1
907#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___bit 4
908#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___lsb 5
909#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___width 1
910#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___bit 5
911#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___lsb 6
912#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___width 1
913#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___bit 6
914#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___lsb 7
915#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___width 1
916#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___bit 7
917#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___lsb 8
918#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___width 1
919#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___bit 8
920#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___lsb 9
921#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___width 1
922#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___bit 9
923#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___lsb 10
924#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___width 1
925#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___bit 10
926#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___lsb 11
927#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___width 1
928#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___bit 11
929#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___lsb 12
930#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___width 1
931#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___bit 12
932#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___lsb 13
933#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___width 1
934#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___bit 13
935#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___lsb 14
936#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___width 1
937#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___bit 14
938#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___lsb 15
939#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___width 1
940#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___bit 15
941#define reg_iop_sw_mpu_rw_intr_grp3_mask_offset 132
942
943/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
944#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___lsb 0
945#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___width 1
946#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___bit 0
947#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___lsb 4
948#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___width 1
949#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___bit 4
950#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___lsb 8
951#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___width 1
952#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___bit 8
953#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___lsb 12
954#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___width 1
955#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___bit 12
956#define reg_iop_sw_mpu_rw_ack_intr_grp3_offset 136
957
958/* Register r_intr_grp3, scope iop_sw_mpu, type r */
959#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___lsb 0
960#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___width 1
961#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___bit 0
962#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___lsb 1
963#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___width 1
964#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___bit 1
965#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___lsb 2
966#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___width 1
967#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___bit 2
968#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___lsb 3
969#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___width 1
970#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___bit 3
971#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___lsb 4
972#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___width 1
973#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___bit 4
974#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___lsb 5
975#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___width 1
976#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___bit 5
977#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___lsb 6
978#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___width 1
979#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___bit 6
980#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___lsb 7
981#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___width 1
982#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___bit 7
983#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___lsb 8
984#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___width 1
985#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___bit 8
986#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___lsb 9
987#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___width 1
988#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___bit 9
989#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___lsb 10
990#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___width 1
991#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___bit 10
992#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___lsb 11
993#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___width 1
994#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___bit 11
995#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___lsb 12
996#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___width 1
997#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___bit 12
998#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___lsb 13
999#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___width 1
1000#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___bit 13
1001#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___lsb 14
1002#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___width 1
1003#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___bit 14
1004#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___lsb 15
1005#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___width 1
1006#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___bit 15
1007#define reg_iop_sw_mpu_r_intr_grp3_offset 140
1008
1009/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */
1010#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___lsb 0
1011#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___width 1
1012#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___bit 0
1013#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___lsb 1
1014#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___width 1
1015#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___bit 1
1016#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___lsb 2
1017#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___width 1
1018#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___bit 2
1019#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___lsb 3
1020#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___width 1
1021#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___bit 3
1022#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___lsb 4
1023#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___width 1
1024#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___bit 4
1025#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___lsb 5
1026#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___width 1
1027#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 5
1028#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___lsb 6
1029#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___width 1
1030#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___bit 6
1031#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___lsb 7
1032#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___width 1
1033#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___bit 7
1034#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___lsb 8
1035#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___width 1
1036#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___bit 8
1037#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___lsb 9
1038#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___width 1
1039#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___bit 9
1040#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___lsb 10
1041#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___width 1
1042#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___bit 10
1043#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___lsb 11
1044#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___width 1
1045#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___bit 11
1046#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___lsb 12
1047#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___width 1
1048#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___bit 12
1049#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___lsb 13
1050#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___width 1
1051#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___bit 13
1052#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___lsb 14
1053#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___width 1
1054#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___bit 14
1055#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___lsb 15
1056#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___width 1
1057#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___bit 15
1058#define reg_iop_sw_mpu_r_masked_intr_grp3_offset 144
1059
1060
1061/* Constants */
1062#define regk_iop_sw_mpu_copy 0x00000000
1063#define regk_iop_sw_mpu_cpu 0x00000000
1064#define regk_iop_sw_mpu_mpu 0x00000001
1065#define regk_iop_sw_mpu_no 0x00000000
1066#define regk_iop_sw_mpu_nop 0x00000000
1067#define regk_iop_sw_mpu_rd 0x00000002
1068#define regk_iop_sw_mpu_reg_copy 0x00000001
1069#define regk_iop_sw_mpu_rw_bus_clr_mask_default 0x00000000
1070#define regk_iop_sw_mpu_rw_bus_oe_clr_mask_default 0x00000000
1071#define regk_iop_sw_mpu_rw_bus_oe_set_mask_default 0x00000000
1072#define regk_iop_sw_mpu_rw_bus_set_mask_default 0x00000000
1073#define regk_iop_sw_mpu_rw_gio_clr_mask_default 0x00000000
1074#define regk_iop_sw_mpu_rw_gio_oe_clr_mask_default 0x00000000
1075#define regk_iop_sw_mpu_rw_gio_oe_set_mask_default 0x00000000
1076#define regk_iop_sw_mpu_rw_gio_set_mask_default 0x00000000
1077#define regk_iop_sw_mpu_rw_intr_grp0_mask_default 0x00000000
1078#define regk_iop_sw_mpu_rw_intr_grp1_mask_default 0x00000000
1079#define regk_iop_sw_mpu_rw_intr_grp2_mask_default 0x00000000
1080#define regk_iop_sw_mpu_rw_intr_grp3_mask_default 0x00000000
1081#define regk_iop_sw_mpu_rw_sw_cfg_owner_default 0x00000000
1082#define regk_iop_sw_mpu_set 0x00000001
1083#define regk_iop_sw_mpu_spu 0x00000002
1084#define regk_iop_sw_mpu_wr 0x00000003
1085#define regk_iop_sw_mpu_yes 0x00000001
1086#endif /* __iop_sw_mpu_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_spu_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_spu_defs_asm.h
new file mode 100644
index 000000000000..67a745338087
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_spu_defs_asm.h
@@ -0,0 +1,523 @@
1#ifndef __iop_sw_spu_defs_asm_h
2#define __iop_sw_spu_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: iop_sw_spu.r
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_spu_defs_asm.h iop_sw_spu.r
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13
14#ifndef REG_FIELD
15#define REG_FIELD( scope, reg, field, value ) \
16 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
17#define REG_FIELD_X_( value, shift ) ((value) << shift)
18#endif
19
20#ifndef REG_STATE
21#define REG_STATE( scope, reg, field, symbolic_value ) \
22 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
23#define REG_STATE_X_( k, shift ) (k << shift)
24#endif
25
26#ifndef REG_MASK
27#define REG_MASK( scope, reg, field ) \
28 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
29#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
30#endif
31
32#ifndef REG_LSB
33#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
34#endif
35
36#ifndef REG_BIT
37#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
38#endif
39
40#ifndef REG_ADDR
41#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
42#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
43#endif
44
45#ifndef REG_ADDR_VECT
46#define REG_ADDR_VECT( scope, inst, reg, index ) \
47 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
48 STRIDE_##scope##_##reg )
49#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
50 ((inst) + offs + (index) * stride)
51#endif
52
53/* Register r_mpu_trace, scope iop_sw_spu, type r */
54#define reg_iop_sw_spu_r_mpu_trace_offset 0
55
56/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
57#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0
58#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1
59#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0
60#define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1
61#define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2
62#define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3
63#define reg_iop_sw_spu_rw_mc_ctrl___size___width 3
64#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___lsb 6
65#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___width 1
66#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___bit 6
67#define reg_iop_sw_spu_rw_mc_ctrl_offset 4
68
69/* Register rw_mc_data, scope iop_sw_spu, type rw */
70#define reg_iop_sw_spu_rw_mc_data___val___lsb 0
71#define reg_iop_sw_spu_rw_mc_data___val___width 32
72#define reg_iop_sw_spu_rw_mc_data_offset 8
73
74/* Register rw_mc_addr, scope iop_sw_spu, type rw */
75#define reg_iop_sw_spu_rw_mc_addr_offset 12
76
77/* Register rs_mc_data, scope iop_sw_spu, type rs */
78#define reg_iop_sw_spu_rs_mc_data_offset 16
79
80/* Register r_mc_data, scope iop_sw_spu, type r */
81#define reg_iop_sw_spu_r_mc_data_offset 20
82
83/* Register r_mc_stat, scope iop_sw_spu, type r */
84#define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0
85#define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1
86#define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0
87#define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1
88#define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1
89#define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1
90#define reg_iop_sw_spu_r_mc_stat___busy_spu___lsb 2
91#define reg_iop_sw_spu_r_mc_stat___busy_spu___width 1
92#define reg_iop_sw_spu_r_mc_stat___busy_spu___bit 2
93#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 3
94#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1
95#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 3
96#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 4
97#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1
98#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 4
99#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___lsb 5
100#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___width 1
101#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___bit 5
102#define reg_iop_sw_spu_r_mc_stat_offset 24
103
104/* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */
105#define reg_iop_sw_spu_rw_bus_clr_mask___byte0___lsb 0
106#define reg_iop_sw_spu_rw_bus_clr_mask___byte0___width 8
107#define reg_iop_sw_spu_rw_bus_clr_mask___byte1___lsb 8
108#define reg_iop_sw_spu_rw_bus_clr_mask___byte1___width 8
109#define reg_iop_sw_spu_rw_bus_clr_mask___byte2___lsb 16
110#define reg_iop_sw_spu_rw_bus_clr_mask___byte2___width 8
111#define reg_iop_sw_spu_rw_bus_clr_mask___byte3___lsb 24
112#define reg_iop_sw_spu_rw_bus_clr_mask___byte3___width 8
113#define reg_iop_sw_spu_rw_bus_clr_mask_offset 28
114
115/* Register rw_bus_set_mask, scope iop_sw_spu, type rw */
116#define reg_iop_sw_spu_rw_bus_set_mask___byte0___lsb 0
117#define reg_iop_sw_spu_rw_bus_set_mask___byte0___width 8
118#define reg_iop_sw_spu_rw_bus_set_mask___byte1___lsb 8
119#define reg_iop_sw_spu_rw_bus_set_mask___byte1___width 8
120#define reg_iop_sw_spu_rw_bus_set_mask___byte2___lsb 16
121#define reg_iop_sw_spu_rw_bus_set_mask___byte2___width 8
122#define reg_iop_sw_spu_rw_bus_set_mask___byte3___lsb 24
123#define reg_iop_sw_spu_rw_bus_set_mask___byte3___width 8
124#define reg_iop_sw_spu_rw_bus_set_mask_offset 32
125
126/* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */
127#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___lsb 0
128#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___width 1
129#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___bit 0
130#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___lsb 1
131#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___width 1
132#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___bit 1
133#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___lsb 2
134#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___width 1
135#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___bit 2
136#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___lsb 3
137#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___width 1
138#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___bit 3
139#define reg_iop_sw_spu_rw_bus_oe_clr_mask_offset 36
140
141/* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */
142#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___lsb 0
143#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___width 1
144#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___bit 0
145#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___lsb 1
146#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___width 1
147#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___bit 1
148#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___lsb 2
149#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___width 1
150#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___bit 2
151#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___lsb 3
152#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___width 1
153#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___bit 3
154#define reg_iop_sw_spu_rw_bus_oe_set_mask_offset 40
155
156/* Register r_bus_in, scope iop_sw_spu, type r */
157#define reg_iop_sw_spu_r_bus_in_offset 44
158
159/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
160#define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0
161#define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32
162#define reg_iop_sw_spu_rw_gio_clr_mask_offset 48
163
164/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
165#define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0
166#define reg_iop_sw_spu_rw_gio_set_mask___val___width 32
167#define reg_iop_sw_spu_rw_gio_set_mask_offset 52
168
169/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
170#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0
171#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32
172#define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 56
173
174/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
175#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0
176#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32
177#define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 60
178
179/* Register r_gio_in, scope iop_sw_spu, type r */
180#define reg_iop_sw_spu_r_gio_in_offset 64
181
182/* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */
183#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___lsb 0
184#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___width 8
185#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___lsb 8
186#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___width 8
187#define reg_iop_sw_spu_rw_bus_clr_mask_lo_offset 68
188
189/* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */
190#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___lsb 0
191#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___width 8
192#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___lsb 8
193#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___width 8
194#define reg_iop_sw_spu_rw_bus_clr_mask_hi_offset 72
195
196/* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */
197#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___lsb 0
198#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___width 8
199#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___lsb 8
200#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___width 8
201#define reg_iop_sw_spu_rw_bus_set_mask_lo_offset 76
202
203/* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */
204#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___lsb 0
205#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___width 8
206#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___lsb 8
207#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___width 8
208#define reg_iop_sw_spu_rw_bus_set_mask_hi_offset 80
209
210/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
211#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0
212#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16
213#define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 84
214
215/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
216#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0
217#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16
218#define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 88
219
220/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
221#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0
222#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16
223#define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 92
224
225/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
226#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0
227#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16
228#define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 96
229
230/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
231#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0
232#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16
233#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 100
234
235/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
236#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0
237#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16
238#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 104
239
240/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
241#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0
242#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16
243#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 108
244
245/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
246#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0
247#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16
248#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 112
249
250/* Register rw_cpu_intr, scope iop_sw_spu, type rw */
251#define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0
252#define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1
253#define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0
254#define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1
255#define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1
256#define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1
257#define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2
258#define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1
259#define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2
260#define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3
261#define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1
262#define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3
263#define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4
264#define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1
265#define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4
266#define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5
267#define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1
268#define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5
269#define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6
270#define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1
271#define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6
272#define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7
273#define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1
274#define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7
275#define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8
276#define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1
277#define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8
278#define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9
279#define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1
280#define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9
281#define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10
282#define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1
283#define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10
284#define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11
285#define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1
286#define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11
287#define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12
288#define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1
289#define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12
290#define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13
291#define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1
292#define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13
293#define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14
294#define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1
295#define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14
296#define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15
297#define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1
298#define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15
299#define reg_iop_sw_spu_rw_cpu_intr_offset 116
300
301/* Register r_cpu_intr, scope iop_sw_spu, type r */
302#define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0
303#define reg_iop_sw_spu_r_cpu_intr___intr0___width 1
304#define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0
305#define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1
306#define reg_iop_sw_spu_r_cpu_intr___intr1___width 1
307#define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1
308#define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2
309#define reg_iop_sw_spu_r_cpu_intr___intr2___width 1
310#define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2
311#define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3
312#define reg_iop_sw_spu_r_cpu_intr___intr3___width 1
313#define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3
314#define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4
315#define reg_iop_sw_spu_r_cpu_intr___intr4___width 1
316#define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4
317#define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5
318#define reg_iop_sw_spu_r_cpu_intr___intr5___width 1
319#define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5
320#define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6
321#define reg_iop_sw_spu_r_cpu_intr___intr6___width 1
322#define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6
323#define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7
324#define reg_iop_sw_spu_r_cpu_intr___intr7___width 1
325#define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7
326#define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8
327#define reg_iop_sw_spu_r_cpu_intr___intr8___width 1
328#define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8
329#define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9
330#define reg_iop_sw_spu_r_cpu_intr___intr9___width 1
331#define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9
332#define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10
333#define reg_iop_sw_spu_r_cpu_intr___intr10___width 1
334#define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10
335#define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11
336#define reg_iop_sw_spu_r_cpu_intr___intr11___width 1
337#define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11
338#define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12
339#define reg_iop_sw_spu_r_cpu_intr___intr12___width 1
340#define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12
341#define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13
342#define reg_iop_sw_spu_r_cpu_intr___intr13___width 1
343#define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13
344#define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14
345#define reg_iop_sw_spu_r_cpu_intr___intr14___width 1
346#define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14
347#define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15
348#define reg_iop_sw_spu_r_cpu_intr___intr15___width 1
349#define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15
350#define reg_iop_sw_spu_r_cpu_intr_offset 120
351
352/* Register r_hw_intr, scope iop_sw_spu, type r */
353#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0
354#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1
355#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0
356#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1
357#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1
358#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1
359#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2
360#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1
361#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2
362#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3
363#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1
364#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3
365#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4
366#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1
367#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4
368#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5
369#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1
370#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5
371#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6
372#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1
373#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6
374#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7
375#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1
376#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7
377#define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8
378#define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1
379#define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8
380#define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9
381#define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1
382#define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9
383#define reg_iop_sw_spu_r_hw_intr___fifo_out___lsb 10
384#define reg_iop_sw_spu_r_hw_intr___fifo_out___width 1
385#define reg_iop_sw_spu_r_hw_intr___fifo_out___bit 10
386#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___lsb 11
387#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___width 1
388#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___bit 11
389#define reg_iop_sw_spu_r_hw_intr___fifo_in___lsb 12
390#define reg_iop_sw_spu_r_hw_intr___fifo_in___width 1
391#define reg_iop_sw_spu_r_hw_intr___fifo_in___bit 12
392#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___lsb 13
393#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___width 1
394#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___bit 13
395#define reg_iop_sw_spu_r_hw_intr___dmc_out___lsb 14
396#define reg_iop_sw_spu_r_hw_intr___dmc_out___width 1
397#define reg_iop_sw_spu_r_hw_intr___dmc_out___bit 14
398#define reg_iop_sw_spu_r_hw_intr___dmc_in___lsb 15
399#define reg_iop_sw_spu_r_hw_intr___dmc_in___width 1
400#define reg_iop_sw_spu_r_hw_intr___dmc_in___bit 15
401#define reg_iop_sw_spu_r_hw_intr_offset 124
402
403/* Register rw_mpu_intr, scope iop_sw_spu, type rw */
404#define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0
405#define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1
406#define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0
407#define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1
408#define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1
409#define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1
410#define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2
411#define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1
412#define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2
413#define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3
414#define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1
415#define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3
416#define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4
417#define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1
418#define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4
419#define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5
420#define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1
421#define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5
422#define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6
423#define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1
424#define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6
425#define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7
426#define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1
427#define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7
428#define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8
429#define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1
430#define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8
431#define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9
432#define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1
433#define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9
434#define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10
435#define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1
436#define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10
437#define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11
438#define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1
439#define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11
440#define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12
441#define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1
442#define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12
443#define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13
444#define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1
445#define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13
446#define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14
447#define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1
448#define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14
449#define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15
450#define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1
451#define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15
452#define reg_iop_sw_spu_rw_mpu_intr_offset 128
453
454/* Register r_mpu_intr, scope iop_sw_spu, type r */
455#define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0
456#define reg_iop_sw_spu_r_mpu_intr___intr0___width 1
457#define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0
458#define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1
459#define reg_iop_sw_spu_r_mpu_intr___intr1___width 1
460#define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1
461#define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2
462#define reg_iop_sw_spu_r_mpu_intr___intr2___width 1
463#define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2
464#define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3
465#define reg_iop_sw_spu_r_mpu_intr___intr3___width 1
466#define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3
467#define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4
468#define reg_iop_sw_spu_r_mpu_intr___intr4___width 1
469#define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4
470#define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5
471#define reg_iop_sw_spu_r_mpu_intr___intr5___width 1
472#define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5
473#define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6
474#define reg_iop_sw_spu_r_mpu_intr___intr6___width 1
475#define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6
476#define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7
477#define reg_iop_sw_spu_r_mpu_intr___intr7___width 1
478#define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7
479#define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8
480#define reg_iop_sw_spu_r_mpu_intr___intr8___width 1
481#define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8
482#define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9
483#define reg_iop_sw_spu_r_mpu_intr___intr9___width 1
484#define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9
485#define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10
486#define reg_iop_sw_spu_r_mpu_intr___intr10___width 1
487#define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10
488#define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11
489#define reg_iop_sw_spu_r_mpu_intr___intr11___width 1
490#define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11
491#define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12
492#define reg_iop_sw_spu_r_mpu_intr___intr12___width 1
493#define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12
494#define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13
495#define reg_iop_sw_spu_r_mpu_intr___intr13___width 1
496#define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13
497#define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14
498#define reg_iop_sw_spu_r_mpu_intr___intr14___width 1
499#define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14
500#define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15
501#define reg_iop_sw_spu_r_mpu_intr___intr15___width 1
502#define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15
503#define reg_iop_sw_spu_r_mpu_intr_offset 132
504
505
506/* Constants */
507#define regk_iop_sw_spu_copy 0x00000000
508#define regk_iop_sw_spu_no 0x00000000
509#define regk_iop_sw_spu_nop 0x00000000
510#define regk_iop_sw_spu_rd 0x00000002
511#define regk_iop_sw_spu_reg_copy 0x00000001
512#define regk_iop_sw_spu_rw_bus_clr_mask_default 0x00000000
513#define regk_iop_sw_spu_rw_bus_oe_clr_mask_default 0x00000000
514#define regk_iop_sw_spu_rw_bus_oe_set_mask_default 0x00000000
515#define regk_iop_sw_spu_rw_bus_set_mask_default 0x00000000
516#define regk_iop_sw_spu_rw_gio_clr_mask_default 0x00000000
517#define regk_iop_sw_spu_rw_gio_oe_clr_mask_default 0x00000000
518#define regk_iop_sw_spu_rw_gio_oe_set_mask_default 0x00000000
519#define regk_iop_sw_spu_rw_gio_set_mask_default 0x00000000
520#define regk_iop_sw_spu_set 0x00000001
521#define regk_iop_sw_spu_wr 0x00000003
522#define regk_iop_sw_spu_yes 0x00000001
523#endif /* __iop_sw_spu_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_version_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_version_defs_asm.h
new file mode 100644
index 000000000000..4ad671202af0
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_version_defs_asm.h
@@ -0,0 +1,61 @@
1#ifndef __iop_version_defs_asm_h
2#define __iop_version_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: iop_version.r
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_version_defs_asm.h iop_version.r
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13
14#ifndef REG_FIELD
15#define REG_FIELD( scope, reg, field, value ) \
16 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
17#define REG_FIELD_X_( value, shift ) ((value) << shift)
18#endif
19
20#ifndef REG_STATE
21#define REG_STATE( scope, reg, field, symbolic_value ) \
22 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
23#define REG_STATE_X_( k, shift ) (k << shift)
24#endif
25
26#ifndef REG_MASK
27#define REG_MASK( scope, reg, field ) \
28 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
29#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
30#endif
31
32#ifndef REG_LSB
33#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
34#endif
35
36#ifndef REG_BIT
37#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
38#endif
39
40#ifndef REG_ADDR
41#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
42#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
43#endif
44
45#ifndef REG_ADDR_VECT
46#define REG_ADDR_VECT( scope, inst, reg, index ) \
47 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
48 STRIDE_##scope##_##reg )
49#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
50 ((inst) + offs + (index) * stride)
51#endif
52
53/* Register r_version, scope iop_version, type r */
54#define reg_iop_version_r_version___nr___lsb 0
55#define reg_iop_version_r_version___nr___width 8
56#define reg_iop_version_r_version_offset 0
57
58
59/* Constants */
60#define regk_iop_version_v2_0 0x00000002
61#endif /* __iop_version_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_reg_space.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_reg_space.h
new file mode 100644
index 000000000000..af3196c60a46
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_reg_space.h
@@ -0,0 +1,31 @@
1/* Autogenerated Changes here will be lost!
2 * generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg
3 */
4#define regi_iop_version (regi_iop + 0)
5#define regi_iop_fifo_in_extra (regi_iop + 64)
6#define regi_iop_fifo_out_extra (regi_iop + 128)
7#define regi_iop_trigger_grp0 (regi_iop + 192)
8#define regi_iop_trigger_grp1 (regi_iop + 256)
9#define regi_iop_trigger_grp2 (regi_iop + 320)
10#define regi_iop_trigger_grp3 (regi_iop + 384)
11#define regi_iop_trigger_grp4 (regi_iop + 448)
12#define regi_iop_trigger_grp5 (regi_iop + 512)
13#define regi_iop_trigger_grp6 (regi_iop + 576)
14#define regi_iop_trigger_grp7 (regi_iop + 640)
15#define regi_iop_crc_par (regi_iop + 768)
16#define regi_iop_dmc_in (regi_iop + 896)
17#define regi_iop_dmc_out (regi_iop + 1024)
18#define regi_iop_fifo_in (regi_iop + 1152)
19#define regi_iop_fifo_out (regi_iop + 1280)
20#define regi_iop_scrc_in (regi_iop + 1408)
21#define regi_iop_scrc_out (regi_iop + 1536)
22#define regi_iop_timer_grp0 (regi_iop + 1664)
23#define regi_iop_timer_grp1 (regi_iop + 1792)
24#define regi_iop_sap_in (regi_iop + 2048)
25#define regi_iop_sap_out (regi_iop + 2304)
26#define regi_iop_spu (regi_iop + 2560)
27#define regi_iop_sw_cfg (regi_iop + 2816)
28#define regi_iop_sw_cpu (regi_iop + 3072)
29#define regi_iop_sw_mpu (regi_iop + 3328)
30#define regi_iop_sw_spu (regi_iop + 3584)
31#define regi_iop_mpu (regi_iop + 4096)
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_in_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_in_defs.h
new file mode 100644
index 000000000000..51dde016c03a
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_in_defs.h
@@ -0,0 +1,141 @@
1#ifndef __iop_sap_in_defs_h
2#define __iop_sap_in_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: iop_sap_in.r
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_in_defs.h iop_sap_in.r
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13/* Main access macros */
14#ifndef REG_RD
15#define REG_RD( scope, inst, reg ) \
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
18#endif
19
20#ifndef REG_WR
21#define REG_WR( scope, inst, reg, val ) \
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
24#endif
25
26#ifndef REG_RD_VECT
27#define REG_RD_VECT( scope, inst, reg, index ) \
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
31#endif
32
33#ifndef REG_WR_VECT
34#define REG_WR_VECT( scope, inst, reg, index, val ) \
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
38#endif
39
40#ifndef REG_RD_INT
41#define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
43#endif
44
45#ifndef REG_WR_INT
46#define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
48#endif
49
50#ifndef REG_RD_INT_VECT
51#define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
53 (index) * STRIDE_##scope##_##reg )
54#endif
55
56#ifndef REG_WR_INT_VECT
57#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
59 (index) * STRIDE_##scope##_##reg, (val) )
60#endif
61
62#ifndef REG_TYPE_CONV
63#define REG_TYPE_CONV( type, orgtype, val ) \
64 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
65#endif
66
67#ifndef reg_page_size
68#define reg_page_size 8192
69#endif
70
71#ifndef REG_ADDR
72#define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
74#endif
75
76#ifndef REG_ADDR_VECT
77#define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
79 (index) * STRIDE_##scope##_##reg )
80#endif
81
82/* C-code for register scope iop_sap_in */
83
84#define STRIDE_iop_sap_in_rw_bus_byte 4
85/* Register rw_bus_byte, scope iop_sap_in, type rw */
86typedef struct {
87 unsigned int sync_sel : 2;
88 unsigned int sync_ext_src : 3;
89 unsigned int sync_edge : 2;
90 unsigned int delay : 2;
91 unsigned int dummy1 : 23;
92} reg_iop_sap_in_rw_bus_byte;
93#define REG_RD_ADDR_iop_sap_in_rw_bus_byte 0
94#define REG_WR_ADDR_iop_sap_in_rw_bus_byte 0
95
96#define STRIDE_iop_sap_in_rw_gio 4
97/* Register rw_gio, scope iop_sap_in, type rw */
98typedef struct {
99 unsigned int sync_sel : 2;
100 unsigned int sync_ext_src : 3;
101 unsigned int sync_edge : 2;
102 unsigned int delay : 2;
103 unsigned int logic : 2;
104 unsigned int dummy1 : 21;
105} reg_iop_sap_in_rw_gio;
106#define REG_RD_ADDR_iop_sap_in_rw_gio 16
107#define REG_WR_ADDR_iop_sap_in_rw_gio 16
108
109
110/* Constants */
111enum {
112 regk_iop_sap_in_and = 0x00000002,
113 regk_iop_sap_in_ext_clk200 = 0x00000003,
114 regk_iop_sap_in_gio0 = 0x00000000,
115 regk_iop_sap_in_gio12 = 0x00000003,
116 regk_iop_sap_in_gio16 = 0x00000004,
117 regk_iop_sap_in_gio20 = 0x00000005,
118 regk_iop_sap_in_gio24 = 0x00000006,
119 regk_iop_sap_in_gio28 = 0x00000007,
120 regk_iop_sap_in_gio4 = 0x00000001,
121 regk_iop_sap_in_gio8 = 0x00000002,
122 regk_iop_sap_in_inv = 0x00000001,
123 regk_iop_sap_in_neg = 0x00000002,
124 regk_iop_sap_in_no = 0x00000000,
125 regk_iop_sap_in_no_del_ext_clk200 = 0x00000002,
126 regk_iop_sap_in_none = 0x00000000,
127 regk_iop_sap_in_one = 0x00000001,
128 regk_iop_sap_in_or = 0x00000003,
129 regk_iop_sap_in_pos = 0x00000001,
130 regk_iop_sap_in_pos_neg = 0x00000003,
131 regk_iop_sap_in_rw_bus_byte_default = 0x00000000,
132 regk_iop_sap_in_rw_bus_byte_size = 0x00000004,
133 regk_iop_sap_in_rw_gio_default = 0x00000000,
134 regk_iop_sap_in_rw_gio_size = 0x00000020,
135 regk_iop_sap_in_timer_grp0_tmr3 = 0x00000000,
136 regk_iop_sap_in_timer_grp1_tmr3 = 0x00000001,
137 regk_iop_sap_in_tmr_clk200 = 0x00000001,
138 regk_iop_sap_in_two = 0x00000002,
139 regk_iop_sap_in_two_clk200 = 0x00000000
140};
141#endif /* __iop_sap_in_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_out_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_out_defs.h
new file mode 100644
index 000000000000..5af88baa2ac1
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_out_defs.h
@@ -0,0 +1,231 @@
1#ifndef __iop_sap_out_defs_h
2#define __iop_sap_out_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: iop_sap_out.r
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_out_defs.h iop_sap_out.r
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13/* Main access macros */
14#ifndef REG_RD
15#define REG_RD( scope, inst, reg ) \
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
18#endif
19
20#ifndef REG_WR
21#define REG_WR( scope, inst, reg, val ) \
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
24#endif
25
26#ifndef REG_RD_VECT
27#define REG_RD_VECT( scope, inst, reg, index ) \
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
31#endif
32
33#ifndef REG_WR_VECT
34#define REG_WR_VECT( scope, inst, reg, index, val ) \
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
38#endif
39
40#ifndef REG_RD_INT
41#define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
43#endif
44
45#ifndef REG_WR_INT
46#define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
48#endif
49
50#ifndef REG_RD_INT_VECT
51#define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
53 (index) * STRIDE_##scope##_##reg )
54#endif
55
56#ifndef REG_WR_INT_VECT
57#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
59 (index) * STRIDE_##scope##_##reg, (val) )
60#endif
61
62#ifndef REG_TYPE_CONV
63#define REG_TYPE_CONV( type, orgtype, val ) \
64 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
65#endif
66
67#ifndef reg_page_size
68#define reg_page_size 8192
69#endif
70
71#ifndef REG_ADDR
72#define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
74#endif
75
76#ifndef REG_ADDR_VECT
77#define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
79 (index) * STRIDE_##scope##_##reg )
80#endif
81
82/* C-code for register scope iop_sap_out */
83
84/* Register rw_gen_gated, scope iop_sap_out, type rw */
85typedef struct {
86 unsigned int clk0_src : 2;
87 unsigned int clk0_gate_src : 2;
88 unsigned int clk0_force_src : 3;
89 unsigned int clk1_src : 2;
90 unsigned int clk1_gate_src : 2;
91 unsigned int clk1_force_src : 3;
92 unsigned int dummy1 : 18;
93} reg_iop_sap_out_rw_gen_gated;
94#define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0
95#define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0
96
97/* Register rw_bus, scope iop_sap_out, type rw */
98typedef struct {
99 unsigned int byte0_clk_sel : 2;
100 unsigned int byte0_clk_ext : 2;
101 unsigned int byte0_gated_clk : 1;
102 unsigned int byte0_clk_inv : 1;
103 unsigned int byte0_delay : 1;
104 unsigned int byte1_clk_sel : 2;
105 unsigned int byte1_clk_ext : 2;
106 unsigned int byte1_gated_clk : 1;
107 unsigned int byte1_clk_inv : 1;
108 unsigned int byte1_delay : 1;
109 unsigned int byte2_clk_sel : 2;
110 unsigned int byte2_clk_ext : 2;
111 unsigned int byte2_gated_clk : 1;
112 unsigned int byte2_clk_inv : 1;
113 unsigned int byte2_delay : 1;
114 unsigned int byte3_clk_sel : 2;
115 unsigned int byte3_clk_ext : 2;
116 unsigned int byte3_gated_clk : 1;
117 unsigned int byte3_clk_inv : 1;
118 unsigned int byte3_delay : 1;
119 unsigned int dummy1 : 4;
120} reg_iop_sap_out_rw_bus;
121#define REG_RD_ADDR_iop_sap_out_rw_bus 4
122#define REG_WR_ADDR_iop_sap_out_rw_bus 4
123
124/* Register rw_bus_lo_oe, scope iop_sap_out, type rw */
125typedef struct {
126 unsigned int byte0_clk_sel : 2;
127 unsigned int byte0_clk_ext : 2;
128 unsigned int byte0_gated_clk : 1;
129 unsigned int byte0_clk_inv : 1;
130 unsigned int byte0_delay : 1;
131 unsigned int byte0_logic : 2;
132 unsigned int byte0_logic_src : 2;
133 unsigned int byte1_clk_sel : 2;
134 unsigned int byte1_clk_ext : 2;
135 unsigned int byte1_gated_clk : 1;
136 unsigned int byte1_clk_inv : 1;
137 unsigned int byte1_delay : 1;
138 unsigned int byte1_logic : 2;
139 unsigned int byte1_logic_src : 2;
140 unsigned int dummy1 : 10;
141} reg_iop_sap_out_rw_bus_lo_oe;
142#define REG_RD_ADDR_iop_sap_out_rw_bus_lo_oe 8
143#define REG_WR_ADDR_iop_sap_out_rw_bus_lo_oe 8
144
145/* Register rw_bus_hi_oe, scope iop_sap_out, type rw */
146typedef struct {
147 unsigned int byte2_clk_sel : 2;
148 unsigned int byte2_clk_ext : 2;
149 unsigned int byte2_gated_clk : 1;
150 unsigned int byte2_clk_inv : 1;
151 unsigned int byte2_delay : 1;
152 unsigned int byte2_logic : 2;
153 unsigned int byte2_logic_src : 2;
154 unsigned int byte3_clk_sel : 2;
155 unsigned int byte3_clk_ext : 2;
156 unsigned int byte3_gated_clk : 1;
157 unsigned int byte3_clk_inv : 1;
158 unsigned int byte3_delay : 1;
159 unsigned int byte3_logic : 2;
160 unsigned int byte3_logic_src : 2;
161 unsigned int dummy1 : 10;
162} reg_iop_sap_out_rw_bus_hi_oe;
163#define REG_RD_ADDR_iop_sap_out_rw_bus_hi_oe 12
164#define REG_WR_ADDR_iop_sap_out_rw_bus_hi_oe 12
165
166#define STRIDE_iop_sap_out_rw_gio 4
167/* Register rw_gio, scope iop_sap_out, type rw */
168typedef struct {
169 unsigned int out_clk_sel : 3;
170 unsigned int out_clk_ext : 2;
171 unsigned int out_gated_clk : 1;
172 unsigned int out_clk_inv : 1;
173 unsigned int out_delay : 1;
174 unsigned int out_logic : 2;
175 unsigned int out_logic_src : 2;
176 unsigned int oe_clk_sel : 3;
177 unsigned int oe_clk_ext : 2;
178 unsigned int oe_gated_clk : 1;
179 unsigned int oe_clk_inv : 1;
180 unsigned int oe_delay : 1;
181 unsigned int oe_logic : 2;
182 unsigned int oe_logic_src : 2;
183 unsigned int dummy1 : 8;
184} reg_iop_sap_out_rw_gio;
185#define REG_RD_ADDR_iop_sap_out_rw_gio 16
186#define REG_WR_ADDR_iop_sap_out_rw_gio 16
187
188
189/* Constants */
190enum {
191 regk_iop_sap_out_always = 0x00000001,
192 regk_iop_sap_out_and = 0x00000002,
193 regk_iop_sap_out_clk0 = 0x00000000,
194 regk_iop_sap_out_clk1 = 0x00000001,
195 regk_iop_sap_out_clk12 = 0x00000004,
196 regk_iop_sap_out_clk200 = 0x00000000,
197 regk_iop_sap_out_ext = 0x00000002,
198 regk_iop_sap_out_gated = 0x00000003,
199 regk_iop_sap_out_gio0 = 0x00000000,
200 regk_iop_sap_out_gio1 = 0x00000000,
201 regk_iop_sap_out_gio16 = 0x00000002,
202 regk_iop_sap_out_gio17 = 0x00000002,
203 regk_iop_sap_out_gio24 = 0x00000003,
204 regk_iop_sap_out_gio25 = 0x00000003,
205 regk_iop_sap_out_gio8 = 0x00000001,
206 regk_iop_sap_out_gio9 = 0x00000001,
207 regk_iop_sap_out_gio_out10 = 0x00000005,
208 regk_iop_sap_out_gio_out18 = 0x00000006,
209 regk_iop_sap_out_gio_out2 = 0x00000004,
210 regk_iop_sap_out_gio_out26 = 0x00000007,
211 regk_iop_sap_out_inv = 0x00000001,
212 regk_iop_sap_out_nand = 0x00000003,
213 regk_iop_sap_out_no = 0x00000000,
214 regk_iop_sap_out_none = 0x00000000,
215 regk_iop_sap_out_one = 0x00000001,
216 regk_iop_sap_out_rw_bus_default = 0x00000000,
217 regk_iop_sap_out_rw_bus_hi_oe_default = 0x00000000,
218 regk_iop_sap_out_rw_bus_lo_oe_default = 0x00000000,
219 regk_iop_sap_out_rw_gen_gated_default = 0x00000000,
220 regk_iop_sap_out_rw_gio_default = 0x00000000,
221 regk_iop_sap_out_rw_gio_size = 0x00000020,
222 regk_iop_sap_out_spu_gio6 = 0x00000002,
223 regk_iop_sap_out_spu_gio7 = 0x00000003,
224 regk_iop_sap_out_timer_grp0_tmr2 = 0x00000000,
225 regk_iop_sap_out_timer_grp0_tmr3 = 0x00000001,
226 regk_iop_sap_out_timer_grp1_tmr2 = 0x00000002,
227 regk_iop_sap_out_timer_grp1_tmr3 = 0x00000003,
228 regk_iop_sap_out_tmr200 = 0x00000001,
229 regk_iop_sap_out_yes = 0x00000001
230};
231#endif /* __iop_sap_out_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cfg_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cfg_defs.h
new file mode 100644
index 000000000000..98ac95275a1c
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cfg_defs.h
@@ -0,0 +1,725 @@
1#ifndef __iop_sw_cfg_defs_h
2#define __iop_sw_cfg_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: iop_sw_cfg.r
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cfg_defs.h iop_sw_cfg.r
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13/* Main access macros */
14#ifndef REG_RD
15#define REG_RD( scope, inst, reg ) \
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
18#endif
19
20#ifndef REG_WR
21#define REG_WR( scope, inst, reg, val ) \
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
24#endif
25
26#ifndef REG_RD_VECT
27#define REG_RD_VECT( scope, inst, reg, index ) \
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
31#endif
32
33#ifndef REG_WR_VECT
34#define REG_WR_VECT( scope, inst, reg, index, val ) \
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
38#endif
39
40#ifndef REG_RD_INT
41#define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
43#endif
44
45#ifndef REG_WR_INT
46#define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
48#endif
49
50#ifndef REG_RD_INT_VECT
51#define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
53 (index) * STRIDE_##scope##_##reg )
54#endif
55
56#ifndef REG_WR_INT_VECT
57#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
59 (index) * STRIDE_##scope##_##reg, (val) )
60#endif
61
62#ifndef REG_TYPE_CONV
63#define REG_TYPE_CONV( type, orgtype, val ) \
64 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
65#endif
66
67#ifndef reg_page_size
68#define reg_page_size 8192
69#endif
70
71#ifndef REG_ADDR
72#define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
74#endif
75
76#ifndef REG_ADDR_VECT
77#define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
79 (index) * STRIDE_##scope##_##reg )
80#endif
81
82/* C-code for register scope iop_sw_cfg */
83
84/* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */
85typedef struct {
86 unsigned int cfg : 2;
87 unsigned int dummy1 : 30;
88} reg_iop_sw_cfg_rw_crc_par_owner;
89#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par_owner 0
90#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par_owner 0
91
92/* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */
93typedef struct {
94 unsigned int cfg : 2;
95 unsigned int dummy1 : 30;
96} reg_iop_sw_cfg_rw_dmc_in_owner;
97#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in_owner 4
98#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in_owner 4
99
100/* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */
101typedef struct {
102 unsigned int cfg : 2;
103 unsigned int dummy1 : 30;
104} reg_iop_sw_cfg_rw_dmc_out_owner;
105#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out_owner 8
106#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out_owner 8
107
108/* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */
109typedef struct {
110 unsigned int cfg : 2;
111 unsigned int dummy1 : 30;
112} reg_iop_sw_cfg_rw_fifo_in_owner;
113#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_owner 12
114#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_owner 12
115
116/* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */
117typedef struct {
118 unsigned int cfg : 2;
119 unsigned int dummy1 : 30;
120} reg_iop_sw_cfg_rw_fifo_in_extra_owner;
121#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16
122#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16
123
124/* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */
125typedef struct {
126 unsigned int cfg : 2;
127 unsigned int dummy1 : 30;
128} reg_iop_sw_cfg_rw_fifo_out_owner;
129#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_owner 20
130#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_owner 20
131
132/* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */
133typedef struct {
134 unsigned int cfg : 2;
135 unsigned int dummy1 : 30;
136} reg_iop_sw_cfg_rw_fifo_out_extra_owner;
137#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24
138#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24
139
140/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
141typedef struct {
142 unsigned int cfg : 2;
143 unsigned int dummy1 : 30;
144} reg_iop_sw_cfg_rw_sap_in_owner;
145#define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 28
146#define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 28
147
148/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
149typedef struct {
150 unsigned int cfg : 2;
151 unsigned int dummy1 : 30;
152} reg_iop_sw_cfg_rw_sap_out_owner;
153#define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 32
154#define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 32
155
156/* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */
157typedef struct {
158 unsigned int cfg : 2;
159 unsigned int dummy1 : 30;
160} reg_iop_sw_cfg_rw_scrc_in_owner;
161#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in_owner 36
162#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in_owner 36
163
164/* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */
165typedef struct {
166 unsigned int cfg : 2;
167 unsigned int dummy1 : 30;
168} reg_iop_sw_cfg_rw_scrc_out_owner;
169#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out_owner 40
170#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out_owner 40
171
172/* Register rw_spu_owner, scope iop_sw_cfg, type rw */
173typedef struct {
174 unsigned int cfg : 1;
175 unsigned int dummy1 : 31;
176} reg_iop_sw_cfg_rw_spu_owner;
177#define REG_RD_ADDR_iop_sw_cfg_rw_spu_owner 44
178#define REG_WR_ADDR_iop_sw_cfg_rw_spu_owner 44
179
180/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
181typedef struct {
182 unsigned int cfg : 2;
183 unsigned int dummy1 : 30;
184} reg_iop_sw_cfg_rw_timer_grp0_owner;
185#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48
186#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48
187
188/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
189typedef struct {
190 unsigned int cfg : 2;
191 unsigned int dummy1 : 30;
192} reg_iop_sw_cfg_rw_timer_grp1_owner;
193#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52
194#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52
195
196/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
197typedef struct {
198 unsigned int cfg : 2;
199 unsigned int dummy1 : 30;
200} reg_iop_sw_cfg_rw_trigger_grp0_owner;
201#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56
202#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56
203
204/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
205typedef struct {
206 unsigned int cfg : 2;
207 unsigned int dummy1 : 30;
208} reg_iop_sw_cfg_rw_trigger_grp1_owner;
209#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60
210#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60
211
212/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
213typedef struct {
214 unsigned int cfg : 2;
215 unsigned int dummy1 : 30;
216} reg_iop_sw_cfg_rw_trigger_grp2_owner;
217#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64
218#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64
219
220/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
221typedef struct {
222 unsigned int cfg : 2;
223 unsigned int dummy1 : 30;
224} reg_iop_sw_cfg_rw_trigger_grp3_owner;
225#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68
226#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68
227
228/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
229typedef struct {
230 unsigned int cfg : 2;
231 unsigned int dummy1 : 30;
232} reg_iop_sw_cfg_rw_trigger_grp4_owner;
233#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72
234#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72
235
236/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
237typedef struct {
238 unsigned int cfg : 2;
239 unsigned int dummy1 : 30;
240} reg_iop_sw_cfg_rw_trigger_grp5_owner;
241#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76
242#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76
243
244/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
245typedef struct {
246 unsigned int cfg : 2;
247 unsigned int dummy1 : 30;
248} reg_iop_sw_cfg_rw_trigger_grp6_owner;
249#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80
250#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80
251
252/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
253typedef struct {
254 unsigned int cfg : 2;
255 unsigned int dummy1 : 30;
256} reg_iop_sw_cfg_rw_trigger_grp7_owner;
257#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84
258#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84
259
260/* Register rw_bus_mask, scope iop_sw_cfg, type rw */
261typedef struct {
262 unsigned int byte0 : 8;
263 unsigned int byte1 : 8;
264 unsigned int byte2 : 8;
265 unsigned int byte3 : 8;
266} reg_iop_sw_cfg_rw_bus_mask;
267#define REG_RD_ADDR_iop_sw_cfg_rw_bus_mask 88
268#define REG_WR_ADDR_iop_sw_cfg_rw_bus_mask 88
269
270/* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */
271typedef struct {
272 unsigned int byte0 : 1;
273 unsigned int byte1 : 1;
274 unsigned int byte2 : 1;
275 unsigned int byte3 : 1;
276 unsigned int dummy1 : 28;
277} reg_iop_sw_cfg_rw_bus_oe_mask;
278#define REG_RD_ADDR_iop_sw_cfg_rw_bus_oe_mask 92
279#define REG_WR_ADDR_iop_sw_cfg_rw_bus_oe_mask 92
280
281/* Register rw_gio_mask, scope iop_sw_cfg, type rw */
282typedef struct {
283 unsigned int val : 32;
284} reg_iop_sw_cfg_rw_gio_mask;
285#define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 96
286#define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 96
287
288/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
289typedef struct {
290 unsigned int val : 32;
291} reg_iop_sw_cfg_rw_gio_oe_mask;
292#define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 100
293#define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 100
294
295/* Register rw_pinmapping, scope iop_sw_cfg, type rw */
296typedef struct {
297 unsigned int bus_byte0 : 2;
298 unsigned int bus_byte1 : 2;
299 unsigned int bus_byte2 : 2;
300 unsigned int bus_byte3 : 2;
301 unsigned int gio3_0 : 2;
302 unsigned int gio7_4 : 2;
303 unsigned int gio11_8 : 2;
304 unsigned int gio15_12 : 2;
305 unsigned int gio19_16 : 2;
306 unsigned int gio23_20 : 2;
307 unsigned int gio27_24 : 2;
308 unsigned int gio31_28 : 2;
309 unsigned int dummy1 : 8;
310} reg_iop_sw_cfg_rw_pinmapping;
311#define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 104
312#define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 104
313
314/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
315typedef struct {
316 unsigned int bus_lo : 2;
317 unsigned int bus_hi : 2;
318 unsigned int bus_lo_oe : 2;
319 unsigned int bus_hi_oe : 2;
320 unsigned int dummy1 : 24;
321} reg_iop_sw_cfg_rw_bus_out_cfg;
322#define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 108
323#define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 108
324
325/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
326typedef struct {
327 unsigned int gio0 : 3;
328 unsigned int gio0_oe : 1;
329 unsigned int gio1 : 3;
330 unsigned int gio1_oe : 1;
331 unsigned int gio2 : 3;
332 unsigned int gio2_oe : 1;
333 unsigned int gio3 : 3;
334 unsigned int gio3_oe : 1;
335 unsigned int dummy1 : 16;
336} reg_iop_sw_cfg_rw_gio_out_grp0_cfg;
337#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112
338#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112
339
340/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
341typedef struct {
342 unsigned int gio4 : 3;
343 unsigned int gio4_oe : 1;
344 unsigned int gio5 : 3;
345 unsigned int gio5_oe : 1;
346 unsigned int gio6 : 3;
347 unsigned int gio6_oe : 1;
348 unsigned int gio7 : 3;
349 unsigned int gio7_oe : 1;
350 unsigned int dummy1 : 16;
351} reg_iop_sw_cfg_rw_gio_out_grp1_cfg;
352#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116
353#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116
354
355/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
356typedef struct {
357 unsigned int gio8 : 3;
358 unsigned int gio8_oe : 1;
359 unsigned int gio9 : 3;
360 unsigned int gio9_oe : 1;
361 unsigned int gio10 : 3;
362 unsigned int gio10_oe : 1;
363 unsigned int gio11 : 3;
364 unsigned int gio11_oe : 1;
365 unsigned int dummy1 : 16;
366} reg_iop_sw_cfg_rw_gio_out_grp2_cfg;
367#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120
368#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120
369
370/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */
371typedef struct {
372 unsigned int gio12 : 3;
373 unsigned int gio12_oe : 1;
374 unsigned int gio13 : 3;
375 unsigned int gio13_oe : 1;
376 unsigned int gio14 : 3;
377 unsigned int gio14_oe : 1;
378 unsigned int gio15 : 3;
379 unsigned int gio15_oe : 1;
380 unsigned int dummy1 : 16;
381} reg_iop_sw_cfg_rw_gio_out_grp3_cfg;
382#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124
383#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124
384
385/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */
386typedef struct {
387 unsigned int gio16 : 3;
388 unsigned int gio16_oe : 1;
389 unsigned int gio17 : 3;
390 unsigned int gio17_oe : 1;
391 unsigned int gio18 : 3;
392 unsigned int gio18_oe : 1;
393 unsigned int gio19 : 3;
394 unsigned int gio19_oe : 1;
395 unsigned int dummy1 : 16;
396} reg_iop_sw_cfg_rw_gio_out_grp4_cfg;
397#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128
398#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128
399
400/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */
401typedef struct {
402 unsigned int gio20 : 3;
403 unsigned int gio20_oe : 1;
404 unsigned int gio21 : 3;
405 unsigned int gio21_oe : 1;
406 unsigned int gio22 : 3;
407 unsigned int gio22_oe : 1;
408 unsigned int gio23 : 3;
409 unsigned int gio23_oe : 1;
410 unsigned int dummy1 : 16;
411} reg_iop_sw_cfg_rw_gio_out_grp5_cfg;
412#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132
413#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132
414
415/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */
416typedef struct {
417 unsigned int gio24 : 3;
418 unsigned int gio24_oe : 1;
419 unsigned int gio25 : 3;
420 unsigned int gio25_oe : 1;
421 unsigned int gio26 : 3;
422 unsigned int gio26_oe : 1;
423 unsigned int gio27 : 3;
424 unsigned int gio27_oe : 1;
425 unsigned int dummy1 : 16;
426} reg_iop_sw_cfg_rw_gio_out_grp6_cfg;
427#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136
428#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136
429
430/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */
431typedef struct {
432 unsigned int gio28 : 3;
433 unsigned int gio28_oe : 1;
434 unsigned int gio29 : 3;
435 unsigned int gio29_oe : 1;
436 unsigned int gio30 : 3;
437 unsigned int gio30_oe : 1;
438 unsigned int gio31 : 3;
439 unsigned int gio31_oe : 1;
440 unsigned int dummy1 : 16;
441} reg_iop_sw_cfg_rw_gio_out_grp7_cfg;
442#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140
443#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140
444
445/* Register rw_spu_cfg, scope iop_sw_cfg, type rw */
446typedef struct {
447 unsigned int bus0_in : 1;
448 unsigned int bus1_in : 1;
449 unsigned int dummy1 : 30;
450} reg_iop_sw_cfg_rw_spu_cfg;
451#define REG_RD_ADDR_iop_sw_cfg_rw_spu_cfg 144
452#define REG_WR_ADDR_iop_sw_cfg_rw_spu_cfg 144
453
454/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */
455typedef struct {
456 unsigned int ext_clk : 3;
457 unsigned int tmr0_en : 2;
458 unsigned int tmr1_en : 2;
459 unsigned int tmr2_en : 2;
460 unsigned int tmr3_en : 2;
461 unsigned int tmr0_dis : 2;
462 unsigned int tmr1_dis : 2;
463 unsigned int tmr2_dis : 2;
464 unsigned int tmr3_dis : 2;
465 unsigned int dummy1 : 13;
466} reg_iop_sw_cfg_rw_timer_grp0_cfg;
467#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148
468#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148
469
470/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */
471typedef struct {
472 unsigned int ext_clk : 3;
473 unsigned int tmr0_en : 2;
474 unsigned int tmr1_en : 2;
475 unsigned int tmr2_en : 2;
476 unsigned int tmr3_en : 2;
477 unsigned int tmr0_dis : 2;
478 unsigned int tmr1_dis : 2;
479 unsigned int tmr2_dis : 2;
480 unsigned int tmr3_dis : 2;
481 unsigned int dummy1 : 13;
482} reg_iop_sw_cfg_rw_timer_grp1_cfg;
483#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152
484#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152
485
486/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */
487typedef struct {
488 unsigned int grp0_dis : 1;
489 unsigned int grp0_en : 1;
490 unsigned int grp1_dis : 1;
491 unsigned int grp1_en : 1;
492 unsigned int grp2_dis : 1;
493 unsigned int grp2_en : 1;
494 unsigned int grp3_dis : 1;
495 unsigned int grp3_en : 1;
496 unsigned int grp4_dis : 1;
497 unsigned int grp4_en : 1;
498 unsigned int grp5_dis : 1;
499 unsigned int grp5_en : 1;
500 unsigned int grp6_dis : 1;
501 unsigned int grp6_en : 1;
502 unsigned int grp7_dis : 1;
503 unsigned int grp7_en : 1;
504 unsigned int dummy1 : 16;
505} reg_iop_sw_cfg_rw_trigger_grps_cfg;
506#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156
507#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156
508
509/* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */
510typedef struct {
511 unsigned int out_strb : 4;
512 unsigned int in_src : 2;
513 unsigned int in_size : 3;
514 unsigned int in_last : 2;
515 unsigned int in_strb : 4;
516 unsigned int dummy1 : 17;
517} reg_iop_sw_cfg_rw_pdp_cfg;
518#define REG_RD_ADDR_iop_sw_cfg_rw_pdp_cfg 160
519#define REG_WR_ADDR_iop_sw_cfg_rw_pdp_cfg 160
520
521/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
522typedef struct {
523 unsigned int sdp_out_strb : 3;
524 unsigned int sdp_in_data : 3;
525 unsigned int sdp_in_last : 2;
526 unsigned int sdp_in_strb : 3;
527 unsigned int dummy1 : 21;
528} reg_iop_sw_cfg_rw_sdp_cfg;
529#define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 164
530#define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 164
531
532
533/* Constants */
534enum {
535 regk_iop_sw_cfg_a = 0x00000001,
536 regk_iop_sw_cfg_b = 0x00000002,
537 regk_iop_sw_cfg_bus = 0x00000000,
538 regk_iop_sw_cfg_bus_rot16 = 0x00000002,
539 regk_iop_sw_cfg_bus_rot24 = 0x00000003,
540 regk_iop_sw_cfg_bus_rot8 = 0x00000001,
541 regk_iop_sw_cfg_clk12 = 0x00000000,
542 regk_iop_sw_cfg_cpu = 0x00000000,
543 regk_iop_sw_cfg_gated_clk0 = 0x0000000e,
544 regk_iop_sw_cfg_gated_clk1 = 0x0000000f,
545 regk_iop_sw_cfg_gio0 = 0x00000004,
546 regk_iop_sw_cfg_gio1 = 0x00000001,
547 regk_iop_sw_cfg_gio2 = 0x00000005,
548 regk_iop_sw_cfg_gio3 = 0x00000002,
549 regk_iop_sw_cfg_gio4 = 0x00000006,
550 regk_iop_sw_cfg_gio5 = 0x00000003,
551 regk_iop_sw_cfg_gio6 = 0x00000007,
552 regk_iop_sw_cfg_gio7 = 0x00000004,
553 regk_iop_sw_cfg_gio_in18 = 0x00000002,
554 regk_iop_sw_cfg_gio_in19 = 0x00000003,
555 regk_iop_sw_cfg_gio_in20 = 0x00000004,
556 regk_iop_sw_cfg_gio_in21 = 0x00000005,
557 regk_iop_sw_cfg_gio_in26 = 0x00000006,
558 regk_iop_sw_cfg_gio_in27 = 0x00000007,
559 regk_iop_sw_cfg_gio_in4 = 0x00000000,
560 regk_iop_sw_cfg_gio_in5 = 0x00000001,
561 regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001,
562 regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000002,
563 regk_iop_sw_cfg_last_timer_grp1_tmr3 = 0x00000003,
564 regk_iop_sw_cfg_mpu = 0x00000001,
565 regk_iop_sw_cfg_none = 0x00000000,
566 regk_iop_sw_cfg_pdp_out = 0x00000001,
567 regk_iop_sw_cfg_pdp_out_hi = 0x00000001,
568 regk_iop_sw_cfg_pdp_out_lo = 0x00000000,
569 regk_iop_sw_cfg_rw_bus_mask_default = 0x00000000,
570 regk_iop_sw_cfg_rw_bus_oe_mask_default = 0x00000000,
571 regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000,
572 regk_iop_sw_cfg_rw_crc_par_owner_default = 0x00000000,
573 regk_iop_sw_cfg_rw_dmc_in_owner_default = 0x00000000,
574 regk_iop_sw_cfg_rw_dmc_out_owner_default = 0x00000000,
575 regk_iop_sw_cfg_rw_fifo_in_extra_owner_default = 0x00000000,
576 regk_iop_sw_cfg_rw_fifo_in_owner_default = 0x00000000,
577 regk_iop_sw_cfg_rw_fifo_out_extra_owner_default = 0x00000000,
578 regk_iop_sw_cfg_rw_fifo_out_owner_default = 0x00000000,
579 regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000,
580 regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000,
581 regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000,
582 regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000,
583 regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000,
584 regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000,
585 regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000,
586 regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000,
587 regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000,
588 regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000,
589 regk_iop_sw_cfg_rw_pdp_cfg_default = 0x00000000,
590 regk_iop_sw_cfg_rw_pinmapping_default = 0x00555555,
591 regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000,
592 regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000,
593 regk_iop_sw_cfg_rw_scrc_in_owner_default = 0x00000000,
594 regk_iop_sw_cfg_rw_scrc_out_owner_default = 0x00000000,
595 regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000,
596 regk_iop_sw_cfg_rw_spu_cfg_default = 0x00000000,
597 regk_iop_sw_cfg_rw_spu_owner_default = 0x00000000,
598 regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000,
599 regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000,
600 regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000,
601 regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000,
602 regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000,
603 regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000,
604 regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000,
605 regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000,
606 regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000,
607 regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000,
608 regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000,
609 regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000,
610 regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000,
611 regk_iop_sw_cfg_sdp_out = 0x00000004,
612 regk_iop_sw_cfg_size16 = 0x00000002,
613 regk_iop_sw_cfg_size24 = 0x00000003,
614 regk_iop_sw_cfg_size32 = 0x00000004,
615 regk_iop_sw_cfg_size8 = 0x00000001,
616 regk_iop_sw_cfg_spu = 0x00000002,
617 regk_iop_sw_cfg_spu_bus_out0_hi = 0x00000002,
618 regk_iop_sw_cfg_spu_bus_out0_lo = 0x00000002,
619 regk_iop_sw_cfg_spu_bus_out1_hi = 0x00000003,
620 regk_iop_sw_cfg_spu_bus_out1_lo = 0x00000003,
621 regk_iop_sw_cfg_spu_g0 = 0x00000007,
622 regk_iop_sw_cfg_spu_g1 = 0x00000007,
623 regk_iop_sw_cfg_spu_g2 = 0x00000007,
624 regk_iop_sw_cfg_spu_g3 = 0x00000007,
625 regk_iop_sw_cfg_spu_g4 = 0x00000007,
626 regk_iop_sw_cfg_spu_g5 = 0x00000007,
627 regk_iop_sw_cfg_spu_g6 = 0x00000007,
628 regk_iop_sw_cfg_spu_g7 = 0x00000007,
629 regk_iop_sw_cfg_spu_gio0 = 0x00000000,
630 regk_iop_sw_cfg_spu_gio1 = 0x00000001,
631 regk_iop_sw_cfg_spu_gio5 = 0x00000005,
632 regk_iop_sw_cfg_spu_gio6 = 0x00000006,
633 regk_iop_sw_cfg_spu_gio7 = 0x00000007,
634 regk_iop_sw_cfg_spu_gio_out0 = 0x00000008,
635 regk_iop_sw_cfg_spu_gio_out1 = 0x00000009,
636 regk_iop_sw_cfg_spu_gio_out2 = 0x0000000a,
637 regk_iop_sw_cfg_spu_gio_out3 = 0x0000000b,
638 regk_iop_sw_cfg_spu_gio_out4 = 0x0000000c,
639 regk_iop_sw_cfg_spu_gio_out5 = 0x0000000d,
640 regk_iop_sw_cfg_spu_gio_out6 = 0x0000000e,
641 regk_iop_sw_cfg_spu_gio_out7 = 0x0000000f,
642 regk_iop_sw_cfg_spu_gioout0 = 0x00000000,
643 regk_iop_sw_cfg_spu_gioout1 = 0x00000000,
644 regk_iop_sw_cfg_spu_gioout10 = 0x00000007,
645 regk_iop_sw_cfg_spu_gioout11 = 0x00000007,
646 regk_iop_sw_cfg_spu_gioout12 = 0x00000007,
647 regk_iop_sw_cfg_spu_gioout13 = 0x00000007,
648 regk_iop_sw_cfg_spu_gioout14 = 0x00000007,
649 regk_iop_sw_cfg_spu_gioout15 = 0x00000007,
650 regk_iop_sw_cfg_spu_gioout16 = 0x00000007,
651 regk_iop_sw_cfg_spu_gioout17 = 0x00000007,
652 regk_iop_sw_cfg_spu_gioout18 = 0x00000007,
653 regk_iop_sw_cfg_spu_gioout19 = 0x00000007,
654 regk_iop_sw_cfg_spu_gioout2 = 0x00000001,
655 regk_iop_sw_cfg_spu_gioout20 = 0x00000007,
656 regk_iop_sw_cfg_spu_gioout21 = 0x00000007,
657 regk_iop_sw_cfg_spu_gioout22 = 0x00000007,
658 regk_iop_sw_cfg_spu_gioout23 = 0x00000007,
659 regk_iop_sw_cfg_spu_gioout24 = 0x00000007,
660 regk_iop_sw_cfg_spu_gioout25 = 0x00000007,
661 regk_iop_sw_cfg_spu_gioout26 = 0x00000007,
662 regk_iop_sw_cfg_spu_gioout27 = 0x00000007,
663 regk_iop_sw_cfg_spu_gioout28 = 0x00000007,
664 regk_iop_sw_cfg_spu_gioout29 = 0x00000007,
665 regk_iop_sw_cfg_spu_gioout3 = 0x00000001,
666 regk_iop_sw_cfg_spu_gioout30 = 0x00000007,
667 regk_iop_sw_cfg_spu_gioout31 = 0x00000007,
668 regk_iop_sw_cfg_spu_gioout4 = 0x00000002,
669 regk_iop_sw_cfg_spu_gioout5 = 0x00000002,
670 regk_iop_sw_cfg_spu_gioout6 = 0x00000003,
671 regk_iop_sw_cfg_spu_gioout7 = 0x00000003,
672 regk_iop_sw_cfg_spu_gioout8 = 0x00000007,
673 regk_iop_sw_cfg_spu_gioout9 = 0x00000007,
674 regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001,
675 regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002,
676 regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000003,
677 regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002,
678 regk_iop_sw_cfg_timer_grp0 = 0x00000000,
679 regk_iop_sw_cfg_timer_grp0_rot = 0x00000001,
680 regk_iop_sw_cfg_timer_grp0_strb0 = 0x00000005,
681 regk_iop_sw_cfg_timer_grp0_strb1 = 0x00000005,
682 regk_iop_sw_cfg_timer_grp0_strb2 = 0x00000005,
683 regk_iop_sw_cfg_timer_grp0_strb3 = 0x00000005,
684 regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000002,
685 regk_iop_sw_cfg_timer_grp1 = 0x00000000,
686 regk_iop_sw_cfg_timer_grp1_rot = 0x00000001,
687 regk_iop_sw_cfg_timer_grp1_strb0 = 0x00000006,
688 regk_iop_sw_cfg_timer_grp1_strb1 = 0x00000006,
689 regk_iop_sw_cfg_timer_grp1_strb2 = 0x00000006,
690 regk_iop_sw_cfg_timer_grp1_strb3 = 0x00000006,
691 regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000003,
692 regk_iop_sw_cfg_trig0_0 = 0x00000000,
693 regk_iop_sw_cfg_trig0_1 = 0x00000000,
694 regk_iop_sw_cfg_trig0_2 = 0x00000000,
695 regk_iop_sw_cfg_trig0_3 = 0x00000000,
696 regk_iop_sw_cfg_trig1_0 = 0x00000000,
697 regk_iop_sw_cfg_trig1_1 = 0x00000000,
698 regk_iop_sw_cfg_trig1_2 = 0x00000000,
699 regk_iop_sw_cfg_trig1_3 = 0x00000000,
700 regk_iop_sw_cfg_trig2_0 = 0x00000001,
701 regk_iop_sw_cfg_trig2_1 = 0x00000001,
702 regk_iop_sw_cfg_trig2_2 = 0x00000001,
703 regk_iop_sw_cfg_trig2_3 = 0x00000001,
704 regk_iop_sw_cfg_trig3_0 = 0x00000001,
705 regk_iop_sw_cfg_trig3_1 = 0x00000001,
706 regk_iop_sw_cfg_trig3_2 = 0x00000001,
707 regk_iop_sw_cfg_trig3_3 = 0x00000001,
708 regk_iop_sw_cfg_trig4_0 = 0x00000002,
709 regk_iop_sw_cfg_trig4_1 = 0x00000002,
710 regk_iop_sw_cfg_trig4_2 = 0x00000002,
711 regk_iop_sw_cfg_trig4_3 = 0x00000002,
712 regk_iop_sw_cfg_trig5_0 = 0x00000002,
713 regk_iop_sw_cfg_trig5_1 = 0x00000002,
714 regk_iop_sw_cfg_trig5_2 = 0x00000002,
715 regk_iop_sw_cfg_trig5_3 = 0x00000002,
716 regk_iop_sw_cfg_trig6_0 = 0x00000003,
717 regk_iop_sw_cfg_trig6_1 = 0x00000003,
718 regk_iop_sw_cfg_trig6_2 = 0x00000003,
719 regk_iop_sw_cfg_trig6_3 = 0x00000003,
720 regk_iop_sw_cfg_trig7_0 = 0x00000003,
721 regk_iop_sw_cfg_trig7_1 = 0x00000003,
722 regk_iop_sw_cfg_trig7_2 = 0x00000003,
723 regk_iop_sw_cfg_trig7_3 = 0x00000003
724};
725#endif /* __iop_sw_cfg_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cpu_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cpu_defs.h
new file mode 100644
index 000000000000..a16f556370eb
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cpu_defs.h
@@ -0,0 +1,522 @@
1#ifndef __iop_sw_cpu_defs_h
2#define __iop_sw_cpu_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: iop_sw_cpu.r
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cpu_defs.h iop_sw_cpu.r
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13/* Main access macros */
14#ifndef REG_RD
15#define REG_RD( scope, inst, reg ) \
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
18#endif
19
20#ifndef REG_WR
21#define REG_WR( scope, inst, reg, val ) \
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
24#endif
25
26#ifndef REG_RD_VECT
27#define REG_RD_VECT( scope, inst, reg, index ) \
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
31#endif
32
33#ifndef REG_WR_VECT
34#define REG_WR_VECT( scope, inst, reg, index, val ) \
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
38#endif
39
40#ifndef REG_RD_INT
41#define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
43#endif
44
45#ifndef REG_WR_INT
46#define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
48#endif
49
50#ifndef REG_RD_INT_VECT
51#define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
53 (index) * STRIDE_##scope##_##reg )
54#endif
55
56#ifndef REG_WR_INT_VECT
57#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
59 (index) * STRIDE_##scope##_##reg, (val) )
60#endif
61
62#ifndef REG_TYPE_CONV
63#define REG_TYPE_CONV( type, orgtype, val ) \
64 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
65#endif
66
67#ifndef reg_page_size
68#define reg_page_size 8192
69#endif
70
71#ifndef REG_ADDR
72#define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
74#endif
75
76#ifndef REG_ADDR_VECT
77#define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
79 (index) * STRIDE_##scope##_##reg )
80#endif
81
82/* C-code for register scope iop_sw_cpu */
83
84/* Register r_mpu_trace, scope iop_sw_cpu, type r */
85typedef unsigned int reg_iop_sw_cpu_r_mpu_trace;
86#define REG_RD_ADDR_iop_sw_cpu_r_mpu_trace 0
87
88/* Register r_spu_trace, scope iop_sw_cpu, type r */
89typedef unsigned int reg_iop_sw_cpu_r_spu_trace;
90#define REG_RD_ADDR_iop_sw_cpu_r_spu_trace 4
91
92/* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */
93typedef unsigned int reg_iop_sw_cpu_r_spu_fsm_trace;
94#define REG_RD_ADDR_iop_sw_cpu_r_spu_fsm_trace 8
95
96/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */
97typedef struct {
98 unsigned int keep_owner : 1;
99 unsigned int cmd : 2;
100 unsigned int size : 3;
101 unsigned int wr_spu_mem : 1;
102 unsigned int dummy1 : 25;
103} reg_iop_sw_cpu_rw_mc_ctrl;
104#define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 12
105#define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 12
106
107/* Register rw_mc_data, scope iop_sw_cpu, type rw */
108typedef struct {
109 unsigned int val : 32;
110} reg_iop_sw_cpu_rw_mc_data;
111#define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 16
112#define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 16
113
114/* Register rw_mc_addr, scope iop_sw_cpu, type rw */
115typedef unsigned int reg_iop_sw_cpu_rw_mc_addr;
116#define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 20
117#define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 20
118
119/* Register rs_mc_data, scope iop_sw_cpu, type rs */
120typedef unsigned int reg_iop_sw_cpu_rs_mc_data;
121#define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 24
122
123/* Register r_mc_data, scope iop_sw_cpu, type r */
124typedef unsigned int reg_iop_sw_cpu_r_mc_data;
125#define REG_RD_ADDR_iop_sw_cpu_r_mc_data 28
126
127/* Register r_mc_stat, scope iop_sw_cpu, type r */
128typedef struct {
129 unsigned int busy_cpu : 1;
130 unsigned int busy_mpu : 1;
131 unsigned int busy_spu : 1;
132 unsigned int owned_by_cpu : 1;
133 unsigned int owned_by_mpu : 1;
134 unsigned int owned_by_spu : 1;
135 unsigned int dummy1 : 26;
136} reg_iop_sw_cpu_r_mc_stat;
137#define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 32
138
139/* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */
140typedef struct {
141 unsigned int byte0 : 8;
142 unsigned int byte1 : 8;
143 unsigned int byte2 : 8;
144 unsigned int byte3 : 8;
145} reg_iop_sw_cpu_rw_bus_clr_mask;
146#define REG_RD_ADDR_iop_sw_cpu_rw_bus_clr_mask 36
147#define REG_WR_ADDR_iop_sw_cpu_rw_bus_clr_mask 36
148
149/* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */
150typedef struct {
151 unsigned int byte0 : 8;
152 unsigned int byte1 : 8;
153 unsigned int byte2 : 8;
154 unsigned int byte3 : 8;
155} reg_iop_sw_cpu_rw_bus_set_mask;
156#define REG_RD_ADDR_iop_sw_cpu_rw_bus_set_mask 40
157#define REG_WR_ADDR_iop_sw_cpu_rw_bus_set_mask 40
158
159/* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */
160typedef struct {
161 unsigned int byte0 : 1;
162 unsigned int byte1 : 1;
163 unsigned int byte2 : 1;
164 unsigned int byte3 : 1;
165 unsigned int dummy1 : 28;
166} reg_iop_sw_cpu_rw_bus_oe_clr_mask;
167#define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44
168#define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44
169
170/* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */
171typedef struct {
172 unsigned int byte0 : 1;
173 unsigned int byte1 : 1;
174 unsigned int byte2 : 1;
175 unsigned int byte3 : 1;
176 unsigned int dummy1 : 28;
177} reg_iop_sw_cpu_rw_bus_oe_set_mask;
178#define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48
179#define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48
180
181/* Register r_bus_in, scope iop_sw_cpu, type r */
182typedef unsigned int reg_iop_sw_cpu_r_bus_in;
183#define REG_RD_ADDR_iop_sw_cpu_r_bus_in 52
184
185/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */
186typedef struct {
187 unsigned int val : 32;
188} reg_iop_sw_cpu_rw_gio_clr_mask;
189#define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 56
190#define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 56
191
192/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */
193typedef struct {
194 unsigned int val : 32;
195} reg_iop_sw_cpu_rw_gio_set_mask;
196#define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 60
197#define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 60
198
199/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */
200typedef struct {
201 unsigned int val : 32;
202} reg_iop_sw_cpu_rw_gio_oe_clr_mask;
203#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64
204#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64
205
206/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */
207typedef struct {
208 unsigned int val : 32;
209} reg_iop_sw_cpu_rw_gio_oe_set_mask;
210#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68
211#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68
212
213/* Register r_gio_in, scope iop_sw_cpu, type r */
214typedef unsigned int reg_iop_sw_cpu_r_gio_in;
215#define REG_RD_ADDR_iop_sw_cpu_r_gio_in 72
216
217/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */
218typedef struct {
219 unsigned int mpu_0 : 1;
220 unsigned int mpu_1 : 1;
221 unsigned int mpu_2 : 1;
222 unsigned int mpu_3 : 1;
223 unsigned int mpu_4 : 1;
224 unsigned int mpu_5 : 1;
225 unsigned int mpu_6 : 1;
226 unsigned int mpu_7 : 1;
227 unsigned int mpu_8 : 1;
228 unsigned int mpu_9 : 1;
229 unsigned int mpu_10 : 1;
230 unsigned int mpu_11 : 1;
231 unsigned int mpu_12 : 1;
232 unsigned int mpu_13 : 1;
233 unsigned int mpu_14 : 1;
234 unsigned int mpu_15 : 1;
235 unsigned int spu_0 : 1;
236 unsigned int spu_1 : 1;
237 unsigned int spu_2 : 1;
238 unsigned int spu_3 : 1;
239 unsigned int spu_4 : 1;
240 unsigned int spu_5 : 1;
241 unsigned int spu_6 : 1;
242 unsigned int spu_7 : 1;
243 unsigned int spu_8 : 1;
244 unsigned int spu_9 : 1;
245 unsigned int spu_10 : 1;
246 unsigned int spu_11 : 1;
247 unsigned int spu_12 : 1;
248 unsigned int spu_13 : 1;
249 unsigned int spu_14 : 1;
250 unsigned int spu_15 : 1;
251} reg_iop_sw_cpu_rw_intr0_mask;
252#define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 76
253#define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 76
254
255/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */
256typedef struct {
257 unsigned int mpu_0 : 1;
258 unsigned int mpu_1 : 1;
259 unsigned int mpu_2 : 1;
260 unsigned int mpu_3 : 1;
261 unsigned int mpu_4 : 1;
262 unsigned int mpu_5 : 1;
263 unsigned int mpu_6 : 1;
264 unsigned int mpu_7 : 1;
265 unsigned int mpu_8 : 1;
266 unsigned int mpu_9 : 1;
267 unsigned int mpu_10 : 1;
268 unsigned int mpu_11 : 1;
269 unsigned int mpu_12 : 1;
270 unsigned int mpu_13 : 1;
271 unsigned int mpu_14 : 1;
272 unsigned int mpu_15 : 1;
273 unsigned int spu_0 : 1;
274 unsigned int spu_1 : 1;
275 unsigned int spu_2 : 1;
276 unsigned int spu_3 : 1;
277 unsigned int spu_4 : 1;
278 unsigned int spu_5 : 1;
279 unsigned int spu_6 : 1;
280 unsigned int spu_7 : 1;
281 unsigned int spu_8 : 1;
282 unsigned int spu_9 : 1;
283 unsigned int spu_10 : 1;
284 unsigned int spu_11 : 1;
285 unsigned int spu_12 : 1;
286 unsigned int spu_13 : 1;
287 unsigned int spu_14 : 1;
288 unsigned int spu_15 : 1;
289} reg_iop_sw_cpu_rw_ack_intr0;
290#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 80
291#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 80
292
293/* Register r_intr0, scope iop_sw_cpu, type r */
294typedef struct {
295 unsigned int mpu_0 : 1;
296 unsigned int mpu_1 : 1;
297 unsigned int mpu_2 : 1;
298 unsigned int mpu_3 : 1;
299 unsigned int mpu_4 : 1;
300 unsigned int mpu_5 : 1;
301 unsigned int mpu_6 : 1;
302 unsigned int mpu_7 : 1;
303 unsigned int mpu_8 : 1;
304 unsigned int mpu_9 : 1;
305 unsigned int mpu_10 : 1;
306 unsigned int mpu_11 : 1;
307 unsigned int mpu_12 : 1;
308 unsigned int mpu_13 : 1;
309 unsigned int mpu_14 : 1;
310 unsigned int mpu_15 : 1;
311 unsigned int spu_0 : 1;
312 unsigned int spu_1 : 1;
313 unsigned int spu_2 : 1;
314 unsigned int spu_3 : 1;
315 unsigned int spu_4 : 1;
316 unsigned int spu_5 : 1;
317 unsigned int spu_6 : 1;
318 unsigned int spu_7 : 1;
319 unsigned int spu_8 : 1;
320 unsigned int spu_9 : 1;
321 unsigned int spu_10 : 1;
322 unsigned int spu_11 : 1;
323 unsigned int spu_12 : 1;
324 unsigned int spu_13 : 1;
325 unsigned int spu_14 : 1;
326 unsigned int spu_15 : 1;
327} reg_iop_sw_cpu_r_intr0;
328#define REG_RD_ADDR_iop_sw_cpu_r_intr0 84
329
330/* Register r_masked_intr0, scope iop_sw_cpu, type r */
331typedef struct {
332 unsigned int mpu_0 : 1;
333 unsigned int mpu_1 : 1;
334 unsigned int mpu_2 : 1;
335 unsigned int mpu_3 : 1;
336 unsigned int mpu_4 : 1;
337 unsigned int mpu_5 : 1;
338 unsigned int mpu_6 : 1;
339 unsigned int mpu_7 : 1;
340 unsigned int mpu_8 : 1;
341 unsigned int mpu_9 : 1;
342 unsigned int mpu_10 : 1;
343 unsigned int mpu_11 : 1;
344 unsigned int mpu_12 : 1;
345 unsigned int mpu_13 : 1;
346 unsigned int mpu_14 : 1;
347 unsigned int mpu_15 : 1;
348 unsigned int spu_0 : 1;
349 unsigned int spu_1 : 1;
350 unsigned int spu_2 : 1;
351 unsigned int spu_3 : 1;
352 unsigned int spu_4 : 1;
353 unsigned int spu_5 : 1;
354 unsigned int spu_6 : 1;
355 unsigned int spu_7 : 1;
356 unsigned int spu_8 : 1;
357 unsigned int spu_9 : 1;
358 unsigned int spu_10 : 1;
359 unsigned int spu_11 : 1;
360 unsigned int spu_12 : 1;
361 unsigned int spu_13 : 1;
362 unsigned int spu_14 : 1;
363 unsigned int spu_15 : 1;
364} reg_iop_sw_cpu_r_masked_intr0;
365#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 88
366
367/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */
368typedef struct {
369 unsigned int mpu_16 : 1;
370 unsigned int mpu_17 : 1;
371 unsigned int mpu_18 : 1;
372 unsigned int mpu_19 : 1;
373 unsigned int mpu_20 : 1;
374 unsigned int mpu_21 : 1;
375 unsigned int mpu_22 : 1;
376 unsigned int mpu_23 : 1;
377 unsigned int mpu_24 : 1;
378 unsigned int mpu_25 : 1;
379 unsigned int mpu_26 : 1;
380 unsigned int mpu_27 : 1;
381 unsigned int mpu_28 : 1;
382 unsigned int mpu_29 : 1;
383 unsigned int mpu_30 : 1;
384 unsigned int mpu_31 : 1;
385 unsigned int dmc_in : 1;
386 unsigned int dmc_out : 1;
387 unsigned int fifo_in : 1;
388 unsigned int fifo_out : 1;
389 unsigned int fifo_in_extra : 1;
390 unsigned int fifo_out_extra : 1;
391 unsigned int trigger_grp0 : 1;
392 unsigned int trigger_grp1 : 1;
393 unsigned int trigger_grp2 : 1;
394 unsigned int trigger_grp3 : 1;
395 unsigned int trigger_grp4 : 1;
396 unsigned int trigger_grp5 : 1;
397 unsigned int trigger_grp6 : 1;
398 unsigned int trigger_grp7 : 1;
399 unsigned int timer_grp0 : 1;
400 unsigned int timer_grp1 : 1;
401} reg_iop_sw_cpu_rw_intr1_mask;
402#define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 92
403#define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 92
404
405/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */
406typedef struct {
407 unsigned int mpu_16 : 1;
408 unsigned int mpu_17 : 1;
409 unsigned int mpu_18 : 1;
410 unsigned int mpu_19 : 1;
411 unsigned int mpu_20 : 1;
412 unsigned int mpu_21 : 1;
413 unsigned int mpu_22 : 1;
414 unsigned int mpu_23 : 1;
415 unsigned int mpu_24 : 1;
416 unsigned int mpu_25 : 1;
417 unsigned int mpu_26 : 1;
418 unsigned int mpu_27 : 1;
419 unsigned int mpu_28 : 1;
420 unsigned int mpu_29 : 1;
421 unsigned int mpu_30 : 1;
422 unsigned int mpu_31 : 1;
423 unsigned int dummy1 : 16;
424} reg_iop_sw_cpu_rw_ack_intr1;
425#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 96
426#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 96
427
428/* Register r_intr1, scope iop_sw_cpu, type r */
429typedef struct {
430 unsigned int mpu_16 : 1;
431 unsigned int mpu_17 : 1;
432 unsigned int mpu_18 : 1;
433 unsigned int mpu_19 : 1;
434 unsigned int mpu_20 : 1;
435 unsigned int mpu_21 : 1;
436 unsigned int mpu_22 : 1;
437 unsigned int mpu_23 : 1;
438 unsigned int mpu_24 : 1;
439 unsigned int mpu_25 : 1;
440 unsigned int mpu_26 : 1;
441 unsigned int mpu_27 : 1;
442 unsigned int mpu_28 : 1;
443 unsigned int mpu_29 : 1;
444 unsigned int mpu_30 : 1;
445 unsigned int mpu_31 : 1;
446 unsigned int dmc_in : 1;
447 unsigned int dmc_out : 1;
448 unsigned int fifo_in : 1;
449 unsigned int fifo_out : 1;
450 unsigned int fifo_in_extra : 1;
451 unsigned int fifo_out_extra : 1;
452 unsigned int trigger_grp0 : 1;
453 unsigned int trigger_grp1 : 1;
454 unsigned int trigger_grp2 : 1;
455 unsigned int trigger_grp3 : 1;
456 unsigned int trigger_grp4 : 1;
457 unsigned int trigger_grp5 : 1;
458 unsigned int trigger_grp6 : 1;
459 unsigned int trigger_grp7 : 1;
460 unsigned int timer_grp0 : 1;
461 unsigned int timer_grp1 : 1;
462} reg_iop_sw_cpu_r_intr1;
463#define REG_RD_ADDR_iop_sw_cpu_r_intr1 100
464
465/* Register r_masked_intr1, scope iop_sw_cpu, type r */
466typedef struct {
467 unsigned int mpu_16 : 1;
468 unsigned int mpu_17 : 1;
469 unsigned int mpu_18 : 1;
470 unsigned int mpu_19 : 1;
471 unsigned int mpu_20 : 1;
472 unsigned int mpu_21 : 1;
473 unsigned int mpu_22 : 1;
474 unsigned int mpu_23 : 1;
475 unsigned int mpu_24 : 1;
476 unsigned int mpu_25 : 1;
477 unsigned int mpu_26 : 1;
478 unsigned int mpu_27 : 1;
479 unsigned int mpu_28 : 1;
480 unsigned int mpu_29 : 1;
481 unsigned int mpu_30 : 1;
482 unsigned int mpu_31 : 1;
483 unsigned int dmc_in : 1;
484 unsigned int dmc_out : 1;
485 unsigned int fifo_in : 1;
486 unsigned int fifo_out : 1;
487 unsigned int fifo_in_extra : 1;
488 unsigned int fifo_out_extra : 1;
489 unsigned int trigger_grp0 : 1;
490 unsigned int trigger_grp1 : 1;
491 unsigned int trigger_grp2 : 1;
492 unsigned int trigger_grp3 : 1;
493 unsigned int trigger_grp4 : 1;
494 unsigned int trigger_grp5 : 1;
495 unsigned int trigger_grp6 : 1;
496 unsigned int trigger_grp7 : 1;
497 unsigned int timer_grp0 : 1;
498 unsigned int timer_grp1 : 1;
499} reg_iop_sw_cpu_r_masked_intr1;
500#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 104
501
502
503/* Constants */
504enum {
505 regk_iop_sw_cpu_copy = 0x00000000,
506 regk_iop_sw_cpu_no = 0x00000000,
507 regk_iop_sw_cpu_rd = 0x00000002,
508 regk_iop_sw_cpu_reg_copy = 0x00000001,
509 regk_iop_sw_cpu_rw_bus_clr_mask_default = 0x00000000,
510 regk_iop_sw_cpu_rw_bus_oe_clr_mask_default = 0x00000000,
511 regk_iop_sw_cpu_rw_bus_oe_set_mask_default = 0x00000000,
512 regk_iop_sw_cpu_rw_bus_set_mask_default = 0x00000000,
513 regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000,
514 regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000,
515 regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000,
516 regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000,
517 regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000,
518 regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000,
519 regk_iop_sw_cpu_wr = 0x00000003,
520 regk_iop_sw_cpu_yes = 0x00000001
521};
522#endif /* __iop_sw_cpu_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_mpu_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_mpu_defs.h
new file mode 100644
index 000000000000..a2e4e1a33e57
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_mpu_defs.h
@@ -0,0 +1,648 @@
1#ifndef __iop_sw_mpu_defs_h
2#define __iop_sw_mpu_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: iop_sw_mpu.r
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_mpu_defs.h iop_sw_mpu.r
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13/* Main access macros */
14#ifndef REG_RD
15#define REG_RD( scope, inst, reg ) \
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
18#endif
19
20#ifndef REG_WR
21#define REG_WR( scope, inst, reg, val ) \
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
24#endif
25
26#ifndef REG_RD_VECT
27#define REG_RD_VECT( scope, inst, reg, index ) \
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
31#endif
32
33#ifndef REG_WR_VECT
34#define REG_WR_VECT( scope, inst, reg, index, val ) \
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
38#endif
39
40#ifndef REG_RD_INT
41#define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
43#endif
44
45#ifndef REG_WR_INT
46#define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
48#endif
49
50#ifndef REG_RD_INT_VECT
51#define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
53 (index) * STRIDE_##scope##_##reg )
54#endif
55
56#ifndef REG_WR_INT_VECT
57#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
59 (index) * STRIDE_##scope##_##reg, (val) )
60#endif
61
62#ifndef REG_TYPE_CONV
63#define REG_TYPE_CONV( type, orgtype, val ) \
64 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
65#endif
66
67#ifndef reg_page_size
68#define reg_page_size 8192
69#endif
70
71#ifndef REG_ADDR
72#define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
74#endif
75
76#ifndef REG_ADDR_VECT
77#define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
79 (index) * STRIDE_##scope##_##reg )
80#endif
81
82/* C-code for register scope iop_sw_mpu */
83
84/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */
85typedef struct {
86 unsigned int cfg : 2;
87 unsigned int dummy1 : 30;
88} reg_iop_sw_mpu_rw_sw_cfg_owner;
89#define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
90#define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
91
92/* Register r_spu_trace, scope iop_sw_mpu, type r */
93typedef unsigned int reg_iop_sw_mpu_r_spu_trace;
94#define REG_RD_ADDR_iop_sw_mpu_r_spu_trace 4
95
96/* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */
97typedef unsigned int reg_iop_sw_mpu_r_spu_fsm_trace;
98#define REG_RD_ADDR_iop_sw_mpu_r_spu_fsm_trace 8
99
100/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */
101typedef struct {
102 unsigned int keep_owner : 1;
103 unsigned int cmd : 2;
104 unsigned int size : 3;
105 unsigned int wr_spu_mem : 1;
106 unsigned int dummy1 : 25;
107} reg_iop_sw_mpu_rw_mc_ctrl;
108#define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 12
109#define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 12
110
111/* Register rw_mc_data, scope iop_sw_mpu, type rw */
112typedef struct {
113 unsigned int val : 32;
114} reg_iop_sw_mpu_rw_mc_data;
115#define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 16
116#define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 16
117
118/* Register rw_mc_addr, scope iop_sw_mpu, type rw */
119typedef unsigned int reg_iop_sw_mpu_rw_mc_addr;
120#define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 20
121#define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 20
122
123/* Register rs_mc_data, scope iop_sw_mpu, type rs */
124typedef unsigned int reg_iop_sw_mpu_rs_mc_data;
125#define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 24
126
127/* Register r_mc_data, scope iop_sw_mpu, type r */
128typedef unsigned int reg_iop_sw_mpu_r_mc_data;
129#define REG_RD_ADDR_iop_sw_mpu_r_mc_data 28
130
131/* Register r_mc_stat, scope iop_sw_mpu, type r */
132typedef struct {
133 unsigned int busy_cpu : 1;
134 unsigned int busy_mpu : 1;
135 unsigned int busy_spu : 1;
136 unsigned int owned_by_cpu : 1;
137 unsigned int owned_by_mpu : 1;
138 unsigned int owned_by_spu : 1;
139 unsigned int dummy1 : 26;
140} reg_iop_sw_mpu_r_mc_stat;
141#define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 32
142
143/* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */
144typedef struct {
145 unsigned int byte0 : 8;
146 unsigned int byte1 : 8;
147 unsigned int byte2 : 8;
148 unsigned int byte3 : 8;
149} reg_iop_sw_mpu_rw_bus_clr_mask;
150#define REG_RD_ADDR_iop_sw_mpu_rw_bus_clr_mask 36
151#define REG_WR_ADDR_iop_sw_mpu_rw_bus_clr_mask 36
152
153/* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */
154typedef struct {
155 unsigned int byte0 : 8;
156 unsigned int byte1 : 8;
157 unsigned int byte2 : 8;
158 unsigned int byte3 : 8;
159} reg_iop_sw_mpu_rw_bus_set_mask;
160#define REG_RD_ADDR_iop_sw_mpu_rw_bus_set_mask 40
161#define REG_WR_ADDR_iop_sw_mpu_rw_bus_set_mask 40
162
163/* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */
164typedef struct {
165 unsigned int byte0 : 1;
166 unsigned int byte1 : 1;
167 unsigned int byte2 : 1;
168 unsigned int byte3 : 1;
169 unsigned int dummy1 : 28;
170} reg_iop_sw_mpu_rw_bus_oe_clr_mask;
171#define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44
172#define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44
173
174/* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */
175typedef struct {
176 unsigned int byte0 : 1;
177 unsigned int byte1 : 1;
178 unsigned int byte2 : 1;
179 unsigned int byte3 : 1;
180 unsigned int dummy1 : 28;
181} reg_iop_sw_mpu_rw_bus_oe_set_mask;
182#define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48
183#define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48
184
185/* Register r_bus_in, scope iop_sw_mpu, type r */
186typedef unsigned int reg_iop_sw_mpu_r_bus_in;
187#define REG_RD_ADDR_iop_sw_mpu_r_bus_in 52
188
189/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */
190typedef struct {
191 unsigned int val : 32;
192} reg_iop_sw_mpu_rw_gio_clr_mask;
193#define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 56
194#define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 56
195
196/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */
197typedef struct {
198 unsigned int val : 32;
199} reg_iop_sw_mpu_rw_gio_set_mask;
200#define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 60
201#define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 60
202
203/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */
204typedef struct {
205 unsigned int val : 32;
206} reg_iop_sw_mpu_rw_gio_oe_clr_mask;
207#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64
208#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64
209
210/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */
211typedef struct {
212 unsigned int val : 32;
213} reg_iop_sw_mpu_rw_gio_oe_set_mask;
214#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68
215#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68
216
217/* Register r_gio_in, scope iop_sw_mpu, type r */
218typedef unsigned int reg_iop_sw_mpu_r_gio_in;
219#define REG_RD_ADDR_iop_sw_mpu_r_gio_in 72
220
221/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */
222typedef struct {
223 unsigned int intr0 : 1;
224 unsigned int intr1 : 1;
225 unsigned int intr2 : 1;
226 unsigned int intr3 : 1;
227 unsigned int intr4 : 1;
228 unsigned int intr5 : 1;
229 unsigned int intr6 : 1;
230 unsigned int intr7 : 1;
231 unsigned int intr8 : 1;
232 unsigned int intr9 : 1;
233 unsigned int intr10 : 1;
234 unsigned int intr11 : 1;
235 unsigned int intr12 : 1;
236 unsigned int intr13 : 1;
237 unsigned int intr14 : 1;
238 unsigned int intr15 : 1;
239 unsigned int intr16 : 1;
240 unsigned int intr17 : 1;
241 unsigned int intr18 : 1;
242 unsigned int intr19 : 1;
243 unsigned int intr20 : 1;
244 unsigned int intr21 : 1;
245 unsigned int intr22 : 1;
246 unsigned int intr23 : 1;
247 unsigned int intr24 : 1;
248 unsigned int intr25 : 1;
249 unsigned int intr26 : 1;
250 unsigned int intr27 : 1;
251 unsigned int intr28 : 1;
252 unsigned int intr29 : 1;
253 unsigned int intr30 : 1;
254 unsigned int intr31 : 1;
255} reg_iop_sw_mpu_rw_cpu_intr;
256#define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 76
257#define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 76
258
259/* Register r_cpu_intr, scope iop_sw_mpu, type r */
260typedef struct {
261 unsigned int intr0 : 1;
262 unsigned int intr1 : 1;
263 unsigned int intr2 : 1;
264 unsigned int intr3 : 1;
265 unsigned int intr4 : 1;
266 unsigned int intr5 : 1;
267 unsigned int intr6 : 1;
268 unsigned int intr7 : 1;
269 unsigned int intr8 : 1;
270 unsigned int intr9 : 1;
271 unsigned int intr10 : 1;
272 unsigned int intr11 : 1;
273 unsigned int intr12 : 1;
274 unsigned int intr13 : 1;
275 unsigned int intr14 : 1;
276 unsigned int intr15 : 1;
277 unsigned int intr16 : 1;
278 unsigned int intr17 : 1;
279 unsigned int intr18 : 1;
280 unsigned int intr19 : 1;
281 unsigned int intr20 : 1;
282 unsigned int intr21 : 1;
283 unsigned int intr22 : 1;
284 unsigned int intr23 : 1;
285 unsigned int intr24 : 1;
286 unsigned int intr25 : 1;
287 unsigned int intr26 : 1;
288 unsigned int intr27 : 1;
289 unsigned int intr28 : 1;
290 unsigned int intr29 : 1;
291 unsigned int intr30 : 1;
292 unsigned int intr31 : 1;
293} reg_iop_sw_mpu_r_cpu_intr;
294#define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 80
295
296/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
297typedef struct {
298 unsigned int spu_intr0 : 1;
299 unsigned int trigger_grp0 : 1;
300 unsigned int timer_grp0 : 1;
301 unsigned int fifo_out : 1;
302 unsigned int spu_intr1 : 1;
303 unsigned int trigger_grp1 : 1;
304 unsigned int timer_grp1 : 1;
305 unsigned int fifo_in : 1;
306 unsigned int spu_intr2 : 1;
307 unsigned int trigger_grp2 : 1;
308 unsigned int fifo_out_extra : 1;
309 unsigned int dmc_out : 1;
310 unsigned int spu_intr3 : 1;
311 unsigned int trigger_grp3 : 1;
312 unsigned int fifo_in_extra : 1;
313 unsigned int dmc_in : 1;
314 unsigned int dummy1 : 16;
315} reg_iop_sw_mpu_rw_intr_grp0_mask;
316#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84
317#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84
318
319/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
320typedef struct {
321 unsigned int spu_intr0 : 1;
322 unsigned int dummy1 : 3;
323 unsigned int spu_intr1 : 1;
324 unsigned int dummy2 : 3;
325 unsigned int spu_intr2 : 1;
326 unsigned int dummy3 : 3;
327 unsigned int spu_intr3 : 1;
328 unsigned int dummy4 : 19;
329} reg_iop_sw_mpu_rw_ack_intr_grp0;
330#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88
331#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88
332
333/* Register r_intr_grp0, scope iop_sw_mpu, type r */
334typedef struct {
335 unsigned int spu_intr0 : 1;
336 unsigned int trigger_grp0 : 1;
337 unsigned int timer_grp0 : 1;
338 unsigned int fifo_out : 1;
339 unsigned int spu_intr1 : 1;
340 unsigned int trigger_grp1 : 1;
341 unsigned int timer_grp1 : 1;
342 unsigned int fifo_in : 1;
343 unsigned int spu_intr2 : 1;
344 unsigned int trigger_grp2 : 1;
345 unsigned int fifo_out_extra : 1;
346 unsigned int dmc_out : 1;
347 unsigned int spu_intr3 : 1;
348 unsigned int trigger_grp3 : 1;
349 unsigned int fifo_in_extra : 1;
350 unsigned int dmc_in : 1;
351 unsigned int dummy1 : 16;
352} reg_iop_sw_mpu_r_intr_grp0;
353#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 92
354
355/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */
356typedef struct {
357 unsigned int spu_intr0 : 1;
358 unsigned int trigger_grp0 : 1;
359 unsigned int timer_grp0 : 1;
360 unsigned int fifo_out : 1;
361 unsigned int spu_intr1 : 1;
362 unsigned int trigger_grp1 : 1;
363 unsigned int timer_grp1 : 1;
364 unsigned int fifo_in : 1;
365 unsigned int spu_intr2 : 1;
366 unsigned int trigger_grp2 : 1;
367 unsigned int fifo_out_extra : 1;
368 unsigned int dmc_out : 1;
369 unsigned int spu_intr3 : 1;
370 unsigned int trigger_grp3 : 1;
371 unsigned int fifo_in_extra : 1;
372 unsigned int dmc_in : 1;
373 unsigned int dummy1 : 16;
374} reg_iop_sw_mpu_r_masked_intr_grp0;
375#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 96
376
377/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
378typedef struct {
379 unsigned int spu_intr4 : 1;
380 unsigned int trigger_grp4 : 1;
381 unsigned int fifo_out_extra : 1;
382 unsigned int dmc_out : 1;
383 unsigned int spu_intr5 : 1;
384 unsigned int trigger_grp5 : 1;
385 unsigned int fifo_in_extra : 1;
386 unsigned int dmc_in : 1;
387 unsigned int spu_intr6 : 1;
388 unsigned int trigger_grp6 : 1;
389 unsigned int timer_grp0 : 1;
390 unsigned int fifo_out : 1;
391 unsigned int spu_intr7 : 1;
392 unsigned int trigger_grp7 : 1;
393 unsigned int timer_grp1 : 1;
394 unsigned int fifo_in : 1;
395 unsigned int dummy1 : 16;
396} reg_iop_sw_mpu_rw_intr_grp1_mask;
397#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100
398#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100
399
400/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
401typedef struct {
402 unsigned int spu_intr4 : 1;
403 unsigned int dummy1 : 3;
404 unsigned int spu_intr5 : 1;
405 unsigned int dummy2 : 3;
406 unsigned int spu_intr6 : 1;
407 unsigned int dummy3 : 3;
408 unsigned int spu_intr7 : 1;
409 unsigned int dummy4 : 19;
410} reg_iop_sw_mpu_rw_ack_intr_grp1;
411#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104
412#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104
413
414/* Register r_intr_grp1, scope iop_sw_mpu, type r */
415typedef struct {
416 unsigned int spu_intr4 : 1;
417 unsigned int trigger_grp4 : 1;
418 unsigned int fifo_out_extra : 1;
419 unsigned int dmc_out : 1;
420 unsigned int spu_intr5 : 1;
421 unsigned int trigger_grp5 : 1;
422 unsigned int fifo_in_extra : 1;
423 unsigned int dmc_in : 1;
424 unsigned int spu_intr6 : 1;
425 unsigned int trigger_grp6 : 1;
426 unsigned int timer_grp0 : 1;
427 unsigned int fifo_out : 1;
428 unsigned int spu_intr7 : 1;
429 unsigned int trigger_grp7 : 1;
430 unsigned int timer_grp1 : 1;
431 unsigned int fifo_in : 1;
432 unsigned int dummy1 : 16;
433} reg_iop_sw_mpu_r_intr_grp1;
434#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 108
435
436/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */
437typedef struct {
438 unsigned int spu_intr4 : 1;
439 unsigned int trigger_grp4 : 1;
440 unsigned int fifo_out_extra : 1;
441 unsigned int dmc_out : 1;
442 unsigned int spu_intr5 : 1;
443 unsigned int trigger_grp5 : 1;
444 unsigned int fifo_in_extra : 1;
445 unsigned int dmc_in : 1;
446 unsigned int spu_intr6 : 1;
447 unsigned int trigger_grp6 : 1;
448 unsigned int timer_grp0 : 1;
449 unsigned int fifo_out : 1;
450 unsigned int spu_intr7 : 1;
451 unsigned int trigger_grp7 : 1;
452 unsigned int timer_grp1 : 1;
453 unsigned int fifo_in : 1;
454 unsigned int dummy1 : 16;
455} reg_iop_sw_mpu_r_masked_intr_grp1;
456#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 112
457
458/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
459typedef struct {
460 unsigned int spu_intr8 : 1;
461 unsigned int trigger_grp0 : 1;
462 unsigned int timer_grp0 : 1;
463 unsigned int fifo_out : 1;
464 unsigned int spu_intr9 : 1;
465 unsigned int trigger_grp1 : 1;
466 unsigned int timer_grp1 : 1;
467 unsigned int fifo_in : 1;
468 unsigned int spu_intr10 : 1;
469 unsigned int trigger_grp2 : 1;
470 unsigned int fifo_out_extra : 1;
471 unsigned int dmc_out : 1;
472 unsigned int spu_intr11 : 1;
473 unsigned int trigger_grp3 : 1;
474 unsigned int fifo_in_extra : 1;
475 unsigned int dmc_in : 1;
476 unsigned int dummy1 : 16;
477} reg_iop_sw_mpu_rw_intr_grp2_mask;
478#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116
479#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116
480
481/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
482typedef struct {
483 unsigned int spu_intr8 : 1;
484 unsigned int dummy1 : 3;
485 unsigned int spu_intr9 : 1;
486 unsigned int dummy2 : 3;
487 unsigned int spu_intr10 : 1;
488 unsigned int dummy3 : 3;
489 unsigned int spu_intr11 : 1;
490 unsigned int dummy4 : 19;
491} reg_iop_sw_mpu_rw_ack_intr_grp2;
492#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120
493#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120
494
495/* Register r_intr_grp2, scope iop_sw_mpu, type r */
496typedef struct {
497 unsigned int spu_intr8 : 1;
498 unsigned int trigger_grp0 : 1;
499 unsigned int timer_grp0 : 1;
500 unsigned int fifo_out : 1;
501 unsigned int spu_intr9 : 1;
502 unsigned int trigger_grp1 : 1;
503 unsigned int timer_grp1 : 1;
504 unsigned int fifo_in : 1;
505 unsigned int spu_intr10 : 1;
506 unsigned int trigger_grp2 : 1;
507 unsigned int fifo_out_extra : 1;
508 unsigned int dmc_out : 1;
509 unsigned int spu_intr11 : 1;
510 unsigned int trigger_grp3 : 1;
511 unsigned int fifo_in_extra : 1;
512 unsigned int dmc_in : 1;
513 unsigned int dummy1 : 16;
514} reg_iop_sw_mpu_r_intr_grp2;
515#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 124
516
517/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */
518typedef struct {
519 unsigned int spu_intr8 : 1;
520 unsigned int trigger_grp0 : 1;
521 unsigned int timer_grp0 : 1;
522 unsigned int fifo_out : 1;
523 unsigned int spu_intr9 : 1;
524 unsigned int trigger_grp1 : 1;
525 unsigned int timer_grp1 : 1;
526 unsigned int fifo_in : 1;
527 unsigned int spu_intr10 : 1;
528 unsigned int trigger_grp2 : 1;
529 unsigned int fifo_out_extra : 1;
530 unsigned int dmc_out : 1;
531 unsigned int spu_intr11 : 1;
532 unsigned int trigger_grp3 : 1;
533 unsigned int fifo_in_extra : 1;
534 unsigned int dmc_in : 1;
535 unsigned int dummy1 : 16;
536} reg_iop_sw_mpu_r_masked_intr_grp2;
537#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 128
538
539/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
540typedef struct {
541 unsigned int spu_intr12 : 1;
542 unsigned int trigger_grp4 : 1;
543 unsigned int fifo_out_extra : 1;
544 unsigned int dmc_out : 1;
545 unsigned int spu_intr13 : 1;
546 unsigned int trigger_grp5 : 1;
547 unsigned int fifo_in_extra : 1;
548 unsigned int dmc_in : 1;
549 unsigned int spu_intr14 : 1;
550 unsigned int trigger_grp6 : 1;
551 unsigned int timer_grp0 : 1;
552 unsigned int fifo_out : 1;
553 unsigned int spu_intr15 : 1;
554 unsigned int trigger_grp7 : 1;
555 unsigned int timer_grp1 : 1;
556 unsigned int fifo_in : 1;
557 unsigned int dummy1 : 16;
558} reg_iop_sw_mpu_rw_intr_grp3_mask;
559#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132
560#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132
561
562/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
563typedef struct {
564 unsigned int spu_intr12 : 1;
565 unsigned int dummy1 : 3;
566 unsigned int spu_intr13 : 1;
567 unsigned int dummy2 : 3;
568 unsigned int spu_intr14 : 1;
569 unsigned int dummy3 : 3;
570 unsigned int spu_intr15 : 1;
571 unsigned int dummy4 : 19;
572} reg_iop_sw_mpu_rw_ack_intr_grp3;
573#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136
574#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136
575
576/* Register r_intr_grp3, scope iop_sw_mpu, type r */
577typedef struct {
578 unsigned int spu_intr12 : 1;
579 unsigned int trigger_grp4 : 1;
580 unsigned int fifo_out_extra : 1;
581 unsigned int dmc_out : 1;
582 unsigned int spu_intr13 : 1;
583 unsigned int trigger_grp5 : 1;
584 unsigned int fifo_in_extra : 1;
585 unsigned int dmc_in : 1;
586 unsigned int spu_intr14 : 1;
587 unsigned int trigger_grp6 : 1;
588 unsigned int timer_grp0 : 1;
589 unsigned int fifo_out : 1;
590 unsigned int spu_intr15 : 1;
591 unsigned int trigger_grp7 : 1;
592 unsigned int timer_grp1 : 1;
593 unsigned int fifo_in : 1;
594 unsigned int dummy1 : 16;
595} reg_iop_sw_mpu_r_intr_grp3;
596#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 140
597
598/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */
599typedef struct {
600 unsigned int spu_intr12 : 1;
601 unsigned int trigger_grp4 : 1;
602 unsigned int fifo_out_extra : 1;
603 unsigned int dmc_out : 1;
604 unsigned int spu_intr13 : 1;
605 unsigned int trigger_grp5 : 1;
606 unsigned int fifo_in_extra : 1;
607 unsigned int dmc_in : 1;
608 unsigned int spu_intr14 : 1;
609 unsigned int trigger_grp6 : 1;
610 unsigned int timer_grp0 : 1;
611 unsigned int fifo_out : 1;
612 unsigned int spu_intr15 : 1;
613 unsigned int trigger_grp7 : 1;
614 unsigned int timer_grp1 : 1;
615 unsigned int fifo_in : 1;
616 unsigned int dummy1 : 16;
617} reg_iop_sw_mpu_r_masked_intr_grp3;
618#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 144
619
620
621/* Constants */
622enum {
623 regk_iop_sw_mpu_copy = 0x00000000,
624 regk_iop_sw_mpu_cpu = 0x00000000,
625 regk_iop_sw_mpu_mpu = 0x00000001,
626 regk_iop_sw_mpu_no = 0x00000000,
627 regk_iop_sw_mpu_nop = 0x00000000,
628 regk_iop_sw_mpu_rd = 0x00000002,
629 regk_iop_sw_mpu_reg_copy = 0x00000001,
630 regk_iop_sw_mpu_rw_bus_clr_mask_default = 0x00000000,
631 regk_iop_sw_mpu_rw_bus_oe_clr_mask_default = 0x00000000,
632 regk_iop_sw_mpu_rw_bus_oe_set_mask_default = 0x00000000,
633 regk_iop_sw_mpu_rw_bus_set_mask_default = 0x00000000,
634 regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000,
635 regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000,
636 regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000,
637 regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000,
638 regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000,
639 regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000,
640 regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000,
641 regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000,
642 regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000,
643 regk_iop_sw_mpu_set = 0x00000001,
644 regk_iop_sw_mpu_spu = 0x00000002,
645 regk_iop_sw_mpu_wr = 0x00000003,
646 regk_iop_sw_mpu_yes = 0x00000001
647};
648#endif /* __iop_sw_mpu_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_spu_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_spu_defs.h
new file mode 100644
index 000000000000..c8560b865a1a
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_spu_defs.h
@@ -0,0 +1,441 @@
1#ifndef __iop_sw_spu_defs_h
2#define __iop_sw_spu_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: iop_sw_spu.r
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_spu_defs.h iop_sw_spu.r
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13/* Main access macros */
14#ifndef REG_RD
15#define REG_RD( scope, inst, reg ) \
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
18#endif
19
20#ifndef REG_WR
21#define REG_WR( scope, inst, reg, val ) \
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
24#endif
25
26#ifndef REG_RD_VECT
27#define REG_RD_VECT( scope, inst, reg, index ) \
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
31#endif
32
33#ifndef REG_WR_VECT
34#define REG_WR_VECT( scope, inst, reg, index, val ) \
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
38#endif
39
40#ifndef REG_RD_INT
41#define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
43#endif
44
45#ifndef REG_WR_INT
46#define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
48#endif
49
50#ifndef REG_RD_INT_VECT
51#define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
53 (index) * STRIDE_##scope##_##reg )
54#endif
55
56#ifndef REG_WR_INT_VECT
57#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
59 (index) * STRIDE_##scope##_##reg, (val) )
60#endif
61
62#ifndef REG_TYPE_CONV
63#define REG_TYPE_CONV( type, orgtype, val ) \
64 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
65#endif
66
67#ifndef reg_page_size
68#define reg_page_size 8192
69#endif
70
71#ifndef REG_ADDR
72#define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
74#endif
75
76#ifndef REG_ADDR_VECT
77#define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
79 (index) * STRIDE_##scope##_##reg )
80#endif
81
82/* C-code for register scope iop_sw_spu */
83
84/* Register r_mpu_trace, scope iop_sw_spu, type r */
85typedef unsigned int reg_iop_sw_spu_r_mpu_trace;
86#define REG_RD_ADDR_iop_sw_spu_r_mpu_trace 0
87
88/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
89typedef struct {
90 unsigned int keep_owner : 1;
91 unsigned int cmd : 2;
92 unsigned int size : 3;
93 unsigned int wr_spu_mem : 1;
94 unsigned int dummy1 : 25;
95} reg_iop_sw_spu_rw_mc_ctrl;
96#define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 4
97#define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 4
98
99/* Register rw_mc_data, scope iop_sw_spu, type rw */
100typedef struct {
101 unsigned int val : 32;
102} reg_iop_sw_spu_rw_mc_data;
103#define REG_RD_ADDR_iop_sw_spu_rw_mc_data 8
104#define REG_WR_ADDR_iop_sw_spu_rw_mc_data 8
105
106/* Register rw_mc_addr, scope iop_sw_spu, type rw */
107typedef unsigned int reg_iop_sw_spu_rw_mc_addr;
108#define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 12
109#define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 12
110
111/* Register rs_mc_data, scope iop_sw_spu, type rs */
112typedef unsigned int reg_iop_sw_spu_rs_mc_data;
113#define REG_RD_ADDR_iop_sw_spu_rs_mc_data 16
114
115/* Register r_mc_data, scope iop_sw_spu, type r */
116typedef unsigned int reg_iop_sw_spu_r_mc_data;
117#define REG_RD_ADDR_iop_sw_spu_r_mc_data 20
118
119/* Register r_mc_stat, scope iop_sw_spu, type r */
120typedef struct {
121 unsigned int busy_cpu : 1;
122 unsigned int busy_mpu : 1;
123 unsigned int busy_spu : 1;
124 unsigned int owned_by_cpu : 1;
125 unsigned int owned_by_mpu : 1;
126 unsigned int owned_by_spu : 1;
127 unsigned int dummy1 : 26;
128} reg_iop_sw_spu_r_mc_stat;
129#define REG_RD_ADDR_iop_sw_spu_r_mc_stat 24
130
131/* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */
132typedef struct {
133 unsigned int byte0 : 8;
134 unsigned int byte1 : 8;
135 unsigned int byte2 : 8;
136 unsigned int byte3 : 8;
137} reg_iop_sw_spu_rw_bus_clr_mask;
138#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask 28
139#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask 28
140
141/* Register rw_bus_set_mask, scope iop_sw_spu, type rw */
142typedef struct {
143 unsigned int byte0 : 8;
144 unsigned int byte1 : 8;
145 unsigned int byte2 : 8;
146 unsigned int byte3 : 8;
147} reg_iop_sw_spu_rw_bus_set_mask;
148#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask 32
149#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask 32
150
151/* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */
152typedef struct {
153 unsigned int byte0 : 1;
154 unsigned int byte1 : 1;
155 unsigned int byte2 : 1;
156 unsigned int byte3 : 1;
157 unsigned int dummy1 : 28;
158} reg_iop_sw_spu_rw_bus_oe_clr_mask;
159#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36
160#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36
161
162/* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */
163typedef struct {
164 unsigned int byte0 : 1;
165 unsigned int byte1 : 1;
166 unsigned int byte2 : 1;
167 unsigned int byte3 : 1;
168 unsigned int dummy1 : 28;
169} reg_iop_sw_spu_rw_bus_oe_set_mask;
170#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40
171#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40
172
173/* Register r_bus_in, scope iop_sw_spu, type r */
174typedef unsigned int reg_iop_sw_spu_r_bus_in;
175#define REG_RD_ADDR_iop_sw_spu_r_bus_in 44
176
177/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
178typedef struct {
179 unsigned int val : 32;
180} reg_iop_sw_spu_rw_gio_clr_mask;
181#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 48
182#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 48
183
184/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
185typedef struct {
186 unsigned int val : 32;
187} reg_iop_sw_spu_rw_gio_set_mask;
188#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 52
189#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 52
190
191/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
192typedef struct {
193 unsigned int val : 32;
194} reg_iop_sw_spu_rw_gio_oe_clr_mask;
195#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56
196#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56
197
198/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
199typedef struct {
200 unsigned int val : 32;
201} reg_iop_sw_spu_rw_gio_oe_set_mask;
202#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60
203#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60
204
205/* Register r_gio_in, scope iop_sw_spu, type r */
206typedef unsigned int reg_iop_sw_spu_r_gio_in;
207#define REG_RD_ADDR_iop_sw_spu_r_gio_in 64
208
209/* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */
210typedef struct {
211 unsigned int byte0 : 8;
212 unsigned int byte1 : 8;
213 unsigned int dummy1 : 16;
214} reg_iop_sw_spu_rw_bus_clr_mask_lo;
215#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68
216#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68
217
218/* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */
219typedef struct {
220 unsigned int byte2 : 8;
221 unsigned int byte3 : 8;
222 unsigned int dummy1 : 16;
223} reg_iop_sw_spu_rw_bus_clr_mask_hi;
224#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72
225#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72
226
227/* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */
228typedef struct {
229 unsigned int byte0 : 8;
230 unsigned int byte1 : 8;
231 unsigned int dummy1 : 16;
232} reg_iop_sw_spu_rw_bus_set_mask_lo;
233#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76
234#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76
235
236/* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */
237typedef struct {
238 unsigned int byte2 : 8;
239 unsigned int byte3 : 8;
240 unsigned int dummy1 : 16;
241} reg_iop_sw_spu_rw_bus_set_mask_hi;
242#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80
243#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80
244
245/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
246typedef struct {
247 unsigned int val : 16;
248 unsigned int dummy1 : 16;
249} reg_iop_sw_spu_rw_gio_clr_mask_lo;
250#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84
251#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84
252
253/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
254typedef struct {
255 unsigned int val : 16;
256 unsigned int dummy1 : 16;
257} reg_iop_sw_spu_rw_gio_clr_mask_hi;
258#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88
259#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88
260
261/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
262typedef struct {
263 unsigned int val : 16;
264 unsigned int dummy1 : 16;
265} reg_iop_sw_spu_rw_gio_set_mask_lo;
266#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92
267#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92
268
269/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
270typedef struct {
271 unsigned int val : 16;
272 unsigned int dummy1 : 16;
273} reg_iop_sw_spu_rw_gio_set_mask_hi;
274#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96
275#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96
276
277/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
278typedef struct {
279 unsigned int val : 16;
280 unsigned int dummy1 : 16;
281} reg_iop_sw_spu_rw_gio_oe_clr_mask_lo;
282#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100
283#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100
284
285/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
286typedef struct {
287 unsigned int val : 16;
288 unsigned int dummy1 : 16;
289} reg_iop_sw_spu_rw_gio_oe_clr_mask_hi;
290#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104
291#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104
292
293/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
294typedef struct {
295 unsigned int val : 16;
296 unsigned int dummy1 : 16;
297} reg_iop_sw_spu_rw_gio_oe_set_mask_lo;
298#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108
299#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108
300
301/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
302typedef struct {
303 unsigned int val : 16;
304 unsigned int dummy1 : 16;
305} reg_iop_sw_spu_rw_gio_oe_set_mask_hi;
306#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112
307#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112
308
309/* Register rw_cpu_intr, scope iop_sw_spu, type rw */
310typedef struct {
311 unsigned int intr0 : 1;
312 unsigned int intr1 : 1;
313 unsigned int intr2 : 1;
314 unsigned int intr3 : 1;
315 unsigned int intr4 : 1;
316 unsigned int intr5 : 1;
317 unsigned int intr6 : 1;
318 unsigned int intr7 : 1;
319 unsigned int intr8 : 1;
320 unsigned int intr9 : 1;
321 unsigned int intr10 : 1;
322 unsigned int intr11 : 1;
323 unsigned int intr12 : 1;
324 unsigned int intr13 : 1;
325 unsigned int intr14 : 1;
326 unsigned int intr15 : 1;
327 unsigned int dummy1 : 16;
328} reg_iop_sw_spu_rw_cpu_intr;
329#define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 116
330#define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 116
331
332/* Register r_cpu_intr, scope iop_sw_spu, type r */
333typedef struct {
334 unsigned int intr0 : 1;
335 unsigned int intr1 : 1;
336 unsigned int intr2 : 1;
337 unsigned int intr3 : 1;
338 unsigned int intr4 : 1;
339 unsigned int intr5 : 1;
340 unsigned int intr6 : 1;
341 unsigned int intr7 : 1;
342 unsigned int intr8 : 1;
343 unsigned int intr9 : 1;
344 unsigned int intr10 : 1;
345 unsigned int intr11 : 1;
346 unsigned int intr12 : 1;
347 unsigned int intr13 : 1;
348 unsigned int intr14 : 1;
349 unsigned int intr15 : 1;
350 unsigned int dummy1 : 16;
351} reg_iop_sw_spu_r_cpu_intr;
352#define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 120
353
354/* Register r_hw_intr, scope iop_sw_spu, type r */
355typedef struct {
356 unsigned int trigger_grp0 : 1;
357 unsigned int trigger_grp1 : 1;
358 unsigned int trigger_grp2 : 1;
359 unsigned int trigger_grp3 : 1;
360 unsigned int trigger_grp4 : 1;
361 unsigned int trigger_grp5 : 1;
362 unsigned int trigger_grp6 : 1;
363 unsigned int trigger_grp7 : 1;
364 unsigned int timer_grp0 : 1;
365 unsigned int timer_grp1 : 1;
366 unsigned int fifo_out : 1;
367 unsigned int fifo_out_extra : 1;
368 unsigned int fifo_in : 1;
369 unsigned int fifo_in_extra : 1;
370 unsigned int dmc_out : 1;
371 unsigned int dmc_in : 1;
372 unsigned int dummy1 : 16;
373} reg_iop_sw_spu_r_hw_intr;
374#define REG_RD_ADDR_iop_sw_spu_r_hw_intr 124
375
376/* Register rw_mpu_intr, scope iop_sw_spu, type rw */
377typedef struct {
378 unsigned int intr0 : 1;
379 unsigned int intr1 : 1;
380 unsigned int intr2 : 1;
381 unsigned int intr3 : 1;
382 unsigned int intr4 : 1;
383 unsigned int intr5 : 1;
384 unsigned int intr6 : 1;
385 unsigned int intr7 : 1;
386 unsigned int intr8 : 1;
387 unsigned int intr9 : 1;
388 unsigned int intr10 : 1;
389 unsigned int intr11 : 1;
390 unsigned int intr12 : 1;
391 unsigned int intr13 : 1;
392 unsigned int intr14 : 1;
393 unsigned int intr15 : 1;
394 unsigned int dummy1 : 16;
395} reg_iop_sw_spu_rw_mpu_intr;
396#define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 128
397#define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 128
398
399/* Register r_mpu_intr, scope iop_sw_spu, type r */
400typedef struct {
401 unsigned int intr0 : 1;
402 unsigned int intr1 : 1;
403 unsigned int intr2 : 1;
404 unsigned int intr3 : 1;
405 unsigned int intr4 : 1;
406 unsigned int intr5 : 1;
407 unsigned int intr6 : 1;
408 unsigned int intr7 : 1;
409 unsigned int intr8 : 1;
410 unsigned int intr9 : 1;
411 unsigned int intr10 : 1;
412 unsigned int intr11 : 1;
413 unsigned int intr12 : 1;
414 unsigned int intr13 : 1;
415 unsigned int intr14 : 1;
416 unsigned int intr15 : 1;
417 unsigned int dummy1 : 16;
418} reg_iop_sw_spu_r_mpu_intr;
419#define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 132
420
421
422/* Constants */
423enum {
424 regk_iop_sw_spu_copy = 0x00000000,
425 regk_iop_sw_spu_no = 0x00000000,
426 regk_iop_sw_spu_nop = 0x00000000,
427 regk_iop_sw_spu_rd = 0x00000002,
428 regk_iop_sw_spu_reg_copy = 0x00000001,
429 regk_iop_sw_spu_rw_bus_clr_mask_default = 0x00000000,
430 regk_iop_sw_spu_rw_bus_oe_clr_mask_default = 0x00000000,
431 regk_iop_sw_spu_rw_bus_oe_set_mask_default = 0x00000000,
432 regk_iop_sw_spu_rw_bus_set_mask_default = 0x00000000,
433 regk_iop_sw_spu_rw_gio_clr_mask_default = 0x00000000,
434 regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000,
435 regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000,
436 regk_iop_sw_spu_rw_gio_set_mask_default = 0x00000000,
437 regk_iop_sw_spu_set = 0x00000001,
438 regk_iop_sw_spu_wr = 0x00000003,
439 regk_iop_sw_spu_yes = 0x00000001
440};
441#endif /* __iop_sw_spu_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_version_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_version_defs.h
new file mode 100644
index 000000000000..20de425e652b
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_version_defs.h
@@ -0,0 +1,96 @@
1#ifndef __iop_version_defs_h
2#define __iop_version_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: iop_version.r
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -outfile iop_version_defs.h iop_version.r
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13/* Main access macros */
14#ifndef REG_RD
15#define REG_RD( scope, inst, reg ) \
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
18#endif
19
20#ifndef REG_WR
21#define REG_WR( scope, inst, reg, val ) \
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
24#endif
25
26#ifndef REG_RD_VECT
27#define REG_RD_VECT( scope, inst, reg, index ) \
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
31#endif
32
33#ifndef REG_WR_VECT
34#define REG_WR_VECT( scope, inst, reg, index, val ) \
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
38#endif
39
40#ifndef REG_RD_INT
41#define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
43#endif
44
45#ifndef REG_WR_INT
46#define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
48#endif
49
50#ifndef REG_RD_INT_VECT
51#define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
53 (index) * STRIDE_##scope##_##reg )
54#endif
55
56#ifndef REG_WR_INT_VECT
57#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
59 (index) * STRIDE_##scope##_##reg, (val) )
60#endif
61
62#ifndef REG_TYPE_CONV
63#define REG_TYPE_CONV( type, orgtype, val ) \
64 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
65#endif
66
67#ifndef reg_page_size
68#define reg_page_size 8192
69#endif
70
71#ifndef REG_ADDR
72#define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
74#endif
75
76#ifndef REG_ADDR_VECT
77#define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
79 (index) * STRIDE_##scope##_##reg )
80#endif
81
82/* C-code for register scope iop_version */
83
84/* Register r_version, scope iop_version, type r */
85typedef struct {
86 unsigned int nr : 8;
87 unsigned int dummy1 : 24;
88} reg_iop_version_r_version;
89#define REG_RD_ADDR_iop_version_r_version 0
90
91
92/* Constants */
93enum {
94 regk_iop_version_v2_0 = 0x00000002
95};
96#endif /* __iop_version_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/l2cache_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/l2cache_defs.h
new file mode 100644
index 000000000000..243ac3c882cb
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/l2cache_defs.h
@@ -0,0 +1,142 @@
1#ifndef __l2cache_defs_h
2#define __l2cache_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: l2cache.r
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -outfile l2cache_defs.h l2cache.r
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13/* Main access macros */
14#ifndef REG_RD
15#define REG_RD( scope, inst, reg ) \
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
18#endif
19
20#ifndef REG_WR
21#define REG_WR( scope, inst, reg, val ) \
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
24#endif
25
26#ifndef REG_RD_VECT
27#define REG_RD_VECT( scope, inst, reg, index ) \
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
31#endif
32
33#ifndef REG_WR_VECT
34#define REG_WR_VECT( scope, inst, reg, index, val ) \
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
38#endif
39
40#ifndef REG_RD_INT
41#define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
43#endif
44
45#ifndef REG_WR_INT
46#define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
48#endif
49
50#ifndef REG_RD_INT_VECT
51#define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
53 (index) * STRIDE_##scope##_##reg )
54#endif
55
56#ifndef REG_WR_INT_VECT
57#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
59 (index) * STRIDE_##scope##_##reg, (val) )
60#endif
61
62#ifndef REG_TYPE_CONV
63#define REG_TYPE_CONV( type, orgtype, val ) \
64 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
65#endif
66
67#ifndef reg_page_size
68#define reg_page_size 8192
69#endif
70
71#ifndef REG_ADDR
72#define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
74#endif
75
76#ifndef REG_ADDR_VECT
77#define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
79 (index) * STRIDE_##scope##_##reg )
80#endif
81
82/* C-code for register scope l2cache */
83
84/* Register rw_cfg, scope l2cache, type rw */
85typedef struct {
86 unsigned int en : 1;
87 unsigned int dummy1 : 31;
88} reg_l2cache_rw_cfg;
89#define REG_RD_ADDR_l2cache_rw_cfg 0
90#define REG_WR_ADDR_l2cache_rw_cfg 0
91
92/* Register rw_ctrl, scope l2cache, type rw */
93typedef struct {
94 unsigned int dummy1 : 7;
95 unsigned int cbase : 9;
96 unsigned int dummy2 : 4;
97 unsigned int csize : 10;
98 unsigned int dummy3 : 2;
99} reg_l2cache_rw_ctrl;
100#define REG_RD_ADDR_l2cache_rw_ctrl 4
101#define REG_WR_ADDR_l2cache_rw_ctrl 4
102
103/* Register rw_idxop, scope l2cache, type rw */
104typedef struct {
105 unsigned int idx : 10;
106 unsigned int dummy1 : 14;
107 unsigned int way : 3;
108 unsigned int dummy2 : 2;
109 unsigned int cmd : 3;
110} reg_l2cache_rw_idxop;
111#define REG_RD_ADDR_l2cache_rw_idxop 8
112#define REG_WR_ADDR_l2cache_rw_idxop 8
113
114/* Register rw_addrop_addr, scope l2cache, type rw */
115typedef struct {
116 unsigned int addr : 32;
117} reg_l2cache_rw_addrop_addr;
118#define REG_RD_ADDR_l2cache_rw_addrop_addr 12
119#define REG_WR_ADDR_l2cache_rw_addrop_addr 12
120
121/* Register rw_addrop_ctrl, scope l2cache, type rw */
122typedef struct {
123 unsigned int size : 16;
124 unsigned int dummy1 : 13;
125 unsigned int cmd : 3;
126} reg_l2cache_rw_addrop_ctrl;
127#define REG_RD_ADDR_l2cache_rw_addrop_ctrl 16
128#define REG_WR_ADDR_l2cache_rw_addrop_ctrl 16
129
130
131/* Constants */
132enum {
133 regk_l2cache_flush = 0x00000001,
134 regk_l2cache_no = 0x00000000,
135 regk_l2cache_rw_addrop_addr_default = 0x00000000,
136 regk_l2cache_rw_addrop_ctrl_default = 0x00000000,
137 regk_l2cache_rw_cfg_default = 0x00000000,
138 regk_l2cache_rw_ctrl_default = 0x00000000,
139 regk_l2cache_rw_idxop_default = 0x00000000,
140 regk_l2cache_yes = 0x00000001
141};
142#endif /* __l2cache_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/marb_bar_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/marb_bar_defs.h
new file mode 100644
index 000000000000..c0e7628cbf7d
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/marb_bar_defs.h
@@ -0,0 +1,482 @@
1#ifndef __marb_bar_defs_h
2#define __marb_bar_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: marb_bar.r
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -outfile marb_bar_defs.h marb_bar.r
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13/* Main access macros */
14#ifndef REG_RD
15#define REG_RD( scope, inst, reg ) \
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
18#endif
19
20#ifndef REG_WR
21#define REG_WR( scope, inst, reg, val ) \
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
24#endif
25
26#ifndef REG_RD_VECT
27#define REG_RD_VECT( scope, inst, reg, index ) \
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
31#endif
32
33#ifndef REG_WR_VECT
34#define REG_WR_VECT( scope, inst, reg, index, val ) \
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
38#endif
39
40#ifndef REG_RD_INT
41#define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
43#endif
44
45#ifndef REG_WR_INT
46#define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
48#endif
49
50#ifndef REG_RD_INT_VECT
51#define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
53 (index) * STRIDE_##scope##_##reg )
54#endif
55
56#ifndef REG_WR_INT_VECT
57#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
59 (index) * STRIDE_##scope##_##reg, (val) )
60#endif
61
62#ifndef REG_TYPE_CONV
63#define REG_TYPE_CONV( type, orgtype, val ) \
64 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
65#endif
66
67#ifndef reg_page_size
68#define reg_page_size 8192
69#endif
70
71#ifndef REG_ADDR
72#define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
74#endif
75
76#ifndef REG_ADDR_VECT
77#define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
79 (index) * STRIDE_##scope##_##reg )
80#endif
81
82/* C-code for register scope marb_bar */
83
84#define STRIDE_marb_bar_rw_ddr2_slots 4
85/* Register rw_ddr2_slots, scope marb_bar, type rw */
86typedef struct {
87 unsigned int owner : 4;
88 unsigned int dummy1 : 28;
89} reg_marb_bar_rw_ddr2_slots;
90#define REG_RD_ADDR_marb_bar_rw_ddr2_slots 0
91#define REG_WR_ADDR_marb_bar_rw_ddr2_slots 0
92
93/* Register rw_h264_rd_burst, scope marb_bar, type rw */
94typedef struct {
95 unsigned int ddr2_bsize : 2;
96 unsigned int dummy1 : 30;
97} reg_marb_bar_rw_h264_rd_burst;
98#define REG_RD_ADDR_marb_bar_rw_h264_rd_burst 256
99#define REG_WR_ADDR_marb_bar_rw_h264_rd_burst 256
100
101/* Register rw_h264_wr_burst, scope marb_bar, type rw */
102typedef struct {
103 unsigned int ddr2_bsize : 2;
104 unsigned int dummy1 : 30;
105} reg_marb_bar_rw_h264_wr_burst;
106#define REG_RD_ADDR_marb_bar_rw_h264_wr_burst 260
107#define REG_WR_ADDR_marb_bar_rw_h264_wr_burst 260
108
109/* Register rw_ccd_burst, scope marb_bar, type rw */
110typedef struct {
111 unsigned int ddr2_bsize : 2;
112 unsigned int dummy1 : 30;
113} reg_marb_bar_rw_ccd_burst;
114#define REG_RD_ADDR_marb_bar_rw_ccd_burst 264
115#define REG_WR_ADDR_marb_bar_rw_ccd_burst 264
116
117/* Register rw_vin_wr_burst, scope marb_bar, type rw */
118typedef struct {
119 unsigned int ddr2_bsize : 2;
120 unsigned int dummy1 : 30;
121} reg_marb_bar_rw_vin_wr_burst;
122#define REG_RD_ADDR_marb_bar_rw_vin_wr_burst 268
123#define REG_WR_ADDR_marb_bar_rw_vin_wr_burst 268
124
125/* Register rw_vin_rd_burst, scope marb_bar, type rw */
126typedef struct {
127 unsigned int ddr2_bsize : 2;
128 unsigned int dummy1 : 30;
129} reg_marb_bar_rw_vin_rd_burst;
130#define REG_RD_ADDR_marb_bar_rw_vin_rd_burst 272
131#define REG_WR_ADDR_marb_bar_rw_vin_rd_burst 272
132
133/* Register rw_sclr_rd_burst, scope marb_bar, type rw */
134typedef struct {
135 unsigned int ddr2_bsize : 2;
136 unsigned int dummy1 : 30;
137} reg_marb_bar_rw_sclr_rd_burst;
138#define REG_RD_ADDR_marb_bar_rw_sclr_rd_burst 276
139#define REG_WR_ADDR_marb_bar_rw_sclr_rd_burst 276
140
141/* Register rw_vout_burst, scope marb_bar, type rw */
142typedef struct {
143 unsigned int ddr2_bsize : 2;
144 unsigned int dummy1 : 30;
145} reg_marb_bar_rw_vout_burst;
146#define REG_RD_ADDR_marb_bar_rw_vout_burst 280
147#define REG_WR_ADDR_marb_bar_rw_vout_burst 280
148
149/* Register rw_sclr_fifo_burst, scope marb_bar, type rw */
150typedef struct {
151 unsigned int ddr2_bsize : 2;
152 unsigned int dummy1 : 30;
153} reg_marb_bar_rw_sclr_fifo_burst;
154#define REG_RD_ADDR_marb_bar_rw_sclr_fifo_burst 284
155#define REG_WR_ADDR_marb_bar_rw_sclr_fifo_burst 284
156
157/* Register rw_l2cache_burst, scope marb_bar, type rw */
158typedef struct {
159 unsigned int ddr2_bsize : 2;
160 unsigned int dummy1 : 30;
161} reg_marb_bar_rw_l2cache_burst;
162#define REG_RD_ADDR_marb_bar_rw_l2cache_burst 288
163#define REG_WR_ADDR_marb_bar_rw_l2cache_burst 288
164
165/* Register rw_intr_mask, scope marb_bar, type rw */
166typedef struct {
167 unsigned int bp0 : 1;
168 unsigned int bp1 : 1;
169 unsigned int bp2 : 1;
170 unsigned int bp3 : 1;
171 unsigned int dummy1 : 28;
172} reg_marb_bar_rw_intr_mask;
173#define REG_RD_ADDR_marb_bar_rw_intr_mask 292
174#define REG_WR_ADDR_marb_bar_rw_intr_mask 292
175
176/* Register rw_ack_intr, scope marb_bar, type rw */
177typedef struct {
178 unsigned int bp0 : 1;
179 unsigned int bp1 : 1;
180 unsigned int bp2 : 1;
181 unsigned int bp3 : 1;
182 unsigned int dummy1 : 28;
183} reg_marb_bar_rw_ack_intr;
184#define REG_RD_ADDR_marb_bar_rw_ack_intr 296
185#define REG_WR_ADDR_marb_bar_rw_ack_intr 296
186
187/* Register r_intr, scope marb_bar, type r */
188typedef struct {
189 unsigned int bp0 : 1;
190 unsigned int bp1 : 1;
191 unsigned int bp2 : 1;
192 unsigned int bp3 : 1;
193 unsigned int dummy1 : 28;
194} reg_marb_bar_r_intr;
195#define REG_RD_ADDR_marb_bar_r_intr 300
196
197/* Register r_masked_intr, scope marb_bar, type r */
198typedef struct {
199 unsigned int bp0 : 1;
200 unsigned int bp1 : 1;
201 unsigned int bp2 : 1;
202 unsigned int bp3 : 1;
203 unsigned int dummy1 : 28;
204} reg_marb_bar_r_masked_intr;
205#define REG_RD_ADDR_marb_bar_r_masked_intr 304
206
207/* Register rw_stop_mask, scope marb_bar, type rw */
208typedef struct {
209 unsigned int h264_rd : 1;
210 unsigned int h264_wr : 1;
211 unsigned int ccd : 1;
212 unsigned int vin_wr : 1;
213 unsigned int vin_rd : 1;
214 unsigned int sclr_rd : 1;
215 unsigned int vout : 1;
216 unsigned int sclr_fifo : 1;
217 unsigned int l2cache : 1;
218 unsigned int dummy1 : 23;
219} reg_marb_bar_rw_stop_mask;
220#define REG_RD_ADDR_marb_bar_rw_stop_mask 308
221#define REG_WR_ADDR_marb_bar_rw_stop_mask 308
222
223/* Register r_stopped, scope marb_bar, type r */
224typedef struct {
225 unsigned int h264_rd : 1;
226 unsigned int h264_wr : 1;
227 unsigned int ccd : 1;
228 unsigned int vin_wr : 1;
229 unsigned int vin_rd : 1;
230 unsigned int sclr_rd : 1;
231 unsigned int vout : 1;
232 unsigned int sclr_fifo : 1;
233 unsigned int l2cache : 1;
234 unsigned int dummy1 : 23;
235} reg_marb_bar_r_stopped;
236#define REG_RD_ADDR_marb_bar_r_stopped 312
237
238/* Register rw_no_snoop, scope marb_bar, type rw */
239typedef struct {
240 unsigned int h264_rd : 1;
241 unsigned int h264_wr : 1;
242 unsigned int ccd : 1;
243 unsigned int vin_wr : 1;
244 unsigned int vin_rd : 1;
245 unsigned int sclr_rd : 1;
246 unsigned int vout : 1;
247 unsigned int sclr_fifo : 1;
248 unsigned int l2cache : 1;
249 unsigned int dummy1 : 23;
250} reg_marb_bar_rw_no_snoop;
251#define REG_RD_ADDR_marb_bar_rw_no_snoop 576
252#define REG_WR_ADDR_marb_bar_rw_no_snoop 576
253
254
255/* Constants */
256enum {
257 regk_marb_bar_ccd = 0x00000002,
258 regk_marb_bar_h264_rd = 0x00000000,
259 regk_marb_bar_h264_wr = 0x00000001,
260 regk_marb_bar_l2cache = 0x00000008,
261 regk_marb_bar_no = 0x00000000,
262 regk_marb_bar_r_stopped_default = 0x00000000,
263 regk_marb_bar_rw_ccd_burst_default = 0x00000000,
264 regk_marb_bar_rw_ddr2_slots_default = 0x00000000,
265 regk_marb_bar_rw_ddr2_slots_size = 0x00000040,
266 regk_marb_bar_rw_h264_rd_burst_default = 0x00000000,
267 regk_marb_bar_rw_h264_wr_burst_default = 0x00000000,
268 regk_marb_bar_rw_intr_mask_default = 0x00000000,
269 regk_marb_bar_rw_l2cache_burst_default = 0x00000000,
270 regk_marb_bar_rw_no_snoop_default = 0x00000000,
271 regk_marb_bar_rw_sclr_fifo_burst_default = 0x00000000,
272 regk_marb_bar_rw_sclr_rd_burst_default = 0x00000000,
273 regk_marb_bar_rw_stop_mask_default = 0x00000000,
274 regk_marb_bar_rw_vin_rd_burst_default = 0x00000000,
275 regk_marb_bar_rw_vin_wr_burst_default = 0x00000000,
276 regk_marb_bar_rw_vout_burst_default = 0x00000000,
277 regk_marb_bar_sclr_fifo = 0x00000007,
278 regk_marb_bar_sclr_rd = 0x00000005,
279 regk_marb_bar_vin_rd = 0x00000004,
280 regk_marb_bar_vin_wr = 0x00000003,
281 regk_marb_bar_vout = 0x00000006,
282 regk_marb_bar_yes = 0x00000001
283};
284#endif /* __marb_bar_defs_h */
285#ifndef __marb_bar_bp_defs_h
286#define __marb_bar_bp_defs_h
287
288/*
289 * This file is autogenerated from
290 * file: marb_bar.r
291 *
292 * by ../../../tools/rdesc/bin/rdes2c -outfile marb_bar_defs.h marb_bar.r
293 * Any changes here will be lost.
294 *
295 * -*- buffer-read-only: t -*-
296 */
297/* Main access macros */
298#ifndef REG_RD
299#define REG_RD( scope, inst, reg ) \
300 REG_READ( reg_##scope##_##reg, \
301 (inst) + REG_RD_ADDR_##scope##_##reg )
302#endif
303
304#ifndef REG_WR
305#define REG_WR( scope, inst, reg, val ) \
306 REG_WRITE( reg_##scope##_##reg, \
307 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
308#endif
309
310#ifndef REG_RD_VECT
311#define REG_RD_VECT( scope, inst, reg, index ) \
312 REG_READ( reg_##scope##_##reg, \
313 (inst) + REG_RD_ADDR_##scope##_##reg + \
314 (index) * STRIDE_##scope##_##reg )
315#endif
316
317#ifndef REG_WR_VECT
318#define REG_WR_VECT( scope, inst, reg, index, val ) \
319 REG_WRITE( reg_##scope##_##reg, \
320 (inst) + REG_WR_ADDR_##scope##_##reg + \
321 (index) * STRIDE_##scope##_##reg, (val) )
322#endif
323
324#ifndef REG_RD_INT
325#define REG_RD_INT( scope, inst, reg ) \
326 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
327#endif
328
329#ifndef REG_WR_INT
330#define REG_WR_INT( scope, inst, reg, val ) \
331 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
332#endif
333
334#ifndef REG_RD_INT_VECT
335#define REG_RD_INT_VECT( scope, inst, reg, index ) \
336 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
337 (index) * STRIDE_##scope##_##reg )
338#endif
339
340#ifndef REG_WR_INT_VECT
341#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
342 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
343 (index) * STRIDE_##scope##_##reg, (val) )
344#endif
345
346#ifndef REG_TYPE_CONV
347#define REG_TYPE_CONV( type, orgtype, val ) \
348 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
349#endif
350
351#ifndef reg_page_size
352#define reg_page_size 8192
353#endif
354
355#ifndef REG_ADDR
356#define REG_ADDR( scope, inst, reg ) \
357 ( (inst) + REG_RD_ADDR_##scope##_##reg )
358#endif
359
360#ifndef REG_ADDR_VECT
361#define REG_ADDR_VECT( scope, inst, reg, index ) \
362 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
363 (index) * STRIDE_##scope##_##reg )
364#endif
365
366/* C-code for register scope marb_bar_bp */
367
368/* Register rw_first_addr, scope marb_bar_bp, type rw */
369typedef unsigned int reg_marb_bar_bp_rw_first_addr;
370#define REG_RD_ADDR_marb_bar_bp_rw_first_addr 0
371#define REG_WR_ADDR_marb_bar_bp_rw_first_addr 0
372
373/* Register rw_last_addr, scope marb_bar_bp, type rw */
374typedef unsigned int reg_marb_bar_bp_rw_last_addr;
375#define REG_RD_ADDR_marb_bar_bp_rw_last_addr 4
376#define REG_WR_ADDR_marb_bar_bp_rw_last_addr 4
377
378/* Register rw_op, scope marb_bar_bp, type rw */
379typedef struct {
380 unsigned int rd : 1;
381 unsigned int wr : 1;
382 unsigned int rd_excl : 1;
383 unsigned int pri_wr : 1;
384 unsigned int us_rd : 1;
385 unsigned int us_wr : 1;
386 unsigned int us_rd_excl : 1;
387 unsigned int us_pri_wr : 1;
388 unsigned int dummy1 : 24;
389} reg_marb_bar_bp_rw_op;
390#define REG_RD_ADDR_marb_bar_bp_rw_op 8
391#define REG_WR_ADDR_marb_bar_bp_rw_op 8
392
393/* Register rw_clients, scope marb_bar_bp, type rw */
394typedef struct {
395 unsigned int h264_rd : 1;
396 unsigned int h264_wr : 1;
397 unsigned int ccd : 1;
398 unsigned int vin_wr : 1;
399 unsigned int vin_rd : 1;
400 unsigned int sclr_rd : 1;
401 unsigned int vout : 1;
402 unsigned int sclr_fifo : 1;
403 unsigned int l2cache : 1;
404 unsigned int dummy1 : 23;
405} reg_marb_bar_bp_rw_clients;
406#define REG_RD_ADDR_marb_bar_bp_rw_clients 12
407#define REG_WR_ADDR_marb_bar_bp_rw_clients 12
408
409/* Register rw_options, scope marb_bar_bp, type rw */
410typedef struct {
411 unsigned int wrap : 1;
412 unsigned int dummy1 : 31;
413} reg_marb_bar_bp_rw_options;
414#define REG_RD_ADDR_marb_bar_bp_rw_options 16
415#define REG_WR_ADDR_marb_bar_bp_rw_options 16
416
417/* Register r_brk_addr, scope marb_bar_bp, type r */
418typedef unsigned int reg_marb_bar_bp_r_brk_addr;
419#define REG_RD_ADDR_marb_bar_bp_r_brk_addr 20
420
421/* Register r_brk_op, scope marb_bar_bp, type r */
422typedef struct {
423 unsigned int rd : 1;
424 unsigned int wr : 1;
425 unsigned int rd_excl : 1;
426 unsigned int pri_wr : 1;
427 unsigned int us_rd : 1;
428 unsigned int us_wr : 1;
429 unsigned int us_rd_excl : 1;
430 unsigned int us_pri_wr : 1;
431 unsigned int dummy1 : 24;
432} reg_marb_bar_bp_r_brk_op;
433#define REG_RD_ADDR_marb_bar_bp_r_brk_op 24
434
435/* Register r_brk_clients, scope marb_bar_bp, type r */
436typedef struct {
437 unsigned int h264_rd : 1;
438 unsigned int h264_wr : 1;
439 unsigned int ccd : 1;
440 unsigned int vin_wr : 1;
441 unsigned int vin_rd : 1;
442 unsigned int sclr_rd : 1;
443 unsigned int vout : 1;
444 unsigned int sclr_fifo : 1;
445 unsigned int l2cache : 1;
446 unsigned int dummy1 : 23;
447} reg_marb_bar_bp_r_brk_clients;
448#define REG_RD_ADDR_marb_bar_bp_r_brk_clients 28
449
450/* Register r_brk_first_client, scope marb_bar_bp, type r */
451typedef struct {
452 unsigned int h264_rd : 1;
453 unsigned int h264_wr : 1;
454 unsigned int ccd : 1;
455 unsigned int vin_wr : 1;
456 unsigned int vin_rd : 1;
457 unsigned int sclr_rd : 1;
458 unsigned int vout : 1;
459 unsigned int sclr_fifo : 1;
460 unsigned int l2cache : 1;
461 unsigned int dummy1 : 23;
462} reg_marb_bar_bp_r_brk_first_client;
463#define REG_RD_ADDR_marb_bar_bp_r_brk_first_client 32
464
465/* Register r_brk_size, scope marb_bar_bp, type r */
466typedef unsigned int reg_marb_bar_bp_r_brk_size;
467#define REG_RD_ADDR_marb_bar_bp_r_brk_size 36
468
469/* Register rw_ack, scope marb_bar_bp, type rw */
470typedef unsigned int reg_marb_bar_bp_rw_ack;
471#define REG_RD_ADDR_marb_bar_bp_rw_ack 40
472#define REG_WR_ADDR_marb_bar_bp_rw_ack 40
473
474
475/* Constants */
476enum {
477 regk_marb_bar_bp_no = 0x00000000,
478 regk_marb_bar_bp_rw_op_default = 0x00000000,
479 regk_marb_bar_bp_rw_options_default = 0x00000000,
480 regk_marb_bar_bp_yes = 0x00000001
481};
482#endif /* __marb_bar_bp_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/marb_foo_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/marb_foo_defs.h
new file mode 100644
index 000000000000..2baa833f109a
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/marb_foo_defs.h
@@ -0,0 +1,626 @@
1#ifndef __marb_foo_defs_h
2#define __marb_foo_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: marb_foo.r
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -outfile marb_foo_defs.h marb_foo.r
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13/* Main access macros */
14#ifndef REG_RD
15#define REG_RD( scope, inst, reg ) \
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
18#endif
19
20#ifndef REG_WR
21#define REG_WR( scope, inst, reg, val ) \
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
24#endif
25
26#ifndef REG_RD_VECT
27#define REG_RD_VECT( scope, inst, reg, index ) \
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
31#endif
32
33#ifndef REG_WR_VECT
34#define REG_WR_VECT( scope, inst, reg, index, val ) \
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
38#endif
39
40#ifndef REG_RD_INT
41#define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
43#endif
44
45#ifndef REG_WR_INT
46#define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
48#endif
49
50#ifndef REG_RD_INT_VECT
51#define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
53 (index) * STRIDE_##scope##_##reg )
54#endif
55
56#ifndef REG_WR_INT_VECT
57#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
59 (index) * STRIDE_##scope##_##reg, (val) )
60#endif
61
62#ifndef REG_TYPE_CONV
63#define REG_TYPE_CONV( type, orgtype, val ) \
64 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
65#endif
66
67#ifndef reg_page_size
68#define reg_page_size 8192
69#endif
70
71#ifndef REG_ADDR
72#define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
74#endif
75
76#ifndef REG_ADDR_VECT
77#define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
79 (index) * STRIDE_##scope##_##reg )
80#endif
81
82/* C-code for register scope marb_foo */
83
84#define STRIDE_marb_foo_rw_intm_slots 4
85/* Register rw_intm_slots, scope marb_foo, type rw */
86typedef struct {
87 unsigned int owner : 4;
88 unsigned int dummy1 : 28;
89} reg_marb_foo_rw_intm_slots;
90#define REG_RD_ADDR_marb_foo_rw_intm_slots 0
91#define REG_WR_ADDR_marb_foo_rw_intm_slots 0
92
93#define STRIDE_marb_foo_rw_l2_slots 4
94/* Register rw_l2_slots, scope marb_foo, type rw */
95typedef struct {
96 unsigned int owner : 4;
97 unsigned int dummy1 : 28;
98} reg_marb_foo_rw_l2_slots;
99#define REG_RD_ADDR_marb_foo_rw_l2_slots 256
100#define REG_WR_ADDR_marb_foo_rw_l2_slots 256
101
102#define STRIDE_marb_foo_rw_regs_slots 4
103/* Register rw_regs_slots, scope marb_foo, type rw */
104typedef struct {
105 unsigned int owner : 4;
106 unsigned int dummy1 : 28;
107} reg_marb_foo_rw_regs_slots;
108#define REG_RD_ADDR_marb_foo_rw_regs_slots 512
109#define REG_WR_ADDR_marb_foo_rw_regs_slots 512
110
111/* Register rw_sclr_burst, scope marb_foo, type rw */
112typedef struct {
113 unsigned int intm_bsize : 2;
114 unsigned int l2_bsize : 2;
115 unsigned int dummy1 : 28;
116} reg_marb_foo_rw_sclr_burst;
117#define REG_RD_ADDR_marb_foo_rw_sclr_burst 528
118#define REG_WR_ADDR_marb_foo_rw_sclr_burst 528
119
120/* Register rw_dma0_burst, scope marb_foo, type rw */
121typedef struct {
122 unsigned int intm_bsize : 2;
123 unsigned int l2_bsize : 2;
124 unsigned int dummy1 : 28;
125} reg_marb_foo_rw_dma0_burst;
126#define REG_RD_ADDR_marb_foo_rw_dma0_burst 532
127#define REG_WR_ADDR_marb_foo_rw_dma0_burst 532
128
129/* Register rw_dma1_burst, scope marb_foo, type rw */
130typedef struct {
131 unsigned int intm_bsize : 2;
132 unsigned int l2_bsize : 2;
133 unsigned int dummy1 : 28;
134} reg_marb_foo_rw_dma1_burst;
135#define REG_RD_ADDR_marb_foo_rw_dma1_burst 536
136#define REG_WR_ADDR_marb_foo_rw_dma1_burst 536
137
138/* Register rw_dma2_burst, scope marb_foo, type rw */
139typedef struct {
140 unsigned int intm_bsize : 2;
141 unsigned int l2_bsize : 2;
142 unsigned int dummy1 : 28;
143} reg_marb_foo_rw_dma2_burst;
144#define REG_RD_ADDR_marb_foo_rw_dma2_burst 540
145#define REG_WR_ADDR_marb_foo_rw_dma2_burst 540
146
147/* Register rw_dma3_burst, scope marb_foo, type rw */
148typedef struct {
149 unsigned int intm_bsize : 2;
150 unsigned int l2_bsize : 2;
151 unsigned int dummy1 : 28;
152} reg_marb_foo_rw_dma3_burst;
153#define REG_RD_ADDR_marb_foo_rw_dma3_burst 544
154#define REG_WR_ADDR_marb_foo_rw_dma3_burst 544
155
156/* Register rw_dma4_burst, scope marb_foo, type rw */
157typedef struct {
158 unsigned int intm_bsize : 2;
159 unsigned int l2_bsize : 2;
160 unsigned int dummy1 : 28;
161} reg_marb_foo_rw_dma4_burst;
162#define REG_RD_ADDR_marb_foo_rw_dma4_burst 548
163#define REG_WR_ADDR_marb_foo_rw_dma4_burst 548
164
165/* Register rw_dma5_burst, scope marb_foo, type rw */
166typedef struct {
167 unsigned int intm_bsize : 2;
168 unsigned int l2_bsize : 2;
169 unsigned int dummy1 : 28;
170} reg_marb_foo_rw_dma5_burst;
171#define REG_RD_ADDR_marb_foo_rw_dma5_burst 552
172#define REG_WR_ADDR_marb_foo_rw_dma5_burst 552
173
174/* Register rw_dma6_burst, scope marb_foo, type rw */
175typedef struct {
176 unsigned int intm_bsize : 2;
177 unsigned int l2_bsize : 2;
178 unsigned int dummy1 : 28;
179} reg_marb_foo_rw_dma6_burst;
180#define REG_RD_ADDR_marb_foo_rw_dma6_burst 556
181#define REG_WR_ADDR_marb_foo_rw_dma6_burst 556
182
183/* Register rw_dma7_burst, scope marb_foo, type rw */
184typedef struct {
185 unsigned int intm_bsize : 2;
186 unsigned int l2_bsize : 2;
187 unsigned int dummy1 : 28;
188} reg_marb_foo_rw_dma7_burst;
189#define REG_RD_ADDR_marb_foo_rw_dma7_burst 560
190#define REG_WR_ADDR_marb_foo_rw_dma7_burst 560
191
192/* Register rw_dma9_burst, scope marb_foo, type rw */
193typedef struct {
194 unsigned int intm_bsize : 2;
195 unsigned int l2_bsize : 2;
196 unsigned int dummy1 : 28;
197} reg_marb_foo_rw_dma9_burst;
198#define REG_RD_ADDR_marb_foo_rw_dma9_burst 564
199#define REG_WR_ADDR_marb_foo_rw_dma9_burst 564
200
201/* Register rw_dma11_burst, scope marb_foo, type rw */
202typedef struct {
203 unsigned int intm_bsize : 2;
204 unsigned int l2_bsize : 2;
205 unsigned int dummy1 : 28;
206} reg_marb_foo_rw_dma11_burst;
207#define REG_RD_ADDR_marb_foo_rw_dma11_burst 568
208#define REG_WR_ADDR_marb_foo_rw_dma11_burst 568
209
210/* Register rw_cpui_burst, scope marb_foo, type rw */
211typedef struct {
212 unsigned int intm_bsize : 2;
213 unsigned int l2_bsize : 2;
214 unsigned int dummy1 : 28;
215} reg_marb_foo_rw_cpui_burst;
216#define REG_RD_ADDR_marb_foo_rw_cpui_burst 572
217#define REG_WR_ADDR_marb_foo_rw_cpui_burst 572
218
219/* Register rw_cpud_burst, scope marb_foo, type rw */
220typedef struct {
221 unsigned int intm_bsize : 2;
222 unsigned int l2_bsize : 2;
223 unsigned int dummy1 : 28;
224} reg_marb_foo_rw_cpud_burst;
225#define REG_RD_ADDR_marb_foo_rw_cpud_burst 576
226#define REG_WR_ADDR_marb_foo_rw_cpud_burst 576
227
228/* Register rw_iop_burst, scope marb_foo, type rw */
229typedef struct {
230 unsigned int intm_bsize : 2;
231 unsigned int l2_bsize : 2;
232 unsigned int dummy1 : 28;
233} reg_marb_foo_rw_iop_burst;
234#define REG_RD_ADDR_marb_foo_rw_iop_burst 580
235#define REG_WR_ADDR_marb_foo_rw_iop_burst 580
236
237/* Register rw_ccdstat_burst, scope marb_foo, type rw */
238typedef struct {
239 unsigned int intm_bsize : 2;
240 unsigned int l2_bsize : 2;
241 unsigned int dummy1 : 28;
242} reg_marb_foo_rw_ccdstat_burst;
243#define REG_RD_ADDR_marb_foo_rw_ccdstat_burst 584
244#define REG_WR_ADDR_marb_foo_rw_ccdstat_burst 584
245
246/* Register rw_intr_mask, scope marb_foo, type rw */
247typedef struct {
248 unsigned int bp0 : 1;
249 unsigned int bp1 : 1;
250 unsigned int bp2 : 1;
251 unsigned int bp3 : 1;
252 unsigned int dummy1 : 28;
253} reg_marb_foo_rw_intr_mask;
254#define REG_RD_ADDR_marb_foo_rw_intr_mask 588
255#define REG_WR_ADDR_marb_foo_rw_intr_mask 588
256
257/* Register rw_ack_intr, scope marb_foo, type rw */
258typedef struct {
259 unsigned int bp0 : 1;
260 unsigned int bp1 : 1;
261 unsigned int bp2 : 1;
262 unsigned int bp3 : 1;
263 unsigned int dummy1 : 28;
264} reg_marb_foo_rw_ack_intr;
265#define REG_RD_ADDR_marb_foo_rw_ack_intr 592
266#define REG_WR_ADDR_marb_foo_rw_ack_intr 592
267
268/* Register r_intr, scope marb_foo, type r */
269typedef struct {
270 unsigned int bp0 : 1;
271 unsigned int bp1 : 1;
272 unsigned int bp2 : 1;
273 unsigned int bp3 : 1;
274 unsigned int dummy1 : 28;
275} reg_marb_foo_r_intr;
276#define REG_RD_ADDR_marb_foo_r_intr 596
277
278/* Register r_masked_intr, scope marb_foo, type r */
279typedef struct {
280 unsigned int bp0 : 1;
281 unsigned int bp1 : 1;
282 unsigned int bp2 : 1;
283 unsigned int bp3 : 1;
284 unsigned int dummy1 : 28;
285} reg_marb_foo_r_masked_intr;
286#define REG_RD_ADDR_marb_foo_r_masked_intr 600
287
288/* Register rw_stop_mask, scope marb_foo, type rw */
289typedef struct {
290 unsigned int sclr : 1;
291 unsigned int dma0 : 1;
292 unsigned int dma1 : 1;
293 unsigned int dma2 : 1;
294 unsigned int dma3 : 1;
295 unsigned int dma4 : 1;
296 unsigned int dma5 : 1;
297 unsigned int dma6 : 1;
298 unsigned int dma7 : 1;
299 unsigned int dma9 : 1;
300 unsigned int dma11 : 1;
301 unsigned int cpui : 1;
302 unsigned int cpud : 1;
303 unsigned int iop : 1;
304 unsigned int ccdstat : 1;
305 unsigned int dummy1 : 17;
306} reg_marb_foo_rw_stop_mask;
307#define REG_RD_ADDR_marb_foo_rw_stop_mask 604
308#define REG_WR_ADDR_marb_foo_rw_stop_mask 604
309
310/* Register r_stopped, scope marb_foo, type r */
311typedef struct {
312 unsigned int sclr : 1;
313 unsigned int dma0 : 1;
314 unsigned int dma1 : 1;
315 unsigned int dma2 : 1;
316 unsigned int dma3 : 1;
317 unsigned int dma4 : 1;
318 unsigned int dma5 : 1;
319 unsigned int dma6 : 1;
320 unsigned int dma7 : 1;
321 unsigned int dma9 : 1;
322 unsigned int dma11 : 1;
323 unsigned int cpui : 1;
324 unsigned int cpud : 1;
325 unsigned int iop : 1;
326 unsigned int ccdstat : 1;
327 unsigned int dummy1 : 17;
328} reg_marb_foo_r_stopped;
329#define REG_RD_ADDR_marb_foo_r_stopped 608
330
331/* Register rw_no_snoop, scope marb_foo, type rw */
332typedef struct {
333 unsigned int sclr : 1;
334 unsigned int dma0 : 1;
335 unsigned int dma1 : 1;
336 unsigned int dma2 : 1;
337 unsigned int dma3 : 1;
338 unsigned int dma4 : 1;
339 unsigned int dma5 : 1;
340 unsigned int dma6 : 1;
341 unsigned int dma7 : 1;
342 unsigned int dma9 : 1;
343 unsigned int dma11 : 1;
344 unsigned int cpui : 1;
345 unsigned int cpud : 1;
346 unsigned int iop : 1;
347 unsigned int ccdstat : 1;
348 unsigned int dummy1 : 17;
349} reg_marb_foo_rw_no_snoop;
350#define REG_RD_ADDR_marb_foo_rw_no_snoop 896
351#define REG_WR_ADDR_marb_foo_rw_no_snoop 896
352
353/* Register rw_no_snoop_rq, scope marb_foo, type rw */
354typedef struct {
355 unsigned int dummy1 : 11;
356 unsigned int cpui : 1;
357 unsigned int cpud : 1;
358 unsigned int dummy2 : 19;
359} reg_marb_foo_rw_no_snoop_rq;
360#define REG_RD_ADDR_marb_foo_rw_no_snoop_rq 900
361#define REG_WR_ADDR_marb_foo_rw_no_snoop_rq 900
362
363
364/* Constants */
365enum {
366 regk_marb_foo_ccdstat = 0x0000000e,
367 regk_marb_foo_cpud = 0x0000000c,
368 regk_marb_foo_cpui = 0x0000000b,
369 regk_marb_foo_dma0 = 0x00000001,
370 regk_marb_foo_dma1 = 0x00000002,
371 regk_marb_foo_dma11 = 0x0000000a,
372 regk_marb_foo_dma2 = 0x00000003,
373 regk_marb_foo_dma3 = 0x00000004,
374 regk_marb_foo_dma4 = 0x00000005,
375 regk_marb_foo_dma5 = 0x00000006,
376 regk_marb_foo_dma6 = 0x00000007,
377 regk_marb_foo_dma7 = 0x00000008,
378 regk_marb_foo_dma9 = 0x00000009,
379 regk_marb_foo_iop = 0x0000000d,
380 regk_marb_foo_no = 0x00000000,
381 regk_marb_foo_r_stopped_default = 0x00000000,
382 regk_marb_foo_rw_ccdstat_burst_default = 0x00000000,
383 regk_marb_foo_rw_cpud_burst_default = 0x00000000,
384 regk_marb_foo_rw_cpui_burst_default = 0x00000000,
385 regk_marb_foo_rw_dma0_burst_default = 0x00000000,
386 regk_marb_foo_rw_dma11_burst_default = 0x00000000,
387 regk_marb_foo_rw_dma1_burst_default = 0x00000000,
388 regk_marb_foo_rw_dma2_burst_default = 0x00000000,
389 regk_marb_foo_rw_dma3_burst_default = 0x00000000,
390 regk_marb_foo_rw_dma4_burst_default = 0x00000000,
391 regk_marb_foo_rw_dma5_burst_default = 0x00000000,
392 regk_marb_foo_rw_dma6_burst_default = 0x00000000,
393 regk_marb_foo_rw_dma7_burst_default = 0x00000000,
394 regk_marb_foo_rw_dma9_burst_default = 0x00000000,
395 regk_marb_foo_rw_intm_slots_default = 0x00000000,
396 regk_marb_foo_rw_intm_slots_size = 0x00000040,
397 regk_marb_foo_rw_intr_mask_default = 0x00000000,
398 regk_marb_foo_rw_iop_burst_default = 0x00000000,
399 regk_marb_foo_rw_l2_slots_default = 0x00000000,
400 regk_marb_foo_rw_l2_slots_size = 0x00000040,
401 regk_marb_foo_rw_no_snoop_default = 0x00000000,
402 regk_marb_foo_rw_no_snoop_rq_default = 0x00000000,
403 regk_marb_foo_rw_regs_slots_default = 0x00000000,
404 regk_marb_foo_rw_regs_slots_size = 0x00000004,
405 regk_marb_foo_rw_sclr_burst_default = 0x00000000,
406 regk_marb_foo_rw_stop_mask_default = 0x00000000,
407 regk_marb_foo_sclr = 0x00000000,
408 regk_marb_foo_yes = 0x00000001
409};
410#endif /* __marb_foo_defs_h */
411#ifndef __marb_foo_bp_defs_h
412#define __marb_foo_bp_defs_h
413
414/*
415 * This file is autogenerated from
416 * file: marb_foo.r
417 *
418 * by ../../../tools/rdesc/bin/rdes2c -outfile marb_foo_defs.h marb_foo.r
419 * Any changes here will be lost.
420 *
421 * -*- buffer-read-only: t -*-
422 */
423/* Main access macros */
424#ifndef REG_RD
425#define REG_RD( scope, inst, reg ) \
426 REG_READ( reg_##scope##_##reg, \
427 (inst) + REG_RD_ADDR_##scope##_##reg )
428#endif
429
430#ifndef REG_WR
431#define REG_WR( scope, inst, reg, val ) \
432 REG_WRITE( reg_##scope##_##reg, \
433 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
434#endif
435
436#ifndef REG_RD_VECT
437#define REG_RD_VECT( scope, inst, reg, index ) \
438 REG_READ( reg_##scope##_##reg, \
439 (inst) + REG_RD_ADDR_##scope##_##reg + \
440 (index) * STRIDE_##scope##_##reg )
441#endif
442
443#ifndef REG_WR_VECT
444#define REG_WR_VECT( scope, inst, reg, index, val ) \
445 REG_WRITE( reg_##scope##_##reg, \
446 (inst) + REG_WR_ADDR_##scope##_##reg + \
447 (index) * STRIDE_##scope##_##reg, (val) )
448#endif
449
450#ifndef REG_RD_INT
451#define REG_RD_INT( scope, inst, reg ) \
452 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
453#endif
454
455#ifndef REG_WR_INT
456#define REG_WR_INT( scope, inst, reg, val ) \
457 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
458#endif
459
460#ifndef REG_RD_INT_VECT
461#define REG_RD_INT_VECT( scope, inst, reg, index ) \
462 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
463 (index) * STRIDE_##scope##_##reg )
464#endif
465
466#ifndef REG_WR_INT_VECT
467#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
468 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
469 (index) * STRIDE_##scope##_##reg, (val) )
470#endif
471
472#ifndef REG_TYPE_CONV
473#define REG_TYPE_CONV( type, orgtype, val ) \
474 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
475#endif
476
477#ifndef reg_page_size
478#define reg_page_size 8192
479#endif
480
481#ifndef REG_ADDR
482#define REG_ADDR( scope, inst, reg ) \
483 ( (inst) + REG_RD_ADDR_##scope##_##reg )
484#endif
485
486#ifndef REG_ADDR_VECT
487#define REG_ADDR_VECT( scope, inst, reg, index ) \
488 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
489 (index) * STRIDE_##scope##_##reg )
490#endif
491
492/* C-code for register scope marb_foo_bp */
493
494/* Register rw_first_addr, scope marb_foo_bp, type rw */
495typedef unsigned int reg_marb_foo_bp_rw_first_addr;
496#define REG_RD_ADDR_marb_foo_bp_rw_first_addr 0
497#define REG_WR_ADDR_marb_foo_bp_rw_first_addr 0
498
499/* Register rw_last_addr, scope marb_foo_bp, type rw */
500typedef unsigned int reg_marb_foo_bp_rw_last_addr;
501#define REG_RD_ADDR_marb_foo_bp_rw_last_addr 4
502#define REG_WR_ADDR_marb_foo_bp_rw_last_addr 4
503
504/* Register rw_op, scope marb_foo_bp, type rw */
505typedef struct {
506 unsigned int rd : 1;
507 unsigned int wr : 1;
508 unsigned int rd_excl : 1;
509 unsigned int pri_wr : 1;
510 unsigned int us_rd : 1;
511 unsigned int us_wr : 1;
512 unsigned int us_rd_excl : 1;
513 unsigned int us_pri_wr : 1;
514 unsigned int dummy1 : 24;
515} reg_marb_foo_bp_rw_op;
516#define REG_RD_ADDR_marb_foo_bp_rw_op 8
517#define REG_WR_ADDR_marb_foo_bp_rw_op 8
518
519/* Register rw_clients, scope marb_foo_bp, type rw */
520typedef struct {
521 unsigned int sclr : 1;
522 unsigned int dma0 : 1;
523 unsigned int dma1 : 1;
524 unsigned int dma2 : 1;
525 unsigned int dma3 : 1;
526 unsigned int dma4 : 1;
527 unsigned int dma5 : 1;
528 unsigned int dma6 : 1;
529 unsigned int dma7 : 1;
530 unsigned int dma9 : 1;
531 unsigned int dma11 : 1;
532 unsigned int cpui : 1;
533 unsigned int cpud : 1;
534 unsigned int iop : 1;
535 unsigned int ccdstat : 1;
536 unsigned int dummy1 : 17;
537} reg_marb_foo_bp_rw_clients;
538#define REG_RD_ADDR_marb_foo_bp_rw_clients 12
539#define REG_WR_ADDR_marb_foo_bp_rw_clients 12
540
541/* Register rw_options, scope marb_foo_bp, type rw */
542typedef struct {
543 unsigned int wrap : 1;
544 unsigned int dummy1 : 31;
545} reg_marb_foo_bp_rw_options;
546#define REG_RD_ADDR_marb_foo_bp_rw_options 16
547#define REG_WR_ADDR_marb_foo_bp_rw_options 16
548
549/* Register r_brk_addr, scope marb_foo_bp, type r */
550typedef unsigned int reg_marb_foo_bp_r_brk_addr;
551#define REG_RD_ADDR_marb_foo_bp_r_brk_addr 20
552
553/* Register r_brk_op, scope marb_foo_bp, type r */
554typedef struct {
555 unsigned int rd : 1;
556 unsigned int wr : 1;
557 unsigned int rd_excl : 1;
558 unsigned int pri_wr : 1;
559 unsigned int us_rd : 1;
560 unsigned int us_wr : 1;
561 unsigned int us_rd_excl : 1;
562 unsigned int us_pri_wr : 1;
563 unsigned int dummy1 : 24;
564} reg_marb_foo_bp_r_brk_op;
565#define REG_RD_ADDR_marb_foo_bp_r_brk_op 24
566
567/* Register r_brk_clients, scope marb_foo_bp, type r */
568typedef struct {
569 unsigned int sclr : 1;
570 unsigned int dma0 : 1;
571 unsigned int dma1 : 1;
572 unsigned int dma2 : 1;
573 unsigned int dma3 : 1;
574 unsigned int dma4 : 1;
575 unsigned int dma5 : 1;
576 unsigned int dma6 : 1;
577 unsigned int dma7 : 1;
578 unsigned int dma9 : 1;
579 unsigned int dma11 : 1;
580 unsigned int cpui : 1;
581 unsigned int cpud : 1;
582 unsigned int iop : 1;
583 unsigned int ccdstat : 1;
584 unsigned int dummy1 : 17;
585} reg_marb_foo_bp_r_brk_clients;
586#define REG_RD_ADDR_marb_foo_bp_r_brk_clients 28
587
588/* Register r_brk_first_client, scope marb_foo_bp, type r */
589typedef struct {
590 unsigned int sclr : 1;
591 unsigned int dma0 : 1;
592 unsigned int dma1 : 1;
593 unsigned int dma2 : 1;
594 unsigned int dma3 : 1;
595 unsigned int dma4 : 1;
596 unsigned int dma5 : 1;
597 unsigned int dma6 : 1;
598 unsigned int dma7 : 1;
599 unsigned int dma9 : 1;
600 unsigned int dma11 : 1;
601 unsigned int cpui : 1;
602 unsigned int cpud : 1;
603 unsigned int iop : 1;
604 unsigned int ccdstat : 1;
605 unsigned int dummy1 : 17;
606} reg_marb_foo_bp_r_brk_first_client;
607#define REG_RD_ADDR_marb_foo_bp_r_brk_first_client 32
608
609/* Register r_brk_size, scope marb_foo_bp, type r */
610typedef unsigned int reg_marb_foo_bp_r_brk_size;
611#define REG_RD_ADDR_marb_foo_bp_r_brk_size 36
612
613/* Register rw_ack, scope marb_foo_bp, type rw */
614typedef unsigned int reg_marb_foo_bp_rw_ack;
615#define REG_RD_ADDR_marb_foo_bp_rw_ack 40
616#define REG_WR_ADDR_marb_foo_bp_rw_ack 40
617
618
619/* Constants */
620enum {
621 regk_marb_foo_bp_no = 0x00000000,
622 regk_marb_foo_bp_rw_op_default = 0x00000000,
623 regk_marb_foo_bp_rw_options_default = 0x00000000,
624 regk_marb_foo_bp_yes = 0x00000001
625};
626#endif /* __marb_foo_bp_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/pinmux_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/pinmux_defs.h
new file mode 100644
index 000000000000..4b96cd2cba8a
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/pinmux_defs.h
@@ -0,0 +1,312 @@
1#ifndef __pinmux_defs_h
2#define __pinmux_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: pinmux.r
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -outfile pinmux_defs.h pinmux.r
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13/* Main access macros */
14#ifndef REG_RD
15#define REG_RD( scope, inst, reg ) \
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
18#endif
19
20#ifndef REG_WR
21#define REG_WR( scope, inst, reg, val ) \
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
24#endif
25
26#ifndef REG_RD_VECT
27#define REG_RD_VECT( scope, inst, reg, index ) \
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
31#endif
32
33#ifndef REG_WR_VECT
34#define REG_WR_VECT( scope, inst, reg, index, val ) \
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
38#endif
39
40#ifndef REG_RD_INT
41#define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
43#endif
44
45#ifndef REG_WR_INT
46#define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
48#endif
49
50#ifndef REG_RD_INT_VECT
51#define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
53 (index) * STRIDE_##scope##_##reg )
54#endif
55
56#ifndef REG_WR_INT_VECT
57#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
59 (index) * STRIDE_##scope##_##reg, (val) )
60#endif
61
62#ifndef REG_TYPE_CONV
63#define REG_TYPE_CONV( type, orgtype, val ) \
64 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
65#endif
66
67#ifndef reg_page_size
68#define reg_page_size 8192
69#endif
70
71#ifndef REG_ADDR
72#define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
74#endif
75
76#ifndef REG_ADDR_VECT
77#define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
79 (index) * STRIDE_##scope##_##reg )
80#endif
81
82/* C-code for register scope pinmux */
83
84/* Register rw_hwprot, scope pinmux, type rw */
85typedef struct {
86 unsigned int eth : 1;
87 unsigned int eth_mdio : 1;
88 unsigned int geth : 1;
89 unsigned int tg : 1;
90 unsigned int tg_clk : 1;
91 unsigned int vout : 1;
92 unsigned int vout_sync : 1;
93 unsigned int ser1 : 1;
94 unsigned int ser2 : 1;
95 unsigned int ser3 : 1;
96 unsigned int ser4 : 1;
97 unsigned int sser : 1;
98 unsigned int pwm0 : 1;
99 unsigned int pwm1 : 1;
100 unsigned int pwm2 : 1;
101 unsigned int timer0 : 1;
102 unsigned int timer1 : 1;
103 unsigned int pio : 1;
104 unsigned int i2c0 : 1;
105 unsigned int i2c1 : 1;
106 unsigned int i2c1_sda1 : 1;
107 unsigned int i2c1_sda2 : 1;
108 unsigned int i2c1_sda3 : 1;
109 unsigned int i2c1_sen : 1;
110 unsigned int dummy1 : 8;
111} reg_pinmux_rw_hwprot;
112#define REG_RD_ADDR_pinmux_rw_hwprot 0
113#define REG_WR_ADDR_pinmux_rw_hwprot 0
114
115/* Register rw_gio_pa, scope pinmux, type rw */
116typedef struct {
117 unsigned int pa0 : 1;
118 unsigned int pa1 : 1;
119 unsigned int pa2 : 1;
120 unsigned int pa3 : 1;
121 unsigned int pa4 : 1;
122 unsigned int pa5 : 1;
123 unsigned int pa6 : 1;
124 unsigned int pa7 : 1;
125 unsigned int pa8 : 1;
126 unsigned int pa9 : 1;
127 unsigned int pa10 : 1;
128 unsigned int pa11 : 1;
129 unsigned int pa12 : 1;
130 unsigned int pa13 : 1;
131 unsigned int pa14 : 1;
132 unsigned int pa15 : 1;
133 unsigned int pa16 : 1;
134 unsigned int pa17 : 1;
135 unsigned int pa18 : 1;
136 unsigned int pa19 : 1;
137 unsigned int pa20 : 1;
138 unsigned int pa21 : 1;
139 unsigned int pa22 : 1;
140 unsigned int pa23 : 1;
141 unsigned int pa24 : 1;
142 unsigned int pa25 : 1;
143 unsigned int pa26 : 1;
144 unsigned int pa27 : 1;
145 unsigned int pa28 : 1;
146 unsigned int pa29 : 1;
147 unsigned int pa30 : 1;
148 unsigned int pa31 : 1;
149} reg_pinmux_rw_gio_pa;
150#define REG_RD_ADDR_pinmux_rw_gio_pa 4
151#define REG_WR_ADDR_pinmux_rw_gio_pa 4
152
153/* Register rw_gio_pb, scope pinmux, type rw */
154typedef struct {
155 unsigned int pb0 : 1;
156 unsigned int pb1 : 1;
157 unsigned int pb2 : 1;
158 unsigned int pb3 : 1;
159 unsigned int pb4 : 1;
160 unsigned int pb5 : 1;
161 unsigned int pb6 : 1;
162 unsigned int pb7 : 1;
163 unsigned int pb8 : 1;
164 unsigned int pb9 : 1;
165 unsigned int pb10 : 1;
166 unsigned int pb11 : 1;
167 unsigned int pb12 : 1;
168 unsigned int pb13 : 1;
169 unsigned int pb14 : 1;
170 unsigned int pb15 : 1;
171 unsigned int pb16 : 1;
172 unsigned int pb17 : 1;
173 unsigned int pb18 : 1;
174 unsigned int pb19 : 1;
175 unsigned int pb20 : 1;
176 unsigned int pb21 : 1;
177 unsigned int pb22 : 1;
178 unsigned int pb23 : 1;
179 unsigned int pb24 : 1;
180 unsigned int pb25 : 1;
181 unsigned int pb26 : 1;
182 unsigned int pb27 : 1;
183 unsigned int pb28 : 1;
184 unsigned int pb29 : 1;
185 unsigned int pb30 : 1;
186 unsigned int pb31 : 1;
187} reg_pinmux_rw_gio_pb;
188#define REG_RD_ADDR_pinmux_rw_gio_pb 8
189#define REG_WR_ADDR_pinmux_rw_gio_pb 8
190
191/* Register rw_gio_pc, scope pinmux, type rw */
192typedef struct {
193 unsigned int pc0 : 1;
194 unsigned int pc1 : 1;
195 unsigned int pc2 : 1;
196 unsigned int pc3 : 1;
197 unsigned int pc4 : 1;
198 unsigned int pc5 : 1;
199 unsigned int pc6 : 1;
200 unsigned int pc7 : 1;
201 unsigned int pc8 : 1;
202 unsigned int pc9 : 1;
203 unsigned int pc10 : 1;
204 unsigned int pc11 : 1;
205 unsigned int pc12 : 1;
206 unsigned int pc13 : 1;
207 unsigned int pc14 : 1;
208 unsigned int pc15 : 1;
209 unsigned int dummy1 : 16;
210} reg_pinmux_rw_gio_pc;
211#define REG_RD_ADDR_pinmux_rw_gio_pc 12
212#define REG_WR_ADDR_pinmux_rw_gio_pc 12
213
214/* Register rw_iop_pa, scope pinmux, type rw */
215typedef struct {
216 unsigned int pa0 : 1;
217 unsigned int pa1 : 1;
218 unsigned int pa2 : 1;
219 unsigned int pa3 : 1;
220 unsigned int pa4 : 1;
221 unsigned int pa5 : 1;
222 unsigned int pa6 : 1;
223 unsigned int pa7 : 1;
224 unsigned int pa8 : 1;
225 unsigned int pa9 : 1;
226 unsigned int pa10 : 1;
227 unsigned int pa11 : 1;
228 unsigned int pa12 : 1;
229 unsigned int pa13 : 1;
230 unsigned int pa14 : 1;
231 unsigned int pa15 : 1;
232 unsigned int pa16 : 1;
233 unsigned int pa17 : 1;
234 unsigned int pa18 : 1;
235 unsigned int pa19 : 1;
236 unsigned int pa20 : 1;
237 unsigned int pa21 : 1;
238 unsigned int pa22 : 1;
239 unsigned int pa23 : 1;
240 unsigned int pa24 : 1;
241 unsigned int pa25 : 1;
242 unsigned int pa26 : 1;
243 unsigned int pa27 : 1;
244 unsigned int pa28 : 1;
245 unsigned int pa29 : 1;
246 unsigned int pa30 : 1;
247 unsigned int pa31 : 1;
248} reg_pinmux_rw_iop_pa;
249#define REG_RD_ADDR_pinmux_rw_iop_pa 16
250#define REG_WR_ADDR_pinmux_rw_iop_pa 16
251
252/* Register rw_iop_pb, scope pinmux, type rw */
253typedef struct {
254 unsigned int pb0 : 1;
255 unsigned int pb1 : 1;
256 unsigned int pb2 : 1;
257 unsigned int pb3 : 1;
258 unsigned int pb4 : 1;
259 unsigned int pb5 : 1;
260 unsigned int pb6 : 1;
261 unsigned int pb7 : 1;
262 unsigned int dummy1 : 24;
263} reg_pinmux_rw_iop_pb;
264#define REG_RD_ADDR_pinmux_rw_iop_pb 20
265#define REG_WR_ADDR_pinmux_rw_iop_pb 20
266
267/* Register rw_iop_pio, scope pinmux, type rw */
268typedef struct {
269 unsigned int d0 : 1;
270 unsigned int d1 : 1;
271 unsigned int d2 : 1;
272 unsigned int d3 : 1;
273 unsigned int d4 : 1;
274 unsigned int d5 : 1;
275 unsigned int d6 : 1;
276 unsigned int d7 : 1;
277 unsigned int rd_n : 1;
278 unsigned int wr_n : 1;
279 unsigned int a0 : 1;
280 unsigned int a1 : 1;
281 unsigned int ce0_n : 1;
282 unsigned int ce1_n : 1;
283 unsigned int ce2_n : 1;
284 unsigned int rdy : 1;
285 unsigned int dummy1 : 16;
286} reg_pinmux_rw_iop_pio;
287#define REG_RD_ADDR_pinmux_rw_iop_pio 24
288#define REG_WR_ADDR_pinmux_rw_iop_pio 24
289
290/* Register rw_iop_usb, scope pinmux, type rw */
291typedef struct {
292 unsigned int usb0 : 1;
293 unsigned int dummy1 : 31;
294} reg_pinmux_rw_iop_usb;
295#define REG_RD_ADDR_pinmux_rw_iop_usb 28
296#define REG_WR_ADDR_pinmux_rw_iop_usb 28
297
298
299/* Constants */
300enum {
301 regk_pinmux_no = 0x00000000,
302 regk_pinmux_rw_gio_pa_default = 0x00000000,
303 regk_pinmux_rw_gio_pb_default = 0x00000000,
304 regk_pinmux_rw_gio_pc_default = 0x00000000,
305 regk_pinmux_rw_hwprot_default = 0x00000000,
306 regk_pinmux_rw_iop_pa_default = 0x00000000,
307 regk_pinmux_rw_iop_pb_default = 0x00000000,
308 regk_pinmux_rw_iop_pio_default = 0x00000000,
309 regk_pinmux_rw_iop_usb_default = 0x00000001,
310 regk_pinmux_yes = 0x00000001
311};
312#endif /* __pinmux_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/pio_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/pio_defs.h
new file mode 100644
index 000000000000..2d8e4b4cc602
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/pio_defs.h
@@ -0,0 +1,371 @@
1#ifndef __pio_defs_h
2#define __pio_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: pio.r
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -outfile pio_defs.h pio.r
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13/* Main access macros */
14#ifndef REG_RD
15#define REG_RD( scope, inst, reg ) \
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
18#endif
19
20#ifndef REG_WR
21#define REG_WR( scope, inst, reg, val ) \
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
24#endif
25
26#ifndef REG_RD_VECT
27#define REG_RD_VECT( scope, inst, reg, index ) \
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
31#endif
32
33#ifndef REG_WR_VECT
34#define REG_WR_VECT( scope, inst, reg, index, val ) \
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
38#endif
39
40#ifndef REG_RD_INT
41#define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
43#endif
44
45#ifndef REG_WR_INT
46#define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
48#endif
49
50#ifndef REG_RD_INT_VECT
51#define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
53 (index) * STRIDE_##scope##_##reg )
54#endif
55
56#ifndef REG_WR_INT_VECT
57#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
59 (index) * STRIDE_##scope##_##reg, (val) )
60#endif
61
62#ifndef REG_TYPE_CONV
63#define REG_TYPE_CONV( type, orgtype, val ) \
64 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
65#endif
66
67#ifndef reg_page_size
68#define reg_page_size 8192
69#endif
70
71#ifndef REG_ADDR
72#define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
74#endif
75
76#ifndef REG_ADDR_VECT
77#define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
79 (index) * STRIDE_##scope##_##reg )
80#endif
81
82/* C-code for register scope pio */
83
84/* Register rw_data, scope pio, type rw */
85typedef unsigned int reg_pio_rw_data;
86#define REG_RD_ADDR_pio_rw_data 64
87#define REG_WR_ADDR_pio_rw_data 64
88
89/* Register rw_io_access0, scope pio, type rw */
90typedef struct {
91 unsigned int data : 8;
92 unsigned int dummy1 : 24;
93} reg_pio_rw_io_access0;
94#define REG_RD_ADDR_pio_rw_io_access0 0
95#define REG_WR_ADDR_pio_rw_io_access0 0
96
97/* Register rw_io_access1, scope pio, type rw */
98typedef struct {
99 unsigned int data : 8;
100 unsigned int dummy1 : 24;
101} reg_pio_rw_io_access1;
102#define REG_RD_ADDR_pio_rw_io_access1 4
103#define REG_WR_ADDR_pio_rw_io_access1 4
104
105/* Register rw_io_access2, scope pio, type rw */
106typedef struct {
107 unsigned int data : 8;
108 unsigned int dummy1 : 24;
109} reg_pio_rw_io_access2;
110#define REG_RD_ADDR_pio_rw_io_access2 8
111#define REG_WR_ADDR_pio_rw_io_access2 8
112
113/* Register rw_io_access3, scope pio, type rw */
114typedef struct {
115 unsigned int data : 8;
116 unsigned int dummy1 : 24;
117} reg_pio_rw_io_access3;
118#define REG_RD_ADDR_pio_rw_io_access3 12
119#define REG_WR_ADDR_pio_rw_io_access3 12
120
121/* Register rw_io_access4, scope pio, type rw */
122typedef struct {
123 unsigned int data : 8;
124 unsigned int dummy1 : 24;
125} reg_pio_rw_io_access4;
126#define REG_RD_ADDR_pio_rw_io_access4 16
127#define REG_WR_ADDR_pio_rw_io_access4 16
128
129/* Register rw_io_access5, scope pio, type rw */
130typedef struct {
131 unsigned int data : 8;
132 unsigned int dummy1 : 24;
133} reg_pio_rw_io_access5;
134#define REG_RD_ADDR_pio_rw_io_access5 20
135#define REG_WR_ADDR_pio_rw_io_access5 20
136
137/* Register rw_io_access6, scope pio, type rw */
138typedef struct {
139 unsigned int data : 8;
140 unsigned int dummy1 : 24;
141} reg_pio_rw_io_access6;
142#define REG_RD_ADDR_pio_rw_io_access6 24
143#define REG_WR_ADDR_pio_rw_io_access6 24
144
145/* Register rw_io_access7, scope pio, type rw */
146typedef struct {
147 unsigned int data : 8;
148 unsigned int dummy1 : 24;
149} reg_pio_rw_io_access7;
150#define REG_RD_ADDR_pio_rw_io_access7 28
151#define REG_WR_ADDR_pio_rw_io_access7 28
152
153/* Register rw_io_access8, scope pio, type rw */
154typedef struct {
155 unsigned int data : 8;
156 unsigned int dummy1 : 24;
157} reg_pio_rw_io_access8;
158#define REG_RD_ADDR_pio_rw_io_access8 32
159#define REG_WR_ADDR_pio_rw_io_access8 32
160
161/* Register rw_io_access9, scope pio, type rw */
162typedef struct {
163 unsigned int data : 8;
164 unsigned int dummy1 : 24;
165} reg_pio_rw_io_access9;
166#define REG_RD_ADDR_pio_rw_io_access9 36
167#define REG_WR_ADDR_pio_rw_io_access9 36
168
169/* Register rw_io_access10, scope pio, type rw */
170typedef struct {
171 unsigned int data : 8;
172 unsigned int dummy1 : 24;
173} reg_pio_rw_io_access10;
174#define REG_RD_ADDR_pio_rw_io_access10 40
175#define REG_WR_ADDR_pio_rw_io_access10 40
176
177/* Register rw_io_access11, scope pio, type rw */
178typedef struct {
179 unsigned int data : 8;
180 unsigned int dummy1 : 24;
181} reg_pio_rw_io_access11;
182#define REG_RD_ADDR_pio_rw_io_access11 44
183#define REG_WR_ADDR_pio_rw_io_access11 44
184
185/* Register rw_io_access12, scope pio, type rw */
186typedef struct {
187 unsigned int data : 8;
188 unsigned int dummy1 : 24;
189} reg_pio_rw_io_access12;
190#define REG_RD_ADDR_pio_rw_io_access12 48
191#define REG_WR_ADDR_pio_rw_io_access12 48
192
193/* Register rw_io_access13, scope pio, type rw */
194typedef struct {
195 unsigned int data : 8;
196 unsigned int dummy1 : 24;
197} reg_pio_rw_io_access13;
198#define REG_RD_ADDR_pio_rw_io_access13 52
199#define REG_WR_ADDR_pio_rw_io_access13 52
200
201/* Register rw_io_access14, scope pio, type rw */
202typedef struct {
203 unsigned int data : 8;
204 unsigned int dummy1 : 24;
205} reg_pio_rw_io_access14;
206#define REG_RD_ADDR_pio_rw_io_access14 56
207#define REG_WR_ADDR_pio_rw_io_access14 56
208
209/* Register rw_io_access15, scope pio, type rw */
210typedef struct {
211 unsigned int data : 8;
212 unsigned int dummy1 : 24;
213} reg_pio_rw_io_access15;
214#define REG_RD_ADDR_pio_rw_io_access15 60
215#define REG_WR_ADDR_pio_rw_io_access15 60
216
217/* Register rw_ce0_cfg, scope pio, type rw */
218typedef struct {
219 unsigned int lw : 6;
220 unsigned int ew : 3;
221 unsigned int zw : 3;
222 unsigned int aw : 2;
223 unsigned int mode : 2;
224 unsigned int dummy1 : 16;
225} reg_pio_rw_ce0_cfg;
226#define REG_RD_ADDR_pio_rw_ce0_cfg 68
227#define REG_WR_ADDR_pio_rw_ce0_cfg 68
228
229/* Register rw_ce1_cfg, scope pio, type rw */
230typedef struct {
231 unsigned int lw : 6;
232 unsigned int ew : 3;
233 unsigned int zw : 3;
234 unsigned int aw : 2;
235 unsigned int mode : 2;
236 unsigned int dummy1 : 16;
237} reg_pio_rw_ce1_cfg;
238#define REG_RD_ADDR_pio_rw_ce1_cfg 72
239#define REG_WR_ADDR_pio_rw_ce1_cfg 72
240
241/* Register rw_ce2_cfg, scope pio, type rw */
242typedef struct {
243 unsigned int lw : 6;
244 unsigned int ew : 3;
245 unsigned int zw : 3;
246 unsigned int aw : 2;
247 unsigned int mode : 2;
248 unsigned int dummy1 : 16;
249} reg_pio_rw_ce2_cfg;
250#define REG_RD_ADDR_pio_rw_ce2_cfg 76
251#define REG_WR_ADDR_pio_rw_ce2_cfg 76
252
253/* Register rw_dout, scope pio, type rw */
254typedef struct {
255 unsigned int data : 8;
256 unsigned int rd_n : 1;
257 unsigned int wr_n : 1;
258 unsigned int a0 : 1;
259 unsigned int a1 : 1;
260 unsigned int ce0_n : 1;
261 unsigned int ce1_n : 1;
262 unsigned int ce2_n : 1;
263 unsigned int rdy : 1;
264 unsigned int dummy1 : 16;
265} reg_pio_rw_dout;
266#define REG_RD_ADDR_pio_rw_dout 80
267#define REG_WR_ADDR_pio_rw_dout 80
268
269/* Register rw_oe, scope pio, type rw */
270typedef struct {
271 unsigned int data : 8;
272 unsigned int rd_n : 1;
273 unsigned int wr_n : 1;
274 unsigned int a0 : 1;
275 unsigned int a1 : 1;
276 unsigned int ce0_n : 1;
277 unsigned int ce1_n : 1;
278 unsigned int ce2_n : 1;
279 unsigned int rdy : 1;
280 unsigned int dummy1 : 16;
281} reg_pio_rw_oe;
282#define REG_RD_ADDR_pio_rw_oe 84
283#define REG_WR_ADDR_pio_rw_oe 84
284
285/* Register rw_man_ctrl, scope pio, type rw */
286typedef struct {
287 unsigned int data : 8;
288 unsigned int rd_n : 1;
289 unsigned int wr_n : 1;
290 unsigned int a0 : 1;
291 unsigned int a1 : 1;
292 unsigned int ce0_n : 1;
293 unsigned int ce1_n : 1;
294 unsigned int ce2_n : 1;
295 unsigned int rdy : 1;
296 unsigned int dummy1 : 16;
297} reg_pio_rw_man_ctrl;
298#define REG_RD_ADDR_pio_rw_man_ctrl 88
299#define REG_WR_ADDR_pio_rw_man_ctrl 88
300
301/* Register r_din, scope pio, type r */
302typedef struct {
303 unsigned int data : 8;
304 unsigned int rd_n : 1;
305 unsigned int wr_n : 1;
306 unsigned int a0 : 1;
307 unsigned int a1 : 1;
308 unsigned int ce0_n : 1;
309 unsigned int ce1_n : 1;
310 unsigned int ce2_n : 1;
311 unsigned int rdy : 1;
312 unsigned int dummy1 : 16;
313} reg_pio_r_din;
314#define REG_RD_ADDR_pio_r_din 92
315
316/* Register r_stat, scope pio, type r */
317typedef struct {
318 unsigned int busy : 1;
319 unsigned int dummy1 : 31;
320} reg_pio_r_stat;
321#define REG_RD_ADDR_pio_r_stat 96
322
323/* Register rw_intr_mask, scope pio, type rw */
324typedef struct {
325 unsigned int rdy : 1;
326 unsigned int dummy1 : 31;
327} reg_pio_rw_intr_mask;
328#define REG_RD_ADDR_pio_rw_intr_mask 100
329#define REG_WR_ADDR_pio_rw_intr_mask 100
330
331/* Register rw_ack_intr, scope pio, type rw */
332typedef struct {
333 unsigned int rdy : 1;
334 unsigned int dummy1 : 31;
335} reg_pio_rw_ack_intr;
336#define REG_RD_ADDR_pio_rw_ack_intr 104
337#define REG_WR_ADDR_pio_rw_ack_intr 104
338
339/* Register r_intr, scope pio, type r */
340typedef struct {
341 unsigned int rdy : 1;
342 unsigned int dummy1 : 31;
343} reg_pio_r_intr;
344#define REG_RD_ADDR_pio_r_intr 108
345
346/* Register r_masked_intr, scope pio, type r */
347typedef struct {
348 unsigned int rdy : 1;
349 unsigned int dummy1 : 31;
350} reg_pio_r_masked_intr;
351#define REG_RD_ADDR_pio_r_masked_intr 112
352
353
354/* Constants */
355enum {
356 regk_pio_a2 = 0x00000003,
357 regk_pio_no = 0x00000000,
358 regk_pio_normal = 0x00000000,
359 regk_pio_rd = 0x00000001,
360 regk_pio_rw_ce0_cfg_default = 0x00000000,
361 regk_pio_rw_ce1_cfg_default = 0x00000000,
362 regk_pio_rw_ce2_cfg_default = 0x00000000,
363 regk_pio_rw_intr_mask_default = 0x00000000,
364 regk_pio_rw_man_ctrl_default = 0x00000000,
365 regk_pio_rw_oe_default = 0x00000000,
366 regk_pio_wr = 0x00000002,
367 regk_pio_wr_ce2 = 0x00000003,
368 regk_pio_yes = 0x00000001,
369 regk_pio_yes_all = 0x000000ff
370};
371#endif /* __pio_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/reg_map.h b/include/asm-cris/arch-v32/mach-a3/hwregs/reg_map.h
new file mode 100644
index 000000000000..36e59d6e96b6
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/reg_map.h
@@ -0,0 +1,103 @@
1#ifndef __reg_map_h
2#define __reg_map_h
3
4/*
5 * This file is autogenerated from
6 * file: reg.rmap
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -base 0xb0000000 -map marb_bar.r marb_foo.r ccd_top.r ccd_stat.r ccd_tg.r ccd_dp.r ccd.r iop_sap_in.r iop_sap_out.r iop_sw_cfg.r iop_sw_cpu.r iop_sw_mpu.r iop_sw_spu.r iop_version.r iop_crc_par.r iop_dmc_in.r iop_dmc_out.r iop_fifo_in_extra.r iop_fifo_in.r iop_fifo_out_extra.r iop_fifo_out.r iop_mc.r iop_mpu.r iop_scrc_in.r iop_scrc_out.r iop_spu.r iop_timer_grp.r iop_trigger_grp.r iop.r -outfile reg_map.h reg.rmap
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13typedef enum {
14 regi_ccd = 0xb0000000,
15 regi_ccd_top = 0xb0000000,
16 regi_ccd_dp = 0xb0000400,
17 regi_ccd_stat = 0xb0000800,
18 regi_ccd_tg = 0xb0001000,
19 regi_cfg = 0xb0002000,
20 regi_clkgen = 0xb0004000,
21 regi_ddr2_ctrl = 0xb0006000,
22 regi_dma0 = 0xb0008000,
23 regi_dma1 = 0xb000a000,
24 regi_dma11 = 0xb000c000,
25 regi_dma2 = 0xb000e000,
26 regi_dma3 = 0xb0010000,
27 regi_dma4 = 0xb0012000,
28 regi_dma5 = 0xb0014000,
29 regi_dma6 = 0xb0016000,
30 regi_dma7 = 0xb0018000,
31 regi_dma9 = 0xb001a000,
32 regi_eth = 0xb001c000,
33 regi_gio = 0xb0020000,
34 regi_h264 = 0xb0022000,
35 regi_hist = 0xb0026000,
36 regi_iop = 0xb0028000,
37 regi_iop_version = 0xb0028000,
38 regi_iop_fifo_in_extra = 0xb0028040,
39 regi_iop_fifo_out_extra = 0xb0028080,
40 regi_iop_trigger_grp0 = 0xb00280c0,
41 regi_iop_trigger_grp1 = 0xb0028100,
42 regi_iop_trigger_grp2 = 0xb0028140,
43 regi_iop_trigger_grp3 = 0xb0028180,
44 regi_iop_trigger_grp4 = 0xb00281c0,
45 regi_iop_trigger_grp5 = 0xb0028200,
46 regi_iop_trigger_grp6 = 0xb0028240,
47 regi_iop_trigger_grp7 = 0xb0028280,
48 regi_iop_crc_par = 0xb0028300,
49 regi_iop_dmc_in = 0xb0028380,
50 regi_iop_dmc_out = 0xb0028400,
51 regi_iop_fifo_in = 0xb0028480,
52 regi_iop_fifo_out = 0xb0028500,
53 regi_iop_scrc_in = 0xb0028580,
54 regi_iop_scrc_out = 0xb0028600,
55 regi_iop_timer_grp0 = 0xb0028680,
56 regi_iop_timer_grp1 = 0xb0028700,
57 regi_iop_sap_in = 0xb0028800,
58 regi_iop_sap_out = 0xb0028900,
59 regi_iop_spu = 0xb0028a00,
60 regi_iop_sw_cfg = 0xb0028b00,
61 regi_iop_sw_cpu = 0xb0028c00,
62 regi_iop_sw_mpu = 0xb0028d00,
63 regi_iop_sw_spu = 0xb0028e00,
64 regi_iop_mpu = 0xb0029000,
65 regi_irq = 0xb002a000,
66 regi_irq2 = 0xb006a000,
67 regi_jpeg = 0xb002c000,
68 regi_l2cache = 0xb0030000,
69 regi_marb_bar = 0xb0032000,
70 regi_marb_bar_bp0 = 0xb0032140,
71 regi_marb_bar_bp1 = 0xb0032180,
72 regi_marb_bar_bp2 = 0xb00321c0,
73 regi_marb_bar_bp3 = 0xb0032200,
74 regi_marb_foo = 0xb0034000,
75 regi_marb_foo_bp0 = 0xb0034280,
76 regi_marb_foo_bp1 = 0xb00342c0,
77 regi_marb_foo_bp2 = 0xb0034300,
78 regi_marb_foo_bp3 = 0xb0034340,
79 regi_pinmux = 0xb0038000,
80 regi_pio = 0xb0036000,
81 regi_sclr = 0xb003a000,
82 regi_sclr_fifo = 0xb003c000,
83 regi_ser0 = 0xb003e000,
84 regi_ser1 = 0xb0040000,
85 regi_ser2 = 0xb0042000,
86 regi_ser3 = 0xb0044000,
87 regi_ser4 = 0xb0046000,
88 regi_sser = 0xb0048000,
89 regi_strcop = 0xb004a000,
90 regi_strdma0 = 0xb004e000,
91 regi_strdma1 = 0xb0050000,
92 regi_strdma2 = 0xb0052000,
93 regi_strdma3 = 0xb0054000,
94 regi_strdma5 = 0xb0056000,
95 regi_strmux = 0xb004c000,
96 regi_timer0 = 0xb0058000,
97 regi_timer1 = 0xb005a000,
98 regi_timer2 = 0xb006e000,
99 regi_trace = 0xb005c000,
100 regi_vin = 0xb005e000,
101 regi_vout = 0xb0060000
102} reg_scope_instances;
103#endif /* __reg_map_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/strmux_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/strmux_defs.h
new file mode 100644
index 000000000000..14f718a4ecc3
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/strmux_defs.h
@@ -0,0 +1,120 @@
1#ifndef __strmux_defs_h
2#define __strmux_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: strmux.r
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -outfile strmux_defs.h strmux.r
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13/* Main access macros */
14#ifndef REG_RD
15#define REG_RD( scope, inst, reg ) \
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
18#endif
19
20#ifndef REG_WR
21#define REG_WR( scope, inst, reg, val ) \
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
24#endif
25
26#ifndef REG_RD_VECT
27#define REG_RD_VECT( scope, inst, reg, index ) \
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
31#endif
32
33#ifndef REG_WR_VECT
34#define REG_WR_VECT( scope, inst, reg, index, val ) \
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
38#endif
39
40#ifndef REG_RD_INT
41#define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
43#endif
44
45#ifndef REG_WR_INT
46#define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
48#endif
49
50#ifndef REG_RD_INT_VECT
51#define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
53 (index) * STRIDE_##scope##_##reg )
54#endif
55
56#ifndef REG_WR_INT_VECT
57#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
59 (index) * STRIDE_##scope##_##reg, (val) )
60#endif
61
62#ifndef REG_TYPE_CONV
63#define REG_TYPE_CONV( type, orgtype, val ) \
64 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
65#endif
66
67#ifndef reg_page_size
68#define reg_page_size 8192
69#endif
70
71#ifndef REG_ADDR
72#define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
74#endif
75
76#ifndef REG_ADDR_VECT
77#define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
79 (index) * STRIDE_##scope##_##reg )
80#endif
81
82/* C-code for register scope strmux */
83
84/* Register rw_cfg, scope strmux, type rw */
85typedef struct {
86 unsigned int dma0 : 2;
87 unsigned int dma1 : 2;
88 unsigned int dma2 : 2;
89 unsigned int dma3 : 2;
90 unsigned int dma4 : 2;
91 unsigned int dma5 : 2;
92 unsigned int dma6 : 2;
93 unsigned int dma7 : 2;
94 unsigned int dummy1 : 2;
95 unsigned int dma9 : 2;
96 unsigned int dummy2 : 2;
97 unsigned int dma11 : 2;
98 unsigned int dummy3 : 8;
99} reg_strmux_rw_cfg;
100#define REG_RD_ADDR_strmux_rw_cfg 0
101#define REG_WR_ADDR_strmux_rw_cfg 0
102
103
104/* Constants */
105enum {
106 regk_strmux_eth = 0x00000001,
107 regk_strmux_h264 = 0x00000001,
108 regk_strmux_iop = 0x00000001,
109 regk_strmux_jpeg = 0x00000001,
110 regk_strmux_off = 0x00000000,
111 regk_strmux_rw_cfg_default = 0x00000000,
112 regk_strmux_ser0 = 0x00000002,
113 regk_strmux_ser1 = 0x00000002,
114 regk_strmux_ser2 = 0x00000002,
115 regk_strmux_ser3 = 0x00000002,
116 regk_strmux_ser4 = 0x00000002,
117 regk_strmux_sser = 0x00000001,
118 regk_strmux_strcop = 0x00000001
119};
120#endif /* __strmux_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/timer_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/timer_defs.h
new file mode 100644
index 000000000000..2c33e097d60a
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/hwregs/timer_defs.h
@@ -0,0 +1,265 @@
1#ifndef __timer_defs_h
2#define __timer_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: timer.r
7 *
8 * by ../../../tools/rdesc/bin/rdes2c -outfile timer_defs.h timer.r
9 * Any changes here will be lost.
10 *
11 * -*- buffer-read-only: t -*-
12 */
13/* Main access macros */
14#ifndef REG_RD
15#define REG_RD( scope, inst, reg ) \
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
18#endif
19
20#ifndef REG_WR
21#define REG_WR( scope, inst, reg, val ) \
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
24#endif
25
26#ifndef REG_RD_VECT
27#define REG_RD_VECT( scope, inst, reg, index ) \
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
31#endif
32
33#ifndef REG_WR_VECT
34#define REG_WR_VECT( scope, inst, reg, index, val ) \
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
38#endif
39
40#ifndef REG_RD_INT
41#define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
43#endif
44
45#ifndef REG_WR_INT
46#define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
48#endif
49
50#ifndef REG_RD_INT_VECT
51#define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
53 (index) * STRIDE_##scope##_##reg )
54#endif
55
56#ifndef REG_WR_INT_VECT
57#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
59 (index) * STRIDE_##scope##_##reg, (val) )
60#endif
61
62#ifndef REG_TYPE_CONV
63#define REG_TYPE_CONV( type, orgtype, val ) \
64 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
65#endif
66
67#ifndef reg_page_size
68#define reg_page_size 8192
69#endif
70
71#ifndef REG_ADDR
72#define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
74#endif
75
76#ifndef REG_ADDR_VECT
77#define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
79 (index) * STRIDE_##scope##_##reg )
80#endif
81
82/* C-code for register scope timer */
83
84/* Register rw_tmr0_div, scope timer, type rw */
85typedef unsigned int reg_timer_rw_tmr0_div;
86#define REG_RD_ADDR_timer_rw_tmr0_div 0
87#define REG_WR_ADDR_timer_rw_tmr0_div 0
88
89/* Register r_tmr0_data, scope timer, type r */
90typedef unsigned int reg_timer_r_tmr0_data;
91#define REG_RD_ADDR_timer_r_tmr0_data 4
92
93/* Register rw_tmr0_ctrl, scope timer, type rw */
94typedef struct {
95 unsigned int op : 2;
96 unsigned int freq : 3;
97 unsigned int dummy1 : 27;
98} reg_timer_rw_tmr0_ctrl;
99#define REG_RD_ADDR_timer_rw_tmr0_ctrl 8
100#define REG_WR_ADDR_timer_rw_tmr0_ctrl 8
101
102/* Register rw_tmr1_div, scope timer, type rw */
103typedef unsigned int reg_timer_rw_tmr1_div;
104#define REG_RD_ADDR_timer_rw_tmr1_div 16
105#define REG_WR_ADDR_timer_rw_tmr1_div 16
106
107/* Register r_tmr1_data, scope timer, type r */
108typedef unsigned int reg_timer_r_tmr1_data;
109#define REG_RD_ADDR_timer_r_tmr1_data 20
110
111/* Register rw_tmr1_ctrl, scope timer, type rw */
112typedef struct {
113 unsigned int op : 2;
114 unsigned int freq : 3;
115 unsigned int dummy1 : 27;
116} reg_timer_rw_tmr1_ctrl;
117#define REG_RD_ADDR_timer_rw_tmr1_ctrl 24
118#define REG_WR_ADDR_timer_rw_tmr1_ctrl 24
119
120/* Register rs_cnt_data, scope timer, type rs */
121typedef struct {
122 unsigned int tmr : 24;
123 unsigned int cnt : 8;
124} reg_timer_rs_cnt_data;
125#define REG_RD_ADDR_timer_rs_cnt_data 32
126
127/* Register r_cnt_data, scope timer, type r */
128typedef struct {
129 unsigned int tmr : 24;
130 unsigned int cnt : 8;
131} reg_timer_r_cnt_data;
132#define REG_RD_ADDR_timer_r_cnt_data 36
133
134/* Register rw_cnt_cfg, scope timer, type rw */
135typedef struct {
136 unsigned int clk : 2;
137 unsigned int dummy1 : 30;
138} reg_timer_rw_cnt_cfg;
139#define REG_RD_ADDR_timer_rw_cnt_cfg 40
140#define REG_WR_ADDR_timer_rw_cnt_cfg 40
141
142/* Register rw_trig, scope timer, type rw */
143typedef unsigned int reg_timer_rw_trig;
144#define REG_RD_ADDR_timer_rw_trig 48
145#define REG_WR_ADDR_timer_rw_trig 48
146
147/* Register rw_trig_cfg, scope timer, type rw */
148typedef struct {
149 unsigned int tmr : 2;
150 unsigned int dummy1 : 30;
151} reg_timer_rw_trig_cfg;
152#define REG_RD_ADDR_timer_rw_trig_cfg 52
153#define REG_WR_ADDR_timer_rw_trig_cfg 52
154
155/* Register r_time, scope timer, type r */
156typedef unsigned int reg_timer_r_time;
157#define REG_RD_ADDR_timer_r_time 56
158
159/* Register rw_out, scope timer, type rw */
160typedef struct {
161 unsigned int tmr : 2;
162 unsigned int dummy1 : 30;
163} reg_timer_rw_out;
164#define REG_RD_ADDR_timer_rw_out 60
165#define REG_WR_ADDR_timer_rw_out 60
166
167/* Register rw_wd_ctrl, scope timer, type rw */
168typedef struct {
169 unsigned int cnt : 8;
170 unsigned int cmd : 1;
171 unsigned int key : 7;
172 unsigned int dummy1 : 16;
173} reg_timer_rw_wd_ctrl;
174#define REG_RD_ADDR_timer_rw_wd_ctrl 64
175#define REG_WR_ADDR_timer_rw_wd_ctrl 64
176
177/* Register r_wd_stat, scope timer, type r */
178typedef struct {
179 unsigned int cnt : 8;
180 unsigned int cmd : 1;
181 unsigned int dummy1 : 23;
182} reg_timer_r_wd_stat;
183#define REG_RD_ADDR_timer_r_wd_stat 68
184
185/* Register rw_intr_mask, scope timer, type rw */
186typedef struct {
187 unsigned int tmr0 : 1;
188 unsigned int tmr1 : 1;
189 unsigned int cnt : 1;
190 unsigned int trig : 1;
191 unsigned int dummy1 : 28;
192} reg_timer_rw_intr_mask;
193#define REG_RD_ADDR_timer_rw_intr_mask 72
194#define REG_WR_ADDR_timer_rw_intr_mask 72
195
196/* Register rw_ack_intr, scope timer, type rw */
197typedef struct {
198 unsigned int tmr0 : 1;
199 unsigned int tmr1 : 1;
200 unsigned int cnt : 1;
201 unsigned int trig : 1;
202 unsigned int dummy1 : 28;
203} reg_timer_rw_ack_intr;
204#define REG_RD_ADDR_timer_rw_ack_intr 76
205#define REG_WR_ADDR_timer_rw_ack_intr 76
206
207/* Register r_intr, scope timer, type r */
208typedef struct {
209 unsigned int tmr0 : 1;
210 unsigned int tmr1 : 1;
211 unsigned int cnt : 1;
212 unsigned int trig : 1;
213 unsigned int dummy1 : 28;
214} reg_timer_r_intr;
215#define REG_RD_ADDR_timer_r_intr 80
216
217/* Register r_masked_intr, scope timer, type r */
218typedef struct {
219 unsigned int tmr0 : 1;
220 unsigned int tmr1 : 1;
221 unsigned int cnt : 1;
222 unsigned int trig : 1;
223 unsigned int dummy1 : 28;
224} reg_timer_r_masked_intr;
225#define REG_RD_ADDR_timer_r_masked_intr 84
226
227/* Register rw_test, scope timer, type rw */
228typedef struct {
229 unsigned int dis : 1;
230 unsigned int en : 1;
231 unsigned int dummy1 : 30;
232} reg_timer_rw_test;
233#define REG_RD_ADDR_timer_rw_test 88
234#define REG_WR_ADDR_timer_rw_test 88
235
236
237/* Constants */
238enum {
239 regk_timer_ext = 0x00000001,
240 regk_timer_f100 = 0x00000007,
241 regk_timer_f29_493 = 0x00000004,
242 regk_timer_f32 = 0x00000005,
243 regk_timer_f32_768 = 0x00000006,
244 regk_timer_f90 = 0x00000003,
245 regk_timer_hold = 0x00000001,
246 regk_timer_ld = 0x00000000,
247 regk_timer_no = 0x00000000,
248 regk_timer_off = 0x00000000,
249 regk_timer_run = 0x00000002,
250 regk_timer_rw_cnt_cfg_default = 0x00000000,
251 regk_timer_rw_intr_mask_default = 0x00000000,
252 regk_timer_rw_out_default = 0x00000000,
253 regk_timer_rw_test_default = 0x00000000,
254 regk_timer_rw_tmr0_ctrl_default = 0x00000000,
255 regk_timer_rw_tmr1_ctrl_default = 0x00000000,
256 regk_timer_rw_trig_cfg_default = 0x00000000,
257 regk_timer_start = 0x00000001,
258 regk_timer_stop = 0x00000000,
259 regk_timer_time = 0x00000001,
260 regk_timer_tmr0 = 0x00000002,
261 regk_timer_tmr1 = 0x00000003,
262 regk_timer_vclk = 0x00000002,
263 regk_timer_yes = 0x00000001
264};
265#endif /* __timer_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/memmap.h b/include/asm-cris/arch-v32/mach-a3/memmap.h
new file mode 100644
index 000000000000..7e15c9eb4e49
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/memmap.h
@@ -0,0 +1,10 @@
1#ifndef _ASM_ARCH_MEMMAP_H
2#define _ASM_ARCH_MEMMAP_H
3
4#define MEM_INTMEM_START (0x38000000)
5#define MEM_INTMEM_SIZE (0x00018000)
6#define MEM_DRAM_START (0x40000000)
7
8#define MEM_NON_CACHEABLE (0x80000000)
9
10#endif
diff --git a/include/asm-cris/arch-v32/mach-a3/pinmux.h b/include/asm-cris/arch-v32/mach-a3/pinmux.h
new file mode 100644
index 000000000000..db42a7254584
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/pinmux.h
@@ -0,0 +1,45 @@
1#ifndef _ASM_CRIS_ARCH_PINMUX_H
2#define _ASM_CRIS_ARCH_PINMUX_H
3
4#define PORT_A 0
5#define PORT_B 1
6#define PORT_C 2
7
8enum pin_mode {
9 pinmux_none = 0,
10 pinmux_fixed,
11 pinmux_gpio,
12 pinmux_iop
13};
14
15enum fixed_function {
16 pinmux_eth,
17 pinmux_geth,
18 pinmux_tg_ccd,
19 pinmux_tg_cmos,
20 pinmux_vout,
21 pinmux_ser1,
22 pinmux_ser2,
23 pinmux_ser3,
24 pinmux_ser4,
25 pinmux_sser,
26 pinmux_pio,
27 pinmux_pwm0,
28 pinmux_pwm1,
29 pinmux_pwm2,
30 pinmux_i2c0,
31 pinmux_i2c1,
32 pinmux_i2c1_3wire,
33 pinmux_i2c1_sda1,
34 pinmux_i2c1_sda2,
35 pinmux_i2c1_sda3,
36};
37
38int crisv32_pinmux_init(void);
39int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode);
40int crisv32_pinmux_alloc_fixed(enum fixed_function function);
41int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin);
42int crisv32_pinmux_dealloc_fixed(enum fixed_function function);
43void crisv32_pinmux_dump(void);
44
45#endif
diff --git a/include/asm-cris/arch-v32/mach-a3/startup.inc b/include/asm-cris/arch-v32/mach-a3/startup.inc
new file mode 100644
index 000000000000..2f23e5e16f4a
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-a3/startup.inc
@@ -0,0 +1,60 @@
1#include <hwregs/asm/reg_map_asm.h>
2#include <hwregs/asm/gio_defs_asm.h>
3#include <hwregs/asm/pio_defs_asm.h>
4#include <hwregs/asm/clkgen_defs_asm.h>
5#include <hwregs/asm/pinmux_defs_asm.h>
6
7 .macro GIO_INIT
8 move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0
9 move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r1
10 move.d $r0, [$r1]
11
12 move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0
13 move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r1
14 move.d $r0, [$r1]
15
16 move.d CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0
17 move.d REG_ADDR(gio, regi_gio, rw_pb_dout), $r1
18 move.d $r0, [$r1]
19
20 move.d CONFIG_ETRAX_DEF_GIO_PB_OE, $r0
21 move.d REG_ADDR(gio, regi_gio, rw_pb_oe), $r1
22 move.d $r0, [$r1]
23
24 move.d CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0
25 move.d REG_ADDR(gio, regi_gio, rw_pc_dout), $r1
26 move.d $r0, [$r1]
27
28 move.d CONFIG_ETRAX_DEF_GIO_PC_OE, $r0
29 move.d REG_ADDR(gio, regi_gio, rw_pc_oe), $r1
30 move.d $r0, [$r1]
31
32 move.d 0xFFFFFFFF, $r0
33 move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pa), $r1
34 move.d $r0, [$r1]
35 move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pb), $r1
36 move.d $r0, [$r1]
37 move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pc), $r1
38 move.d $r0, [$r1]
39 .endm
40
41 .macro START_CLOCKS
42 move.d REG_ADDR(clkgen, regi_clkgen, rw_clk_ctrl), $r1
43 move.d [$r1], $r0
44 or.d REG_STATE(clkgen, rw_clk_ctrl, cpu, yes) | \
45 REG_STATE(clkgen, rw_clk_ctrl, ddr2, yes) | \
46 REG_STATE(clkgen, rw_clk_ctrl, memarb_bar_ddr, yes), $r0
47 move.d $r0, [$r1]
48 .endm
49
50 .macro SETUP_WAIT_STATES
51 move.d REG_ADDR(pio, regi_pio, rw_ce0_cfg), $r0
52 move.d CONFIG_ETRAX_PIO_CE0_CFG, $r1
53 move.d $r1, [$r0]
54 move.d REG_ADDR(pio, regi_pio, rw_ce1_cfg), $r0
55 move.d CONFIG_ETRAX_PIO_CE1_CFG, $r1
56 move.d $r1, [$r0]
57 move.d REG_ADDR(pio, regi_pio, rw_ce2_cfg), $r0
58 move.d CONFIG_ETRAX_PIO_CE2_CFG, $r1
59 move.d $r1, [$r0]
60 .endm
diff --git a/include/asm-cris/arch-v32/mach-fs/arbiter.h b/include/asm-cris/arch-v32/mach-fs/arbiter.h
new file mode 100644
index 000000000000..a2e0ec8faa7d
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-fs/arbiter.h
@@ -0,0 +1,28 @@
1#ifndef _ASM_CRIS_ARCH_ARBITER_H
2#define _ASM_CRIS_ARCH_ARBITER_H
3
4#define EXT_REGION 0
5#define INT_REGION 1
6
7typedef void (watch_callback)(void);
8
9enum {
10 arbiter_all_dmas = 0x3ff,
11 arbiter_cpu = 0xc00,
12 arbiter_all_clients = 0x3fff
13};
14
15enum {
16 arbiter_all_read = 0x55,
17 arbiter_all_write = 0xaa,
18 arbiter_all_accesses = 0xff
19};
20
21int crisv32_arbiter_allocate_bandwidth(int client, int region,
22 unsigned long bandwidth);
23int crisv32_arbiter_watch(unsigned long start, unsigned long size,
24 unsigned long clients, unsigned long accesses,
25 watch_callback * cb);
26int crisv32_arbiter_unwatch(int id);
27
28#endif
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/bif_core_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/bif_core_defs_asm.h
new file mode 100644
index 000000000000..0a409c92837e
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/bif_core_defs_asm.h
@@ -0,0 +1,319 @@
1#ifndef __bif_core_defs_asm_h
2#define __bif_core_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/bif/rtl/bif_core_regs.r
7 * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp
8 * last modfied: Mon Apr 11 16:06:33 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r
11 * id: $Id: bif_core_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_grp1_cfg, scope bif_core, type rw */
57#define reg_bif_core_rw_grp1_cfg___lw___lsb 0
58#define reg_bif_core_rw_grp1_cfg___lw___width 6
59#define reg_bif_core_rw_grp1_cfg___ew___lsb 6
60#define reg_bif_core_rw_grp1_cfg___ew___width 3
61#define reg_bif_core_rw_grp1_cfg___zw___lsb 9
62#define reg_bif_core_rw_grp1_cfg___zw___width 3
63#define reg_bif_core_rw_grp1_cfg___aw___lsb 12
64#define reg_bif_core_rw_grp1_cfg___aw___width 2
65#define reg_bif_core_rw_grp1_cfg___dw___lsb 14
66#define reg_bif_core_rw_grp1_cfg___dw___width 2
67#define reg_bif_core_rw_grp1_cfg___ewb___lsb 16
68#define reg_bif_core_rw_grp1_cfg___ewb___width 2
69#define reg_bif_core_rw_grp1_cfg___bw___lsb 18
70#define reg_bif_core_rw_grp1_cfg___bw___width 1
71#define reg_bif_core_rw_grp1_cfg___bw___bit 18
72#define reg_bif_core_rw_grp1_cfg___wr_extend___lsb 19
73#define reg_bif_core_rw_grp1_cfg___wr_extend___width 1
74#define reg_bif_core_rw_grp1_cfg___wr_extend___bit 19
75#define reg_bif_core_rw_grp1_cfg___erc_en___lsb 20
76#define reg_bif_core_rw_grp1_cfg___erc_en___width 1
77#define reg_bif_core_rw_grp1_cfg___erc_en___bit 20
78#define reg_bif_core_rw_grp1_cfg___mode___lsb 21
79#define reg_bif_core_rw_grp1_cfg___mode___width 1
80#define reg_bif_core_rw_grp1_cfg___mode___bit 21
81#define reg_bif_core_rw_grp1_cfg_offset 0
82
83/* Register rw_grp2_cfg, scope bif_core, type rw */
84#define reg_bif_core_rw_grp2_cfg___lw___lsb 0
85#define reg_bif_core_rw_grp2_cfg___lw___width 6
86#define reg_bif_core_rw_grp2_cfg___ew___lsb 6
87#define reg_bif_core_rw_grp2_cfg___ew___width 3
88#define reg_bif_core_rw_grp2_cfg___zw___lsb 9
89#define reg_bif_core_rw_grp2_cfg___zw___width 3
90#define reg_bif_core_rw_grp2_cfg___aw___lsb 12
91#define reg_bif_core_rw_grp2_cfg___aw___width 2
92#define reg_bif_core_rw_grp2_cfg___dw___lsb 14
93#define reg_bif_core_rw_grp2_cfg___dw___width 2
94#define reg_bif_core_rw_grp2_cfg___ewb___lsb 16
95#define reg_bif_core_rw_grp2_cfg___ewb___width 2
96#define reg_bif_core_rw_grp2_cfg___bw___lsb 18
97#define reg_bif_core_rw_grp2_cfg___bw___width 1
98#define reg_bif_core_rw_grp2_cfg___bw___bit 18
99#define reg_bif_core_rw_grp2_cfg___wr_extend___lsb 19
100#define reg_bif_core_rw_grp2_cfg___wr_extend___width 1
101#define reg_bif_core_rw_grp2_cfg___wr_extend___bit 19
102#define reg_bif_core_rw_grp2_cfg___erc_en___lsb 20
103#define reg_bif_core_rw_grp2_cfg___erc_en___width 1
104#define reg_bif_core_rw_grp2_cfg___erc_en___bit 20
105#define reg_bif_core_rw_grp2_cfg___mode___lsb 21
106#define reg_bif_core_rw_grp2_cfg___mode___width 1
107#define reg_bif_core_rw_grp2_cfg___mode___bit 21
108#define reg_bif_core_rw_grp2_cfg_offset 4
109
110/* Register rw_grp3_cfg, scope bif_core, type rw */
111#define reg_bif_core_rw_grp3_cfg___lw___lsb 0
112#define reg_bif_core_rw_grp3_cfg___lw___width 6
113#define reg_bif_core_rw_grp3_cfg___ew___lsb 6
114#define reg_bif_core_rw_grp3_cfg___ew___width 3
115#define reg_bif_core_rw_grp3_cfg___zw___lsb 9
116#define reg_bif_core_rw_grp3_cfg___zw___width 3
117#define reg_bif_core_rw_grp3_cfg___aw___lsb 12
118#define reg_bif_core_rw_grp3_cfg___aw___width 2
119#define reg_bif_core_rw_grp3_cfg___dw___lsb 14
120#define reg_bif_core_rw_grp3_cfg___dw___width 2
121#define reg_bif_core_rw_grp3_cfg___ewb___lsb 16
122#define reg_bif_core_rw_grp3_cfg___ewb___width 2
123#define reg_bif_core_rw_grp3_cfg___bw___lsb 18
124#define reg_bif_core_rw_grp3_cfg___bw___width 1
125#define reg_bif_core_rw_grp3_cfg___bw___bit 18
126#define reg_bif_core_rw_grp3_cfg___wr_extend___lsb 19
127#define reg_bif_core_rw_grp3_cfg___wr_extend___width 1
128#define reg_bif_core_rw_grp3_cfg___wr_extend___bit 19
129#define reg_bif_core_rw_grp3_cfg___erc_en___lsb 20
130#define reg_bif_core_rw_grp3_cfg___erc_en___width 1
131#define reg_bif_core_rw_grp3_cfg___erc_en___bit 20
132#define reg_bif_core_rw_grp3_cfg___mode___lsb 21
133#define reg_bif_core_rw_grp3_cfg___mode___width 1
134#define reg_bif_core_rw_grp3_cfg___mode___bit 21
135#define reg_bif_core_rw_grp3_cfg___gated_csp0___lsb 24
136#define reg_bif_core_rw_grp3_cfg___gated_csp0___width 2
137#define reg_bif_core_rw_grp3_cfg___gated_csp1___lsb 26
138#define reg_bif_core_rw_grp3_cfg___gated_csp1___width 2
139#define reg_bif_core_rw_grp3_cfg___gated_csp2___lsb 28
140#define reg_bif_core_rw_grp3_cfg___gated_csp2___width 2
141#define reg_bif_core_rw_grp3_cfg___gated_csp3___lsb 30
142#define reg_bif_core_rw_grp3_cfg___gated_csp3___width 2
143#define reg_bif_core_rw_grp3_cfg_offset 8
144
145/* Register rw_grp4_cfg, scope bif_core, type rw */
146#define reg_bif_core_rw_grp4_cfg___lw___lsb 0
147#define reg_bif_core_rw_grp4_cfg___lw___width 6
148#define reg_bif_core_rw_grp4_cfg___ew___lsb 6
149#define reg_bif_core_rw_grp4_cfg___ew___width 3
150#define reg_bif_core_rw_grp4_cfg___zw___lsb 9
151#define reg_bif_core_rw_grp4_cfg___zw___width 3
152#define reg_bif_core_rw_grp4_cfg___aw___lsb 12
153#define reg_bif_core_rw_grp4_cfg___aw___width 2
154#define reg_bif_core_rw_grp4_cfg___dw___lsb 14
155#define reg_bif_core_rw_grp4_cfg___dw___width 2
156#define reg_bif_core_rw_grp4_cfg___ewb___lsb 16
157#define reg_bif_core_rw_grp4_cfg___ewb___width 2
158#define reg_bif_core_rw_grp4_cfg___bw___lsb 18
159#define reg_bif_core_rw_grp4_cfg___bw___width 1
160#define reg_bif_core_rw_grp4_cfg___bw___bit 18
161#define reg_bif_core_rw_grp4_cfg___wr_extend___lsb 19
162#define reg_bif_core_rw_grp4_cfg___wr_extend___width 1
163#define reg_bif_core_rw_grp4_cfg___wr_extend___bit 19
164#define reg_bif_core_rw_grp4_cfg___erc_en___lsb 20
165#define reg_bif_core_rw_grp4_cfg___erc_en___width 1
166#define reg_bif_core_rw_grp4_cfg___erc_en___bit 20
167#define reg_bif_core_rw_grp4_cfg___mode___lsb 21
168#define reg_bif_core_rw_grp4_cfg___mode___width 1
169#define reg_bif_core_rw_grp4_cfg___mode___bit 21
170#define reg_bif_core_rw_grp4_cfg___gated_csp4___lsb 26
171#define reg_bif_core_rw_grp4_cfg___gated_csp4___width 2
172#define reg_bif_core_rw_grp4_cfg___gated_csp5___lsb 28
173#define reg_bif_core_rw_grp4_cfg___gated_csp5___width 2
174#define reg_bif_core_rw_grp4_cfg___gated_csp6___lsb 30
175#define reg_bif_core_rw_grp4_cfg___gated_csp6___width 2
176#define reg_bif_core_rw_grp4_cfg_offset 12
177
178/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
179#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___lsb 0
180#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___width 5
181#define reg_bif_core_rw_sdram_cfg_grp0___ca___lsb 5
182#define reg_bif_core_rw_sdram_cfg_grp0___ca___width 3
183#define reg_bif_core_rw_sdram_cfg_grp0___type___lsb 8
184#define reg_bif_core_rw_sdram_cfg_grp0___type___width 1
185#define reg_bif_core_rw_sdram_cfg_grp0___type___bit 8
186#define reg_bif_core_rw_sdram_cfg_grp0___bw___lsb 9
187#define reg_bif_core_rw_sdram_cfg_grp0___bw___width 1
188#define reg_bif_core_rw_sdram_cfg_grp0___bw___bit 9
189#define reg_bif_core_rw_sdram_cfg_grp0___sh___lsb 10
190#define reg_bif_core_rw_sdram_cfg_grp0___sh___width 3
191#define reg_bif_core_rw_sdram_cfg_grp0___wmm___lsb 13
192#define reg_bif_core_rw_sdram_cfg_grp0___wmm___width 1
193#define reg_bif_core_rw_sdram_cfg_grp0___wmm___bit 13
194#define reg_bif_core_rw_sdram_cfg_grp0___sh16___lsb 14
195#define reg_bif_core_rw_sdram_cfg_grp0___sh16___width 1
196#define reg_bif_core_rw_sdram_cfg_grp0___sh16___bit 14
197#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___lsb 15
198#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___width 5
199#define reg_bif_core_rw_sdram_cfg_grp0_offset 16
200
201/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
202#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___lsb 0
203#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___width 5
204#define reg_bif_core_rw_sdram_cfg_grp1___ca___lsb 5
205#define reg_bif_core_rw_sdram_cfg_grp1___ca___width 3
206#define reg_bif_core_rw_sdram_cfg_grp1___type___lsb 8
207#define reg_bif_core_rw_sdram_cfg_grp1___type___width 1
208#define reg_bif_core_rw_sdram_cfg_grp1___type___bit 8
209#define reg_bif_core_rw_sdram_cfg_grp1___bw___lsb 9
210#define reg_bif_core_rw_sdram_cfg_grp1___bw___width 1
211#define reg_bif_core_rw_sdram_cfg_grp1___bw___bit 9
212#define reg_bif_core_rw_sdram_cfg_grp1___sh___lsb 10
213#define reg_bif_core_rw_sdram_cfg_grp1___sh___width 3
214#define reg_bif_core_rw_sdram_cfg_grp1___wmm___lsb 13
215#define reg_bif_core_rw_sdram_cfg_grp1___wmm___width 1
216#define reg_bif_core_rw_sdram_cfg_grp1___wmm___bit 13
217#define reg_bif_core_rw_sdram_cfg_grp1___sh16___lsb 14
218#define reg_bif_core_rw_sdram_cfg_grp1___sh16___width 1
219#define reg_bif_core_rw_sdram_cfg_grp1___sh16___bit 14
220#define reg_bif_core_rw_sdram_cfg_grp1_offset 20
221
222/* Register rw_sdram_timing, scope bif_core, type rw */
223#define reg_bif_core_rw_sdram_timing___cl___lsb 0
224#define reg_bif_core_rw_sdram_timing___cl___width 3
225#define reg_bif_core_rw_sdram_timing___rcd___lsb 3
226#define reg_bif_core_rw_sdram_timing___rcd___width 3
227#define reg_bif_core_rw_sdram_timing___rp___lsb 6
228#define reg_bif_core_rw_sdram_timing___rp___width 3
229#define reg_bif_core_rw_sdram_timing___rc___lsb 9
230#define reg_bif_core_rw_sdram_timing___rc___width 2
231#define reg_bif_core_rw_sdram_timing___dpl___lsb 11
232#define reg_bif_core_rw_sdram_timing___dpl___width 2
233#define reg_bif_core_rw_sdram_timing___pde___lsb 13
234#define reg_bif_core_rw_sdram_timing___pde___width 1
235#define reg_bif_core_rw_sdram_timing___pde___bit 13
236#define reg_bif_core_rw_sdram_timing___ref___lsb 14
237#define reg_bif_core_rw_sdram_timing___ref___width 2
238#define reg_bif_core_rw_sdram_timing___cpd___lsb 16
239#define reg_bif_core_rw_sdram_timing___cpd___width 1
240#define reg_bif_core_rw_sdram_timing___cpd___bit 16
241#define reg_bif_core_rw_sdram_timing___sdcke___lsb 17
242#define reg_bif_core_rw_sdram_timing___sdcke___width 1
243#define reg_bif_core_rw_sdram_timing___sdcke___bit 17
244#define reg_bif_core_rw_sdram_timing___sdclk___lsb 18
245#define reg_bif_core_rw_sdram_timing___sdclk___width 1
246#define reg_bif_core_rw_sdram_timing___sdclk___bit 18
247#define reg_bif_core_rw_sdram_timing_offset 24
248
249/* Register rw_sdram_cmd, scope bif_core, type rw */
250#define reg_bif_core_rw_sdram_cmd___cmd___lsb 0
251#define reg_bif_core_rw_sdram_cmd___cmd___width 3
252#define reg_bif_core_rw_sdram_cmd___mrs_data___lsb 3
253#define reg_bif_core_rw_sdram_cmd___mrs_data___width 15
254#define reg_bif_core_rw_sdram_cmd_offset 28
255
256/* Register rs_sdram_ref_stat, scope bif_core, type rs */
257#define reg_bif_core_rs_sdram_ref_stat___ok___lsb 0
258#define reg_bif_core_rs_sdram_ref_stat___ok___width 1
259#define reg_bif_core_rs_sdram_ref_stat___ok___bit 0
260#define reg_bif_core_rs_sdram_ref_stat_offset 32
261
262/* Register r_sdram_ref_stat, scope bif_core, type r */
263#define reg_bif_core_r_sdram_ref_stat___ok___lsb 0
264#define reg_bif_core_r_sdram_ref_stat___ok___width 1
265#define reg_bif_core_r_sdram_ref_stat___ok___bit 0
266#define reg_bif_core_r_sdram_ref_stat_offset 36
267
268
269/* Constants */
270#define regk_bif_core_bank2 0x00000000
271#define regk_bif_core_bank4 0x00000001
272#define regk_bif_core_bit10 0x0000000a
273#define regk_bif_core_bit11 0x0000000b
274#define regk_bif_core_bit12 0x0000000c
275#define regk_bif_core_bit13 0x0000000d
276#define regk_bif_core_bit14 0x0000000e
277#define regk_bif_core_bit15 0x0000000f
278#define regk_bif_core_bit16 0x00000010
279#define regk_bif_core_bit17 0x00000011
280#define regk_bif_core_bit18 0x00000012
281#define regk_bif_core_bit19 0x00000013
282#define regk_bif_core_bit20 0x00000014
283#define regk_bif_core_bit21 0x00000015
284#define regk_bif_core_bit22 0x00000016
285#define regk_bif_core_bit23 0x00000017
286#define regk_bif_core_bit24 0x00000018
287#define regk_bif_core_bit25 0x00000019
288#define regk_bif_core_bit26 0x0000001a
289#define regk_bif_core_bit27 0x0000001b
290#define regk_bif_core_bit28 0x0000001c
291#define regk_bif_core_bit29 0x0000001d
292#define regk_bif_core_bit9 0x00000009
293#define regk_bif_core_bw16 0x00000001
294#define regk_bif_core_bw32 0x00000000
295#define regk_bif_core_bwe 0x00000000
296#define regk_bif_core_cwe 0x00000001
297#define regk_bif_core_e15us 0x00000001
298#define regk_bif_core_e7800ns 0x00000002
299#define regk_bif_core_grp0 0x00000000
300#define regk_bif_core_grp1 0x00000001
301#define regk_bif_core_mrs 0x00000003
302#define regk_bif_core_no 0x00000000
303#define regk_bif_core_none 0x00000000
304#define regk_bif_core_nop 0x00000000
305#define regk_bif_core_off 0x00000000
306#define regk_bif_core_pre 0x00000002
307#define regk_bif_core_r_sdram_ref_stat_default 0x00000001
308#define regk_bif_core_rd 0x00000002
309#define regk_bif_core_ref 0x00000001
310#define regk_bif_core_rs_sdram_ref_stat_default 0x00000001
311#define regk_bif_core_rw_grp1_cfg_default 0x000006cf
312#define regk_bif_core_rw_grp2_cfg_default 0x000006cf
313#define regk_bif_core_rw_grp3_cfg_default 0x000006cf
314#define regk_bif_core_rw_grp4_cfg_default 0x000006cf
315#define regk_bif_core_rw_sdram_cfg_grp1_default 0x00000000
316#define regk_bif_core_slf 0x00000004
317#define regk_bif_core_wr 0x00000001
318#define regk_bif_core_yes 0x00000001
319#endif /* __bif_core_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/config_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/config_defs_asm.h
new file mode 100644
index 000000000000..a9908dfc2937
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/config_defs_asm.h
@@ -0,0 +1,131 @@
1#ifndef __config_defs_asm_h
2#define __config_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../rtl/config_regs.r
7 * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp
8 * last modfied: Thu Mar 4 12:34:39 2004
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/config_defs_asm.h ../../rtl/config_regs.r
11 * id: $Id: config_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register r_bootsel, scope config, type r */
57#define reg_config_r_bootsel___boot_mode___lsb 0
58#define reg_config_r_bootsel___boot_mode___width 3
59#define reg_config_r_bootsel___full_duplex___lsb 3
60#define reg_config_r_bootsel___full_duplex___width 1
61#define reg_config_r_bootsel___full_duplex___bit 3
62#define reg_config_r_bootsel___user___lsb 4
63#define reg_config_r_bootsel___user___width 1
64#define reg_config_r_bootsel___user___bit 4
65#define reg_config_r_bootsel___pll___lsb 5
66#define reg_config_r_bootsel___pll___width 1
67#define reg_config_r_bootsel___pll___bit 5
68#define reg_config_r_bootsel___flash_bw___lsb 6
69#define reg_config_r_bootsel___flash_bw___width 1
70#define reg_config_r_bootsel___flash_bw___bit 6
71#define reg_config_r_bootsel_offset 0
72
73/* Register rw_clk_ctrl, scope config, type rw */
74#define reg_config_rw_clk_ctrl___pll___lsb 0
75#define reg_config_rw_clk_ctrl___pll___width 1
76#define reg_config_rw_clk_ctrl___pll___bit 0
77#define reg_config_rw_clk_ctrl___cpu___lsb 1
78#define reg_config_rw_clk_ctrl___cpu___width 1
79#define reg_config_rw_clk_ctrl___cpu___bit 1
80#define reg_config_rw_clk_ctrl___iop___lsb 2
81#define reg_config_rw_clk_ctrl___iop___width 1
82#define reg_config_rw_clk_ctrl___iop___bit 2
83#define reg_config_rw_clk_ctrl___dma01_eth0___lsb 3
84#define reg_config_rw_clk_ctrl___dma01_eth0___width 1
85#define reg_config_rw_clk_ctrl___dma01_eth0___bit 3
86#define reg_config_rw_clk_ctrl___dma23___lsb 4
87#define reg_config_rw_clk_ctrl___dma23___width 1
88#define reg_config_rw_clk_ctrl___dma23___bit 4
89#define reg_config_rw_clk_ctrl___dma45___lsb 5
90#define reg_config_rw_clk_ctrl___dma45___width 1
91#define reg_config_rw_clk_ctrl___dma45___bit 5
92#define reg_config_rw_clk_ctrl___dma67___lsb 6
93#define reg_config_rw_clk_ctrl___dma67___width 1
94#define reg_config_rw_clk_ctrl___dma67___bit 6
95#define reg_config_rw_clk_ctrl___dma89_strcop___lsb 7
96#define reg_config_rw_clk_ctrl___dma89_strcop___width 1
97#define reg_config_rw_clk_ctrl___dma89_strcop___bit 7
98#define reg_config_rw_clk_ctrl___bif___lsb 8
99#define reg_config_rw_clk_ctrl___bif___width 1
100#define reg_config_rw_clk_ctrl___bif___bit 8
101#define reg_config_rw_clk_ctrl___fix_io___lsb 9
102#define reg_config_rw_clk_ctrl___fix_io___width 1
103#define reg_config_rw_clk_ctrl___fix_io___bit 9
104#define reg_config_rw_clk_ctrl_offset 4
105
106/* Register rw_pad_ctrl, scope config, type rw */
107#define reg_config_rw_pad_ctrl___usb_susp___lsb 0
108#define reg_config_rw_pad_ctrl___usb_susp___width 1
109#define reg_config_rw_pad_ctrl___usb_susp___bit 0
110#define reg_config_rw_pad_ctrl___phyrst_n___lsb 1
111#define reg_config_rw_pad_ctrl___phyrst_n___width 1
112#define reg_config_rw_pad_ctrl___phyrst_n___bit 1
113#define reg_config_rw_pad_ctrl_offset 8
114
115
116/* Constants */
117#define regk_config_bw16 0x00000000
118#define regk_config_bw32 0x00000001
119#define regk_config_master 0x00000005
120#define regk_config_nand 0x00000003
121#define regk_config_net_rx 0x00000001
122#define regk_config_net_tx_rx 0x00000002
123#define regk_config_no 0x00000000
124#define regk_config_none 0x00000007
125#define regk_config_nor 0x00000000
126#define regk_config_rw_clk_ctrl_default 0x00000002
127#define regk_config_rw_pad_ctrl_default 0x00000000
128#define regk_config_ser 0x00000004
129#define regk_config_slave 0x00000006
130#define regk_config_yes 0x00000001
131#endif /* __config_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/gio_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/gio_defs_asm.h
new file mode 100644
index 000000000000..be4c63936d90
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/gio_defs_asm.h
@@ -0,0 +1,276 @@
1#ifndef __gio_defs_asm_h
2#define __gio_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/gio/rtl/gio_regs.r
7 * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp
8 * last modfied: Mon Apr 11 16:07:47 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r
11 * id: $Id: gio_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_pa_dout, scope gio, type rw */
57#define reg_gio_rw_pa_dout___data___lsb 0
58#define reg_gio_rw_pa_dout___data___width 8
59#define reg_gio_rw_pa_dout_offset 0
60
61/* Register r_pa_din, scope gio, type r */
62#define reg_gio_r_pa_din___data___lsb 0
63#define reg_gio_r_pa_din___data___width 8
64#define reg_gio_r_pa_din_offset 4
65
66/* Register rw_pa_oe, scope gio, type rw */
67#define reg_gio_rw_pa_oe___oe___lsb 0
68#define reg_gio_rw_pa_oe___oe___width 8
69#define reg_gio_rw_pa_oe_offset 8
70
71/* Register rw_intr_cfg, scope gio, type rw */
72#define reg_gio_rw_intr_cfg___pa0___lsb 0
73#define reg_gio_rw_intr_cfg___pa0___width 3
74#define reg_gio_rw_intr_cfg___pa1___lsb 3
75#define reg_gio_rw_intr_cfg___pa1___width 3
76#define reg_gio_rw_intr_cfg___pa2___lsb 6
77#define reg_gio_rw_intr_cfg___pa2___width 3
78#define reg_gio_rw_intr_cfg___pa3___lsb 9
79#define reg_gio_rw_intr_cfg___pa3___width 3
80#define reg_gio_rw_intr_cfg___pa4___lsb 12
81#define reg_gio_rw_intr_cfg___pa4___width 3
82#define reg_gio_rw_intr_cfg___pa5___lsb 15
83#define reg_gio_rw_intr_cfg___pa5___width 3
84#define reg_gio_rw_intr_cfg___pa6___lsb 18
85#define reg_gio_rw_intr_cfg___pa6___width 3
86#define reg_gio_rw_intr_cfg___pa7___lsb 21
87#define reg_gio_rw_intr_cfg___pa7___width 3
88#define reg_gio_rw_intr_cfg_offset 12
89
90/* Register rw_intr_mask, scope gio, type rw */
91#define reg_gio_rw_intr_mask___pa0___lsb 0
92#define reg_gio_rw_intr_mask___pa0___width 1
93#define reg_gio_rw_intr_mask___pa0___bit 0
94#define reg_gio_rw_intr_mask___pa1___lsb 1
95#define reg_gio_rw_intr_mask___pa1___width 1
96#define reg_gio_rw_intr_mask___pa1___bit 1
97#define reg_gio_rw_intr_mask___pa2___lsb 2
98#define reg_gio_rw_intr_mask___pa2___width 1
99#define reg_gio_rw_intr_mask___pa2___bit 2
100#define reg_gio_rw_intr_mask___pa3___lsb 3
101#define reg_gio_rw_intr_mask___pa3___width 1
102#define reg_gio_rw_intr_mask___pa3___bit 3
103#define reg_gio_rw_intr_mask___pa4___lsb 4
104#define reg_gio_rw_intr_mask___pa4___width 1
105#define reg_gio_rw_intr_mask___pa4___bit 4
106#define reg_gio_rw_intr_mask___pa5___lsb 5
107#define reg_gio_rw_intr_mask___pa5___width 1
108#define reg_gio_rw_intr_mask___pa5___bit 5
109#define reg_gio_rw_intr_mask___pa6___lsb 6
110#define reg_gio_rw_intr_mask___pa6___width 1
111#define reg_gio_rw_intr_mask___pa6___bit 6
112#define reg_gio_rw_intr_mask___pa7___lsb 7
113#define reg_gio_rw_intr_mask___pa7___width 1
114#define reg_gio_rw_intr_mask___pa7___bit 7
115#define reg_gio_rw_intr_mask_offset 16
116
117/* Register rw_ack_intr, scope gio, type rw */
118#define reg_gio_rw_ack_intr___pa0___lsb 0
119#define reg_gio_rw_ack_intr___pa0___width 1
120#define reg_gio_rw_ack_intr___pa0___bit 0
121#define reg_gio_rw_ack_intr___pa1___lsb 1
122#define reg_gio_rw_ack_intr___pa1___width 1
123#define reg_gio_rw_ack_intr___pa1___bit 1
124#define reg_gio_rw_ack_intr___pa2___lsb 2
125#define reg_gio_rw_ack_intr___pa2___width 1
126#define reg_gio_rw_ack_intr___pa2___bit 2
127#define reg_gio_rw_ack_intr___pa3___lsb 3
128#define reg_gio_rw_ack_intr___pa3___width 1
129#define reg_gio_rw_ack_intr___pa3___bit 3
130#define reg_gio_rw_ack_intr___pa4___lsb 4
131#define reg_gio_rw_ack_intr___pa4___width 1
132#define reg_gio_rw_ack_intr___pa4___bit 4
133#define reg_gio_rw_ack_intr___pa5___lsb 5
134#define reg_gio_rw_ack_intr___pa5___width 1
135#define reg_gio_rw_ack_intr___pa5___bit 5
136#define reg_gio_rw_ack_intr___pa6___lsb 6
137#define reg_gio_rw_ack_intr___pa6___width 1
138#define reg_gio_rw_ack_intr___pa6___bit 6
139#define reg_gio_rw_ack_intr___pa7___lsb 7
140#define reg_gio_rw_ack_intr___pa7___width 1
141#define reg_gio_rw_ack_intr___pa7___bit 7
142#define reg_gio_rw_ack_intr_offset 20
143
144/* Register r_intr, scope gio, type r */
145#define reg_gio_r_intr___pa0___lsb 0
146#define reg_gio_r_intr___pa0___width 1
147#define reg_gio_r_intr___pa0___bit 0
148#define reg_gio_r_intr___pa1___lsb 1
149#define reg_gio_r_intr___pa1___width 1
150#define reg_gio_r_intr___pa1___bit 1
151#define reg_gio_r_intr___pa2___lsb 2
152#define reg_gio_r_intr___pa2___width 1
153#define reg_gio_r_intr___pa2___bit 2
154#define reg_gio_r_intr___pa3___lsb 3
155#define reg_gio_r_intr___pa3___width 1
156#define reg_gio_r_intr___pa3___bit 3
157#define reg_gio_r_intr___pa4___lsb 4
158#define reg_gio_r_intr___pa4___width 1
159#define reg_gio_r_intr___pa4___bit 4
160#define reg_gio_r_intr___pa5___lsb 5
161#define reg_gio_r_intr___pa5___width 1
162#define reg_gio_r_intr___pa5___bit 5
163#define reg_gio_r_intr___pa6___lsb 6
164#define reg_gio_r_intr___pa6___width 1
165#define reg_gio_r_intr___pa6___bit 6
166#define reg_gio_r_intr___pa7___lsb 7
167#define reg_gio_r_intr___pa7___width 1
168#define reg_gio_r_intr___pa7___bit 7
169#define reg_gio_r_intr_offset 24
170
171/* Register r_masked_intr, scope gio, type r */
172#define reg_gio_r_masked_intr___pa0___lsb 0
173#define reg_gio_r_masked_intr___pa0___width 1
174#define reg_gio_r_masked_intr___pa0___bit 0
175#define reg_gio_r_masked_intr___pa1___lsb 1
176#define reg_gio_r_masked_intr___pa1___width 1
177#define reg_gio_r_masked_intr___pa1___bit 1
178#define reg_gio_r_masked_intr___pa2___lsb 2
179#define reg_gio_r_masked_intr___pa2___width 1
180#define reg_gio_r_masked_intr___pa2___bit 2
181#define reg_gio_r_masked_intr___pa3___lsb 3
182#define reg_gio_r_masked_intr___pa3___width 1
183#define reg_gio_r_masked_intr___pa3___bit 3
184#define reg_gio_r_masked_intr___pa4___lsb 4
185#define reg_gio_r_masked_intr___pa4___width 1
186#define reg_gio_r_masked_intr___pa4___bit 4
187#define reg_gio_r_masked_intr___pa5___lsb 5
188#define reg_gio_r_masked_intr___pa5___width 1
189#define reg_gio_r_masked_intr___pa5___bit 5
190#define reg_gio_r_masked_intr___pa6___lsb 6
191#define reg_gio_r_masked_intr___pa6___width 1
192#define reg_gio_r_masked_intr___pa6___bit 6
193#define reg_gio_r_masked_intr___pa7___lsb 7
194#define reg_gio_r_masked_intr___pa7___width 1
195#define reg_gio_r_masked_intr___pa7___bit 7
196#define reg_gio_r_masked_intr_offset 28
197
198/* Register rw_pb_dout, scope gio, type rw */
199#define reg_gio_rw_pb_dout___data___lsb 0
200#define reg_gio_rw_pb_dout___data___width 18
201#define reg_gio_rw_pb_dout_offset 32
202
203/* Register r_pb_din, scope gio, type r */
204#define reg_gio_r_pb_din___data___lsb 0
205#define reg_gio_r_pb_din___data___width 18
206#define reg_gio_r_pb_din_offset 36
207
208/* Register rw_pb_oe, scope gio, type rw */
209#define reg_gio_rw_pb_oe___oe___lsb 0
210#define reg_gio_rw_pb_oe___oe___width 18
211#define reg_gio_rw_pb_oe_offset 40
212
213/* Register rw_pc_dout, scope gio, type rw */
214#define reg_gio_rw_pc_dout___data___lsb 0
215#define reg_gio_rw_pc_dout___data___width 18
216#define reg_gio_rw_pc_dout_offset 48
217
218/* Register r_pc_din, scope gio, type r */
219#define reg_gio_r_pc_din___data___lsb 0
220#define reg_gio_r_pc_din___data___width 18
221#define reg_gio_r_pc_din_offset 52
222
223/* Register rw_pc_oe, scope gio, type rw */
224#define reg_gio_rw_pc_oe___oe___lsb 0
225#define reg_gio_rw_pc_oe___oe___width 18
226#define reg_gio_rw_pc_oe_offset 56
227
228/* Register rw_pd_dout, scope gio, type rw */
229#define reg_gio_rw_pd_dout___data___lsb 0
230#define reg_gio_rw_pd_dout___data___width 18
231#define reg_gio_rw_pd_dout_offset 64
232
233/* Register r_pd_din, scope gio, type r */
234#define reg_gio_r_pd_din___data___lsb 0
235#define reg_gio_r_pd_din___data___width 18
236#define reg_gio_r_pd_din_offset 68
237
238/* Register rw_pd_oe, scope gio, type rw */
239#define reg_gio_rw_pd_oe___oe___lsb 0
240#define reg_gio_rw_pd_oe___oe___width 18
241#define reg_gio_rw_pd_oe_offset 72
242
243/* Register rw_pe_dout, scope gio, type rw */
244#define reg_gio_rw_pe_dout___data___lsb 0
245#define reg_gio_rw_pe_dout___data___width 18
246#define reg_gio_rw_pe_dout_offset 80
247
248/* Register r_pe_din, scope gio, type r */
249#define reg_gio_r_pe_din___data___lsb 0
250#define reg_gio_r_pe_din___data___width 18
251#define reg_gio_r_pe_din_offset 84
252
253/* Register rw_pe_oe, scope gio, type rw */
254#define reg_gio_rw_pe_oe___oe___lsb 0
255#define reg_gio_rw_pe_oe___oe___width 18
256#define reg_gio_rw_pe_oe_offset 88
257
258
259/* Constants */
260#define regk_gio_anyedge 0x00000007
261#define regk_gio_hi 0x00000001
262#define regk_gio_lo 0x00000002
263#define regk_gio_negedge 0x00000006
264#define regk_gio_no 0x00000000
265#define regk_gio_off 0x00000000
266#define regk_gio_posedge 0x00000005
267#define regk_gio_rw_intr_cfg_default 0x00000000
268#define regk_gio_rw_intr_mask_default 0x00000000
269#define regk_gio_rw_pa_oe_default 0x00000000
270#define regk_gio_rw_pb_oe_default 0x00000000
271#define regk_gio_rw_pc_oe_default 0x00000000
272#define regk_gio_rw_pd_oe_default 0x00000000
273#define regk_gio_rw_pe_oe_default 0x00000000
274#define regk_gio_set 0x00000003
275#define regk_gio_yes 0x00000001
276#endif /* __gio_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/pinmux_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/pinmux_defs_asm.h
new file mode 100644
index 000000000000..30cf5a936b64
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/pinmux_defs_asm.h
@@ -0,0 +1,632 @@
1#ifndef __pinmux_defs_asm_h
2#define __pinmux_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r
7 * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp
8 * last modfied: Mon Apr 11 16:09:11 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/pinmux_defs_asm.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r
11 * id: $Id: pinmux_defs_asm.h,v 1.1 2007/04/11 11:00:39 ricardw Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_pa, scope pinmux, type rw */
57#define reg_pinmux_rw_pa___pa0___lsb 0
58#define reg_pinmux_rw_pa___pa0___width 1
59#define reg_pinmux_rw_pa___pa0___bit 0
60#define reg_pinmux_rw_pa___pa1___lsb 1
61#define reg_pinmux_rw_pa___pa1___width 1
62#define reg_pinmux_rw_pa___pa1___bit 1
63#define reg_pinmux_rw_pa___pa2___lsb 2
64#define reg_pinmux_rw_pa___pa2___width 1
65#define reg_pinmux_rw_pa___pa2___bit 2
66#define reg_pinmux_rw_pa___pa3___lsb 3
67#define reg_pinmux_rw_pa___pa3___width 1
68#define reg_pinmux_rw_pa___pa3___bit 3
69#define reg_pinmux_rw_pa___pa4___lsb 4
70#define reg_pinmux_rw_pa___pa4___width 1
71#define reg_pinmux_rw_pa___pa4___bit 4
72#define reg_pinmux_rw_pa___pa5___lsb 5
73#define reg_pinmux_rw_pa___pa5___width 1
74#define reg_pinmux_rw_pa___pa5___bit 5
75#define reg_pinmux_rw_pa___pa6___lsb 6
76#define reg_pinmux_rw_pa___pa6___width 1
77#define reg_pinmux_rw_pa___pa6___bit 6
78#define reg_pinmux_rw_pa___pa7___lsb 7
79#define reg_pinmux_rw_pa___pa7___width 1
80#define reg_pinmux_rw_pa___pa7___bit 7
81#define reg_pinmux_rw_pa___csp2_n___lsb 8
82#define reg_pinmux_rw_pa___csp2_n___width 1
83#define reg_pinmux_rw_pa___csp2_n___bit 8
84#define reg_pinmux_rw_pa___csp3_n___lsb 9
85#define reg_pinmux_rw_pa___csp3_n___width 1
86#define reg_pinmux_rw_pa___csp3_n___bit 9
87#define reg_pinmux_rw_pa___csp5_n___lsb 10
88#define reg_pinmux_rw_pa___csp5_n___width 1
89#define reg_pinmux_rw_pa___csp5_n___bit 10
90#define reg_pinmux_rw_pa___csp6_n___lsb 11
91#define reg_pinmux_rw_pa___csp6_n___width 1
92#define reg_pinmux_rw_pa___csp6_n___bit 11
93#define reg_pinmux_rw_pa___hsh4___lsb 12
94#define reg_pinmux_rw_pa___hsh4___width 1
95#define reg_pinmux_rw_pa___hsh4___bit 12
96#define reg_pinmux_rw_pa___hsh5___lsb 13
97#define reg_pinmux_rw_pa___hsh5___width 1
98#define reg_pinmux_rw_pa___hsh5___bit 13
99#define reg_pinmux_rw_pa___hsh6___lsb 14
100#define reg_pinmux_rw_pa___hsh6___width 1
101#define reg_pinmux_rw_pa___hsh6___bit 14
102#define reg_pinmux_rw_pa___hsh7___lsb 15
103#define reg_pinmux_rw_pa___hsh7___width 1
104#define reg_pinmux_rw_pa___hsh7___bit 15
105#define reg_pinmux_rw_pa_offset 0
106
107/* Register rw_hwprot, scope pinmux, type rw */
108#define reg_pinmux_rw_hwprot___ser1___lsb 0
109#define reg_pinmux_rw_hwprot___ser1___width 1
110#define reg_pinmux_rw_hwprot___ser1___bit 0
111#define reg_pinmux_rw_hwprot___ser2___lsb 1
112#define reg_pinmux_rw_hwprot___ser2___width 1
113#define reg_pinmux_rw_hwprot___ser2___bit 1
114#define reg_pinmux_rw_hwprot___ser3___lsb 2
115#define reg_pinmux_rw_hwprot___ser3___width 1
116#define reg_pinmux_rw_hwprot___ser3___bit 2
117#define reg_pinmux_rw_hwprot___sser0___lsb 3
118#define reg_pinmux_rw_hwprot___sser0___width 1
119#define reg_pinmux_rw_hwprot___sser0___bit 3
120#define reg_pinmux_rw_hwprot___sser1___lsb 4
121#define reg_pinmux_rw_hwprot___sser1___width 1
122#define reg_pinmux_rw_hwprot___sser1___bit 4
123#define reg_pinmux_rw_hwprot___ata0___lsb 5
124#define reg_pinmux_rw_hwprot___ata0___width 1
125#define reg_pinmux_rw_hwprot___ata0___bit 5
126#define reg_pinmux_rw_hwprot___ata1___lsb 6
127#define reg_pinmux_rw_hwprot___ata1___width 1
128#define reg_pinmux_rw_hwprot___ata1___bit 6
129#define reg_pinmux_rw_hwprot___ata2___lsb 7
130#define reg_pinmux_rw_hwprot___ata2___width 1
131#define reg_pinmux_rw_hwprot___ata2___bit 7
132#define reg_pinmux_rw_hwprot___ata3___lsb 8
133#define reg_pinmux_rw_hwprot___ata3___width 1
134#define reg_pinmux_rw_hwprot___ata3___bit 8
135#define reg_pinmux_rw_hwprot___ata___lsb 9
136#define reg_pinmux_rw_hwprot___ata___width 1
137#define reg_pinmux_rw_hwprot___ata___bit 9
138#define reg_pinmux_rw_hwprot___eth1___lsb 10
139#define reg_pinmux_rw_hwprot___eth1___width 1
140#define reg_pinmux_rw_hwprot___eth1___bit 10
141#define reg_pinmux_rw_hwprot___eth1_mgm___lsb 11
142#define reg_pinmux_rw_hwprot___eth1_mgm___width 1
143#define reg_pinmux_rw_hwprot___eth1_mgm___bit 11
144#define reg_pinmux_rw_hwprot___timer___lsb 12
145#define reg_pinmux_rw_hwprot___timer___width 1
146#define reg_pinmux_rw_hwprot___timer___bit 12
147#define reg_pinmux_rw_hwprot___p21___lsb 13
148#define reg_pinmux_rw_hwprot___p21___width 1
149#define reg_pinmux_rw_hwprot___p21___bit 13
150#define reg_pinmux_rw_hwprot_offset 4
151
152/* Register rw_pb_gio, scope pinmux, type rw */
153#define reg_pinmux_rw_pb_gio___pb0___lsb 0
154#define reg_pinmux_rw_pb_gio___pb0___width 1
155#define reg_pinmux_rw_pb_gio___pb0___bit 0
156#define reg_pinmux_rw_pb_gio___pb1___lsb 1
157#define reg_pinmux_rw_pb_gio___pb1___width 1
158#define reg_pinmux_rw_pb_gio___pb1___bit 1
159#define reg_pinmux_rw_pb_gio___pb2___lsb 2
160#define reg_pinmux_rw_pb_gio___pb2___width 1
161#define reg_pinmux_rw_pb_gio___pb2___bit 2
162#define reg_pinmux_rw_pb_gio___pb3___lsb 3
163#define reg_pinmux_rw_pb_gio___pb3___width 1
164#define reg_pinmux_rw_pb_gio___pb3___bit 3
165#define reg_pinmux_rw_pb_gio___pb4___lsb 4
166#define reg_pinmux_rw_pb_gio___pb4___width 1
167#define reg_pinmux_rw_pb_gio___pb4___bit 4
168#define reg_pinmux_rw_pb_gio___pb5___lsb 5
169#define reg_pinmux_rw_pb_gio___pb5___width 1
170#define reg_pinmux_rw_pb_gio___pb5___bit 5
171#define reg_pinmux_rw_pb_gio___pb6___lsb 6
172#define reg_pinmux_rw_pb_gio___pb6___width 1
173#define reg_pinmux_rw_pb_gio___pb6___bit 6
174#define reg_pinmux_rw_pb_gio___pb7___lsb 7
175#define reg_pinmux_rw_pb_gio___pb7___width 1
176#define reg_pinmux_rw_pb_gio___pb7___bit 7
177#define reg_pinmux_rw_pb_gio___pb8___lsb 8
178#define reg_pinmux_rw_pb_gio___pb8___width 1
179#define reg_pinmux_rw_pb_gio___pb8___bit 8
180#define reg_pinmux_rw_pb_gio___pb9___lsb 9
181#define reg_pinmux_rw_pb_gio___pb9___width 1
182#define reg_pinmux_rw_pb_gio___pb9___bit 9
183#define reg_pinmux_rw_pb_gio___pb10___lsb 10
184#define reg_pinmux_rw_pb_gio___pb10___width 1
185#define reg_pinmux_rw_pb_gio___pb10___bit 10
186#define reg_pinmux_rw_pb_gio___pb11___lsb 11
187#define reg_pinmux_rw_pb_gio___pb11___width 1
188#define reg_pinmux_rw_pb_gio___pb11___bit 11
189#define reg_pinmux_rw_pb_gio___pb12___lsb 12
190#define reg_pinmux_rw_pb_gio___pb12___width 1
191#define reg_pinmux_rw_pb_gio___pb12___bit 12
192#define reg_pinmux_rw_pb_gio___pb13___lsb 13
193#define reg_pinmux_rw_pb_gio___pb13___width 1
194#define reg_pinmux_rw_pb_gio___pb13___bit 13
195#define reg_pinmux_rw_pb_gio___pb14___lsb 14
196#define reg_pinmux_rw_pb_gio___pb14___width 1
197#define reg_pinmux_rw_pb_gio___pb14___bit 14
198#define reg_pinmux_rw_pb_gio___pb15___lsb 15
199#define reg_pinmux_rw_pb_gio___pb15___width 1
200#define reg_pinmux_rw_pb_gio___pb15___bit 15
201#define reg_pinmux_rw_pb_gio___pb16___lsb 16
202#define reg_pinmux_rw_pb_gio___pb16___width 1
203#define reg_pinmux_rw_pb_gio___pb16___bit 16
204#define reg_pinmux_rw_pb_gio___pb17___lsb 17
205#define reg_pinmux_rw_pb_gio___pb17___width 1
206#define reg_pinmux_rw_pb_gio___pb17___bit 17
207#define reg_pinmux_rw_pb_gio_offset 8
208
209/* Register rw_pb_iop, scope pinmux, type rw */
210#define reg_pinmux_rw_pb_iop___pb0___lsb 0
211#define reg_pinmux_rw_pb_iop___pb0___width 1
212#define reg_pinmux_rw_pb_iop___pb0___bit 0
213#define reg_pinmux_rw_pb_iop___pb1___lsb 1
214#define reg_pinmux_rw_pb_iop___pb1___width 1
215#define reg_pinmux_rw_pb_iop___pb1___bit 1
216#define reg_pinmux_rw_pb_iop___pb2___lsb 2
217#define reg_pinmux_rw_pb_iop___pb2___width 1
218#define reg_pinmux_rw_pb_iop___pb2___bit 2
219#define reg_pinmux_rw_pb_iop___pb3___lsb 3
220#define reg_pinmux_rw_pb_iop___pb3___width 1
221#define reg_pinmux_rw_pb_iop___pb3___bit 3
222#define reg_pinmux_rw_pb_iop___pb4___lsb 4
223#define reg_pinmux_rw_pb_iop___pb4___width 1
224#define reg_pinmux_rw_pb_iop___pb4___bit 4
225#define reg_pinmux_rw_pb_iop___pb5___lsb 5
226#define reg_pinmux_rw_pb_iop___pb5___width 1
227#define reg_pinmux_rw_pb_iop___pb5___bit 5
228#define reg_pinmux_rw_pb_iop___pb6___lsb 6
229#define reg_pinmux_rw_pb_iop___pb6___width 1
230#define reg_pinmux_rw_pb_iop___pb6___bit 6
231#define reg_pinmux_rw_pb_iop___pb7___lsb 7
232#define reg_pinmux_rw_pb_iop___pb7___width 1
233#define reg_pinmux_rw_pb_iop___pb7___bit 7
234#define reg_pinmux_rw_pb_iop___pb8___lsb 8
235#define reg_pinmux_rw_pb_iop___pb8___width 1
236#define reg_pinmux_rw_pb_iop___pb8___bit 8
237#define reg_pinmux_rw_pb_iop___pb9___lsb 9
238#define reg_pinmux_rw_pb_iop___pb9___width 1
239#define reg_pinmux_rw_pb_iop___pb9___bit 9
240#define reg_pinmux_rw_pb_iop___pb10___lsb 10
241#define reg_pinmux_rw_pb_iop___pb10___width 1
242#define reg_pinmux_rw_pb_iop___pb10___bit 10
243#define reg_pinmux_rw_pb_iop___pb11___lsb 11
244#define reg_pinmux_rw_pb_iop___pb11___width 1
245#define reg_pinmux_rw_pb_iop___pb11___bit 11
246#define reg_pinmux_rw_pb_iop___pb12___lsb 12
247#define reg_pinmux_rw_pb_iop___pb12___width 1
248#define reg_pinmux_rw_pb_iop___pb12___bit 12
249#define reg_pinmux_rw_pb_iop___pb13___lsb 13
250#define reg_pinmux_rw_pb_iop___pb13___width 1
251#define reg_pinmux_rw_pb_iop___pb13___bit 13
252#define reg_pinmux_rw_pb_iop___pb14___lsb 14
253#define reg_pinmux_rw_pb_iop___pb14___width 1
254#define reg_pinmux_rw_pb_iop___pb14___bit 14
255#define reg_pinmux_rw_pb_iop___pb15___lsb 15
256#define reg_pinmux_rw_pb_iop___pb15___width 1
257#define reg_pinmux_rw_pb_iop___pb15___bit 15
258#define reg_pinmux_rw_pb_iop___pb16___lsb 16
259#define reg_pinmux_rw_pb_iop___pb16___width 1
260#define reg_pinmux_rw_pb_iop___pb16___bit 16
261#define reg_pinmux_rw_pb_iop___pb17___lsb 17
262#define reg_pinmux_rw_pb_iop___pb17___width 1
263#define reg_pinmux_rw_pb_iop___pb17___bit 17
264#define reg_pinmux_rw_pb_iop_offset 12
265
266/* Register rw_pc_gio, scope pinmux, type rw */
267#define reg_pinmux_rw_pc_gio___pc0___lsb 0
268#define reg_pinmux_rw_pc_gio___pc0___width 1
269#define reg_pinmux_rw_pc_gio___pc0___bit 0
270#define reg_pinmux_rw_pc_gio___pc1___lsb 1
271#define reg_pinmux_rw_pc_gio___pc1___width 1
272#define reg_pinmux_rw_pc_gio___pc1___bit 1
273#define reg_pinmux_rw_pc_gio___pc2___lsb 2
274#define reg_pinmux_rw_pc_gio___pc2___width 1
275#define reg_pinmux_rw_pc_gio___pc2___bit 2
276#define reg_pinmux_rw_pc_gio___pc3___lsb 3
277#define reg_pinmux_rw_pc_gio___pc3___width 1
278#define reg_pinmux_rw_pc_gio___pc3___bit 3
279#define reg_pinmux_rw_pc_gio___pc4___lsb 4
280#define reg_pinmux_rw_pc_gio___pc4___width 1
281#define reg_pinmux_rw_pc_gio___pc4___bit 4
282#define reg_pinmux_rw_pc_gio___pc5___lsb 5
283#define reg_pinmux_rw_pc_gio___pc5___width 1
284#define reg_pinmux_rw_pc_gio___pc5___bit 5
285#define reg_pinmux_rw_pc_gio___pc6___lsb 6
286#define reg_pinmux_rw_pc_gio___pc6___width 1
287#define reg_pinmux_rw_pc_gio___pc6___bit 6
288#define reg_pinmux_rw_pc_gio___pc7___lsb 7
289#define reg_pinmux_rw_pc_gio___pc7___width 1
290#define reg_pinmux_rw_pc_gio___pc7___bit 7
291#define reg_pinmux_rw_pc_gio___pc8___lsb 8
292#define reg_pinmux_rw_pc_gio___pc8___width 1
293#define reg_pinmux_rw_pc_gio___pc8___bit 8
294#define reg_pinmux_rw_pc_gio___pc9___lsb 9
295#define reg_pinmux_rw_pc_gio___pc9___width 1
296#define reg_pinmux_rw_pc_gio___pc9___bit 9
297#define reg_pinmux_rw_pc_gio___pc10___lsb 10
298#define reg_pinmux_rw_pc_gio___pc10___width 1
299#define reg_pinmux_rw_pc_gio___pc10___bit 10
300#define reg_pinmux_rw_pc_gio___pc11___lsb 11
301#define reg_pinmux_rw_pc_gio___pc11___width 1
302#define reg_pinmux_rw_pc_gio___pc11___bit 11
303#define reg_pinmux_rw_pc_gio___pc12___lsb 12
304#define reg_pinmux_rw_pc_gio___pc12___width 1
305#define reg_pinmux_rw_pc_gio___pc12___bit 12
306#define reg_pinmux_rw_pc_gio___pc13___lsb 13
307#define reg_pinmux_rw_pc_gio___pc13___width 1
308#define reg_pinmux_rw_pc_gio___pc13___bit 13
309#define reg_pinmux_rw_pc_gio___pc14___lsb 14
310#define reg_pinmux_rw_pc_gio___pc14___width 1
311#define reg_pinmux_rw_pc_gio___pc14___bit 14
312#define reg_pinmux_rw_pc_gio___pc15___lsb 15
313#define reg_pinmux_rw_pc_gio___pc15___width 1
314#define reg_pinmux_rw_pc_gio___pc15___bit 15
315#define reg_pinmux_rw_pc_gio___pc16___lsb 16
316#define reg_pinmux_rw_pc_gio___pc16___width 1
317#define reg_pinmux_rw_pc_gio___pc16___bit 16
318#define reg_pinmux_rw_pc_gio___pc17___lsb 17
319#define reg_pinmux_rw_pc_gio___pc17___width 1
320#define reg_pinmux_rw_pc_gio___pc17___bit 17
321#define reg_pinmux_rw_pc_gio_offset 16
322
323/* Register rw_pc_iop, scope pinmux, type rw */
324#define reg_pinmux_rw_pc_iop___pc0___lsb 0
325#define reg_pinmux_rw_pc_iop___pc0___width 1
326#define reg_pinmux_rw_pc_iop___pc0___bit 0
327#define reg_pinmux_rw_pc_iop___pc1___lsb 1
328#define reg_pinmux_rw_pc_iop___pc1___width 1
329#define reg_pinmux_rw_pc_iop___pc1___bit 1
330#define reg_pinmux_rw_pc_iop___pc2___lsb 2
331#define reg_pinmux_rw_pc_iop___pc2___width 1
332#define reg_pinmux_rw_pc_iop___pc2___bit 2
333#define reg_pinmux_rw_pc_iop___pc3___lsb 3
334#define reg_pinmux_rw_pc_iop___pc3___width 1
335#define reg_pinmux_rw_pc_iop___pc3___bit 3
336#define reg_pinmux_rw_pc_iop___pc4___lsb 4
337#define reg_pinmux_rw_pc_iop___pc4___width 1
338#define reg_pinmux_rw_pc_iop___pc4___bit 4
339#define reg_pinmux_rw_pc_iop___pc5___lsb 5
340#define reg_pinmux_rw_pc_iop___pc5___width 1
341#define reg_pinmux_rw_pc_iop___pc5___bit 5
342#define reg_pinmux_rw_pc_iop___pc6___lsb 6
343#define reg_pinmux_rw_pc_iop___pc6___width 1
344#define reg_pinmux_rw_pc_iop___pc6___bit 6
345#define reg_pinmux_rw_pc_iop___pc7___lsb 7
346#define reg_pinmux_rw_pc_iop___pc7___width 1
347#define reg_pinmux_rw_pc_iop___pc7___bit 7
348#define reg_pinmux_rw_pc_iop___pc8___lsb 8
349#define reg_pinmux_rw_pc_iop___pc8___width 1
350#define reg_pinmux_rw_pc_iop___pc8___bit 8
351#define reg_pinmux_rw_pc_iop___pc9___lsb 9
352#define reg_pinmux_rw_pc_iop___pc9___width 1
353#define reg_pinmux_rw_pc_iop___pc9___bit 9
354#define reg_pinmux_rw_pc_iop___pc10___lsb 10
355#define reg_pinmux_rw_pc_iop___pc10___width 1
356#define reg_pinmux_rw_pc_iop___pc10___bit 10
357#define reg_pinmux_rw_pc_iop___pc11___lsb 11
358#define reg_pinmux_rw_pc_iop___pc11___width 1
359#define reg_pinmux_rw_pc_iop___pc11___bit 11
360#define reg_pinmux_rw_pc_iop___pc12___lsb 12
361#define reg_pinmux_rw_pc_iop___pc12___width 1
362#define reg_pinmux_rw_pc_iop___pc12___bit 12
363#define reg_pinmux_rw_pc_iop___pc13___lsb 13
364#define reg_pinmux_rw_pc_iop___pc13___width 1
365#define reg_pinmux_rw_pc_iop___pc13___bit 13
366#define reg_pinmux_rw_pc_iop___pc14___lsb 14
367#define reg_pinmux_rw_pc_iop___pc14___width 1
368#define reg_pinmux_rw_pc_iop___pc14___bit 14
369#define reg_pinmux_rw_pc_iop___pc15___lsb 15
370#define reg_pinmux_rw_pc_iop___pc15___width 1
371#define reg_pinmux_rw_pc_iop___pc15___bit 15
372#define reg_pinmux_rw_pc_iop___pc16___lsb 16
373#define reg_pinmux_rw_pc_iop___pc16___width 1
374#define reg_pinmux_rw_pc_iop___pc16___bit 16
375#define reg_pinmux_rw_pc_iop___pc17___lsb 17
376#define reg_pinmux_rw_pc_iop___pc17___width 1
377#define reg_pinmux_rw_pc_iop___pc17___bit 17
378#define reg_pinmux_rw_pc_iop_offset 20
379
380/* Register rw_pd_gio, scope pinmux, type rw */
381#define reg_pinmux_rw_pd_gio___pd0___lsb 0
382#define reg_pinmux_rw_pd_gio___pd0___width 1
383#define reg_pinmux_rw_pd_gio___pd0___bit 0
384#define reg_pinmux_rw_pd_gio___pd1___lsb 1
385#define reg_pinmux_rw_pd_gio___pd1___width 1
386#define reg_pinmux_rw_pd_gio___pd1___bit 1
387#define reg_pinmux_rw_pd_gio___pd2___lsb 2
388#define reg_pinmux_rw_pd_gio___pd2___width 1
389#define reg_pinmux_rw_pd_gio___pd2___bit 2
390#define reg_pinmux_rw_pd_gio___pd3___lsb 3
391#define reg_pinmux_rw_pd_gio___pd3___width 1
392#define reg_pinmux_rw_pd_gio___pd3___bit 3
393#define reg_pinmux_rw_pd_gio___pd4___lsb 4
394#define reg_pinmux_rw_pd_gio___pd4___width 1
395#define reg_pinmux_rw_pd_gio___pd4___bit 4
396#define reg_pinmux_rw_pd_gio___pd5___lsb 5
397#define reg_pinmux_rw_pd_gio___pd5___width 1
398#define reg_pinmux_rw_pd_gio___pd5___bit 5
399#define reg_pinmux_rw_pd_gio___pd6___lsb 6
400#define reg_pinmux_rw_pd_gio___pd6___width 1
401#define reg_pinmux_rw_pd_gio___pd6___bit 6
402#define reg_pinmux_rw_pd_gio___pd7___lsb 7
403#define reg_pinmux_rw_pd_gio___pd7___width 1
404#define reg_pinmux_rw_pd_gio___pd7___bit 7
405#define reg_pinmux_rw_pd_gio___pd8___lsb 8
406#define reg_pinmux_rw_pd_gio___pd8___width 1
407#define reg_pinmux_rw_pd_gio___pd8___bit 8
408#define reg_pinmux_rw_pd_gio___pd9___lsb 9
409#define reg_pinmux_rw_pd_gio___pd9___width 1
410#define reg_pinmux_rw_pd_gio___pd9___bit 9
411#define reg_pinmux_rw_pd_gio___pd10___lsb 10
412#define reg_pinmux_rw_pd_gio___pd10___width 1
413#define reg_pinmux_rw_pd_gio___pd10___bit 10
414#define reg_pinmux_rw_pd_gio___pd11___lsb 11
415#define reg_pinmux_rw_pd_gio___pd11___width 1
416#define reg_pinmux_rw_pd_gio___pd11___bit 11
417#define reg_pinmux_rw_pd_gio___pd12___lsb 12
418#define reg_pinmux_rw_pd_gio___pd12___width 1
419#define reg_pinmux_rw_pd_gio___pd12___bit 12
420#define reg_pinmux_rw_pd_gio___pd13___lsb 13
421#define reg_pinmux_rw_pd_gio___pd13___width 1
422#define reg_pinmux_rw_pd_gio___pd13___bit 13
423#define reg_pinmux_rw_pd_gio___pd14___lsb 14
424#define reg_pinmux_rw_pd_gio___pd14___width 1
425#define reg_pinmux_rw_pd_gio___pd14___bit 14
426#define reg_pinmux_rw_pd_gio___pd15___lsb 15
427#define reg_pinmux_rw_pd_gio___pd15___width 1
428#define reg_pinmux_rw_pd_gio___pd15___bit 15
429#define reg_pinmux_rw_pd_gio___pd16___lsb 16
430#define reg_pinmux_rw_pd_gio___pd16___width 1
431#define reg_pinmux_rw_pd_gio___pd16___bit 16
432#define reg_pinmux_rw_pd_gio___pd17___lsb 17
433#define reg_pinmux_rw_pd_gio___pd17___width 1
434#define reg_pinmux_rw_pd_gio___pd17___bit 17
435#define reg_pinmux_rw_pd_gio_offset 24
436
437/* Register rw_pd_iop, scope pinmux, type rw */
438#define reg_pinmux_rw_pd_iop___pd0___lsb 0
439#define reg_pinmux_rw_pd_iop___pd0___width 1
440#define reg_pinmux_rw_pd_iop___pd0___bit 0
441#define reg_pinmux_rw_pd_iop___pd1___lsb 1
442#define reg_pinmux_rw_pd_iop___pd1___width 1
443#define reg_pinmux_rw_pd_iop___pd1___bit 1
444#define reg_pinmux_rw_pd_iop___pd2___lsb 2
445#define reg_pinmux_rw_pd_iop___pd2___width 1
446#define reg_pinmux_rw_pd_iop___pd2___bit 2
447#define reg_pinmux_rw_pd_iop___pd3___lsb 3
448#define reg_pinmux_rw_pd_iop___pd3___width 1
449#define reg_pinmux_rw_pd_iop___pd3___bit 3
450#define reg_pinmux_rw_pd_iop___pd4___lsb 4
451#define reg_pinmux_rw_pd_iop___pd4___width 1
452#define reg_pinmux_rw_pd_iop___pd4___bit 4
453#define reg_pinmux_rw_pd_iop___pd5___lsb 5
454#define reg_pinmux_rw_pd_iop___pd5___width 1
455#define reg_pinmux_rw_pd_iop___pd5___bit 5
456#define reg_pinmux_rw_pd_iop___pd6___lsb 6
457#define reg_pinmux_rw_pd_iop___pd6___width 1
458#define reg_pinmux_rw_pd_iop___pd6___bit 6
459#define reg_pinmux_rw_pd_iop___pd7___lsb 7
460#define reg_pinmux_rw_pd_iop___pd7___width 1
461#define reg_pinmux_rw_pd_iop___pd7___bit 7
462#define reg_pinmux_rw_pd_iop___pd8___lsb 8
463#define reg_pinmux_rw_pd_iop___pd8___width 1
464#define reg_pinmux_rw_pd_iop___pd8___bit 8
465#define reg_pinmux_rw_pd_iop___pd9___lsb 9
466#define reg_pinmux_rw_pd_iop___pd9___width 1
467#define reg_pinmux_rw_pd_iop___pd9___bit 9
468#define reg_pinmux_rw_pd_iop___pd10___lsb 10
469#define reg_pinmux_rw_pd_iop___pd10___width 1
470#define reg_pinmux_rw_pd_iop___pd10___bit 10
471#define reg_pinmux_rw_pd_iop___pd11___lsb 11
472#define reg_pinmux_rw_pd_iop___pd11___width 1
473#define reg_pinmux_rw_pd_iop___pd11___bit 11
474#define reg_pinmux_rw_pd_iop___pd12___lsb 12
475#define reg_pinmux_rw_pd_iop___pd12___width 1
476#define reg_pinmux_rw_pd_iop___pd12___bit 12
477#define reg_pinmux_rw_pd_iop___pd13___lsb 13
478#define reg_pinmux_rw_pd_iop___pd13___width 1
479#define reg_pinmux_rw_pd_iop___pd13___bit 13
480#define reg_pinmux_rw_pd_iop___pd14___lsb 14
481#define reg_pinmux_rw_pd_iop___pd14___width 1
482#define reg_pinmux_rw_pd_iop___pd14___bit 14
483#define reg_pinmux_rw_pd_iop___pd15___lsb 15
484#define reg_pinmux_rw_pd_iop___pd15___width 1
485#define reg_pinmux_rw_pd_iop___pd15___bit 15
486#define reg_pinmux_rw_pd_iop___pd16___lsb 16
487#define reg_pinmux_rw_pd_iop___pd16___width 1
488#define reg_pinmux_rw_pd_iop___pd16___bit 16
489#define reg_pinmux_rw_pd_iop___pd17___lsb 17
490#define reg_pinmux_rw_pd_iop___pd17___width 1
491#define reg_pinmux_rw_pd_iop___pd17___bit 17
492#define reg_pinmux_rw_pd_iop_offset 28
493
494/* Register rw_pe_gio, scope pinmux, type rw */
495#define reg_pinmux_rw_pe_gio___pe0___lsb 0
496#define reg_pinmux_rw_pe_gio___pe0___width 1
497#define reg_pinmux_rw_pe_gio___pe0___bit 0
498#define reg_pinmux_rw_pe_gio___pe1___lsb 1
499#define reg_pinmux_rw_pe_gio___pe1___width 1
500#define reg_pinmux_rw_pe_gio___pe1___bit 1
501#define reg_pinmux_rw_pe_gio___pe2___lsb 2
502#define reg_pinmux_rw_pe_gio___pe2___width 1
503#define reg_pinmux_rw_pe_gio___pe2___bit 2
504#define reg_pinmux_rw_pe_gio___pe3___lsb 3
505#define reg_pinmux_rw_pe_gio___pe3___width 1
506#define reg_pinmux_rw_pe_gio___pe3___bit 3
507#define reg_pinmux_rw_pe_gio___pe4___lsb 4
508#define reg_pinmux_rw_pe_gio___pe4___width 1
509#define reg_pinmux_rw_pe_gio___pe4___bit 4
510#define reg_pinmux_rw_pe_gio___pe5___lsb 5
511#define reg_pinmux_rw_pe_gio___pe5___width 1
512#define reg_pinmux_rw_pe_gio___pe5___bit 5
513#define reg_pinmux_rw_pe_gio___pe6___lsb 6
514#define reg_pinmux_rw_pe_gio___pe6___width 1
515#define reg_pinmux_rw_pe_gio___pe6___bit 6
516#define reg_pinmux_rw_pe_gio___pe7___lsb 7
517#define reg_pinmux_rw_pe_gio___pe7___width 1
518#define reg_pinmux_rw_pe_gio___pe7___bit 7
519#define reg_pinmux_rw_pe_gio___pe8___lsb 8
520#define reg_pinmux_rw_pe_gio___pe8___width 1
521#define reg_pinmux_rw_pe_gio___pe8___bit 8
522#define reg_pinmux_rw_pe_gio___pe9___lsb 9
523#define reg_pinmux_rw_pe_gio___pe9___width 1
524#define reg_pinmux_rw_pe_gio___pe9___bit 9
525#define reg_pinmux_rw_pe_gio___pe10___lsb 10
526#define reg_pinmux_rw_pe_gio___pe10___width 1
527#define reg_pinmux_rw_pe_gio___pe10___bit 10
528#define reg_pinmux_rw_pe_gio___pe11___lsb 11
529#define reg_pinmux_rw_pe_gio___pe11___width 1
530#define reg_pinmux_rw_pe_gio___pe11___bit 11
531#define reg_pinmux_rw_pe_gio___pe12___lsb 12
532#define reg_pinmux_rw_pe_gio___pe12___width 1
533#define reg_pinmux_rw_pe_gio___pe12___bit 12
534#define reg_pinmux_rw_pe_gio___pe13___lsb 13
535#define reg_pinmux_rw_pe_gio___pe13___width 1
536#define reg_pinmux_rw_pe_gio___pe13___bit 13
537#define reg_pinmux_rw_pe_gio___pe14___lsb 14
538#define reg_pinmux_rw_pe_gio___pe14___width 1
539#define reg_pinmux_rw_pe_gio___pe14___bit 14
540#define reg_pinmux_rw_pe_gio___pe15___lsb 15
541#define reg_pinmux_rw_pe_gio___pe15___width 1
542#define reg_pinmux_rw_pe_gio___pe15___bit 15
543#define reg_pinmux_rw_pe_gio___pe16___lsb 16
544#define reg_pinmux_rw_pe_gio___pe16___width 1
545#define reg_pinmux_rw_pe_gio___pe16___bit 16
546#define reg_pinmux_rw_pe_gio___pe17___lsb 17
547#define reg_pinmux_rw_pe_gio___pe17___width 1
548#define reg_pinmux_rw_pe_gio___pe17___bit 17
549#define reg_pinmux_rw_pe_gio_offset 32
550
551/* Register rw_pe_iop, scope pinmux, type rw */
552#define reg_pinmux_rw_pe_iop___pe0___lsb 0
553#define reg_pinmux_rw_pe_iop___pe0___width 1
554#define reg_pinmux_rw_pe_iop___pe0___bit 0
555#define reg_pinmux_rw_pe_iop___pe1___lsb 1
556#define reg_pinmux_rw_pe_iop___pe1___width 1
557#define reg_pinmux_rw_pe_iop___pe1___bit 1
558#define reg_pinmux_rw_pe_iop___pe2___lsb 2
559#define reg_pinmux_rw_pe_iop___pe2___width 1
560#define reg_pinmux_rw_pe_iop___pe2___bit 2
561#define reg_pinmux_rw_pe_iop___pe3___lsb 3
562#define reg_pinmux_rw_pe_iop___pe3___width 1
563#define reg_pinmux_rw_pe_iop___pe3___bit 3
564#define reg_pinmux_rw_pe_iop___pe4___lsb 4
565#define reg_pinmux_rw_pe_iop___pe4___width 1
566#define reg_pinmux_rw_pe_iop___pe4___bit 4
567#define reg_pinmux_rw_pe_iop___pe5___lsb 5
568#define reg_pinmux_rw_pe_iop___pe5___width 1
569#define reg_pinmux_rw_pe_iop___pe5___bit 5
570#define reg_pinmux_rw_pe_iop___pe6___lsb 6
571#define reg_pinmux_rw_pe_iop___pe6___width 1
572#define reg_pinmux_rw_pe_iop___pe6___bit 6
573#define reg_pinmux_rw_pe_iop___pe7___lsb 7
574#define reg_pinmux_rw_pe_iop___pe7___width 1
575#define reg_pinmux_rw_pe_iop___pe7___bit 7
576#define reg_pinmux_rw_pe_iop___pe8___lsb 8
577#define reg_pinmux_rw_pe_iop___pe8___width 1
578#define reg_pinmux_rw_pe_iop___pe8___bit 8
579#define reg_pinmux_rw_pe_iop___pe9___lsb 9
580#define reg_pinmux_rw_pe_iop___pe9___width 1
581#define reg_pinmux_rw_pe_iop___pe9___bit 9
582#define reg_pinmux_rw_pe_iop___pe10___lsb 10
583#define reg_pinmux_rw_pe_iop___pe10___width 1
584#define reg_pinmux_rw_pe_iop___pe10___bit 10
585#define reg_pinmux_rw_pe_iop___pe11___lsb 11
586#define reg_pinmux_rw_pe_iop___pe11___width 1
587#define reg_pinmux_rw_pe_iop___pe11___bit 11
588#define reg_pinmux_rw_pe_iop___pe12___lsb 12
589#define reg_pinmux_rw_pe_iop___pe12___width 1
590#define reg_pinmux_rw_pe_iop___pe12___bit 12
591#define reg_pinmux_rw_pe_iop___pe13___lsb 13
592#define reg_pinmux_rw_pe_iop___pe13___width 1
593#define reg_pinmux_rw_pe_iop___pe13___bit 13
594#define reg_pinmux_rw_pe_iop___pe14___lsb 14
595#define reg_pinmux_rw_pe_iop___pe14___width 1
596#define reg_pinmux_rw_pe_iop___pe14___bit 14
597#define reg_pinmux_rw_pe_iop___pe15___lsb 15
598#define reg_pinmux_rw_pe_iop___pe15___width 1
599#define reg_pinmux_rw_pe_iop___pe15___bit 15
600#define reg_pinmux_rw_pe_iop___pe16___lsb 16
601#define reg_pinmux_rw_pe_iop___pe16___width 1
602#define reg_pinmux_rw_pe_iop___pe16___bit 16
603#define reg_pinmux_rw_pe_iop___pe17___lsb 17
604#define reg_pinmux_rw_pe_iop___pe17___width 1
605#define reg_pinmux_rw_pe_iop___pe17___bit 17
606#define reg_pinmux_rw_pe_iop_offset 36
607
608/* Register rw_usb_phy, scope pinmux, type rw */
609#define reg_pinmux_rw_usb_phy___en_usb0___lsb 0
610#define reg_pinmux_rw_usb_phy___en_usb0___width 1
611#define reg_pinmux_rw_usb_phy___en_usb0___bit 0
612#define reg_pinmux_rw_usb_phy___en_usb1___lsb 1
613#define reg_pinmux_rw_usb_phy___en_usb1___width 1
614#define reg_pinmux_rw_usb_phy___en_usb1___bit 1
615#define reg_pinmux_rw_usb_phy_offset 40
616
617
618/* Constants */
619#define regk_pinmux_no 0x00000000
620#define regk_pinmux_rw_hwprot_default 0x00000000
621#define regk_pinmux_rw_pa_default 0x00000000
622#define regk_pinmux_rw_pb_gio_default 0x00000000
623#define regk_pinmux_rw_pb_iop_default 0x00000000
624#define regk_pinmux_rw_pc_gio_default 0x00000000
625#define regk_pinmux_rw_pc_iop_default 0x00000000
626#define regk_pinmux_rw_pd_gio_default 0x00000000
627#define regk_pinmux_rw_pd_iop_default 0x00000000
628#define regk_pinmux_rw_pe_gio_default 0x00000000
629#define regk_pinmux_rw_pe_iop_default 0x00000000
630#define regk_pinmux_rw_usb_phy_default 0x00000000
631#define regk_pinmux_yes 0x00000001
632#endif /* __pinmux_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/reg_map_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/reg_map_asm.h
new file mode 100644
index 000000000000..87517aebd2cb
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/reg_map_asm.h
@@ -0,0 +1,96 @@
1#ifndef __reg_map_h
2#define __reg_map_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../mod/fakereg.rmap
7 * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp
8 * last modified: Wed Feb 11 20:53:25 2004
9 * file: ../../rtl/global.rmap
10 * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp
11 * last modified: Mon Aug 18 17:08:23 2003
12 * file: ../../mod/modreg.rmap
13 * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp
14 * last modified: Fri Feb 20 16:40:04 2004
15 *
16 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/reg_map_asm.h -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap
17 * id: $Id: reg_map_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
18 * Any changes here will be lost.
19 *
20 * -*- buffer-read-only: t -*-
21 */
22#define regi_artpec_mod 0xb7044000
23#define regi_ata 0xb0032000
24#define regi_ata_mod 0xb7006000
25#define regi_barber 0xb701a000
26#define regi_bif_core 0xb0014000
27#define regi_bif_dma 0xb0016000
28#define regi_bif_slave 0xb0018000
29#define regi_bif_slave_ext 0xac000000
30#define regi_bus_master 0xb703c000
31#define regi_config 0xb003c000
32#define regi_dma0 0xb0000000
33#define regi_dma1 0xb0002000
34#define regi_dma2 0xb0004000
35#define regi_dma3 0xb0006000
36#define regi_dma4 0xb0008000
37#define regi_dma5 0xb000a000
38#define regi_dma6 0xb000c000
39#define regi_dma7 0xb000e000
40#define regi_dma8 0xb0010000
41#define regi_dma9 0xb0012000
42#define regi_eth0 0xb0034000
43#define regi_eth1 0xb0036000
44#define regi_eth_mod 0xb7004000
45#define regi_eth_mod1 0xb701c000
46#define regi_eth_strmod 0xb7008000
47#define regi_eth_strmod1 0xb7032000
48#define regi_ext_dma 0xb703a000
49#define regi_ext_mem 0xb7046000
50#define regi_gen_io 0xb7016000
51#define regi_gio 0xb001a000
52#define regi_hook 0xb7000000
53#define regi_iop 0xb0020000
54#define regi_irq 0xb001c000
55#define regi_irq_nmi 0xb701e000
56#define regi_marb 0xb003e000
57#define regi_marb_bp0 0xb003e240
58#define regi_marb_bp1 0xb003e280
59#define regi_marb_bp2 0xb003e2c0
60#define regi_marb_bp3 0xb003e300
61#define regi_nand_mod 0xb7014000
62#define regi_p21 0xb002e000
63#define regi_p21_mod 0xb7042000
64#define regi_pci_mod 0xb7010000
65#define regi_pin_test 0xb7018000
66#define regi_pinmux 0xb0038000
67#define regi_sdram_chk 0xb703e000
68#define regi_sdram_mod 0xb7012000
69#define regi_ser0 0xb0026000
70#define regi_ser1 0xb0028000
71#define regi_ser2 0xb002a000
72#define regi_ser3 0xb002c000
73#define regi_ser_mod0 0xb7020000
74#define regi_ser_mod1 0xb7022000
75#define regi_ser_mod2 0xb7024000
76#define regi_ser_mod3 0xb7026000
77#define regi_smif_stat 0xb700e000
78#define regi_sser0 0xb0022000
79#define regi_sser1 0xb0024000
80#define regi_sser_mod0 0xb700a000
81#define regi_sser_mod1 0xb700c000
82#define regi_strcop 0xb0030000
83#define regi_strmux 0xb003a000
84#define regi_strmux_tst 0xb7040000
85#define regi_tap 0xb7002000
86#define regi_timer 0xb001e000
87#define regi_timer_mod 0xb7034000
88#define regi_trace 0xb0040000
89#define regi_usb0 0xb7028000
90#define regi_usb1 0xb702a000
91#define regi_usb2 0xb702c000
92#define regi_usb3 0xb702e000
93#define regi_usb_dev 0xb7030000
94#define regi_utmi_mod0 0xb7036000
95#define regi_utmi_mod1 0xb7038000
96#endif /* __reg_map_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/timer_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/timer_defs_asm.h
new file mode 100644
index 000000000000..e1197194d5c1
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/timer_defs_asm.h
@@ -0,0 +1,229 @@
1#ifndef __timer_defs_asm_h
2#define __timer_defs_asm_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/timer/rtl/timer_regs.r
7 * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp
8 * last modfied: Mon Apr 11 16:09:53 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r
11 * id: $Id: timer_defs_asm.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16
17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56/* Register rw_tmr0_div, scope timer, type rw */
57#define reg_timer_rw_tmr0_div_offset 0
58
59/* Register r_tmr0_data, scope timer, type r */
60#define reg_timer_r_tmr0_data_offset 4
61
62/* Register rw_tmr0_ctrl, scope timer, type rw */
63#define reg_timer_rw_tmr0_ctrl___op___lsb 0
64#define reg_timer_rw_tmr0_ctrl___op___width 2
65#define reg_timer_rw_tmr0_ctrl___freq___lsb 2
66#define reg_timer_rw_tmr0_ctrl___freq___width 3
67#define reg_timer_rw_tmr0_ctrl_offset 8
68
69/* Register rw_tmr1_div, scope timer, type rw */
70#define reg_timer_rw_tmr1_div_offset 16
71
72/* Register r_tmr1_data, scope timer, type r */
73#define reg_timer_r_tmr1_data_offset 20
74
75/* Register rw_tmr1_ctrl, scope timer, type rw */
76#define reg_timer_rw_tmr1_ctrl___op___lsb 0
77#define reg_timer_rw_tmr1_ctrl___op___width 2
78#define reg_timer_rw_tmr1_ctrl___freq___lsb 2
79#define reg_timer_rw_tmr1_ctrl___freq___width 3
80#define reg_timer_rw_tmr1_ctrl_offset 24
81
82/* Register rs_cnt_data, scope timer, type rs */
83#define reg_timer_rs_cnt_data___tmr___lsb 0
84#define reg_timer_rs_cnt_data___tmr___width 24
85#define reg_timer_rs_cnt_data___cnt___lsb 24
86#define reg_timer_rs_cnt_data___cnt___width 8
87#define reg_timer_rs_cnt_data_offset 32
88
89/* Register r_cnt_data, scope timer, type r */
90#define reg_timer_r_cnt_data___tmr___lsb 0
91#define reg_timer_r_cnt_data___tmr___width 24
92#define reg_timer_r_cnt_data___cnt___lsb 24
93#define reg_timer_r_cnt_data___cnt___width 8
94#define reg_timer_r_cnt_data_offset 36
95
96/* Register rw_cnt_cfg, scope timer, type rw */
97#define reg_timer_rw_cnt_cfg___clk___lsb 0
98#define reg_timer_rw_cnt_cfg___clk___width 2
99#define reg_timer_rw_cnt_cfg_offset 40
100
101/* Register rw_trig, scope timer, type rw */
102#define reg_timer_rw_trig_offset 48
103
104/* Register rw_trig_cfg, scope timer, type rw */
105#define reg_timer_rw_trig_cfg___tmr___lsb 0
106#define reg_timer_rw_trig_cfg___tmr___width 2
107#define reg_timer_rw_trig_cfg_offset 52
108
109/* Register r_time, scope timer, type r */
110#define reg_timer_r_time_offset 56
111
112/* Register rw_out, scope timer, type rw */
113#define reg_timer_rw_out___tmr___lsb 0
114#define reg_timer_rw_out___tmr___width 2
115#define reg_timer_rw_out_offset 60
116
117/* Register rw_wd_ctrl, scope timer, type rw */
118#define reg_timer_rw_wd_ctrl___cnt___lsb 0
119#define reg_timer_rw_wd_ctrl___cnt___width 8
120#define reg_timer_rw_wd_ctrl___cmd___lsb 8
121#define reg_timer_rw_wd_ctrl___cmd___width 1
122#define reg_timer_rw_wd_ctrl___cmd___bit 8
123#define reg_timer_rw_wd_ctrl___key___lsb 9
124#define reg_timer_rw_wd_ctrl___key___width 7
125#define reg_timer_rw_wd_ctrl_offset 64
126
127/* Register r_wd_stat, scope timer, type r */
128#define reg_timer_r_wd_stat___cnt___lsb 0
129#define reg_timer_r_wd_stat___cnt___width 8
130#define reg_timer_r_wd_stat___cmd___lsb 8
131#define reg_timer_r_wd_stat___cmd___width 1
132#define reg_timer_r_wd_stat___cmd___bit 8
133#define reg_timer_r_wd_stat_offset 68
134
135/* Register rw_intr_mask, scope timer, type rw */
136#define reg_timer_rw_intr_mask___tmr0___lsb 0
137#define reg_timer_rw_intr_mask___tmr0___width 1
138#define reg_timer_rw_intr_mask___tmr0___bit 0
139#define reg_timer_rw_intr_mask___tmr1___lsb 1
140#define reg_timer_rw_intr_mask___tmr1___width 1
141#define reg_timer_rw_intr_mask___tmr1___bit 1
142#define reg_timer_rw_intr_mask___cnt___lsb 2
143#define reg_timer_rw_intr_mask___cnt___width 1
144#define reg_timer_rw_intr_mask___cnt___bit 2
145#define reg_timer_rw_intr_mask___trig___lsb 3
146#define reg_timer_rw_intr_mask___trig___width 1
147#define reg_timer_rw_intr_mask___trig___bit 3
148#define reg_timer_rw_intr_mask_offset 72
149
150/* Register rw_ack_intr, scope timer, type rw */
151#define reg_timer_rw_ack_intr___tmr0___lsb 0
152#define reg_timer_rw_ack_intr___tmr0___width 1
153#define reg_timer_rw_ack_intr___tmr0___bit 0
154#define reg_timer_rw_ack_intr___tmr1___lsb 1
155#define reg_timer_rw_ack_intr___tmr1___width 1
156#define reg_timer_rw_ack_intr___tmr1___bit 1
157#define reg_timer_rw_ack_intr___cnt___lsb 2
158#define reg_timer_rw_ack_intr___cnt___width 1
159#define reg_timer_rw_ack_intr___cnt___bit 2
160#define reg_timer_rw_ack_intr___trig___lsb 3
161#define reg_timer_rw_ack_intr___trig___width 1
162#define reg_timer_rw_ack_intr___trig___bit 3
163#define reg_timer_rw_ack_intr_offset 76
164
165/* Register r_intr, scope timer, type r */
166#define reg_timer_r_intr___tmr0___lsb 0
167#define reg_timer_r_intr___tmr0___width 1
168#define reg_timer_r_intr___tmr0___bit 0
169#define reg_timer_r_intr___tmr1___lsb 1
170#define reg_timer_r_intr___tmr1___width 1
171#define reg_timer_r_intr___tmr1___bit 1
172#define reg_timer_r_intr___cnt___lsb 2
173#define reg_timer_r_intr___cnt___width 1
174#define reg_timer_r_intr___cnt___bit 2
175#define reg_timer_r_intr___trig___lsb 3
176#define reg_timer_r_intr___trig___width 1
177#define reg_timer_r_intr___trig___bit 3
178#define reg_timer_r_intr_offset 80
179
180/* Register r_masked_intr, scope timer, type r */
181#define reg_timer_r_masked_intr___tmr0___lsb 0
182#define reg_timer_r_masked_intr___tmr0___width 1
183#define reg_timer_r_masked_intr___tmr0___bit 0
184#define reg_timer_r_masked_intr___tmr1___lsb 1
185#define reg_timer_r_masked_intr___tmr1___width 1
186#define reg_timer_r_masked_intr___tmr1___bit 1
187#define reg_timer_r_masked_intr___cnt___lsb 2
188#define reg_timer_r_masked_intr___cnt___width 1
189#define reg_timer_r_masked_intr___cnt___bit 2
190#define reg_timer_r_masked_intr___trig___lsb 3
191#define reg_timer_r_masked_intr___trig___width 1
192#define reg_timer_r_masked_intr___trig___bit 3
193#define reg_timer_r_masked_intr_offset 84
194
195/* Register rw_test, scope timer, type rw */
196#define reg_timer_rw_test___dis___lsb 0
197#define reg_timer_rw_test___dis___width 1
198#define reg_timer_rw_test___dis___bit 0
199#define reg_timer_rw_test___en___lsb 1
200#define reg_timer_rw_test___en___width 1
201#define reg_timer_rw_test___en___bit 1
202#define reg_timer_rw_test_offset 88
203
204
205/* Constants */
206#define regk_timer_ext 0x00000001
207#define regk_timer_f100 0x00000007
208#define regk_timer_f29_493 0x00000004
209#define regk_timer_f32 0x00000005
210#define regk_timer_f32_768 0x00000006
211#define regk_timer_hold 0x00000001
212#define regk_timer_ld 0x00000000
213#define regk_timer_no 0x00000000
214#define regk_timer_off 0x00000000
215#define regk_timer_run 0x00000002
216#define regk_timer_rw_cnt_cfg_default 0x00000000
217#define regk_timer_rw_intr_mask_default 0x00000000
218#define regk_timer_rw_out_default 0x00000000
219#define regk_timer_rw_test_default 0x00000000
220#define regk_timer_rw_tmr0_ctrl_default 0x00000000
221#define regk_timer_rw_tmr1_ctrl_default 0x00000000
222#define regk_timer_rw_trig_cfg_default 0x00000000
223#define regk_timer_start 0x00000001
224#define regk_timer_stop 0x00000000
225#define regk_timer_time 0x00000001
226#define regk_timer_tmr0 0x00000002
227#define regk_timer_tmr1 0x00000003
228#define regk_timer_yes 0x00000001
229#endif /* __timer_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_core_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/bif_core_defs.h
new file mode 100644
index 000000000000..44362a62b47c
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-fs/hwregs/bif_core_defs.h
@@ -0,0 +1,284 @@
1#ifndef __bif_core_defs_h
2#define __bif_core_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/bif/rtl/bif_core_regs.r
7 * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp
8 * last modfied: Mon Apr 11 16:06:33 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r
11 * id: $Id: bif_core_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope bif_core */
86
87/* Register rw_grp1_cfg, scope bif_core, type rw */
88typedef struct {
89 unsigned int lw : 6;
90 unsigned int ew : 3;
91 unsigned int zw : 3;
92 unsigned int aw : 2;
93 unsigned int dw : 2;
94 unsigned int ewb : 2;
95 unsigned int bw : 1;
96 unsigned int wr_extend : 1;
97 unsigned int erc_en : 1;
98 unsigned int mode : 1;
99 unsigned int dummy1 : 10;
100} reg_bif_core_rw_grp1_cfg;
101#define REG_RD_ADDR_bif_core_rw_grp1_cfg 0
102#define REG_WR_ADDR_bif_core_rw_grp1_cfg 0
103
104/* Register rw_grp2_cfg, scope bif_core, type rw */
105typedef struct {
106 unsigned int lw : 6;
107 unsigned int ew : 3;
108 unsigned int zw : 3;
109 unsigned int aw : 2;
110 unsigned int dw : 2;
111 unsigned int ewb : 2;
112 unsigned int bw : 1;
113 unsigned int wr_extend : 1;
114 unsigned int erc_en : 1;
115 unsigned int mode : 1;
116 unsigned int dummy1 : 10;
117} reg_bif_core_rw_grp2_cfg;
118#define REG_RD_ADDR_bif_core_rw_grp2_cfg 4
119#define REG_WR_ADDR_bif_core_rw_grp2_cfg 4
120
121/* Register rw_grp3_cfg, scope bif_core, type rw */
122typedef struct {
123 unsigned int lw : 6;
124 unsigned int ew : 3;
125 unsigned int zw : 3;
126 unsigned int aw : 2;
127 unsigned int dw : 2;
128 unsigned int ewb : 2;
129 unsigned int bw : 1;
130 unsigned int wr_extend : 1;
131 unsigned int erc_en : 1;
132 unsigned int mode : 1;
133 unsigned int dummy1 : 2;
134 unsigned int gated_csp0 : 2;
135 unsigned int gated_csp1 : 2;
136 unsigned int gated_csp2 : 2;
137 unsigned int gated_csp3 : 2;
138} reg_bif_core_rw_grp3_cfg;
139#define REG_RD_ADDR_bif_core_rw_grp3_cfg 8
140#define REG_WR_ADDR_bif_core_rw_grp3_cfg 8
141
142/* Register rw_grp4_cfg, scope bif_core, type rw */
143typedef struct {
144 unsigned int lw : 6;
145 unsigned int ew : 3;
146 unsigned int zw : 3;
147 unsigned int aw : 2;
148 unsigned int dw : 2;
149 unsigned int ewb : 2;
150 unsigned int bw : 1;
151 unsigned int wr_extend : 1;
152 unsigned int erc_en : 1;
153 unsigned int mode : 1;
154 unsigned int dummy1 : 4;
155 unsigned int gated_csp4 : 2;
156 unsigned int gated_csp5 : 2;
157 unsigned int gated_csp6 : 2;
158} reg_bif_core_rw_grp4_cfg;
159#define REG_RD_ADDR_bif_core_rw_grp4_cfg 12
160#define REG_WR_ADDR_bif_core_rw_grp4_cfg 12
161
162/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
163typedef struct {
164 unsigned int bank_sel : 5;
165 unsigned int ca : 3;
166 unsigned int type : 1;
167 unsigned int bw : 1;
168 unsigned int sh : 3;
169 unsigned int wmm : 1;
170 unsigned int sh16 : 1;
171 unsigned int grp_sel : 5;
172 unsigned int dummy1 : 12;
173} reg_bif_core_rw_sdram_cfg_grp0;
174#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16
175#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16
176
177/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
178typedef struct {
179 unsigned int bank_sel : 5;
180 unsigned int ca : 3;
181 unsigned int type : 1;
182 unsigned int bw : 1;
183 unsigned int sh : 3;
184 unsigned int wmm : 1;
185 unsigned int sh16 : 1;
186 unsigned int dummy1 : 17;
187} reg_bif_core_rw_sdram_cfg_grp1;
188#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20
189#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20
190
191/* Register rw_sdram_timing, scope bif_core, type rw */
192typedef struct {
193 unsigned int cl : 3;
194 unsigned int rcd : 3;
195 unsigned int rp : 3;
196 unsigned int rc : 2;
197 unsigned int dpl : 2;
198 unsigned int pde : 1;
199 unsigned int ref : 2;
200 unsigned int cpd : 1;
201 unsigned int sdcke : 1;
202 unsigned int sdclk : 1;
203 unsigned int dummy1 : 13;
204} reg_bif_core_rw_sdram_timing;
205#define REG_RD_ADDR_bif_core_rw_sdram_timing 24
206#define REG_WR_ADDR_bif_core_rw_sdram_timing 24
207
208/* Register rw_sdram_cmd, scope bif_core, type rw */
209typedef struct {
210 unsigned int cmd : 3;
211 unsigned int mrs_data : 15;
212 unsigned int dummy1 : 14;
213} reg_bif_core_rw_sdram_cmd;
214#define REG_RD_ADDR_bif_core_rw_sdram_cmd 28
215#define REG_WR_ADDR_bif_core_rw_sdram_cmd 28
216
217/* Register rs_sdram_ref_stat, scope bif_core, type rs */
218typedef struct {
219 unsigned int ok : 1;
220 unsigned int dummy1 : 31;
221} reg_bif_core_rs_sdram_ref_stat;
222#define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32
223
224/* Register r_sdram_ref_stat, scope bif_core, type r */
225typedef struct {
226 unsigned int ok : 1;
227 unsigned int dummy1 : 31;
228} reg_bif_core_r_sdram_ref_stat;
229#define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36
230
231
232/* Constants */
233enum {
234 regk_bif_core_bank2 = 0x00000000,
235 regk_bif_core_bank4 = 0x00000001,
236 regk_bif_core_bit10 = 0x0000000a,
237 regk_bif_core_bit11 = 0x0000000b,
238 regk_bif_core_bit12 = 0x0000000c,
239 regk_bif_core_bit13 = 0x0000000d,
240 regk_bif_core_bit14 = 0x0000000e,
241 regk_bif_core_bit15 = 0x0000000f,
242 regk_bif_core_bit16 = 0x00000010,
243 regk_bif_core_bit17 = 0x00000011,
244 regk_bif_core_bit18 = 0x00000012,
245 regk_bif_core_bit19 = 0x00000013,
246 regk_bif_core_bit20 = 0x00000014,
247 regk_bif_core_bit21 = 0x00000015,
248 regk_bif_core_bit22 = 0x00000016,
249 regk_bif_core_bit23 = 0x00000017,
250 regk_bif_core_bit24 = 0x00000018,
251 regk_bif_core_bit25 = 0x00000019,
252 regk_bif_core_bit26 = 0x0000001a,
253 regk_bif_core_bit27 = 0x0000001b,
254 regk_bif_core_bit28 = 0x0000001c,
255 regk_bif_core_bit29 = 0x0000001d,
256 regk_bif_core_bit9 = 0x00000009,
257 regk_bif_core_bw16 = 0x00000001,
258 regk_bif_core_bw32 = 0x00000000,
259 regk_bif_core_bwe = 0x00000000,
260 regk_bif_core_cwe = 0x00000001,
261 regk_bif_core_e15us = 0x00000001,
262 regk_bif_core_e7800ns = 0x00000002,
263 regk_bif_core_grp0 = 0x00000000,
264 regk_bif_core_grp1 = 0x00000001,
265 regk_bif_core_mrs = 0x00000003,
266 regk_bif_core_no = 0x00000000,
267 regk_bif_core_none = 0x00000000,
268 regk_bif_core_nop = 0x00000000,
269 regk_bif_core_off = 0x00000000,
270 regk_bif_core_pre = 0x00000002,
271 regk_bif_core_r_sdram_ref_stat_default = 0x00000001,
272 regk_bif_core_rd = 0x00000002,
273 regk_bif_core_ref = 0x00000001,
274 regk_bif_core_rs_sdram_ref_stat_default = 0x00000001,
275 regk_bif_core_rw_grp1_cfg_default = 0x000006cf,
276 regk_bif_core_rw_grp2_cfg_default = 0x000006cf,
277 regk_bif_core_rw_grp3_cfg_default = 0x000006cf,
278 regk_bif_core_rw_grp4_cfg_default = 0x000006cf,
279 regk_bif_core_rw_sdram_cfg_grp1_default = 0x00000000,
280 regk_bif_core_slf = 0x00000004,
281 regk_bif_core_wr = 0x00000001,
282 regk_bif_core_yes = 0x00000001
283};
284#endif /* __bif_core_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_dma_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/bif_dma_defs.h
new file mode 100644
index 000000000000..3cb51a09dba7
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-fs/hwregs/bif_dma_defs.h
@@ -0,0 +1,473 @@
1#ifndef __bif_dma_defs_h
2#define __bif_dma_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/bif/rtl/bif_dma_regs.r
7 * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp
8 * last modfied: Mon Apr 11 16:06:33 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r
11 * id: $Id: bif_dma_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope bif_dma */
86
87/* Register rw_ch0_ctrl, scope bif_dma, type rw */
88typedef struct {
89 unsigned int bw : 2;
90 unsigned int burst_len : 1;
91 unsigned int cont : 1;
92 unsigned int end_pad : 1;
93 unsigned int cnt : 1;
94 unsigned int dreq_pin : 3;
95 unsigned int dreq_mode : 2;
96 unsigned int tc_in_pin : 3;
97 unsigned int tc_in_mode : 2;
98 unsigned int bus_mode : 2;
99 unsigned int rate_en : 1;
100 unsigned int wr_all : 1;
101 unsigned int dummy1 : 12;
102} reg_bif_dma_rw_ch0_ctrl;
103#define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0
104#define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0
105
106/* Register rw_ch0_addr, scope bif_dma, type rw */
107typedef struct {
108 unsigned int addr : 32;
109} reg_bif_dma_rw_ch0_addr;
110#define REG_RD_ADDR_bif_dma_rw_ch0_addr 4
111#define REG_WR_ADDR_bif_dma_rw_ch0_addr 4
112
113/* Register rw_ch0_start, scope bif_dma, type rw */
114typedef struct {
115 unsigned int run : 1;
116 unsigned int dummy1 : 31;
117} reg_bif_dma_rw_ch0_start;
118#define REG_RD_ADDR_bif_dma_rw_ch0_start 8
119#define REG_WR_ADDR_bif_dma_rw_ch0_start 8
120
121/* Register rw_ch0_cnt, scope bif_dma, type rw */
122typedef struct {
123 unsigned int start_cnt : 16;
124 unsigned int dummy1 : 16;
125} reg_bif_dma_rw_ch0_cnt;
126#define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12
127#define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12
128
129/* Register r_ch0_stat, scope bif_dma, type r */
130typedef struct {
131 unsigned int cnt : 16;
132 unsigned int dummy1 : 15;
133 unsigned int run : 1;
134} reg_bif_dma_r_ch0_stat;
135#define REG_RD_ADDR_bif_dma_r_ch0_stat 16
136
137/* Register rw_ch1_ctrl, scope bif_dma, type rw */
138typedef struct {
139 unsigned int bw : 2;
140 unsigned int burst_len : 1;
141 unsigned int cont : 1;
142 unsigned int end_discard : 1;
143 unsigned int cnt : 1;
144 unsigned int dreq_pin : 3;
145 unsigned int dreq_mode : 2;
146 unsigned int tc_in_pin : 3;
147 unsigned int tc_in_mode : 2;
148 unsigned int bus_mode : 2;
149 unsigned int rate_en : 1;
150 unsigned int dummy1 : 13;
151} reg_bif_dma_rw_ch1_ctrl;
152#define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32
153#define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32
154
155/* Register rw_ch1_addr, scope bif_dma, type rw */
156typedef struct {
157 unsigned int addr : 32;
158} reg_bif_dma_rw_ch1_addr;
159#define REG_RD_ADDR_bif_dma_rw_ch1_addr 36
160#define REG_WR_ADDR_bif_dma_rw_ch1_addr 36
161
162/* Register rw_ch1_start, scope bif_dma, type rw */
163typedef struct {
164 unsigned int run : 1;
165 unsigned int dummy1 : 31;
166} reg_bif_dma_rw_ch1_start;
167#define REG_RD_ADDR_bif_dma_rw_ch1_start 40
168#define REG_WR_ADDR_bif_dma_rw_ch1_start 40
169
170/* Register rw_ch1_cnt, scope bif_dma, type rw */
171typedef struct {
172 unsigned int start_cnt : 16;
173 unsigned int dummy1 : 16;
174} reg_bif_dma_rw_ch1_cnt;
175#define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44
176#define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44
177
178/* Register r_ch1_stat, scope bif_dma, type r */
179typedef struct {
180 unsigned int cnt : 16;
181 unsigned int dummy1 : 15;
182 unsigned int run : 1;
183} reg_bif_dma_r_ch1_stat;
184#define REG_RD_ADDR_bif_dma_r_ch1_stat 48
185
186/* Register rw_ch2_ctrl, scope bif_dma, type rw */
187typedef struct {
188 unsigned int bw : 2;
189 unsigned int burst_len : 1;
190 unsigned int cont : 1;
191 unsigned int end_pad : 1;
192 unsigned int cnt : 1;
193 unsigned int dreq_pin : 3;
194 unsigned int dreq_mode : 2;
195 unsigned int tc_in_pin : 3;
196 unsigned int tc_in_mode : 2;
197 unsigned int bus_mode : 2;
198 unsigned int rate_en : 1;
199 unsigned int wr_all : 1;
200 unsigned int dummy1 : 12;
201} reg_bif_dma_rw_ch2_ctrl;
202#define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64
203#define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64
204
205/* Register rw_ch2_addr, scope bif_dma, type rw */
206typedef struct {
207 unsigned int addr : 32;
208} reg_bif_dma_rw_ch2_addr;
209#define REG_RD_ADDR_bif_dma_rw_ch2_addr 68
210#define REG_WR_ADDR_bif_dma_rw_ch2_addr 68
211
212/* Register rw_ch2_start, scope bif_dma, type rw */
213typedef struct {
214 unsigned int run : 1;
215 unsigned int dummy1 : 31;
216} reg_bif_dma_rw_ch2_start;
217#define REG_RD_ADDR_bif_dma_rw_ch2_start 72
218#define REG_WR_ADDR_bif_dma_rw_ch2_start 72
219
220/* Register rw_ch2_cnt, scope bif_dma, type rw */
221typedef struct {
222 unsigned int start_cnt : 16;
223 unsigned int dummy1 : 16;
224} reg_bif_dma_rw_ch2_cnt;
225#define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76
226#define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76
227
228/* Register r_ch2_stat, scope bif_dma, type r */
229typedef struct {
230 unsigned int cnt : 16;
231 unsigned int dummy1 : 15;
232 unsigned int run : 1;
233} reg_bif_dma_r_ch2_stat;
234#define REG_RD_ADDR_bif_dma_r_ch2_stat 80
235
236/* Register rw_ch3_ctrl, scope bif_dma, type rw */
237typedef struct {
238 unsigned int bw : 2;
239 unsigned int burst_len : 1;
240 unsigned int cont : 1;
241 unsigned int end_discard : 1;
242 unsigned int cnt : 1;
243 unsigned int dreq_pin : 3;
244 unsigned int dreq_mode : 2;
245 unsigned int tc_in_pin : 3;
246 unsigned int tc_in_mode : 2;
247 unsigned int bus_mode : 2;
248 unsigned int rate_en : 1;
249 unsigned int dummy1 : 13;
250} reg_bif_dma_rw_ch3_ctrl;
251#define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96
252#define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96
253
254/* Register rw_ch3_addr, scope bif_dma, type rw */
255typedef struct {
256 unsigned int addr : 32;
257} reg_bif_dma_rw_ch3_addr;
258#define REG_RD_ADDR_bif_dma_rw_ch3_addr 100
259#define REG_WR_ADDR_bif_dma_rw_ch3_addr 100
260
261/* Register rw_ch3_start, scope bif_dma, type rw */
262typedef struct {
263 unsigned int run : 1;
264 unsigned int dummy1 : 31;
265} reg_bif_dma_rw_ch3_start;
266#define REG_RD_ADDR_bif_dma_rw_ch3_start 104
267#define REG_WR_ADDR_bif_dma_rw_ch3_start 104
268
269/* Register rw_ch3_cnt, scope bif_dma, type rw */
270typedef struct {
271 unsigned int start_cnt : 16;
272 unsigned int dummy1 : 16;
273} reg_bif_dma_rw_ch3_cnt;
274#define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108
275#define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108
276
277/* Register r_ch3_stat, scope bif_dma, type r */
278typedef struct {
279 unsigned int cnt : 16;
280 unsigned int dummy1 : 15;
281 unsigned int run : 1;
282} reg_bif_dma_r_ch3_stat;
283#define REG_RD_ADDR_bif_dma_r_ch3_stat 112
284
285/* Register rw_intr_mask, scope bif_dma, type rw */
286typedef struct {
287 unsigned int ext_dma0 : 1;
288 unsigned int ext_dma1 : 1;
289 unsigned int ext_dma2 : 1;
290 unsigned int ext_dma3 : 1;
291 unsigned int dummy1 : 28;
292} reg_bif_dma_rw_intr_mask;
293#define REG_RD_ADDR_bif_dma_rw_intr_mask 128
294#define REG_WR_ADDR_bif_dma_rw_intr_mask 128
295
296/* Register rw_ack_intr, scope bif_dma, type rw */
297typedef struct {
298 unsigned int ext_dma0 : 1;
299 unsigned int ext_dma1 : 1;
300 unsigned int ext_dma2 : 1;
301 unsigned int ext_dma3 : 1;
302 unsigned int dummy1 : 28;
303} reg_bif_dma_rw_ack_intr;
304#define REG_RD_ADDR_bif_dma_rw_ack_intr 132
305#define REG_WR_ADDR_bif_dma_rw_ack_intr 132
306
307/* Register r_intr, scope bif_dma, type r */
308typedef struct {
309 unsigned int ext_dma0 : 1;
310 unsigned int ext_dma1 : 1;
311 unsigned int ext_dma2 : 1;
312 unsigned int ext_dma3 : 1;
313 unsigned int dummy1 : 28;
314} reg_bif_dma_r_intr;
315#define REG_RD_ADDR_bif_dma_r_intr 136
316
317/* Register r_masked_intr, scope bif_dma, type r */
318typedef struct {
319 unsigned int ext_dma0 : 1;
320 unsigned int ext_dma1 : 1;
321 unsigned int ext_dma2 : 1;
322 unsigned int ext_dma3 : 1;
323 unsigned int dummy1 : 28;
324} reg_bif_dma_r_masked_intr;
325#define REG_RD_ADDR_bif_dma_r_masked_intr 140
326
327/* Register rw_pin0_cfg, scope bif_dma, type rw */
328typedef struct {
329 unsigned int master_ch : 2;
330 unsigned int master_mode : 3;
331 unsigned int slave_ch : 2;
332 unsigned int slave_mode : 3;
333 unsigned int dummy1 : 22;
334} reg_bif_dma_rw_pin0_cfg;
335#define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160
336#define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160
337
338/* Register rw_pin1_cfg, scope bif_dma, type rw */
339typedef struct {
340 unsigned int master_ch : 2;
341 unsigned int master_mode : 3;
342 unsigned int slave_ch : 2;
343 unsigned int slave_mode : 3;
344 unsigned int dummy1 : 22;
345} reg_bif_dma_rw_pin1_cfg;
346#define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164
347#define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164
348
349/* Register rw_pin2_cfg, scope bif_dma, type rw */
350typedef struct {
351 unsigned int master_ch : 2;
352 unsigned int master_mode : 3;
353 unsigned int slave_ch : 2;
354 unsigned int slave_mode : 3;
355 unsigned int dummy1 : 22;
356} reg_bif_dma_rw_pin2_cfg;
357#define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168
358#define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168
359
360/* Register rw_pin3_cfg, scope bif_dma, type rw */
361typedef struct {
362 unsigned int master_ch : 2;
363 unsigned int master_mode : 3;
364 unsigned int slave_ch : 2;
365 unsigned int slave_mode : 3;
366 unsigned int dummy1 : 22;
367} reg_bif_dma_rw_pin3_cfg;
368#define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172
369#define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172
370
371/* Register rw_pin4_cfg, scope bif_dma, type rw */
372typedef struct {
373 unsigned int master_ch : 2;
374 unsigned int master_mode : 3;
375 unsigned int slave_ch : 2;
376 unsigned int slave_mode : 3;
377 unsigned int dummy1 : 22;
378} reg_bif_dma_rw_pin4_cfg;
379#define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176
380#define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176
381
382/* Register rw_pin5_cfg, scope bif_dma, type rw */
383typedef struct {
384 unsigned int master_ch : 2;
385 unsigned int master_mode : 3;
386 unsigned int slave_ch : 2;
387 unsigned int slave_mode : 3;
388 unsigned int dummy1 : 22;
389} reg_bif_dma_rw_pin5_cfg;
390#define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180
391#define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180
392
393/* Register rw_pin6_cfg, scope bif_dma, type rw */
394typedef struct {
395 unsigned int master_ch : 2;
396 unsigned int master_mode : 3;
397 unsigned int slave_ch : 2;
398 unsigned int slave_mode : 3;
399 unsigned int dummy1 : 22;
400} reg_bif_dma_rw_pin6_cfg;
401#define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184
402#define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184
403
404/* Register rw_pin7_cfg, scope bif_dma, type rw */
405typedef struct {
406 unsigned int master_ch : 2;
407 unsigned int master_mode : 3;
408 unsigned int slave_ch : 2;
409 unsigned int slave_mode : 3;
410 unsigned int dummy1 : 22;
411} reg_bif_dma_rw_pin7_cfg;
412#define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188
413#define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188
414
415/* Register r_pin_stat, scope bif_dma, type r */
416typedef struct {
417 unsigned int pin0 : 1;
418 unsigned int pin1 : 1;
419 unsigned int pin2 : 1;
420 unsigned int pin3 : 1;
421 unsigned int pin4 : 1;
422 unsigned int pin5 : 1;
423 unsigned int pin6 : 1;
424 unsigned int pin7 : 1;
425 unsigned int dummy1 : 24;
426} reg_bif_dma_r_pin_stat;
427#define REG_RD_ADDR_bif_dma_r_pin_stat 192
428
429
430/* Constants */
431enum {
432 regk_bif_dma_as_master = 0x00000001,
433 regk_bif_dma_as_slave = 0x00000001,
434 regk_bif_dma_burst1 = 0x00000000,
435 regk_bif_dma_burst8 = 0x00000001,
436 regk_bif_dma_bw16 = 0x00000001,
437 regk_bif_dma_bw32 = 0x00000002,
438 regk_bif_dma_bw8 = 0x00000000,
439 regk_bif_dma_dack = 0x00000006,
440 regk_bif_dma_dack_inv = 0x00000007,
441 regk_bif_dma_force = 0x00000001,
442 regk_bif_dma_hi = 0x00000003,
443 regk_bif_dma_inv = 0x00000003,
444 regk_bif_dma_lo = 0x00000002,
445 regk_bif_dma_master = 0x00000001,
446 regk_bif_dma_no = 0x00000000,
447 regk_bif_dma_norm = 0x00000002,
448 regk_bif_dma_off = 0x00000000,
449 regk_bif_dma_rw_ch0_ctrl_default = 0x00000000,
450 regk_bif_dma_rw_ch0_start_default = 0x00000000,
451 regk_bif_dma_rw_ch1_ctrl_default = 0x00000000,
452 regk_bif_dma_rw_ch1_start_default = 0x00000000,
453 regk_bif_dma_rw_ch2_ctrl_default = 0x00000000,
454 regk_bif_dma_rw_ch2_start_default = 0x00000000,
455 regk_bif_dma_rw_ch3_ctrl_default = 0x00000000,
456 regk_bif_dma_rw_ch3_start_default = 0x00000000,
457 regk_bif_dma_rw_intr_mask_default = 0x00000000,
458 regk_bif_dma_rw_pin0_cfg_default = 0x00000000,
459 regk_bif_dma_rw_pin1_cfg_default = 0x00000000,
460 regk_bif_dma_rw_pin2_cfg_default = 0x00000000,
461 regk_bif_dma_rw_pin3_cfg_default = 0x00000000,
462 regk_bif_dma_rw_pin4_cfg_default = 0x00000000,
463 regk_bif_dma_rw_pin5_cfg_default = 0x00000000,
464 regk_bif_dma_rw_pin6_cfg_default = 0x00000000,
465 regk_bif_dma_rw_pin7_cfg_default = 0x00000000,
466 regk_bif_dma_slave = 0x00000002,
467 regk_bif_dma_sreq = 0x00000006,
468 regk_bif_dma_sreq_inv = 0x00000007,
469 regk_bif_dma_tc = 0x00000004,
470 regk_bif_dma_tc_inv = 0x00000005,
471 regk_bif_dma_yes = 0x00000001
472};
473#endif /* __bif_dma_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_slave_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/bif_slave_defs.h
new file mode 100644
index 000000000000..0c434585a3f9
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-fs/hwregs/bif_slave_defs.h
@@ -0,0 +1,249 @@
1#ifndef __bif_slave_defs_h
2#define __bif_slave_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/bif/rtl/bif_slave_regs.r
7 * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp
8 * last modfied: Mon Apr 11 16:06:34 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r
11 * id: $Id: bif_slave_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope bif_slave */
86
87/* Register rw_slave_cfg, scope bif_slave, type rw */
88typedef struct {
89 unsigned int slave_id : 3;
90 unsigned int use_slave_id : 1;
91 unsigned int boot_rdy : 1;
92 unsigned int loopback : 1;
93 unsigned int dis : 1;
94 unsigned int dummy1 : 25;
95} reg_bif_slave_rw_slave_cfg;
96#define REG_RD_ADDR_bif_slave_rw_slave_cfg 0
97#define REG_WR_ADDR_bif_slave_rw_slave_cfg 0
98
99/* Register r_slave_mode, scope bif_slave, type r */
100typedef struct {
101 unsigned int ch0_mode : 1;
102 unsigned int ch1_mode : 1;
103 unsigned int ch2_mode : 1;
104 unsigned int ch3_mode : 1;
105 unsigned int dummy1 : 28;
106} reg_bif_slave_r_slave_mode;
107#define REG_RD_ADDR_bif_slave_r_slave_mode 4
108
109/* Register rw_ch0_cfg, scope bif_slave, type rw */
110typedef struct {
111 unsigned int rd_hold : 2;
112 unsigned int access_mode : 1;
113 unsigned int access_ctrl : 1;
114 unsigned int data_cs : 2;
115 unsigned int dummy1 : 26;
116} reg_bif_slave_rw_ch0_cfg;
117#define REG_RD_ADDR_bif_slave_rw_ch0_cfg 16
118#define REG_WR_ADDR_bif_slave_rw_ch0_cfg 16
119
120/* Register rw_ch1_cfg, scope bif_slave, type rw */
121typedef struct {
122 unsigned int rd_hold : 2;
123 unsigned int access_mode : 1;
124 unsigned int access_ctrl : 1;
125 unsigned int data_cs : 2;
126 unsigned int dummy1 : 26;
127} reg_bif_slave_rw_ch1_cfg;
128#define REG_RD_ADDR_bif_slave_rw_ch1_cfg 20
129#define REG_WR_ADDR_bif_slave_rw_ch1_cfg 20
130
131/* Register rw_ch2_cfg, scope bif_slave, type rw */
132typedef struct {
133 unsigned int rd_hold : 2;
134 unsigned int access_mode : 1;
135 unsigned int access_ctrl : 1;
136 unsigned int data_cs : 2;
137 unsigned int dummy1 : 26;
138} reg_bif_slave_rw_ch2_cfg;
139#define REG_RD_ADDR_bif_slave_rw_ch2_cfg 24
140#define REG_WR_ADDR_bif_slave_rw_ch2_cfg 24
141
142/* Register rw_ch3_cfg, scope bif_slave, type rw */
143typedef struct {
144 unsigned int rd_hold : 2;
145 unsigned int access_mode : 1;
146 unsigned int access_ctrl : 1;
147 unsigned int data_cs : 2;
148 unsigned int dummy1 : 26;
149} reg_bif_slave_rw_ch3_cfg;
150#define REG_RD_ADDR_bif_slave_rw_ch3_cfg 28
151#define REG_WR_ADDR_bif_slave_rw_ch3_cfg 28
152
153/* Register rw_arb_cfg, scope bif_slave, type rw */
154typedef struct {
155 unsigned int brin_mode : 1;
156 unsigned int brout_mode : 3;
157 unsigned int bg_mode : 3;
158 unsigned int release : 2;
159 unsigned int acquire : 1;
160 unsigned int settle_time : 2;
161 unsigned int dram_ctrl : 1;
162 unsigned int dummy1 : 19;
163} reg_bif_slave_rw_arb_cfg;
164#define REG_RD_ADDR_bif_slave_rw_arb_cfg 32
165#define REG_WR_ADDR_bif_slave_rw_arb_cfg 32
166
167/* Register r_arb_stat, scope bif_slave, type r */
168typedef struct {
169 unsigned int init_mode : 1;
170 unsigned int mode : 1;
171 unsigned int brin : 1;
172 unsigned int brout : 1;
173 unsigned int bg : 1;
174 unsigned int dummy1 : 27;
175} reg_bif_slave_r_arb_stat;
176#define REG_RD_ADDR_bif_slave_r_arb_stat 36
177
178/* Register rw_intr_mask, scope bif_slave, type rw */
179typedef struct {
180 unsigned int bus_release : 1;
181 unsigned int bus_acquire : 1;
182 unsigned int dummy1 : 30;
183} reg_bif_slave_rw_intr_mask;
184#define REG_RD_ADDR_bif_slave_rw_intr_mask 64
185#define REG_WR_ADDR_bif_slave_rw_intr_mask 64
186
187/* Register rw_ack_intr, scope bif_slave, type rw */
188typedef struct {
189 unsigned int bus_release : 1;
190 unsigned int bus_acquire : 1;
191 unsigned int dummy1 : 30;
192} reg_bif_slave_rw_ack_intr;
193#define REG_RD_ADDR_bif_slave_rw_ack_intr 68
194#define REG_WR_ADDR_bif_slave_rw_ack_intr 68
195
196/* Register r_intr, scope bif_slave, type r */
197typedef struct {
198 unsigned int bus_release : 1;
199 unsigned int bus_acquire : 1;
200 unsigned int dummy1 : 30;
201} reg_bif_slave_r_intr;
202#define REG_RD_ADDR_bif_slave_r_intr 72
203
204/* Register r_masked_intr, scope bif_slave, type r */
205typedef struct {
206 unsigned int bus_release : 1;
207 unsigned int bus_acquire : 1;
208 unsigned int dummy1 : 30;
209} reg_bif_slave_r_masked_intr;
210#define REG_RD_ADDR_bif_slave_r_masked_intr 76
211
212
213/* Constants */
214enum {
215 regk_bif_slave_active_hi = 0x00000003,
216 regk_bif_slave_active_lo = 0x00000002,
217 regk_bif_slave_addr = 0x00000000,
218 regk_bif_slave_always = 0x00000001,
219 regk_bif_slave_at_idle = 0x00000002,
220 regk_bif_slave_burst_end = 0x00000003,
221 regk_bif_slave_dma = 0x00000001,
222 regk_bif_slave_hi = 0x00000003,
223 regk_bif_slave_inv = 0x00000001,
224 regk_bif_slave_lo = 0x00000002,
225 regk_bif_slave_local = 0x00000001,
226 regk_bif_slave_master = 0x00000000,
227 regk_bif_slave_mode_reg = 0x00000001,
228 regk_bif_slave_no = 0x00000000,
229 regk_bif_slave_norm = 0x00000000,
230 regk_bif_slave_on_access = 0x00000000,
231 regk_bif_slave_rw_arb_cfg_default = 0x00000000,
232 regk_bif_slave_rw_ch0_cfg_default = 0x00000000,
233 regk_bif_slave_rw_ch1_cfg_default = 0x00000000,
234 regk_bif_slave_rw_ch2_cfg_default = 0x00000000,
235 regk_bif_slave_rw_ch3_cfg_default = 0x00000000,
236 regk_bif_slave_rw_intr_mask_default = 0x00000000,
237 regk_bif_slave_rw_slave_cfg_default = 0x00000000,
238 regk_bif_slave_shared = 0x00000000,
239 regk_bif_slave_slave = 0x00000001,
240 regk_bif_slave_t0ns = 0x00000003,
241 regk_bif_slave_t10ns = 0x00000002,
242 regk_bif_slave_t20ns = 0x00000003,
243 regk_bif_slave_t30ns = 0x00000002,
244 regk_bif_slave_t40ns = 0x00000001,
245 regk_bif_slave_t50ns = 0x00000000,
246 regk_bif_slave_yes = 0x00000001,
247 regk_bif_slave_z = 0x00000004
248};
249#endif /* __bif_slave_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/config_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/config_defs.h
new file mode 100644
index 000000000000..abc5f20705f7
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-fs/hwregs/config_defs.h
@@ -0,0 +1,142 @@
1#ifndef __config_defs_h
2#define __config_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../rtl/config_regs.r
7 * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp
8 * last modfied: Thu Mar 4 12:34:39 2004
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile config_defs.h ../../rtl/config_regs.r
11 * id: $Id: config_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope config */
86
87/* Register r_bootsel, scope config, type r */
88typedef struct {
89 unsigned int boot_mode : 3;
90 unsigned int full_duplex : 1;
91 unsigned int user : 1;
92 unsigned int pll : 1;
93 unsigned int flash_bw : 1;
94 unsigned int dummy1 : 25;
95} reg_config_r_bootsel;
96#define REG_RD_ADDR_config_r_bootsel 0
97
98/* Register rw_clk_ctrl, scope config, type rw */
99typedef struct {
100 unsigned int pll : 1;
101 unsigned int cpu : 1;
102 unsigned int iop : 1;
103 unsigned int dma01_eth0 : 1;
104 unsigned int dma23 : 1;
105 unsigned int dma45 : 1;
106 unsigned int dma67 : 1;
107 unsigned int dma89_strcop : 1;
108 unsigned int bif : 1;
109 unsigned int fix_io : 1;
110 unsigned int dummy1 : 22;
111} reg_config_rw_clk_ctrl;
112#define REG_RD_ADDR_config_rw_clk_ctrl 4
113#define REG_WR_ADDR_config_rw_clk_ctrl 4
114
115/* Register rw_pad_ctrl, scope config, type rw */
116typedef struct {
117 unsigned int usb_susp : 1;
118 unsigned int phyrst_n : 1;
119 unsigned int dummy1 : 30;
120} reg_config_rw_pad_ctrl;
121#define REG_RD_ADDR_config_rw_pad_ctrl 8
122#define REG_WR_ADDR_config_rw_pad_ctrl 8
123
124
125/* Constants */
126enum {
127 regk_config_bw16 = 0x00000000,
128 regk_config_bw32 = 0x00000001,
129 regk_config_master = 0x00000005,
130 regk_config_nand = 0x00000003,
131 regk_config_net_rx = 0x00000001,
132 regk_config_net_tx_rx = 0x00000002,
133 regk_config_no = 0x00000000,
134 regk_config_none = 0x00000007,
135 regk_config_nor = 0x00000000,
136 regk_config_rw_clk_ctrl_default = 0x00000002,
137 regk_config_rw_pad_ctrl_default = 0x00000000,
138 regk_config_ser = 0x00000004,
139 regk_config_slave = 0x00000006,
140 regk_config_yes = 0x00000001
141};
142#endif /* __config_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/gio_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/gio_defs.h
new file mode 100644
index 000000000000..26aa3efcf91b
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-fs/hwregs/gio_defs.h
@@ -0,0 +1,295 @@
1#ifndef __gio_defs_h
2#define __gio_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/gio/rtl/gio_regs.r
7 * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp
8 * last modfied: Mon Apr 11 16:07:47 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile gio_defs.h ../../inst/gio/rtl/gio_regs.r
11 * id: $Id: gio_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope gio */
86
87/* Register rw_pa_dout, scope gio, type rw */
88typedef struct {
89 unsigned int data : 8;
90 unsigned int dummy1 : 24;
91} reg_gio_rw_pa_dout;
92#define REG_RD_ADDR_gio_rw_pa_dout 0
93#define REG_WR_ADDR_gio_rw_pa_dout 0
94
95/* Register r_pa_din, scope gio, type r */
96typedef struct {
97 unsigned int data : 8;
98 unsigned int dummy1 : 24;
99} reg_gio_r_pa_din;
100#define REG_RD_ADDR_gio_r_pa_din 4
101
102/* Register rw_pa_oe, scope gio, type rw */
103typedef struct {
104 unsigned int oe : 8;
105 unsigned int dummy1 : 24;
106} reg_gio_rw_pa_oe;
107#define REG_RD_ADDR_gio_rw_pa_oe 8
108#define REG_WR_ADDR_gio_rw_pa_oe 8
109
110/* Register rw_intr_cfg, scope gio, type rw */
111typedef struct {
112 unsigned int pa0 : 3;
113 unsigned int pa1 : 3;
114 unsigned int pa2 : 3;
115 unsigned int pa3 : 3;
116 unsigned int pa4 : 3;
117 unsigned int pa5 : 3;
118 unsigned int pa6 : 3;
119 unsigned int pa7 : 3;
120 unsigned int dummy1 : 8;
121} reg_gio_rw_intr_cfg;
122#define REG_RD_ADDR_gio_rw_intr_cfg 12
123#define REG_WR_ADDR_gio_rw_intr_cfg 12
124
125/* Register rw_intr_mask, scope gio, type rw */
126typedef struct {
127 unsigned int pa0 : 1;
128 unsigned int pa1 : 1;
129 unsigned int pa2 : 1;
130 unsigned int pa3 : 1;
131 unsigned int pa4 : 1;
132 unsigned int pa5 : 1;
133 unsigned int pa6 : 1;
134 unsigned int pa7 : 1;
135 unsigned int dummy1 : 24;
136} reg_gio_rw_intr_mask;
137#define REG_RD_ADDR_gio_rw_intr_mask 16
138#define REG_WR_ADDR_gio_rw_intr_mask 16
139
140/* Register rw_ack_intr, scope gio, type rw */
141typedef struct {
142 unsigned int pa0 : 1;
143 unsigned int pa1 : 1;
144 unsigned int pa2 : 1;
145 unsigned int pa3 : 1;
146 unsigned int pa4 : 1;
147 unsigned int pa5 : 1;
148 unsigned int pa6 : 1;
149 unsigned int pa7 : 1;
150 unsigned int dummy1 : 24;
151} reg_gio_rw_ack_intr;
152#define REG_RD_ADDR_gio_rw_ack_intr 20
153#define REG_WR_ADDR_gio_rw_ack_intr 20
154
155/* Register r_intr, scope gio, type r */
156typedef struct {
157 unsigned int pa0 : 1;
158 unsigned int pa1 : 1;
159 unsigned int pa2 : 1;
160 unsigned int pa3 : 1;
161 unsigned int pa4 : 1;
162 unsigned int pa5 : 1;
163 unsigned int pa6 : 1;
164 unsigned int pa7 : 1;
165 unsigned int dummy1 : 24;
166} reg_gio_r_intr;
167#define REG_RD_ADDR_gio_r_intr 24
168
169/* Register r_masked_intr, scope gio, type r */
170typedef struct {
171 unsigned int pa0 : 1;
172 unsigned int pa1 : 1;
173 unsigned int pa2 : 1;
174 unsigned int pa3 : 1;
175 unsigned int pa4 : 1;
176 unsigned int pa5 : 1;
177 unsigned int pa6 : 1;
178 unsigned int pa7 : 1;
179 unsigned int dummy1 : 24;
180} reg_gio_r_masked_intr;
181#define REG_RD_ADDR_gio_r_masked_intr 28
182
183/* Register rw_pb_dout, scope gio, type rw */
184typedef struct {
185 unsigned int data : 18;
186 unsigned int dummy1 : 14;
187} reg_gio_rw_pb_dout;
188#define REG_RD_ADDR_gio_rw_pb_dout 32
189#define REG_WR_ADDR_gio_rw_pb_dout 32
190
191/* Register r_pb_din, scope gio, type r */
192typedef struct {
193 unsigned int data : 18;
194 unsigned int dummy1 : 14;
195} reg_gio_r_pb_din;
196#define REG_RD_ADDR_gio_r_pb_din 36
197
198/* Register rw_pb_oe, scope gio, type rw */
199typedef struct {
200 unsigned int oe : 18;
201 unsigned int dummy1 : 14;
202} reg_gio_rw_pb_oe;
203#define REG_RD_ADDR_gio_rw_pb_oe 40
204#define REG_WR_ADDR_gio_rw_pb_oe 40
205
206/* Register rw_pc_dout, scope gio, type rw */
207typedef struct {
208 unsigned int data : 18;
209 unsigned int dummy1 : 14;
210} reg_gio_rw_pc_dout;
211#define REG_RD_ADDR_gio_rw_pc_dout 48
212#define REG_WR_ADDR_gio_rw_pc_dout 48
213
214/* Register r_pc_din, scope gio, type r */
215typedef struct {
216 unsigned int data : 18;
217 unsigned int dummy1 : 14;
218} reg_gio_r_pc_din;
219#define REG_RD_ADDR_gio_r_pc_din 52
220
221/* Register rw_pc_oe, scope gio, type rw */
222typedef struct {
223 unsigned int oe : 18;
224 unsigned int dummy1 : 14;
225} reg_gio_rw_pc_oe;
226#define REG_RD_ADDR_gio_rw_pc_oe 56
227#define REG_WR_ADDR_gio_rw_pc_oe 56
228
229/* Register rw_pd_dout, scope gio, type rw */
230typedef struct {
231 unsigned int data : 18;
232 unsigned int dummy1 : 14;
233} reg_gio_rw_pd_dout;
234#define REG_RD_ADDR_gio_rw_pd_dout 64
235#define REG_WR_ADDR_gio_rw_pd_dout 64
236
237/* Register r_pd_din, scope gio, type r */
238typedef struct {
239 unsigned int data : 18;
240 unsigned int dummy1 : 14;
241} reg_gio_r_pd_din;
242#define REG_RD_ADDR_gio_r_pd_din 68
243
244/* Register rw_pd_oe, scope gio, type rw */
245typedef struct {
246 unsigned int oe : 18;
247 unsigned int dummy1 : 14;
248} reg_gio_rw_pd_oe;
249#define REG_RD_ADDR_gio_rw_pd_oe 72
250#define REG_WR_ADDR_gio_rw_pd_oe 72
251
252/* Register rw_pe_dout, scope gio, type rw */
253typedef struct {
254 unsigned int data : 18;
255 unsigned int dummy1 : 14;
256} reg_gio_rw_pe_dout;
257#define REG_RD_ADDR_gio_rw_pe_dout 80
258#define REG_WR_ADDR_gio_rw_pe_dout 80
259
260/* Register r_pe_din, scope gio, type r */
261typedef struct {
262 unsigned int data : 18;
263 unsigned int dummy1 : 14;
264} reg_gio_r_pe_din;
265#define REG_RD_ADDR_gio_r_pe_din 84
266
267/* Register rw_pe_oe, scope gio, type rw */
268typedef struct {
269 unsigned int oe : 18;
270 unsigned int dummy1 : 14;
271} reg_gio_rw_pe_oe;
272#define REG_RD_ADDR_gio_rw_pe_oe 88
273#define REG_WR_ADDR_gio_rw_pe_oe 88
274
275
276/* Constants */
277enum {
278 regk_gio_anyedge = 0x00000007,
279 regk_gio_hi = 0x00000001,
280 regk_gio_lo = 0x00000002,
281 regk_gio_negedge = 0x00000006,
282 regk_gio_no = 0x00000000,
283 regk_gio_off = 0x00000000,
284 regk_gio_posedge = 0x00000005,
285 regk_gio_rw_intr_cfg_default = 0x00000000,
286 regk_gio_rw_intr_mask_default = 0x00000000,
287 regk_gio_rw_pa_oe_default = 0x00000000,
288 regk_gio_rw_pb_oe_default = 0x00000000,
289 regk_gio_rw_pc_oe_default = 0x00000000,
290 regk_gio_rw_pd_oe_default = 0x00000000,
291 regk_gio_rw_pe_oe_default = 0x00000000,
292 regk_gio_set = 0x00000003,
293 regk_gio_yes = 0x00000001
294};
295#endif /* __gio_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect.h b/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect.h
new file mode 100644
index 000000000000..bacc2a895c21
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect.h
@@ -0,0 +1,41 @@
1/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
2 from ../../inst/intr_vect/rtl/guinness/ivmask.config.r
3version . */
4
5#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
6#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
7#define MEMARB_INTR_VECT 0x31
8#define GEN_IO_INTR_VECT 0x32
9#define GIO_INTR_VECT GEN_IO_INTR_VECT
10#define IOP0_INTR_VECT 0x33
11#define IOP1_INTR_VECT 0x34
12#define IOP2_INTR_VECT 0x35
13#define IOP3_INTR_VECT 0x36
14#define DMA0_INTR_VECT 0x37
15#define DMA1_INTR_VECT 0x38
16#define DMA2_INTR_VECT 0x39
17#define DMA3_INTR_VECT 0x3a
18#define DMA4_INTR_VECT 0x3b
19#define DMA5_INTR_VECT 0x3c
20#define DMA6_INTR_VECT 0x3d
21#define DMA7_INTR_VECT 0x3e
22#define DMA8_INTR_VECT 0x3f
23#define DMA9_INTR_VECT 0x40
24#define ATA_INTR_VECT 0x41
25#define SSER0_INTR_VECT 0x42
26#define SSER1_INTR_VECT 0x43
27#define SER0_INTR_VECT 0x44
28#define SER1_INTR_VECT 0x45
29#define SER2_INTR_VECT 0x46
30#define SER3_INTR_VECT 0x47
31#define P21_INTR_VECT 0x48
32#define ETH0_INTR_VECT 0x49
33#define ETH1_INTR_VECT 0x4a
34#define TIMER_INTR_VECT 0x4b
35#define TIMER0_INTR_VECT TIMER_INTR_VECT
36#define BIF_ARB_INTR_VECT 0x4c
37#define BIF_DMA_INTR_VECT 0x4d
38#define EXT_INTR_VECT 0x4e
39#define IPI_INTR_VECT 0x4f
40#define NBR_INTR_VECT 0x50
41#endif
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect_defs.h
new file mode 100644
index 000000000000..aa65128ae1aa
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect_defs.h
@@ -0,0 +1,228 @@
1#ifndef __intr_vect_defs_h
2#define __intr_vect_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r
7 * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp
8 * last modfied: Mon Apr 11 16:08:03 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile intr_vect_defs.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r
11 * id: $Id: intr_vect_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope intr_vect */
86
87#define STRIDE_intr_vect_rw_mask 0
88/* Register rw_mask, scope intr_vect, type rw */
89typedef struct {
90 unsigned int memarb : 1;
91 unsigned int gen_io : 1;
92 unsigned int iop0 : 1;
93 unsigned int iop1 : 1;
94 unsigned int iop2 : 1;
95 unsigned int iop3 : 1;
96 unsigned int dma0 : 1;
97 unsigned int dma1 : 1;
98 unsigned int dma2 : 1;
99 unsigned int dma3 : 1;
100 unsigned int dma4 : 1;
101 unsigned int dma5 : 1;
102 unsigned int dma6 : 1;
103 unsigned int dma7 : 1;
104 unsigned int dma8 : 1;
105 unsigned int dma9 : 1;
106 unsigned int ata : 1;
107 unsigned int sser0 : 1;
108 unsigned int sser1 : 1;
109 unsigned int ser0 : 1;
110 unsigned int ser1 : 1;
111 unsigned int ser2 : 1;
112 unsigned int ser3 : 1;
113 unsigned int p21 : 1;
114 unsigned int eth0 : 1;
115 unsigned int eth1 : 1;
116 unsigned int timer0 : 1;
117 unsigned int bif_arb : 1;
118 unsigned int bif_dma : 1;
119 unsigned int ext : 1;
120 unsigned int dummy1 : 2;
121} reg_intr_vect_rw_mask;
122#define REG_RD_ADDR_intr_vect_rw_mask 0
123#define REG_WR_ADDR_intr_vect_rw_mask 0
124
125#define STRIDE_intr_vect_r_vect 0
126/* Register r_vect, scope intr_vect, type r */
127typedef struct {
128 unsigned int memarb : 1;
129 unsigned int gen_io : 1;
130 unsigned int iop0 : 1;
131 unsigned int iop1 : 1;
132 unsigned int iop2 : 1;
133 unsigned int iop3 : 1;
134 unsigned int dma0 : 1;
135 unsigned int dma1 : 1;
136 unsigned int dma2 : 1;
137 unsigned int dma3 : 1;
138 unsigned int dma4 : 1;
139 unsigned int dma5 : 1;
140 unsigned int dma6 : 1;
141 unsigned int dma7 : 1;
142 unsigned int dma8 : 1;
143 unsigned int dma9 : 1;
144 unsigned int ata : 1;
145 unsigned int sser0 : 1;
146 unsigned int sser1 : 1;
147 unsigned int ser0 : 1;
148 unsigned int ser1 : 1;
149 unsigned int ser2 : 1;
150 unsigned int ser3 : 1;
151 unsigned int p21 : 1;
152 unsigned int eth0 : 1;
153 unsigned int eth1 : 1;
154 unsigned int timer : 1;
155 unsigned int bif_arb : 1;
156 unsigned int bif_dma : 1;
157 unsigned int ext : 1;
158 unsigned int dummy1 : 2;
159} reg_intr_vect_r_vect;
160#define REG_RD_ADDR_intr_vect_r_vect 4
161
162#define STRIDE_intr_vect_r_masked_vect 0
163/* Register r_masked_vect, scope intr_vect, type r */
164typedef struct {
165 unsigned int memarb : 1;
166 unsigned int gen_io : 1;
167 unsigned int iop0 : 1;
168 unsigned int iop1 : 1;
169 unsigned int iop2 : 1;
170 unsigned int iop3 : 1;
171 unsigned int dma0 : 1;
172 unsigned int dma1 : 1;
173 unsigned int dma2 : 1;
174 unsigned int dma3 : 1;
175 unsigned int dma4 : 1;
176 unsigned int dma5 : 1;
177 unsigned int dma6 : 1;
178 unsigned int dma7 : 1;
179 unsigned int dma8 : 1;
180 unsigned int dma9 : 1;
181 unsigned int ata : 1;
182 unsigned int sser0 : 1;
183 unsigned int sser1 : 1;
184 unsigned int ser0 : 1;
185 unsigned int ser1 : 1;
186 unsigned int ser2 : 1;
187 unsigned int ser3 : 1;
188 unsigned int p21 : 1;
189 unsigned int eth0 : 1;
190 unsigned int eth1 : 1;
191 unsigned int timer : 1;
192 unsigned int bif_arb : 1;
193 unsigned int bif_dma : 1;
194 unsigned int ext : 1;
195 unsigned int dummy1 : 2;
196} reg_intr_vect_r_masked_vect;
197#define REG_RD_ADDR_intr_vect_r_masked_vect 8
198
199/* Register r_nmi, scope intr_vect, type r */
200typedef struct {
201 unsigned int ext : 1;
202 unsigned int watchdog : 1;
203 unsigned int dummy1 : 30;
204} reg_intr_vect_r_nmi;
205#define REG_RD_ADDR_intr_vect_r_nmi 12
206
207/* Register r_guru, scope intr_vect, type r */
208typedef struct {
209 unsigned int jtag : 1;
210 unsigned int dummy1 : 31;
211} reg_intr_vect_r_guru;
212#define REG_RD_ADDR_intr_vect_r_guru 16
213
214/* Register rw_ipi, scope intr_vect, type rw */
215typedef struct
216{
217 unsigned int vector;
218} reg_intr_vect_rw_ipi;
219#define REG_RD_ADDR_intr_vect_rw_ipi 20
220#define REG_WR_ADDR_intr_vect_rw_ipi 20
221
222/* Constants */
223enum {
224 regk_intr_vect_off = 0x00000000,
225 regk_intr_vect_on = 0x00000001,
226 regk_intr_vect_rw_mask_default = 0x00000000
227};
228#endif /* __intr_vect_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/marb_bp_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/marb_bp_defs.h
new file mode 100644
index 000000000000..dcaaec4620ba
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-fs/hwregs/marb_bp_defs.h
@@ -0,0 +1,205 @@
1#ifndef __marb_bp_defs_h
2#define __marb_bp_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/memarb/rtl/guinness/marb_top.r
7 * id: <not found>
8 * last modfied: Fri Nov 7 15:36:04 2003
9 *
10 * by /n/asic/projects/guinness/design/top/inst/rdesc/rdes2c ../../rtl/global.rmap ../../mod/modreg.rmap -base 0xb0000000 ../../inst/memarb/rtl/guinness/marb_top.r
11 * id: $Id: marb_bp_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74/* C-code for register scope marb_bp */
75
76/* Register rw_first_addr, scope marb_bp, type rw */
77typedef unsigned int reg_marb_bp_rw_first_addr;
78#define REG_RD_ADDR_marb_bp_rw_first_addr 0
79#define REG_WR_ADDR_marb_bp_rw_first_addr 0
80
81/* Register rw_last_addr, scope marb_bp, type rw */
82typedef unsigned int reg_marb_bp_rw_last_addr;
83#define REG_RD_ADDR_marb_bp_rw_last_addr 4
84#define REG_WR_ADDR_marb_bp_rw_last_addr 4
85
86/* Register rw_op, scope marb_bp, type rw */
87typedef struct {
88 unsigned int read : 1;
89 unsigned int write : 1;
90 unsigned int read_excl : 1;
91 unsigned int pri_write : 1;
92 unsigned int us_read : 1;
93 unsigned int us_write : 1;
94 unsigned int us_read_excl : 1;
95 unsigned int us_pri_write : 1;
96 unsigned int dummy1 : 24;
97} reg_marb_bp_rw_op;
98#define REG_RD_ADDR_marb_bp_rw_op 8
99#define REG_WR_ADDR_marb_bp_rw_op 8
100
101/* Register rw_clients, scope marb_bp, type rw */
102typedef struct {
103 unsigned int dma0 : 1;
104 unsigned int dma1 : 1;
105 unsigned int dma2 : 1;
106 unsigned int dma3 : 1;
107 unsigned int dma4 : 1;
108 unsigned int dma5 : 1;
109 unsigned int dma6 : 1;
110 unsigned int dma7 : 1;
111 unsigned int dma8 : 1;
112 unsigned int dma9 : 1;
113 unsigned int cpui : 1;
114 unsigned int cpud : 1;
115 unsigned int iop : 1;
116 unsigned int slave : 1;
117 unsigned int dummy1 : 18;
118} reg_marb_bp_rw_clients;
119#define REG_RD_ADDR_marb_bp_rw_clients 12
120#define REG_WR_ADDR_marb_bp_rw_clients 12
121
122/* Register rw_options, scope marb_bp, type rw */
123typedef struct {
124 unsigned int wrap : 1;
125 unsigned int dummy1 : 31;
126} reg_marb_bp_rw_options;
127#define REG_RD_ADDR_marb_bp_rw_options 16
128#define REG_WR_ADDR_marb_bp_rw_options 16
129
130/* Register r_break_addr, scope marb_bp, type r */
131typedef unsigned int reg_marb_bp_r_break_addr;
132#define REG_RD_ADDR_marb_bp_r_break_addr 20
133
134/* Register r_break_op, scope marb_bp, type r */
135typedef struct {
136 unsigned int read : 1;
137 unsigned int write : 1;
138 unsigned int read_excl : 1;
139 unsigned int pri_write : 1;
140 unsigned int us_read : 1;
141 unsigned int us_write : 1;
142 unsigned int us_read_excl : 1;
143 unsigned int us_pri_write : 1;
144 unsigned int dummy1 : 24;
145} reg_marb_bp_r_break_op;
146#define REG_RD_ADDR_marb_bp_r_break_op 24
147
148/* Register r_break_clients, scope marb_bp, type r */
149typedef struct {
150 unsigned int dma0 : 1;
151 unsigned int dma1 : 1;
152 unsigned int dma2 : 1;
153 unsigned int dma3 : 1;
154 unsigned int dma4 : 1;
155 unsigned int dma5 : 1;
156 unsigned int dma6 : 1;
157 unsigned int dma7 : 1;
158 unsigned int dma8 : 1;
159 unsigned int dma9 : 1;
160 unsigned int cpui : 1;
161 unsigned int cpud : 1;
162 unsigned int iop : 1;
163 unsigned int slave : 1;
164 unsigned int dummy1 : 18;
165} reg_marb_bp_r_break_clients;
166#define REG_RD_ADDR_marb_bp_r_break_clients 28
167
168/* Register r_break_first_client, scope marb_bp, type r */
169typedef struct {
170 unsigned int dma0 : 1;
171 unsigned int dma1 : 1;
172 unsigned int dma2 : 1;
173 unsigned int dma3 : 1;
174 unsigned int dma4 : 1;
175 unsigned int dma5 : 1;
176 unsigned int dma6 : 1;
177 unsigned int dma7 : 1;
178 unsigned int dma8 : 1;
179 unsigned int dma9 : 1;
180 unsigned int cpui : 1;
181 unsigned int cpud : 1;
182 unsigned int iop : 1;
183 unsigned int slave : 1;
184 unsigned int dummy1 : 18;
185} reg_marb_bp_r_break_first_client;
186#define REG_RD_ADDR_marb_bp_r_break_first_client 32
187
188/* Register r_break_size, scope marb_bp, type r */
189typedef unsigned int reg_marb_bp_r_break_size;
190#define REG_RD_ADDR_marb_bp_r_break_size 36
191
192/* Register rw_ack, scope marb_bp, type rw */
193typedef unsigned int reg_marb_bp_rw_ack;
194#define REG_RD_ADDR_marb_bp_rw_ack 40
195#define REG_WR_ADDR_marb_bp_rw_ack 40
196
197
198/* Constants */
199enum {
200 regk_marb_bp_no = 0x00000000,
201 regk_marb_bp_rw_op_default = 0x00000000,
202 regk_marb_bp_rw_options_default = 0x00000000,
203 regk_marb_bp_yes = 0x00000001
204};
205#endif /* __marb_bp_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/marb_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/marb_defs.h
new file mode 100644
index 000000000000..254da0854986
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-fs/hwregs/marb_defs.h
@@ -0,0 +1,475 @@
1#ifndef __marb_defs_h
2#define __marb_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/memarb/rtl/guinness/marb_top.r
7 * id: <not found>
8 * last modfied: Mon Apr 11 16:12:16 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r
11 * id: $Id: marb_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope marb */
86
87#define STRIDE_marb_rw_int_slots 4
88/* Register rw_int_slots, scope marb, type rw */
89typedef struct {
90 unsigned int owner : 4;
91 unsigned int dummy1 : 28;
92} reg_marb_rw_int_slots;
93#define REG_RD_ADDR_marb_rw_int_slots 0
94#define REG_WR_ADDR_marb_rw_int_slots 0
95
96#define STRIDE_marb_rw_ext_slots 4
97/* Register rw_ext_slots, scope marb, type rw */
98typedef struct {
99 unsigned int owner : 4;
100 unsigned int dummy1 : 28;
101} reg_marb_rw_ext_slots;
102#define REG_RD_ADDR_marb_rw_ext_slots 256
103#define REG_WR_ADDR_marb_rw_ext_slots 256
104
105#define STRIDE_marb_rw_regs_slots 4
106/* Register rw_regs_slots, scope marb, type rw */
107typedef struct {
108 unsigned int owner : 4;
109 unsigned int dummy1 : 28;
110} reg_marb_rw_regs_slots;
111#define REG_RD_ADDR_marb_rw_regs_slots 512
112#define REG_WR_ADDR_marb_rw_regs_slots 512
113
114/* Register rw_intr_mask, scope marb, type rw */
115typedef struct {
116 unsigned int bp0 : 1;
117 unsigned int bp1 : 1;
118 unsigned int bp2 : 1;
119 unsigned int bp3 : 1;
120 unsigned int dummy1 : 28;
121} reg_marb_rw_intr_mask;
122#define REG_RD_ADDR_marb_rw_intr_mask 528
123#define REG_WR_ADDR_marb_rw_intr_mask 528
124
125/* Register rw_ack_intr, scope marb, type rw */
126typedef struct {
127 unsigned int bp0 : 1;
128 unsigned int bp1 : 1;
129 unsigned int bp2 : 1;
130 unsigned int bp3 : 1;
131 unsigned int dummy1 : 28;
132} reg_marb_rw_ack_intr;
133#define REG_RD_ADDR_marb_rw_ack_intr 532
134#define REG_WR_ADDR_marb_rw_ack_intr 532
135
136/* Register r_intr, scope marb, type r */
137typedef struct {
138 unsigned int bp0 : 1;
139 unsigned int bp1 : 1;
140 unsigned int bp2 : 1;
141 unsigned int bp3 : 1;
142 unsigned int dummy1 : 28;
143} reg_marb_r_intr;
144#define REG_RD_ADDR_marb_r_intr 536
145
146/* Register r_masked_intr, scope marb, type r */
147typedef struct {
148 unsigned int bp0 : 1;
149 unsigned int bp1 : 1;
150 unsigned int bp2 : 1;
151 unsigned int bp3 : 1;
152 unsigned int dummy1 : 28;
153} reg_marb_r_masked_intr;
154#define REG_RD_ADDR_marb_r_masked_intr 540
155
156/* Register rw_stop_mask, scope marb, type rw */
157typedef struct {
158 unsigned int dma0 : 1;
159 unsigned int dma1 : 1;
160 unsigned int dma2 : 1;
161 unsigned int dma3 : 1;
162 unsigned int dma4 : 1;
163 unsigned int dma5 : 1;
164 unsigned int dma6 : 1;
165 unsigned int dma7 : 1;
166 unsigned int dma8 : 1;
167 unsigned int dma9 : 1;
168 unsigned int cpui : 1;
169 unsigned int cpud : 1;
170 unsigned int iop : 1;
171 unsigned int slave : 1;
172 unsigned int dummy1 : 18;
173} reg_marb_rw_stop_mask;
174#define REG_RD_ADDR_marb_rw_stop_mask 544
175#define REG_WR_ADDR_marb_rw_stop_mask 544
176
177/* Register r_stopped, scope marb, type r */
178typedef struct {
179 unsigned int dma0 : 1;
180 unsigned int dma1 : 1;
181 unsigned int dma2 : 1;
182 unsigned int dma3 : 1;
183 unsigned int dma4 : 1;
184 unsigned int dma5 : 1;
185 unsigned int dma6 : 1;
186 unsigned int dma7 : 1;
187 unsigned int dma8 : 1;
188 unsigned int dma9 : 1;
189 unsigned int cpui : 1;
190 unsigned int cpud : 1;
191 unsigned int iop : 1;
192 unsigned int slave : 1;
193 unsigned int dummy1 : 18;
194} reg_marb_r_stopped;
195#define REG_RD_ADDR_marb_r_stopped 548
196
197/* Register rw_no_snoop, scope marb, type rw */
198typedef struct {
199 unsigned int dma0 : 1;
200 unsigned int dma1 : 1;
201 unsigned int dma2 : 1;
202 unsigned int dma3 : 1;
203 unsigned int dma4 : 1;
204 unsigned int dma5 : 1;
205 unsigned int dma6 : 1;
206 unsigned int dma7 : 1;
207 unsigned int dma8 : 1;
208 unsigned int dma9 : 1;
209 unsigned int cpui : 1;
210 unsigned int cpud : 1;
211 unsigned int iop : 1;
212 unsigned int slave : 1;
213 unsigned int dummy1 : 18;
214} reg_marb_rw_no_snoop;
215#define REG_RD_ADDR_marb_rw_no_snoop 832
216#define REG_WR_ADDR_marb_rw_no_snoop 832
217
218/* Register rw_no_snoop_rq, scope marb, type rw */
219typedef struct {
220 unsigned int dummy1 : 10;
221 unsigned int cpui : 1;
222 unsigned int cpud : 1;
223 unsigned int dummy2 : 20;
224} reg_marb_rw_no_snoop_rq;
225#define REG_RD_ADDR_marb_rw_no_snoop_rq 836
226#define REG_WR_ADDR_marb_rw_no_snoop_rq 836
227
228
229/* Constants */
230enum {
231 regk_marb_cpud = 0x0000000b,
232 regk_marb_cpui = 0x0000000a,
233 regk_marb_dma0 = 0x00000000,
234 regk_marb_dma1 = 0x00000001,
235 regk_marb_dma2 = 0x00000002,
236 regk_marb_dma3 = 0x00000003,
237 regk_marb_dma4 = 0x00000004,
238 regk_marb_dma5 = 0x00000005,
239 regk_marb_dma6 = 0x00000006,
240 regk_marb_dma7 = 0x00000007,
241 regk_marb_dma8 = 0x00000008,
242 regk_marb_dma9 = 0x00000009,
243 regk_marb_iop = 0x0000000c,
244 regk_marb_no = 0x00000000,
245 regk_marb_r_stopped_default = 0x00000000,
246 regk_marb_rw_ext_slots_default = 0x00000000,
247 regk_marb_rw_ext_slots_size = 0x00000040,
248 regk_marb_rw_int_slots_default = 0x00000000,
249 regk_marb_rw_int_slots_size = 0x00000040,
250 regk_marb_rw_intr_mask_default = 0x00000000,
251 regk_marb_rw_no_snoop_default = 0x00000000,
252 regk_marb_rw_no_snoop_rq_default = 0x00000000,
253 regk_marb_rw_regs_slots_default = 0x00000000,
254 regk_marb_rw_regs_slots_size = 0x00000004,
255 regk_marb_rw_stop_mask_default = 0x00000000,
256 regk_marb_slave = 0x0000000d,
257 regk_marb_yes = 0x00000001
258};
259#endif /* __marb_defs_h */
260#ifndef __marb_bp_defs_h
261#define __marb_bp_defs_h
262
263/*
264 * This file is autogenerated from
265 * file: ../../inst/memarb/rtl/guinness/marb_top.r
266 * id: <not found>
267 * last modfied: Mon Apr 11 16:12:16 2005
268 *
269 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r
270 * id: $Id: marb_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
271 * Any changes here will be lost.
272 *
273 * -*- buffer-read-only: t -*-
274 */
275/* Main access macros */
276#ifndef REG_RD
277#define REG_RD( scope, inst, reg ) \
278 REG_READ( reg_##scope##_##reg, \
279 (inst) + REG_RD_ADDR_##scope##_##reg )
280#endif
281
282#ifndef REG_WR
283#define REG_WR( scope, inst, reg, val ) \
284 REG_WRITE( reg_##scope##_##reg, \
285 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
286#endif
287
288#ifndef REG_RD_VECT
289#define REG_RD_VECT( scope, inst, reg, index ) \
290 REG_READ( reg_##scope##_##reg, \
291 (inst) + REG_RD_ADDR_##scope##_##reg + \
292 (index) * STRIDE_##scope##_##reg )
293#endif
294
295#ifndef REG_WR_VECT
296#define REG_WR_VECT( scope, inst, reg, index, val ) \
297 REG_WRITE( reg_##scope##_##reg, \
298 (inst) + REG_WR_ADDR_##scope##_##reg + \
299 (index) * STRIDE_##scope##_##reg, (val) )
300#endif
301
302#ifndef REG_RD_INT
303#define REG_RD_INT( scope, inst, reg ) \
304 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
305#endif
306
307#ifndef REG_WR_INT
308#define REG_WR_INT( scope, inst, reg, val ) \
309 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
310#endif
311
312#ifndef REG_RD_INT_VECT
313#define REG_RD_INT_VECT( scope, inst, reg, index ) \
314 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
315 (index) * STRIDE_##scope##_##reg )
316#endif
317
318#ifndef REG_WR_INT_VECT
319#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
320 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
321 (index) * STRIDE_##scope##_##reg, (val) )
322#endif
323
324#ifndef REG_TYPE_CONV
325#define REG_TYPE_CONV( type, orgtype, val ) \
326 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
327#endif
328
329#ifndef reg_page_size
330#define reg_page_size 8192
331#endif
332
333#ifndef REG_ADDR
334#define REG_ADDR( scope, inst, reg ) \
335 ( (inst) + REG_RD_ADDR_##scope##_##reg )
336#endif
337
338#ifndef REG_ADDR_VECT
339#define REG_ADDR_VECT( scope, inst, reg, index ) \
340 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
341 (index) * STRIDE_##scope##_##reg )
342#endif
343
344/* C-code for register scope marb_bp */
345
346/* Register rw_first_addr, scope marb_bp, type rw */
347typedef unsigned int reg_marb_bp_rw_first_addr;
348#define REG_RD_ADDR_marb_bp_rw_first_addr 0
349#define REG_WR_ADDR_marb_bp_rw_first_addr 0
350
351/* Register rw_last_addr, scope marb_bp, type rw */
352typedef unsigned int reg_marb_bp_rw_last_addr;
353#define REG_RD_ADDR_marb_bp_rw_last_addr 4
354#define REG_WR_ADDR_marb_bp_rw_last_addr 4
355
356/* Register rw_op, scope marb_bp, type rw */
357typedef struct {
358 unsigned int rd : 1;
359 unsigned int wr : 1;
360 unsigned int rd_excl : 1;
361 unsigned int pri_wr : 1;
362 unsigned int us_rd : 1;
363 unsigned int us_wr : 1;
364 unsigned int us_rd_excl : 1;
365 unsigned int us_pri_wr : 1;
366 unsigned int dummy1 : 24;
367} reg_marb_bp_rw_op;
368#define REG_RD_ADDR_marb_bp_rw_op 8
369#define REG_WR_ADDR_marb_bp_rw_op 8
370
371/* Register rw_clients, scope marb_bp, type rw */
372typedef struct {
373 unsigned int dma0 : 1;
374 unsigned int dma1 : 1;
375 unsigned int dma2 : 1;
376 unsigned int dma3 : 1;
377 unsigned int dma4 : 1;
378 unsigned int dma5 : 1;
379 unsigned int dma6 : 1;
380 unsigned int dma7 : 1;
381 unsigned int dma8 : 1;
382 unsigned int dma9 : 1;
383 unsigned int cpui : 1;
384 unsigned int cpud : 1;
385 unsigned int iop : 1;
386 unsigned int slave : 1;
387 unsigned int dummy1 : 18;
388} reg_marb_bp_rw_clients;
389#define REG_RD_ADDR_marb_bp_rw_clients 12
390#define REG_WR_ADDR_marb_bp_rw_clients 12
391
392/* Register rw_options, scope marb_bp, type rw */
393typedef struct {
394 unsigned int wrap : 1;
395 unsigned int dummy1 : 31;
396} reg_marb_bp_rw_options;
397#define REG_RD_ADDR_marb_bp_rw_options 16
398#define REG_WR_ADDR_marb_bp_rw_options 16
399
400/* Register r_brk_addr, scope marb_bp, type r */
401typedef unsigned int reg_marb_bp_r_brk_addr;
402#define REG_RD_ADDR_marb_bp_r_brk_addr 20
403
404/* Register r_brk_op, scope marb_bp, type r */
405typedef struct {
406 unsigned int rd : 1;
407 unsigned int wr : 1;
408 unsigned int rd_excl : 1;
409 unsigned int pri_wr : 1;
410 unsigned int us_rd : 1;
411 unsigned int us_wr : 1;
412 unsigned int us_rd_excl : 1;
413 unsigned int us_pri_wr : 1;
414 unsigned int dummy1 : 24;
415} reg_marb_bp_r_brk_op;
416#define REG_RD_ADDR_marb_bp_r_brk_op 24
417
418/* Register r_brk_clients, scope marb_bp, type r */
419typedef struct {
420 unsigned int dma0 : 1;
421 unsigned int dma1 : 1;
422 unsigned int dma2 : 1;
423 unsigned int dma3 : 1;
424 unsigned int dma4 : 1;
425 unsigned int dma5 : 1;
426 unsigned int dma6 : 1;
427 unsigned int dma7 : 1;
428 unsigned int dma8 : 1;
429 unsigned int dma9 : 1;
430 unsigned int cpui : 1;
431 unsigned int cpud : 1;
432 unsigned int iop : 1;
433 unsigned int slave : 1;
434 unsigned int dummy1 : 18;
435} reg_marb_bp_r_brk_clients;
436#define REG_RD_ADDR_marb_bp_r_brk_clients 28
437
438/* Register r_brk_first_client, scope marb_bp, type r */
439typedef struct {
440 unsigned int dma0 : 1;
441 unsigned int dma1 : 1;
442 unsigned int dma2 : 1;
443 unsigned int dma3 : 1;
444 unsigned int dma4 : 1;
445 unsigned int dma5 : 1;
446 unsigned int dma6 : 1;
447 unsigned int dma7 : 1;
448 unsigned int dma8 : 1;
449 unsigned int dma9 : 1;
450 unsigned int cpui : 1;
451 unsigned int cpud : 1;
452 unsigned int iop : 1;
453 unsigned int slave : 1;
454 unsigned int dummy1 : 18;
455} reg_marb_bp_r_brk_first_client;
456#define REG_RD_ADDR_marb_bp_r_brk_first_client 32
457
458/* Register r_brk_size, scope marb_bp, type r */
459typedef unsigned int reg_marb_bp_r_brk_size;
460#define REG_RD_ADDR_marb_bp_r_brk_size 36
461
462/* Register rw_ack, scope marb_bp, type rw */
463typedef unsigned int reg_marb_bp_rw_ack;
464#define REG_RD_ADDR_marb_bp_rw_ack 40
465#define REG_WR_ADDR_marb_bp_rw_ack 40
466
467
468/* Constants */
469enum {
470 regk_marb_bp_no = 0x00000000,
471 regk_marb_bp_rw_op_default = 0x00000000,
472 regk_marb_bp_rw_options_default = 0x00000000,
473 regk_marb_bp_yes = 0x00000001
474};
475#endif /* __marb_bp_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/pinmux_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/pinmux_defs.h
new file mode 100644
index 000000000000..751eab5f191c
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-fs/hwregs/pinmux_defs.h
@@ -0,0 +1,357 @@
1#ifndef __pinmux_defs_h
2#define __pinmux_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r
7 * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp
8 * last modfied: Mon Apr 11 16:09:11 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile pinmux_defs.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r
11 * id: $Id: pinmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope pinmux */
86
87/* Register rw_pa, scope pinmux, type rw */
88typedef struct {
89 unsigned int pa0 : 1;
90 unsigned int pa1 : 1;
91 unsigned int pa2 : 1;
92 unsigned int pa3 : 1;
93 unsigned int pa4 : 1;
94 unsigned int pa5 : 1;
95 unsigned int pa6 : 1;
96 unsigned int pa7 : 1;
97 unsigned int csp2_n : 1;
98 unsigned int csp3_n : 1;
99 unsigned int csp5_n : 1;
100 unsigned int csp6_n : 1;
101 unsigned int hsh4 : 1;
102 unsigned int hsh5 : 1;
103 unsigned int hsh6 : 1;
104 unsigned int hsh7 : 1;
105 unsigned int dummy1 : 16;
106} reg_pinmux_rw_pa;
107#define REG_RD_ADDR_pinmux_rw_pa 0
108#define REG_WR_ADDR_pinmux_rw_pa 0
109
110/* Register rw_hwprot, scope pinmux, type rw */
111typedef struct {
112 unsigned int ser1 : 1;
113 unsigned int ser2 : 1;
114 unsigned int ser3 : 1;
115 unsigned int sser0 : 1;
116 unsigned int sser1 : 1;
117 unsigned int ata0 : 1;
118 unsigned int ata1 : 1;
119 unsigned int ata2 : 1;
120 unsigned int ata3 : 1;
121 unsigned int ata : 1;
122 unsigned int eth1 : 1;
123 unsigned int eth1_mgm : 1;
124 unsigned int timer : 1;
125 unsigned int p21 : 1;
126 unsigned int dummy1 : 18;
127} reg_pinmux_rw_hwprot;
128#define REG_RD_ADDR_pinmux_rw_hwprot 4
129#define REG_WR_ADDR_pinmux_rw_hwprot 4
130
131/* Register rw_pb_gio, scope pinmux, type rw */
132typedef struct {
133 unsigned int pb0 : 1;
134 unsigned int pb1 : 1;
135 unsigned int pb2 : 1;
136 unsigned int pb3 : 1;
137 unsigned int pb4 : 1;
138 unsigned int pb5 : 1;
139 unsigned int pb6 : 1;
140 unsigned int pb7 : 1;
141 unsigned int pb8 : 1;
142 unsigned int pb9 : 1;
143 unsigned int pb10 : 1;
144 unsigned int pb11 : 1;
145 unsigned int pb12 : 1;
146 unsigned int pb13 : 1;
147 unsigned int pb14 : 1;
148 unsigned int pb15 : 1;
149 unsigned int pb16 : 1;
150 unsigned int pb17 : 1;
151 unsigned int dummy1 : 14;
152} reg_pinmux_rw_pb_gio;
153#define REG_RD_ADDR_pinmux_rw_pb_gio 8
154#define REG_WR_ADDR_pinmux_rw_pb_gio 8
155
156/* Register rw_pb_iop, scope pinmux, type rw */
157typedef struct {
158 unsigned int pb0 : 1;
159 unsigned int pb1 : 1;
160 unsigned int pb2 : 1;
161 unsigned int pb3 : 1;
162 unsigned int pb4 : 1;
163 unsigned int pb5 : 1;
164 unsigned int pb6 : 1;
165 unsigned int pb7 : 1;
166 unsigned int pb8 : 1;
167 unsigned int pb9 : 1;
168 unsigned int pb10 : 1;
169 unsigned int pb11 : 1;
170 unsigned int pb12 : 1;
171 unsigned int pb13 : 1;
172 unsigned int pb14 : 1;
173 unsigned int pb15 : 1;
174 unsigned int pb16 : 1;
175 unsigned int pb17 : 1;
176 unsigned int dummy1 : 14;
177} reg_pinmux_rw_pb_iop;
178#define REG_RD_ADDR_pinmux_rw_pb_iop 12
179#define REG_WR_ADDR_pinmux_rw_pb_iop 12
180
181/* Register rw_pc_gio, scope pinmux, type rw */
182typedef struct {
183 unsigned int pc0 : 1;
184 unsigned int pc1 : 1;
185 unsigned int pc2 : 1;
186 unsigned int pc3 : 1;
187 unsigned int pc4 : 1;
188 unsigned int pc5 : 1;
189 unsigned int pc6 : 1;
190 unsigned int pc7 : 1;
191 unsigned int pc8 : 1;
192 unsigned int pc9 : 1;
193 unsigned int pc10 : 1;
194 unsigned int pc11 : 1;
195 unsigned int pc12 : 1;
196 unsigned int pc13 : 1;
197 unsigned int pc14 : 1;
198 unsigned int pc15 : 1;
199 unsigned int pc16 : 1;
200 unsigned int pc17 : 1;
201 unsigned int dummy1 : 14;
202} reg_pinmux_rw_pc_gio;
203#define REG_RD_ADDR_pinmux_rw_pc_gio 16
204#define REG_WR_ADDR_pinmux_rw_pc_gio 16
205
206/* Register rw_pc_iop, scope pinmux, type rw */
207typedef struct {
208 unsigned int pc0 : 1;
209 unsigned int pc1 : 1;
210 unsigned int pc2 : 1;
211 unsigned int pc3 : 1;
212 unsigned int pc4 : 1;
213 unsigned int pc5 : 1;
214 unsigned int pc6 : 1;
215 unsigned int pc7 : 1;
216 unsigned int pc8 : 1;
217 unsigned int pc9 : 1;
218 unsigned int pc10 : 1;
219 unsigned int pc11 : 1;
220 unsigned int pc12 : 1;
221 unsigned int pc13 : 1;
222 unsigned int pc14 : 1;
223 unsigned int pc15 : 1;
224 unsigned int pc16 : 1;
225 unsigned int pc17 : 1;
226 unsigned int dummy1 : 14;
227} reg_pinmux_rw_pc_iop;
228#define REG_RD_ADDR_pinmux_rw_pc_iop 20
229#define REG_WR_ADDR_pinmux_rw_pc_iop 20
230
231/* Register rw_pd_gio, scope pinmux, type rw */
232typedef struct {
233 unsigned int pd0 : 1;
234 unsigned int pd1 : 1;
235 unsigned int pd2 : 1;
236 unsigned int pd3 : 1;
237 unsigned int pd4 : 1;
238 unsigned int pd5 : 1;
239 unsigned int pd6 : 1;
240 unsigned int pd7 : 1;
241 unsigned int pd8 : 1;
242 unsigned int pd9 : 1;
243 unsigned int pd10 : 1;
244 unsigned int pd11 : 1;
245 unsigned int pd12 : 1;
246 unsigned int pd13 : 1;
247 unsigned int pd14 : 1;
248 unsigned int pd15 : 1;
249 unsigned int pd16 : 1;
250 unsigned int pd17 : 1;
251 unsigned int dummy1 : 14;
252} reg_pinmux_rw_pd_gio;
253#define REG_RD_ADDR_pinmux_rw_pd_gio 24
254#define REG_WR_ADDR_pinmux_rw_pd_gio 24
255
256/* Register rw_pd_iop, scope pinmux, type rw */
257typedef struct {
258 unsigned int pd0 : 1;
259 unsigned int pd1 : 1;
260 unsigned int pd2 : 1;
261 unsigned int pd3 : 1;
262 unsigned int pd4 : 1;
263 unsigned int pd5 : 1;
264 unsigned int pd6 : 1;
265 unsigned int pd7 : 1;
266 unsigned int pd8 : 1;
267 unsigned int pd9 : 1;
268 unsigned int pd10 : 1;
269 unsigned int pd11 : 1;
270 unsigned int pd12 : 1;
271 unsigned int pd13 : 1;
272 unsigned int pd14 : 1;
273 unsigned int pd15 : 1;
274 unsigned int pd16 : 1;
275 unsigned int pd17 : 1;
276 unsigned int dummy1 : 14;
277} reg_pinmux_rw_pd_iop;
278#define REG_RD_ADDR_pinmux_rw_pd_iop 28
279#define REG_WR_ADDR_pinmux_rw_pd_iop 28
280
281/* Register rw_pe_gio, scope pinmux, type rw */
282typedef struct {
283 unsigned int pe0 : 1;
284 unsigned int pe1 : 1;
285 unsigned int pe2 : 1;
286 unsigned int pe3 : 1;
287 unsigned int pe4 : 1;
288 unsigned int pe5 : 1;
289 unsigned int pe6 : 1;
290 unsigned int pe7 : 1;
291 unsigned int pe8 : 1;
292 unsigned int pe9 : 1;
293 unsigned int pe10 : 1;
294 unsigned int pe11 : 1;
295 unsigned int pe12 : 1;
296 unsigned int pe13 : 1;
297 unsigned int pe14 : 1;
298 unsigned int pe15 : 1;
299 unsigned int pe16 : 1;
300 unsigned int pe17 : 1;
301 unsigned int dummy1 : 14;
302} reg_pinmux_rw_pe_gio;
303#define REG_RD_ADDR_pinmux_rw_pe_gio 32
304#define REG_WR_ADDR_pinmux_rw_pe_gio 32
305
306/* Register rw_pe_iop, scope pinmux, type rw */
307typedef struct {
308 unsigned int pe0 : 1;
309 unsigned int pe1 : 1;
310 unsigned int pe2 : 1;
311 unsigned int pe3 : 1;
312 unsigned int pe4 : 1;
313 unsigned int pe5 : 1;
314 unsigned int pe6 : 1;
315 unsigned int pe7 : 1;
316 unsigned int pe8 : 1;
317 unsigned int pe9 : 1;
318 unsigned int pe10 : 1;
319 unsigned int pe11 : 1;
320 unsigned int pe12 : 1;
321 unsigned int pe13 : 1;
322 unsigned int pe14 : 1;
323 unsigned int pe15 : 1;
324 unsigned int pe16 : 1;
325 unsigned int pe17 : 1;
326 unsigned int dummy1 : 14;
327} reg_pinmux_rw_pe_iop;
328#define REG_RD_ADDR_pinmux_rw_pe_iop 36
329#define REG_WR_ADDR_pinmux_rw_pe_iop 36
330
331/* Register rw_usb_phy, scope pinmux, type rw */
332typedef struct {
333 unsigned int en_usb0 : 1;
334 unsigned int en_usb1 : 1;
335 unsigned int dummy1 : 30;
336} reg_pinmux_rw_usb_phy;
337#define REG_RD_ADDR_pinmux_rw_usb_phy 40
338#define REG_WR_ADDR_pinmux_rw_usb_phy 40
339
340
341/* Constants */
342enum {
343 regk_pinmux_no = 0x00000000,
344 regk_pinmux_rw_hwprot_default = 0x00000000,
345 regk_pinmux_rw_pa_default = 0x00000000,
346 regk_pinmux_rw_pb_gio_default = 0x00000000,
347 regk_pinmux_rw_pb_iop_default = 0x00000000,
348 regk_pinmux_rw_pc_gio_default = 0x00000000,
349 regk_pinmux_rw_pc_iop_default = 0x00000000,
350 regk_pinmux_rw_pd_gio_default = 0x00000000,
351 regk_pinmux_rw_pd_iop_default = 0x00000000,
352 regk_pinmux_rw_pe_gio_default = 0x00000000,
353 regk_pinmux_rw_pe_iop_default = 0x00000000,
354 regk_pinmux_rw_usb_phy_default = 0x00000000,
355 regk_pinmux_yes = 0x00000001
356};
357#endif /* __pinmux_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/reg_map.h b/include/asm-cris/arch-v32/mach-fs/hwregs/reg_map.h
new file mode 100644
index 000000000000..4146973a58b3
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-fs/hwregs/reg_map.h
@@ -0,0 +1,104 @@
1#ifndef __reg_map_h
2#define __reg_map_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../mod/fakereg.rmap
7 * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp
8 * last modified: Wed Feb 11 20:53:25 2004
9 * file: ../../rtl/global.rmap
10 * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp
11 * last modified: Mon Aug 18 17:08:23 2003
12 * file: ../../mod/modreg.rmap
13 * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp
14 * last modified: Fri Feb 20 16:40:04 2004
15 *
16 * by /n/asic/design/tools/rdesc/src/rdes2c -map -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/io_proc/rtl/guinness/iop_top.r ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap
17 * id: $Id: reg_map.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
18 * Any changes here will be lost.
19 *
20 * -*- buffer-read-only: t -*-
21 */
22typedef enum {
23 regi_ata = 0xb0032000,
24 regi_bif_core = 0xb0014000,
25 regi_bif_dma = 0xb0016000,
26 regi_bif_slave = 0xb0018000,
27 regi_config = 0xb003c000,
28 regi_dma0 = 0xb0000000,
29 regi_dma1 = 0xb0002000,
30 regi_dma2 = 0xb0004000,
31 regi_dma3 = 0xb0006000,
32 regi_dma4 = 0xb0008000,
33 regi_dma5 = 0xb000a000,
34 regi_dma6 = 0xb000c000,
35 regi_dma7 = 0xb000e000,
36 regi_dma8 = 0xb0010000,
37 regi_dma9 = 0xb0012000,
38 regi_eth0 = 0xb0034000,
39 regi_eth1 = 0xb0036000,
40 regi_gio = 0xb001a000,
41 regi_iop = 0xb0020000,
42 regi_iop_version = 0xb0020000,
43 regi_iop_fifo_in0_extra = 0xb0020040,
44 regi_iop_fifo_in1_extra = 0xb0020080,
45 regi_iop_fifo_out0_extra = 0xb00200c0,
46 regi_iop_fifo_out1_extra = 0xb0020100,
47 regi_iop_trigger_grp0 = 0xb0020140,
48 regi_iop_trigger_grp1 = 0xb0020180,
49 regi_iop_trigger_grp2 = 0xb00201c0,
50 regi_iop_trigger_grp3 = 0xb0020200,
51 regi_iop_trigger_grp4 = 0xb0020240,
52 regi_iop_trigger_grp5 = 0xb0020280,
53 regi_iop_trigger_grp6 = 0xb00202c0,
54 regi_iop_trigger_grp7 = 0xb0020300,
55 regi_iop_crc_par0 = 0xb0020380,
56 regi_iop_crc_par1 = 0xb0020400,
57 regi_iop_dmc_in0 = 0xb0020480,
58 regi_iop_dmc_in1 = 0xb0020500,
59 regi_iop_dmc_out0 = 0xb0020580,
60 regi_iop_dmc_out1 = 0xb0020600,
61 regi_iop_fifo_in0 = 0xb0020680,
62 regi_iop_fifo_in1 = 0xb0020700,
63 regi_iop_fifo_out0 = 0xb0020780,
64 regi_iop_fifo_out1 = 0xb0020800,
65 regi_iop_scrc_in0 = 0xb0020880,
66 regi_iop_scrc_in1 = 0xb0020900,
67 regi_iop_scrc_out0 = 0xb0020980,
68 regi_iop_scrc_out1 = 0xb0020a00,
69 regi_iop_timer_grp0 = 0xb0020a80,
70 regi_iop_timer_grp1 = 0xb0020b00,
71 regi_iop_timer_grp2 = 0xb0020b80,
72 regi_iop_timer_grp3 = 0xb0020c00,
73 regi_iop_sap_in = 0xb0020d00,
74 regi_iop_sap_out = 0xb0020e00,
75 regi_iop_spu0 = 0xb0020f00,
76 regi_iop_spu1 = 0xb0021000,
77 regi_iop_sw_cfg = 0xb0021100,
78 regi_iop_sw_cpu = 0xb0021200,
79 regi_iop_sw_mpu = 0xb0021300,
80 regi_iop_sw_spu0 = 0xb0021400,
81 regi_iop_sw_spu1 = 0xb0021500,
82 regi_iop_mpu = 0xb0021600,
83 regi_irq = 0xb001c000,
84 regi_irq2 = 0xb005c000,
85 regi_marb = 0xb003e000,
86 regi_marb_bp0 = 0xb003e240,
87 regi_marb_bp1 = 0xb003e280,
88 regi_marb_bp2 = 0xb003e2c0,
89 regi_marb_bp3 = 0xb003e300,
90 regi_pinmux = 0xb0038000,
91 regi_ser0 = 0xb0026000,
92 regi_ser1 = 0xb0028000,
93 regi_ser2 = 0xb002a000,
94 regi_ser3 = 0xb002c000,
95 regi_sser0 = 0xb0022000,
96 regi_sser1 = 0xb0024000,
97 regi_strcop = 0xb0030000,
98 regi_strmux = 0xb003a000,
99 regi_timer = 0xb001e000,
100 regi_timer0 = 0xb001e000,
101 regi_timer2 = 0xb005e000,
102 regi_trace = 0xb0040000,
103} reg_scope_instances;
104#endif /* __reg_map_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/strmux_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/strmux_defs.h
new file mode 100644
index 000000000000..cbfaa867829e
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-fs/hwregs/strmux_defs.h
@@ -0,0 +1,127 @@
1#ifndef __strmux_defs_h
2#define __strmux_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/strmux/rtl/guinness/strmux_regs.r
7 * id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp
8 * last modfied: Mon Apr 11 16:09:43 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile strmux_defs.h ../../inst/strmux/rtl/guinness/strmux_regs.r
11 * id: $Id: strmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope strmux */
86
87/* Register rw_cfg, scope strmux, type rw */
88typedef struct {
89 unsigned int dma0 : 3;
90 unsigned int dma1 : 3;
91 unsigned int dma2 : 3;
92 unsigned int dma3 : 3;
93 unsigned int dma4 : 3;
94 unsigned int dma5 : 3;
95 unsigned int dma6 : 3;
96 unsigned int dma7 : 3;
97 unsigned int dma8 : 3;
98 unsigned int dma9 : 3;
99 unsigned int dummy1 : 2;
100} reg_strmux_rw_cfg;
101#define REG_RD_ADDR_strmux_rw_cfg 0
102#define REG_WR_ADDR_strmux_rw_cfg 0
103
104
105/* Constants */
106enum {
107 regk_strmux_ata = 0x00000003,
108 regk_strmux_eth0 = 0x00000001,
109 regk_strmux_eth1 = 0x00000004,
110 regk_strmux_ext0 = 0x00000001,
111 regk_strmux_ext1 = 0x00000001,
112 regk_strmux_ext2 = 0x00000001,
113 regk_strmux_ext3 = 0x00000001,
114 regk_strmux_iop0 = 0x00000002,
115 regk_strmux_iop1 = 0x00000001,
116 regk_strmux_off = 0x00000000,
117 regk_strmux_p21 = 0x00000004,
118 regk_strmux_rw_cfg_default = 0x00000000,
119 regk_strmux_ser0 = 0x00000002,
120 regk_strmux_ser1 = 0x00000002,
121 regk_strmux_ser2 = 0x00000004,
122 regk_strmux_ser3 = 0x00000003,
123 regk_strmux_sser0 = 0x00000003,
124 regk_strmux_sser1 = 0x00000003,
125 regk_strmux_strcop = 0x00000002
126};
127#endif /* __strmux_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/timer_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/timer_defs.h
new file mode 100644
index 000000000000..76bcc591921d
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-fs/hwregs/timer_defs.h
@@ -0,0 +1,266 @@
1#ifndef __timer_defs_h
2#define __timer_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/timer/rtl/timer_regs.r
7 * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp
8 * last modfied: Mon Apr 11 16:09:53 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile timer_defs.h ../../inst/timer/rtl/timer_regs.r
11 * id: $Id: timer_defs.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope timer */
86
87/* Register rw_tmr0_div, scope timer, type rw */
88typedef unsigned int reg_timer_rw_tmr0_div;
89#define REG_RD_ADDR_timer_rw_tmr0_div 0
90#define REG_WR_ADDR_timer_rw_tmr0_div 0
91
92/* Register r_tmr0_data, scope timer, type r */
93typedef unsigned int reg_timer_r_tmr0_data;
94#define REG_RD_ADDR_timer_r_tmr0_data 4
95
96/* Register rw_tmr0_ctrl, scope timer, type rw */
97typedef struct {
98 unsigned int op : 2;
99 unsigned int freq : 3;
100 unsigned int dummy1 : 27;
101} reg_timer_rw_tmr0_ctrl;
102#define REG_RD_ADDR_timer_rw_tmr0_ctrl 8
103#define REG_WR_ADDR_timer_rw_tmr0_ctrl 8
104
105/* Register rw_tmr1_div, scope timer, type rw */
106typedef unsigned int reg_timer_rw_tmr1_div;
107#define REG_RD_ADDR_timer_rw_tmr1_div 16
108#define REG_WR_ADDR_timer_rw_tmr1_div 16
109
110/* Register r_tmr1_data, scope timer, type r */
111typedef unsigned int reg_timer_r_tmr1_data;
112#define REG_RD_ADDR_timer_r_tmr1_data 20
113
114/* Register rw_tmr1_ctrl, scope timer, type rw */
115typedef struct {
116 unsigned int op : 2;
117 unsigned int freq : 3;
118 unsigned int dummy1 : 27;
119} reg_timer_rw_tmr1_ctrl;
120#define REG_RD_ADDR_timer_rw_tmr1_ctrl 24
121#define REG_WR_ADDR_timer_rw_tmr1_ctrl 24
122
123/* Register rs_cnt_data, scope timer, type rs */
124typedef struct {
125 unsigned int tmr : 24;
126 unsigned int cnt : 8;
127} reg_timer_rs_cnt_data;
128#define REG_RD_ADDR_timer_rs_cnt_data 32
129
130/* Register r_cnt_data, scope timer, type r */
131typedef struct {
132 unsigned int tmr : 24;
133 unsigned int cnt : 8;
134} reg_timer_r_cnt_data;
135#define REG_RD_ADDR_timer_r_cnt_data 36
136
137/* Register rw_cnt_cfg, scope timer, type rw */
138typedef struct {
139 unsigned int clk : 2;
140 unsigned int dummy1 : 30;
141} reg_timer_rw_cnt_cfg;
142#define REG_RD_ADDR_timer_rw_cnt_cfg 40
143#define REG_WR_ADDR_timer_rw_cnt_cfg 40
144
145/* Register rw_trig, scope timer, type rw */
146typedef unsigned int reg_timer_rw_trig;
147#define REG_RD_ADDR_timer_rw_trig 48
148#define REG_WR_ADDR_timer_rw_trig 48
149
150/* Register rw_trig_cfg, scope timer, type rw */
151typedef struct {
152 unsigned int tmr : 2;
153 unsigned int dummy1 : 30;
154} reg_timer_rw_trig_cfg;
155#define REG_RD_ADDR_timer_rw_trig_cfg 52
156#define REG_WR_ADDR_timer_rw_trig_cfg 52
157
158/* Register r_time, scope timer, type r */
159typedef unsigned int reg_timer_r_time;
160#define REG_RD_ADDR_timer_r_time 56
161
162/* Register rw_out, scope timer, type rw */
163typedef struct {
164 unsigned int tmr : 2;
165 unsigned int dummy1 : 30;
166} reg_timer_rw_out;
167#define REG_RD_ADDR_timer_rw_out 60
168#define REG_WR_ADDR_timer_rw_out 60
169
170/* Register rw_wd_ctrl, scope timer, type rw */
171typedef struct {
172 unsigned int cnt : 8;
173 unsigned int cmd : 1;
174 unsigned int key : 7;
175 unsigned int dummy1 : 16;
176} reg_timer_rw_wd_ctrl;
177#define REG_RD_ADDR_timer_rw_wd_ctrl 64
178#define REG_WR_ADDR_timer_rw_wd_ctrl 64
179
180/* Register r_wd_stat, scope timer, type r */
181typedef struct {
182 unsigned int cnt : 8;
183 unsigned int cmd : 1;
184 unsigned int dummy1 : 23;
185} reg_timer_r_wd_stat;
186#define REG_RD_ADDR_timer_r_wd_stat 68
187
188/* Register rw_intr_mask, scope timer, type rw */
189typedef struct {
190 unsigned int tmr0 : 1;
191 unsigned int tmr1 : 1;
192 unsigned int cnt : 1;
193 unsigned int trig : 1;
194 unsigned int dummy1 : 28;
195} reg_timer_rw_intr_mask;
196#define REG_RD_ADDR_timer_rw_intr_mask 72
197#define REG_WR_ADDR_timer_rw_intr_mask 72
198
199/* Register rw_ack_intr, scope timer, type rw */
200typedef struct {
201 unsigned int tmr0 : 1;
202 unsigned int tmr1 : 1;
203 unsigned int cnt : 1;
204 unsigned int trig : 1;
205 unsigned int dummy1 : 28;
206} reg_timer_rw_ack_intr;
207#define REG_RD_ADDR_timer_rw_ack_intr 76
208#define REG_WR_ADDR_timer_rw_ack_intr 76
209
210/* Register r_intr, scope timer, type r */
211typedef struct {
212 unsigned int tmr0 : 1;
213 unsigned int tmr1 : 1;
214 unsigned int cnt : 1;
215 unsigned int trig : 1;
216 unsigned int dummy1 : 28;
217} reg_timer_r_intr;
218#define REG_RD_ADDR_timer_r_intr 80
219
220/* Register r_masked_intr, scope timer, type r */
221typedef struct {
222 unsigned int tmr0 : 1;
223 unsigned int tmr1 : 1;
224 unsigned int cnt : 1;
225 unsigned int trig : 1;
226 unsigned int dummy1 : 28;
227} reg_timer_r_masked_intr;
228#define REG_RD_ADDR_timer_r_masked_intr 84
229
230/* Register rw_test, scope timer, type rw */
231typedef struct {
232 unsigned int dis : 1;
233 unsigned int en : 1;
234 unsigned int dummy1 : 30;
235} reg_timer_rw_test;
236#define REG_RD_ADDR_timer_rw_test 88
237#define REG_WR_ADDR_timer_rw_test 88
238
239
240/* Constants */
241enum {
242 regk_timer_ext = 0x00000001,
243 regk_timer_f100 = 0x00000007,
244 regk_timer_f29_493 = 0x00000004,
245 regk_timer_f32 = 0x00000005,
246 regk_timer_f32_768 = 0x00000006,
247 regk_timer_hold = 0x00000001,
248 regk_timer_ld = 0x00000000,
249 regk_timer_no = 0x00000000,
250 regk_timer_off = 0x00000000,
251 regk_timer_run = 0x00000002,
252 regk_timer_rw_cnt_cfg_default = 0x00000000,
253 regk_timer_rw_intr_mask_default = 0x00000000,
254 regk_timer_rw_out_default = 0x00000000,
255 regk_timer_rw_test_default = 0x00000000,
256 regk_timer_rw_tmr0_ctrl_default = 0x00000000,
257 regk_timer_rw_tmr1_ctrl_default = 0x00000000,
258 regk_timer_rw_trig_cfg_default = 0x00000000,
259 regk_timer_start = 0x00000001,
260 regk_timer_stop = 0x00000000,
261 regk_timer_time = 0x00000001,
262 regk_timer_tmr0 = 0x00000002,
263 regk_timer_tmr1 = 0x00000003,
264 regk_timer_yes = 0x00000001
265};
266#endif /* __timer_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/pinmux.h b/include/asm-cris/arch-v32/mach-fs/pinmux.h
new file mode 100644
index 000000000000..c2b3036779df
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-fs/pinmux.h
@@ -0,0 +1,38 @@
1#ifndef _ASM_CRIS_ARCH_PINMUX_H
2#define _ASM_CRIS_ARCH_PINMUX_H
3
4#define PORT_B 0
5#define PORT_C 1
6#define PORT_D 2
7#define PORT_E 3
8
9enum pin_mode {
10 pinmux_none = 0,
11 pinmux_fixed,
12 pinmux_gpio,
13 pinmux_iop
14};
15
16enum fixed_function {
17 pinmux_ser1,
18 pinmux_ser2,
19 pinmux_ser3,
20 pinmux_sser0,
21 pinmux_sser1,
22 pinmux_ata0,
23 pinmux_ata1,
24 pinmux_ata2,
25 pinmux_ata3,
26 pinmux_ata,
27 pinmux_eth1,
28 pinmux_timer
29};
30
31int crisv32_pinmux_init(void);
32int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode);
33int crisv32_pinmux_alloc_fixed(enum fixed_function function);
34int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin);
35int crisv32_pinmux_dealloc_fixed(enum fixed_function function);
36void crisv32_pinmux_dump(void);
37
38#endif
diff --git a/include/asm-cris/arch-v32/mach-fs/startup.inc b/include/asm-cris/arch-v32/mach-fs/startup.inc
new file mode 100644
index 000000000000..4a10ccbd6cc1
--- /dev/null
+++ b/include/asm-cris/arch-v32/mach-fs/startup.inc
@@ -0,0 +1,77 @@
1#include <hwregs/asm/reg_map_asm.h>
2#include <hwregs/asm/bif_core_defs_asm.h>
3#include <hwregs/asm/gio_defs_asm.h>
4#include <hwregs/asm/config_defs_asm.h>
5
6 .macro GIO_INIT
7 move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0
8 move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r1
9 move.d $r0, [$r1]
10
11 move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0
12 move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r1
13 move.d $r0, [$r1]
14
15 move.d CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0
16 move.d REG_ADDR(gio, regi_gio, rw_pb_dout), $r1
17 move.d $r0, [$r1]
18
19 move.d CONFIG_ETRAX_DEF_GIO_PB_OE, $r0
20 move.d REG_ADDR(gio, regi_gio, rw_pb_oe), $r1
21 move.d $r0, [$r1]
22
23 move.d CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0
24 move.d REG_ADDR(gio, regi_gio, rw_pc_dout), $r1
25 move.d $r0, [$r1]
26
27 move.d CONFIG_ETRAX_DEF_GIO_PC_OE, $r0
28 move.d REG_ADDR(gio, regi_gio, rw_pc_oe), $r1
29 move.d $r0, [$r1]
30
31 move.d CONFIG_ETRAX_DEF_GIO_PD_OUT, $r0
32 move.d REG_ADDR(gio, regi_gio, rw_pd_dout), $r1
33 move.d $r0, [$r1]
34
35 move.d CONFIG_ETRAX_DEF_GIO_PD_OE, $r0
36 move.d REG_ADDR(gio, regi_gio, rw_pd_oe), $r1
37 move.d $r0, [$r1]
38
39 move.d CONFIG_ETRAX_DEF_GIO_PE_OUT, $r0
40 move.d REG_ADDR(gio, regi_gio, rw_pe_dout), $r1
41 move.d $r0, [$r1]
42
43 move.d CONFIG_ETRAX_DEF_GIO_PE_OE, $r0
44 move.d REG_ADDR(gio, regi_gio, rw_pe_oe), $r1
45 move.d $r0, [$r1]
46 .endm
47
48 .macro START_CLOCKS
49 move.d REG_ADDR(config, regi_config, rw_clk_ctrl), $r1
50 move.d [$r1], $r0
51 or.d REG_STATE(config, rw_clk_ctrl, cpu, yes) | \
52 REG_STATE(config, rw_clk_ctrl, bif, yes) | \
53 REG_STATE(config, rw_clk_ctrl, fix_io, yes), $r0
54 move.d $r0, [$r1]
55 .endm
56
57 .macro SETUP_WAIT_STATES
58 ;; Set up waitstates etc
59 move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r0
60 move.d CONFIG_ETRAX_MEM_GRP1_CONFIG, $r1
61 move.d $r1, [$r0]
62 move.d REG_ADDR(bif_core, regi_bif_core, rw_grp2_cfg), $r0
63 move.d CONFIG_ETRAX_MEM_GRP2_CONFIG, $r1
64 move.d $r1, [$r0]
65 move.d REG_ADDR(bif_core, regi_bif_core, rw_grp3_cfg), $r0
66 move.d CONFIG_ETRAX_MEM_GRP3_CONFIG, $r1
67 move.d $r1, [$r0]
68 move.d REG_ADDR(bif_core, regi_bif_core, rw_grp4_cfg), $r0
69 move.d CONFIG_ETRAX_MEM_GRP4_CONFIG, $r1
70 move.d $r1, [$r0]
71#ifdef CONFIG_ETRAX_VCS_SIM
72 ;; Set up minimal flash waitstates
73 move.d 0, $r10
74 move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r11
75 move.d $r10, [$r11]
76#endif
77 .endm