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authorMikael Starvik <mikael.starvik@axis.com>2005-07-27 14:44:44 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2005-07-27 19:26:01 -0400
commit51533b615e605d86154ec1b4e585c8ca1b0b15b7 (patch)
tree4a6d7d8494d2017632d83624fb71b36031e0e7e5 /include/asm-cris/arch-v32/hwregs/intr_vect.h
parent5d01e6ce785884a5db5792cd2e5bb36fa82fe23c (diff)
[PATCH] CRIS update: new subarchitecture v32
New CRIS sub architecture named v32. From: Dave Jones <davej@redhat.com> Fix swapped kmalloc args Signed-off-by: Mikael Starvik <starvik@axis.com> Signed-off-by: Dave Jones <davej@redhat.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-cris/arch-v32/hwregs/intr_vect.h')
-rw-r--r--include/asm-cris/arch-v32/hwregs/intr_vect.h39
1 files changed, 39 insertions, 0 deletions
diff --git a/include/asm-cris/arch-v32/hwregs/intr_vect.h b/include/asm-cris/arch-v32/hwregs/intr_vect.h
new file mode 100644
index 000000000000..5c1b28fb205d
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/intr_vect.h
@@ -0,0 +1,39 @@
1/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
2 from ../../inst/intr_vect/rtl/guinness/ivmask.config.r
3version . */
4
5#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
6#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
7#define MEMARB_INTR_VECT 0x31
8#define GEN_IO_INTR_VECT 0x32
9#define IOP0_INTR_VECT 0x33
10#define IOP1_INTR_VECT 0x34
11#define IOP2_INTR_VECT 0x35
12#define IOP3_INTR_VECT 0x36
13#define DMA0_INTR_VECT 0x37
14#define DMA1_INTR_VECT 0x38
15#define DMA2_INTR_VECT 0x39
16#define DMA3_INTR_VECT 0x3a
17#define DMA4_INTR_VECT 0x3b
18#define DMA5_INTR_VECT 0x3c
19#define DMA6_INTR_VECT 0x3d
20#define DMA7_INTR_VECT 0x3e
21#define DMA8_INTR_VECT 0x3f
22#define DMA9_INTR_VECT 0x40
23#define ATA_INTR_VECT 0x41
24#define SSER0_INTR_VECT 0x42
25#define SSER1_INTR_VECT 0x43
26#define SER0_INTR_VECT 0x44
27#define SER1_INTR_VECT 0x45
28#define SER2_INTR_VECT 0x46
29#define SER3_INTR_VECT 0x47
30#define P21_INTR_VECT 0x48
31#define ETH0_INTR_VECT 0x49
32#define ETH1_INTR_VECT 0x4a
33#define TIMER_INTR_VECT 0x4b
34#define BIF_ARB_INTR_VECT 0x4c
35#define BIF_DMA_INTR_VECT 0x4d
36#define EXT_INTR_VECT 0x4e
37#define IPI_INTR_VECT 0x4f
38
39#endif