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authorRobin Getz <robin.getz@analog.com>2007-08-05 05:21:55 -0400
committerBryan Wu <bryan.wu@analog.com>2007-08-05 05:21:55 -0400
commite62687f995fd7ba0b68c3b0a4f4d9fd9d1c54ec2 (patch)
treec7be40ad9dea5028994aa640f90b841d1a3c54c4 /include/asm-blackfin
parent4bbd10fd312f50de74ba53f6cb968986da5dfe92 (diff)
Blackfin arch: fix the aliased write macros
Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include/asm-blackfin')
-rw-r--r--include/asm-blackfin/mach-bf561/cdefBF561.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h
index 6e87ab269ffe..73d4d65249cd 100644
--- a/include/asm-blackfin/mach-bf561/cdefBF561.h
+++ b/include/asm-blackfin/mach-bf561/cdefBF561.h
@@ -83,9 +83,9 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
83 83
84/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ 84/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
85#define bfin_read_SWRST() bfin_read_SICA_SWRST() 85#define bfin_read_SWRST() bfin_read_SICA_SWRST()
86#define bfin_write_SWRST() bfin_write_SICA_SWRST() 86#define bfin_write_SWRST(val) bfin_write_SICA_SWRST(val)
87#define bfin_read_SYSCR() bfin_read_SICA_SYSCR() 87#define bfin_read_SYSCR() bfin_read_SICA_SYSCR()
88#define bfin_write_SYSCR() bfin_write_SICA_SYSCR() 88#define bfin_write_SYSCR(val) bfin_write_SICA_SYSCR(val)
89 89
90/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ 90/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
91#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST) 91#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST)