Blackfin arch: add missing implementations SIC_IWR crosses several registers

SIC_IWR crosses several registers
 - add missing implementations
 - make sure SIC_IWR is SET after boot

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>

2 files changed, 33 insertions, 4 deletions

diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
index b1338000e27b..87f2385ed971 100644
--- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
@@ -32,6 +32,7 @@
 #define _CDEF_BF54X_H
 
 #include "defBF54x_base.h"
+#include <asm/system.h>
 
 /* ************************************************************** */
 /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x    */
@@ -44,7 +45,31 @@
 #define bfin_read_PLL_DIV()             bfin_read16(PLL_DIV)
 #define bfin_write_PLL_DIV(val)         bfin_write16(PLL_DIV, val)
 #define bfin_read_VR_CTL()              bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val)          bfin_write16(VR_CTL, val)
+/* Writing to VR_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_VR_CTL(unsigned int val)
+{
+        unsigned long flags, iwr0, iwr1, iwr2;
+
+        /* Enable the PLL Wakeup bit in SIC IWR */
+        iwr0 = bfin_read32(SIC_IWR0);
+        iwr1 = bfin_read32(SIC_IWR1);
+        iwr2 = bfin_read32(SIC_IWR2);
+        /* Only allow PPL Wakeup) */
+        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
+        bfin_write32(SIC_IWR1, 0);
+        bfin_write32(SIC_IWR2, 0);
+
+        bfin_write16(VR_CTL, val);
+        __builtin_bfin_ssync();
+
+        local_irq_save(flags);
+        asm("IDLE;");
+        local_irq_restore(flags);
+        bfin_write32(SIC_IWR0, iwr0);
+        bfin_write32(SIC_IWR1, iwr1);
+        bfin_write32(SIC_IWR2, iwr2);
+        
+}
 #define bfin_read_PLL_STAT()            bfin_read16(PLL_STAT)
 #define bfin_write_PLL_STAT(val)        bfin_write16(PLL_STAT, val)
 #define bfin_read_PLL_LOCKCNT()         bfin_read16(PLL_LOCKCNT)
diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h
index b14f872e5703..6e8b8168a97a 100644
--- a/include/asm-blackfin/mach-bf561/cdefBF561.h
+++ b/include/asm-blackfin/mach-bf561/cdefBF561.h
@@ -57,12 +57,14 @@
 /* Writing to VR_CTL initiates a PLL relock sequence. */
 static __inline__ void bfin_write_VR_CTL(unsigned int val)
 {
-        unsigned long flags, iwr;
+        unsigned long flags, iwr0, iwr1;
 
         /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr = bfin_read32(SICA_IWR0);
+        iwr0 = bfin_read32(SICA_IWR0);
+        iwr1 = bfin_read32(SICA_IWR1);
         /* Only allow PPL Wakeup) */
         bfin_write32(SICA_IWR0, IWR_ENABLE(0));
+        bfin_write32(SICA_IWR1, 0);
 
         bfin_write16(VR_CTL, val);
         __builtin_bfin_ssync();
@@ -70,7 +72,9 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
         local_irq_save(flags);
         asm("IDLE;");
         local_irq_restore(flags);
-        bfin_write32(SICA_IWR0, iwr);
+        bfin_write32(SICA_IWR0, iwr0);
+        bfin_write32(SICA_IWR1, iwr1);
+
 }
 #define bfin_read_PLL_STAT()                 bfin_read16(PLL_STAT)
 #define bfin_write_PLL_STAT(val)             bfin_write16(PLL_STAT,val)