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authorMike Frysinger <michael.frysinger@analog.com>2007-08-05 05:32:25 -0400
committerBryan Wu <bryan.wu@analog.com>2007-08-05 05:32:25 -0400
commitbc8c84c947ad65cd2850c43f96bea825e426f9eb (patch)
treeb0115bbd27e6158d753e4fc58633bcbb510b5c2c /include/asm-blackfin
parentfb51d566803413d2682ca718aef1c6f946fdab05 (diff)
Blackfin arch: update to latest anomaly sheets
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include/asm-blackfin')
-rw-r--r--include/asm-blackfin/mach-bf527/anomaly.h39
-rw-r--r--include/asm-blackfin/mach-bf537/anomaly.h2
-rw-r--r--include/asm-blackfin/mach-bf548/anomaly.h18
-rw-r--r--include/asm-blackfin/mach-bf561/anomaly.h1
4 files changed, 55 insertions, 5 deletions
diff --git a/include/asm-blackfin/mach-bf527/anomaly.h b/include/asm-blackfin/mach-bf527/anomaly.h
new file mode 100644
index 000000000000..6112bc38282f
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/anomaly.h
@@ -0,0 +1,39 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 *
5 * Copyright (C) 2004-2007 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
7 */
8
9/* This file shoule be up to date with:
10 * - Revision A, May 30, 2007; ADSP-BF527 Blackfin Processor Anomaly List
11 */
12
13#ifndef _MACH_ANOMALY_H_
14#define _MACH_ANOMALY_H_
15
16/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
17#define ANOMALY_05000074 (1)
18/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
19#define ANOMALY_05000119 (1)
20/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
21#define ANOMALY_05000122 (1)
22/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
23#define ANOMALY_05000245 (1)
24/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
25#define ANOMALY_05000265 (1)
26/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
27#define ANOMALY_05000301 (1)
28/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
29#define ANOMALY_05000312 (1)
30/* Incorrect Access of OTP_STATUS During otp_write() Function */
31#define ANOMALY_05000328 (1)
32/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
33#define ANOMALY_05000337 (1)
34/* TWI Does Not Operate Correctly Under Certain Signal Termination Conditions */
35#define ANOMALY_05000342 (1)
36/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
37#define ANOMALY_05000347 (1)
38
39#endif
diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h
index dc736c61980f..3803f156bf1c 100644
--- a/include/asm-blackfin/mach-bf537/anomaly.h
+++ b/include/asm-blackfin/mach-bf537/anomaly.h
@@ -44,8 +44,6 @@
44#define ANOMALY_05000122 (1) 44#define ANOMALY_05000122 (1)
45/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ 45/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
46#define ANOMALY_05000157 (__SILICON_REVISION__ < 2) 46#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
47/* PPI Data Lengths Between 8 and 16 do not zero out upper bits*/
48#define ANOMALY_05000166 (1) /* XXX: deleted from BF537 sheet ? */
49/* PPI_DELAY not functional in PPI modes with 0 frame syncs */ 47/* PPI_DELAY not functional in PPI modes with 0 frame syncs */
50#define ANOMALY_05000180 (1) 48#define ANOMALY_05000180 (1)
51/* Instruction Cache Is Not Functional */ 49/* Instruction Cache Is Not Functional */
diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h
index 37e0bd22b64b..224837845c7c 100644
--- a/include/asm-blackfin/mach-bf548/anomaly.h
+++ b/include/asm-blackfin/mach-bf548/anomaly.h
@@ -7,7 +7,7 @@
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision B, April 6, 2007; ADSP-BF549 Silicon Anomaly List 10 * - Revision C, July 16, 2007; ADSP-BF549 Silicon Anomaly List
11 */ 11 */
12 12
13#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -21,14 +21,14 @@
21#define ANOMALY_05000122 (1) 21#define ANOMALY_05000122 (1)
22/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ 22/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
23#define ANOMALY_05000245 (1) 23#define ANOMALY_05000245 (1)
24/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
25#define ANOMALY_05000255 (1)
26/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ 24/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
27#define ANOMALY_05000265 (1) 25#define ANOMALY_05000265 (1)
28/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ 26/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
29#define ANOMALY_05000272 (1) 27#define ANOMALY_05000272 (1)
30/* False Hardware Error Exception when ISR context is not restored */ 28/* False Hardware Error Exception when ISR context is not restored */
31#define ANOMALY_05000281 (1) 29#define ANOMALY_05000281 (1)
30/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
31#define ANOMALY_05000304 (1)
32/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ 32/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
33#define ANOMALY_05000310 (1) 33#define ANOMALY_05000310 (1)
34/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ 34/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
@@ -55,6 +55,18 @@
55#define ANOMALY_05000337 (1) 55#define ANOMALY_05000337 (1)
56/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ 56/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
57#define ANOMALY_05000338 (1) 57#define ANOMALY_05000338 (1)
58/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
59#define ANOMALY_05000340 (1)
60/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
61#define ANOMALY_05000344 (1)
62/* USB Calibration Value Is Not Intialized */
63#define ANOMALY_05000346 (1)
64/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
65#define ANOMALY_05000347 (1)
66/* Data Lost when Core Reads SDH Data FIFO */
67#define ANOMALY_05000349 (1)
68/* PLL Status Register Is Inaccurate */
69#define ANOMALY_05000351 (1)
58 70
59/* Anomalies that don't exist on this proc */ 71/* Anomalies that don't exist on this proc */
60#define ANOMALY_05000125 (0) 72#define ANOMALY_05000125 (0)
diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h
index 4cb3337d45ee..bed956456884 100644
--- a/include/asm-blackfin/mach-bf561/anomaly.h
+++ b/include/asm-blackfin/mach-bf561/anomaly.h
@@ -248,6 +248,7 @@
248#define ANOMALY_05000333 (__SILICON_REVISION__ < 5) 248#define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
249 249
250/* Anomalies that don't exist on this proc */ 250/* Anomalies that don't exist on this proc */
251#define ANOMALY_05000158 (0)
251#define ANOMALY_05000183 (0) 252#define ANOMALY_05000183 (0)
252#define ANOMALY_05000273 (0) 253#define ANOMALY_05000273 (0)
253#define ANOMALY_05000311 (0) 254#define ANOMALY_05000311 (0)